[linux-block.git] / drivers / clk / qcom / lpasscc-sc7280.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/qcom,lpass-sc7280.h>

#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"

static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
	.halt_reg = 0x0,
	.halt_check = BRANCH_HALT,
	.clkr = {
		.enable_reg = 0x0,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
			.ops = &clk_branch2_ops,
		},
	},
};

static struct clk_branch lpass_qdsp6ss_core_clk = {
	.halt_reg = 0x20,
	/* CLK_OFF would not toggle until LPASS is out of reset */
	.halt_check = BRANCH_HALT_SKIP,
	.clkr = {
		.enable_reg = 0x20,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "lpass_qdsp6ss_core_clk",
			.ops = &clk_branch2_ops,
		},
	},
};

static struct clk_branch lpass_qdsp6ss_xo_clk = {
	.halt_reg = 0x38,
	/* CLK_OFF would not toggle until LPASS is out of reset */
	.halt_check = BRANCH_HALT_SKIP,
	.clkr = {
		.enable_reg = 0x38,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "lpass_qdsp6ss_xo_clk",
			.ops = &clk_branch2_ops,
		},
	},
};

static struct clk_branch lpass_qdsp6ss_sleep_clk = {
	.halt_reg = 0x3c,
	/* CLK_OFF would not toggle until LPASS is out of reset */
	.halt_check = BRANCH_HALT_SKIP,
	.clkr = {
		.enable_reg = 0x3c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "lpass_qdsp6ss_sleep_clk",
			.ops = &clk_branch2_ops,
		},
	},
};

static struct regmap_config lpass_regmap_config = {
	.reg_bits	= 32,
	.reg_stride	= 4,
	.val_bits	= 32,
	.fast_io	= true,
};

static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
	[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
				&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
};

static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
	.config = &lpass_regmap_config,
	.clks = lpass_cc_top_sc7280_clocks,
	.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
};

static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
	[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
	[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
	[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
};

static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
	.config = &lpass_regmap_config,
	.clks = lpass_qdsp6ss_sc7280_clocks,
	.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
};

static int lpass_cc_sc7280_probe(struct platform_device *pdev)
{
	const struct qcom_cc_desc *desc;
	int ret;

	ret = devm_pm_runtime_enable(&pdev->dev);
	if (ret)
		return ret;

	ret = pm_clk_create(&pdev->dev);
	if (ret)
		return ret;

	ret = pm_clk_add(&pdev->dev, "iface");
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to acquire iface clock\n");
		goto destroy_pm_clk;
	}

	if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
		lpass_regmap_config.name = "qdsp6ss";
		lpass_regmap_config.max_register = 0x3f;
		desc = &lpass_qdsp6ss_sc7280_desc;

		ret = qcom_cc_probe_by_index(pdev, 0, desc);
		if (ret)
			goto destroy_pm_clk;
	}

	lpass_regmap_config.name = "top_cc";
	lpass_regmap_config.max_register = 0x4;
	desc = &lpass_cc_top_sc7280_desc;

	ret = qcom_cc_probe_by_index(pdev, 1, desc);
	if (ret)
		goto destroy_pm_clk;

	return 0;

destroy_pm_clk:
	pm_clk_destroy(&pdev->dev);

	return ret;
}

static const struct of_device_id lpass_cc_sc7280_match_table[] = {
	{ .compatible = "qcom,sc7280-lpasscc" },
	{ }
};
MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);

static struct platform_driver lpass_cc_sc7280_driver = {
	.probe		= lpass_cc_sc7280_probe,
	.driver		= {
		.name	= "sc7280-lpasscc",
		.of_match_table = lpass_cc_sc7280_match_table,
	},
};

static int __init lpass_cc_sc7280_init(void)
{
	return platform_driver_register(&lpass_cc_sc7280_driver);
}
subsys_initcall(lpass_cc_sc7280_init);

static void __exit lpass_cc_sc7280_exit(void)
{
	platform_driver_unregister(&lpass_cc_sc7280_driver);
}
module_exit(lpass_cc_sc7280_exit);

MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4ab43d17 TD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2021, The Linux Foundation. All rights reserved.
	4	*/
	5
27f239a4	6	#include <linux/clk-provider.h>
4ab43d17 TD	7	#include <linux/platform_device.h>
	8	#include <linux/pm_clock.h>
	9	#include <linux/pm_runtime.h>
	10	#include <linux/module.h>
	11	#include <linux/of_address.h>
	12	#include <linux/regmap.h>
	13
	14	#include <dt-bindings/clock/qcom,lpass-sc7280.h>
	15
	16	#include "clk-regmap.h"
	17	#include "clk-branch.h"
	18	#include "common.h"
	19
4ab43d17 TD	20	static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
	21	.halt_reg = 0x0,
	22	.halt_check = BRANCH_HALT,
	23	.clkr = {
	24	.enable_reg = 0x0,
	25	.enable_mask = BIT(0),
	26	.hw.init = &(struct clk_init_data){
	27	.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
	28	.ops = &clk_branch2_ops,
	29	},
	30	},
	31	};
	32
	33	static struct clk_branch lpass_qdsp6ss_core_clk = {
	34	.halt_reg = 0x20,
	35	/* CLK_OFF would not toggle until LPASS is out of reset */
	36	.halt_check = BRANCH_HALT_SKIP,
	37	.clkr = {
	38	.enable_reg = 0x20,
	39	.enable_mask = BIT(0),
	40	.hw.init = &(struct clk_init_data){
	41	.name = "lpass_qdsp6ss_core_clk",
	42	.ops = &clk_branch2_ops,
	43	},
	44	},
	45	};
	46
	47	static struct clk_branch lpass_qdsp6ss_xo_clk = {
	48	.halt_reg = 0x38,
	49	/* CLK_OFF would not toggle until LPASS is out of reset */
	50	.halt_check = BRANCH_HALT_SKIP,
	51	.clkr = {
	52	.enable_reg = 0x38,
	53	.enable_mask = BIT(0),
	54	.hw.init = &(struct clk_init_data){
	55	.name = "lpass_qdsp6ss_xo_clk",
	56	.ops = &clk_branch2_ops,
	57	},
	58	},
	59	};
	60
	61	static struct clk_branch lpass_qdsp6ss_sleep_clk = {
	62	.halt_reg = 0x3c,
	63	/* CLK_OFF would not toggle until LPASS is out of reset */
	64	.halt_check = BRANCH_HALT_SKIP,
	65	.clkr = {
	66	.enable_reg = 0x3c,
	67	.enable_mask = BIT(0),
	68	.hw.init = &(struct clk_init_data){
	69	.name = "lpass_qdsp6ss_sleep_clk",
	70	.ops = &clk_branch2_ops,
	71	},
	72	},
	73	};
	74
	75	static struct regmap_config lpass_regmap_config = {
	76	.reg_bits = 32,
	77	.reg_stride = 4,
	78	.val_bits = 32,
	79	.fast_io = true,
	80	};
	81
4ab43d17 TD	82	static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
	83	[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
	84	&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
	85	};
	86
	87	static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
	88	.config = &lpass_regmap_config,
	89	.clks = lpass_cc_top_sc7280_clocks,
	90	.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
	91	};
	92
	93	static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
	94	[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
	95	[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
	96	[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
	97	};
	98
	99	static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
	100	.config = &lpass_regmap_config,
	101	.clks = lpass_qdsp6ss_sc7280_clocks,
	102	.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
	103	};
	104
	105	static int lpass_cc_sc7280_probe(struct platform_device *pdev)
	106	{
	107	const struct qcom_cc_desc *desc;
	108	int ret;
	109
f9048217 DB	110	ret = devm_pm_runtime_enable(&pdev->dev);
	111	if (ret)
	112	return ret;
	113
4ab43d17 TD	114	ret = pm_clk_create(&pdev->dev);
4ab43d17 TD	115	if (ret)
f9048217	116	return ret;
4ab43d17 TD	117
	118	ret = pm_clk_add(&pdev->dev, "iface");
	119	if (ret < 0) {
	120	dev_err(&pdev->dev, "failed to acquire iface clock\n");
	121	goto destroy_pm_clk;
	122	}
	123
4fc1c2d9 SRM	124	if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
	125	lpass_regmap_config.name = "qdsp6ss";
	126	lpass_regmap_config.max_register = 0x3f;
	127	desc = &lpass_qdsp6ss_sc7280_desc;
	128
	129	ret = qcom_cc_probe_by_index(pdev, 0, desc);
	130	if (ret)
	131	goto destroy_pm_clk;
	132	}
4ab43d17 TD	133
4ab43d17 TD	134	lpass_regmap_config.name = "top_cc";
4fc1c2d9	135	lpass_regmap_config.max_register = 0x4;
4ab43d17 TD	136	desc = &lpass_cc_top_sc7280_desc;
	137
	138	ret = qcom_cc_probe_by_index(pdev, 1, desc);
	139	if (ret)
	140	goto destroy_pm_clk;
	141
4ab43d17 TD	142	return 0;
	143
	144	destroy_pm_clk:
	145	pm_clk_destroy(&pdev->dev);
	146
4ab43d17 TD	147	return ret;
	148	}
	149
	150	static const struct of_device_id lpass_cc_sc7280_match_table[] = {
	151	{ .compatible = "qcom,sc7280-lpasscc" },
	152	{ }
	153	};
	154	MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
	155
	156	static struct platform_driver lpass_cc_sc7280_driver = {
	157	.probe = lpass_cc_sc7280_probe,
	158	.driver = {
	159	.name = "sc7280-lpasscc",
	160	.of_match_table = lpass_cc_sc7280_match_table,
	161	},
	162	};
	163
	164	static int __init lpass_cc_sc7280_init(void)
	165	{
	166	return platform_driver_register(&lpass_cc_sc7280_driver);
	167	}
	168	subsys_initcall(lpass_cc_sc7280_init);
	169
	170	static void __exit lpass_cc_sc7280_exit(void)
	171	{
	172	platform_driver_unregister(&lpass_cc_sc7280_driver);
	173	}
	174	module_exit(lpass_cc_sc7280_exit);
	175
	176	MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
	177	MODULE_LICENSE("GPL v2");