[linux-2.6-block.git] / drivers / clk / qcom / gdsc.h

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __QCOM_GDSC_H__
#define __QCOM_GDSC_H__

#include <linux/err.h>
#include <linux/pm_domain.h>

struct regmap;
struct reset_controller_dev;

/**
 * struct gdsc - Globally Distributed Switch Controller
 * @pd: generic power domain
 * @regmap: regmap for MMIO accesses
 * @gdscr: gsdc control register
 * @gds_hw_ctrl: gds_hw_ctrl register
 * @cxcs: offsets of branch registers to toggle mem/periph bits in
 * @cxc_count: number of @cxcs
 * @pwrsts: Possible powerdomain power states
 * @resets: ids of resets associated with this gdsc
 * @reset_count: number of @resets
 * @rcdev: reset controller
 */
struct gdsc {
	struct generic_pm_domain	pd;
	struct generic_pm_domain	*parent;
	struct regmap			*regmap;
	unsigned int			gdscr;
	unsigned int			gds_hw_ctrl;
	unsigned int			*cxcs;
	unsigned int			cxc_count;
	const u8			pwrsts;
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF		BIT(0)
#define PWRSTS_RET		BIT(1)
#define PWRSTS_ON		BIT(2)
#define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
#define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
	const u8			flags;
#define VOTABLE		BIT(0)
	struct reset_controller_dev	*rcdev;
	unsigned int			*resets;
	unsigned int			reset_count;
};

struct gdsc_desc {
	struct device *dev;
	struct gdsc **scs;
	size_t num;
};

#ifdef CONFIG_QCOM_GDSC
int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
		  struct regmap *);
void gdsc_unregister(struct gdsc_desc *desc);
#else
static inline int gdsc_register(struct gdsc_desc *desc,
				struct reset_controller_dev *rcdev,
				struct regmap *r)
{
	return -ENOSYS;
}

static inline void gdsc_unregister(struct gdsc_desc *desc) {};
#endif /* CONFIG_QCOM_GDSC */
#endif /* __QCOM_GDSC_H__ */
Commit	Line	Data
45dd0e55 SB	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#ifndef __QCOM_GDSC_H__
	15	#define __QCOM_GDSC_H__
	16
	17	#include <linux/err.h>
	18	#include <linux/pm_domain.h>
	19
	20	struct regmap;
3c53f5e2	21	struct reset_controller_dev;
45dd0e55 SB	22
	23	/**
	24	* struct gdsc - Globally Distributed Switch Controller
	25	* @pd: generic power domain
	26	* @regmap: regmap for MMIO accesses
	27	* @gdscr: gsdc control register
77b1067a	28	* @gds_hw_ctrl: gds_hw_ctrl register
014e193c RN	29	* @cxcs: offsets of branch registers to toggle mem/periph bits in
	30	* @cxc_count: number of @cxcs
	31	* @pwrsts: Possible powerdomain power states
3c53f5e2 RN	32	* @resets: ids of resets associated with this gdsc
	33	* @reset_count: number of @resets
	34	* @rcdev: reset controller
45dd0e55 SB	35	*/
	36	struct gdsc {
	37	struct generic_pm_domain pd;
c2c7f0a4	38	struct generic_pm_domain *parent;
45dd0e55 SB	39	struct regmap *regmap;
45dd0e55 SB	40	unsigned int gdscr;
77b1067a	41	unsigned int gds_hw_ctrl;
014e193c RN	42	unsigned int *cxcs;
	43	unsigned int cxc_count;
	44	const u8 pwrsts;
a823bb9f RN	45	/* Powerdomain allowable state bitfields */
	46	#define PWRSTS_OFF BIT(0)
	47	#define PWRSTS_RET BIT(1)
	48	#define PWRSTS_ON BIT(2)
	49	#define PWRSTS_OFF_ON (PWRSTS_OFF \| PWRSTS_ON)
	50	#define PWRSTS_RET_ON (PWRSTS_RET \| PWRSTS_ON)
	51	const u8 flags;
	52	#define VOTABLE BIT(0)
3c53f5e2 RN	53	struct reset_controller_dev *rcdev;
	54	unsigned int *resets;
	55	unsigned int reset_count;
45dd0e55 SB	56	};
45dd0e55 SB	57
c2c7f0a4 RN	58	struct gdsc_desc {
	59	struct device *dev;
	60	struct gdsc **scs;
	61	size_t num;
	62	};
	63
45dd0e55	64	#ifdef CONFIG_QCOM_GDSC
c2c7f0a4 RN	65	int gdsc_register(struct gdsc_desc desc, struct reset_controller_dev ,
	66	struct regmap *);
	67	void gdsc_unregister(struct gdsc_desc *desc);
45dd0e55	68	#else
c2c7f0a4	69	static inline int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	70	struct reset_controller_dev *rcdev,
45dd0e55 SB	71	struct regmap *r)
	72	{
	73	return -ENOSYS;
	74	}
	75
c2c7f0a4	76	static inline void gdsc_unregister(struct gdsc_desc *desc) {};
45dd0e55 SB	77	#endif /* CONFIG_QCOM_GDSC */
45dd0e55 SB	78	#endif /* __QCOM_GDSC_H__ */