[linux-block.git] / drivers / clk / qcom / gdsc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)
#define GMEM_CLAMP_IO_MASK	BIT(0)
#define GMEM_RESET_MASK		BIT(4)

/* CFG_GDSCR */
#define GDSC_POWER_UP_COMPLETE		BIT(16)
#define GDSC_POWER_DOWN_COMPLETE	BIT(15)
#define GDSC_RETAIN_FF_ENABLE		BIT(11)
#define CFG_GDSCR_OFFSET		0x4

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	0x2
#define EN_FEW_WAIT_VAL		0x8
#define CLK_DIS_WAIT_VAL	0x2

/* Transition delay shifts */
#define EN_REST_WAIT_SHIFT	20
#define EN_FEW_WAIT_SHIFT	16
#define CLK_DIS_WAIT_SHIFT	12

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define STATUS_POLL_TIMEOUT_US	2000
#define TIMEOUT_US		500

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

enum gdsc_status {
	GDSC_OFF,
	GDSC_ON
};

/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
{
	unsigned int reg;
	u32 val;
	int ret;

	if (sc->flags & POLL_CFG_GDSCR)
		reg = sc->gdscr + CFG_GDSCR_OFFSET;
	else if (sc->gds_hw_ctrl)
		reg = sc->gds_hw_ctrl;
	else
		reg = sc->gdscr;

	ret = regmap_read(sc->regmap, reg, &val);
	if (ret)
		return ret;

	if (sc->flags & POLL_CFG_GDSCR) {
		switch (status) {
		case GDSC_ON:
			return !!(val & GDSC_POWER_UP_COMPLETE);
		case GDSC_OFF:
			return !!(val & GDSC_POWER_DOWN_COMPLETE);
		}
	}

	switch (status) {
	case GDSC_ON:
		return !!(val & PWR_ON_MASK);
	case GDSC_OFF:
		return !(val & PWR_ON_MASK);
	}

	return -EINVAL;
}

static int gdsc_hwctrl(struct gdsc *sc, bool en)
{
	u32 val = en ? HW_CONTROL_MASK : 0;

	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}

static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
{
	ktime_t start;

	start = ktime_get();
	do {
		if (gdsc_check_status(sc, status))
			return 0;
	} while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);

	if (gdsc_check_status(sc, status))
		return 0;

	return -ETIMEDOUT;
}

static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
{
	u32 reg, mask;
	int ret;

	if (sc->collapse_mask) {
		reg = sc->collapse_ctrl;
		mask = sc->collapse_mask;
	} else {
		reg = sc->gdscr;
		mask = SW_COLLAPSE_MASK;
	}

	ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
	if (ret)
		return ret;

	return 0;
}

static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
		bool wait)
{
	int ret;

	if (status == GDSC_ON && sc->rsupply) {
		ret = regulator_enable(sc->rsupply);
		if (ret < 0)
			return ret;
	}

	ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);

	/* If disabling votable gdscs, don't poll on status */
	if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {
		/*
		 * Add a short delay here to ensure that an enable
		 * right after it was disabled does not put it in an
		 * unknown state
		 */
		udelay(TIMEOUT_US);
		return 0;
	}

	if (sc->gds_hw_ctrl) {
		/*
		 * The gds hw controller asserts/de-asserts the status bit soon
		 * after it receives a power on/off request from a master.
		 * The controller then takes around 8 xo cycles to start its
		 * internal state machine and update the status bit. During
		 * this time, the status bit does not reflect the true status
		 * of the core.
		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
		 * and polling the status bit.
		 */
		udelay(1);
	}

	ret = gdsc_poll_status(sc, status);
	WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");

	if (!ret && status == GDSC_OFF && sc->rsupply) {
		ret = regulator_disable(sc->rsupply);
		if (ret < 0)
			return ret;
	}

	return ret;
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM;

	if (!(sc->flags & NO_RET_PERIPH))
		mask |= RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM;

	if (!(sc->flags & NO_RET_PERIPH))
		mask |= RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 0);
}

static inline void gdsc_assert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 1);
}

static inline void gdsc_assert_reset_aon(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_RESET_MASK, 1);
	udelay(1);
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_RESET_MASK, 0);
}

static void gdsc_retain_ff_on(struct gdsc *sc)
{
	u32 mask = GDSC_RETAIN_FF_ENABLE;

	regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
}

static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	if (sc->flags & SW_RESET) {
		gdsc_assert_reset(sc);
		udelay(1);
		gdsc_deassert_reset(sc);
	}

	if (sc->flags & CLAMP_IO) {
		if (sc->flags & AON_RESET)
			gdsc_assert_reset_aon(sc);
		gdsc_deassert_clamp_io(sc);
	}

	ret = gdsc_toggle_logic(sc, GDSC_ON, false);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	if (sc->flags & RETAIN_FF_ENABLE)
		gdsc_retain_ff_on(sc);

	/* Turn on HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, true);
		if (ret)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case a firmware ends up polling status
		 * bits for the gdsc, it might read an 'on' status before
		 * the GDSC can finish the power cycle.
		 * We wait 1us before returning to ensure the firmware
		 * can't immediately poll the status bits.
		 */
		udelay(1);
	}

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	/* Turn off HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, false);
		if (ret < 0)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case we end up polling status
		 * bits for the gdsc before the power cycle is completed
		 * it might read an 'on' status wrongly.
		 */
		udelay(1);

		ret = gdsc_poll_status(sc, GDSC_ON);
		if (ret)
			return ret;
	}

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	/*
	 * If the GDSC supports only a Retention state, apart from ON,
	 * leave it in ON state.
	 * There is no SW control to transition the GDSC into
	 * Retention state. This happens in HW when the parent
	 * domain goes down to a Low power state
	 */
	if (sc->pwrsts == PWRSTS_RET_ON)
		return 0;

	ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);
	if (ret)
		return ret;

	if (sc->flags & CLAMP_IO)
		gdsc_assert_clamp_io(sc);

	return 0;
}

static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	ret = gdsc_hwctrl(sc, mode);
	if (ret)
		return ret;

	/*
	 * Wait for the GDSC to go through a power down and
	 * up cycle. If we poll the status register before the
	 * power cycle is finished we might read incorrect values.
	 */
	udelay(1);

	/*
	 * When the GDSC is switched to HW mode, HW can disable the GDSC.
	 * When the GDSC is switched back to SW mode, the GDSC will be enabled
	 * again, hence we need to poll for GDSC to complete the power up.
	 */
	if (!mode)
		return gdsc_poll_status(sc, GDSC_ON);

	return 0;
}

static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	u32 val;

	regmap_read(sc->regmap, sc->gdscr, &val);

	return !!(val & HW_CONTROL_MASK);
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;

	if (!sc->en_rest_wait_val)
		sc->en_rest_wait_val = EN_REST_WAIT_VAL;
	if (!sc->en_few_wait_val)
		sc->en_few_wait_val = EN_FEW_WAIT_VAL;
	if (!sc->clk_dis_wait_val)
		sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;

	val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
		sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
		sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, GDSC_ON, false);
		if (ret)
			return ret;
	}

	on = gdsc_check_status(sc, GDSC_ON);
	if (on < 0)
		return on;

	if (on) {
		/* The regulator must be on, sync the kernel state */
		if (sc->rsupply) {
			ret = regulator_enable(sc->rsupply);
			if (ret < 0)
				return ret;
		}

		/*
		 * Votable GDSCs can be ON due to Vote from other masters.
		 * If a Votable GDSC is ON, make sure we have a Vote.
		 */
		if (sc->flags & VOTABLE) {
			ret = gdsc_update_collapse_bit(sc, false);
			if (ret)
				goto err_disable_supply;
		}

		/*
		 * Make sure the retain bit is set if the GDSC is already on,
		 * otherwise we end up turning off the GDSC and destroying all
		 * the register contents that we thought we were saving.
		 */
		if (sc->flags & RETAIN_FF_ENABLE)
			gdsc_retain_ff_on(sc);

		/* Turn on HW trigger mode if supported */
		if (sc->flags & HW_CTRL) {
			ret = gdsc_hwctrl(sc, true);
			if (ret < 0)
				goto err_disable_supply;
		}

	} else if (sc->flags & ALWAYS_ON) {
		/* If ALWAYS_ON GDSCs are not ON, turn them ON */
		gdsc_enable(&sc->pd);
		on = true;
	}

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	if (sc->flags & ALWAYS_ON)
		sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
	if (!sc->pd.power_off)
		sc->pd.power_off = gdsc_disable;
	if (!sc->pd.power_on)
		sc->pd.power_on = gdsc_enable;
	if (sc->flags & HW_CTRL_TRIGGER) {
		sc->pd.set_hwmode_dev = gdsc_set_hwmode;
		sc->pd.get_hwmode_dev = gdsc_get_hwmode;
	}

	ret = pm_genpd_init(&sc->pd, NULL, !on);
	if (ret)
		goto err_disable_supply;

	return 0;

err_disable_supply:
	if (on && sc->rsupply)
		regulator_disable(sc->rsupply);

	return ret;
}

static int gdsc_add_subdomain_list(struct dev_pm_domain_list *pd_list,
				   struct generic_pm_domain *subdomain)
{
	int i, ret;

	for (i = 0; i < pd_list->num_pds; i++) {
		struct device *dev = pd_list->pd_devs[i];
		struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);

		ret = pm_genpd_add_subdomain(genpd, subdomain);
		if (ret)
			return ret;
	}

	return 0;
}

static void gdsc_remove_subdomain_list(struct dev_pm_domain_list *pd_list,
				       struct generic_pm_domain *subdomain)
{
	int i;

	for (i = 0; i < pd_list->num_pds; i++) {
		struct device *dev = pd_list->pd_devs[i];
		struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);

		pm_genpd_remove_subdomain(genpd, subdomain);
	}
}

static void gdsc_pm_subdomain_remove(struct gdsc_desc *desc, size_t num)
{
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	int i;

	/* Remove subdomains */
	for (i = num - 1; i >= 0; i--) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
		else if (!IS_ERR_OR_NULL(dev->pm_domain))
			pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
		else if (desc->pd_list)
			gdsc_remove_subdomain_list(desc->pd_list, &scs[i]->pd);
	}
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	for (i = 0; i < num; i++) {
		if (!scs[i] || !scs[i]->supply)
			continue;

		scs[i]->rsupply = devm_regulator_get_optional(dev, scs[i]->supply);
		if (IS_ERR(scs[i]->rsupply)) {
			ret = PTR_ERR(scs[i]->rsupply);
			if (ret != -ENODEV)
				return ret;

			scs[i]->rsupply = NULL;
		}
	}

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			ret = pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
		else if (!IS_ERR_OR_NULL(dev->pm_domain))
			ret = pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
		else if (desc->pd_list)
			ret = gdsc_add_subdomain_list(desc->pd_list, &scs[i]->pd);

		if (ret)
			goto err_pm_subdomain_remove;
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);

err_pm_subdomain_remove:
	gdsc_pm_subdomain_remove(desc, i);

	return ret;
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	struct device *dev = desc->dev;
	size_t num = desc->num;

	gdsc_pm_subdomain_remove(desc, num);
	of_genpd_del_provider(dev->of_node);
}

/*
 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
 * running in the CX domain so the CPU doesn't need to know anything about the
 * GX domain EXCEPT....
 *
 * Hardware constraints dictate that the GX be powered down before the CX. If
 * the GMU crashes it could leave the GX on. In order to successfully bring back
 * the device the CPU needs to disable the GX headswitch. There being no sane
 * way to reach in and touch that register from deep inside the GPU driver we
 * need to set up the infrastructure to be able to ensure that the GPU can
 * ensure that the GX is off during this super special case. We do this by
 * defining a GX gdsc with a dummy enable function and a "default" disable
 * function.
 *
 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
 * driver. During power up, nothing will happen from the CPU (and the GMU will
 * power up normally but during power down this will ensure that the GX domain
 * is *really* off - this gives us a semi standard way of doing what we need.
 */
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret = 0;

	/* Enable the parent supply, when controlled through the regulator framework. */
	if (sc->rsupply)
		ret = regulator_enable(sc->rsupply);

	/* Do nothing with the GDSC itself */

	return ret;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
45dd0e55	2	/*
4e7c4d36	3	* Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
45dd0e55 SB	4	*/
	5
	6	#include <linux/bitops.h>
	7	#include <linux/delay.h>
	8	#include <linux/err.h>
413d84b8	9	#include <linux/export.h>
45dd0e55 SB	10	#include <linux/jiffies.h>
45dd0e55 SB	11	#include <linux/kernel.h>
77b1067a	12	#include <linux/ktime.h>
45dd0e55 SB	13	#include <linux/pm_domain.h>
45dd0e55 SB	14	#include <linux/regmap.h>
37416e55	15	#include <linux/regulator/consumer.h>
3c53f5e2	16	#include <linux/reset-controller.h>
45dd0e55 SB	17	#include <linux/slab.h>
	18	#include "gdsc.h"
	19
	20	#define PWR_ON_MASK BIT(31)
	21	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	22	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	23	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	24	#define SW_OVERRIDE_MASK BIT(2)
	25	#define HW_CONTROL_MASK BIT(1)
	26	#define SW_COLLAPSE_MASK BIT(0)
e7cc455f	27	#define GMEM_CLAMP_IO_MASK BIT(0)
44dbeebf	28	#define GMEM_RESET_MASK BIT(4)
45dd0e55	29
e892e17d AN	30	/* CFG_GDSCR */
	31	#define GDSC_POWER_UP_COMPLETE BIT(16)
	32	#define GDSC_POWER_DOWN_COMPLETE BIT(15)
17372299	33	#define GDSC_RETAIN_FF_ENABLE BIT(11)
e892e17d	34	#define CFG_GDSCR_OFFSET 0x4
45dd0e55 SB	35
45dd0e55 SB	36	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
4e7c4d36 TD	37	#define EN_REST_WAIT_VAL 0x2
	38	#define EN_FEW_WAIT_VAL 0x8
	39	#define CLK_DIS_WAIT_VAL 0x2
	40
	41	/* Transition delay shifts */
	42	#define EN_REST_WAIT_SHIFT 20
	43	#define EN_FEW_WAIT_SHIFT 16
	44	#define CLK_DIS_WAIT_SHIFT 12
45dd0e55	45
014e193c RN	46	#define RETAIN_MEM BIT(14)
	47	#define RETAIN_PERIPH BIT(13)
	48
172320f5	49	#define STATUS_POLL_TIMEOUT_US 2000
9fb38cae	50	#define TIMEOUT_US 500
45dd0e55 SB	51
	52	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	53
88051f55 SB	54	enum gdsc_status {
	55	GDSC_OFF,
	56	GDSC_ON
	57	};
	58
	59	/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
	60	static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
45dd0e55	61	{
e892e17d	62	unsigned int reg;
45dd0e55 SB	63	u32 val;
	64	int ret;
	65
e892e17d AN	66	if (sc->flags & POLL_CFG_GDSCR)
e892e17d AN	67	reg = sc->gdscr + CFG_GDSCR_OFFSET;
88051f55 SB	68	else if (sc->gds_hw_ctrl)
88051f55 SB	69	reg = sc->gds_hw_ctrl;
e892e17d	70	else
88051f55	71	reg = sc->gdscr;
e892e17d	72
77b1067a	73	ret = regmap_read(sc->regmap, reg, &val);
45dd0e55 SB	74	if (ret)
	75	return ret;
	76
e892e17d	77	if (sc->flags & POLL_CFG_GDSCR) {
88051f55 SB	78	switch (status) {
88051f55 SB	79	case GDSC_ON:
e892e17d	80	return !!(val & GDSC_POWER_UP_COMPLETE);
88051f55 SB	81	case GDSC_OFF:
	82	return !!(val & GDSC_POWER_DOWN_COMPLETE);
	83	}
	84	}
	85
	86	switch (status) {
	87	case GDSC_ON:
	88	return !!(val & PWR_ON_MASK);
	89	case GDSC_OFF:
	90	return !(val & PWR_ON_MASK);
e892e17d AN	91	}
e892e17d AN	92
88051f55	93	return -EINVAL;
45dd0e55 SB	94	}
45dd0e55 SB	95
904bb4f5 RN	96	static int gdsc_hwctrl(struct gdsc *sc, bool en)
	97	{
	98	u32 val = en ? HW_CONTROL_MASK : 0;
	99
	100	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
	101	}
	102
88051f55	103	static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
843be1e7 RN	104	{
	105	ktime_t start;
	106
	107	start = ktime_get();
	108	do {
88051f55	109	if (gdsc_check_status(sc, status))
843be1e7	110	return 0;
7364379d	111	} while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);
843be1e7	112
88051f55	113	if (gdsc_check_status(sc, status))
843be1e7 RN	114	return 0;
	115
	116	return -ETIMEDOUT;
	117	}
	118
e73cb852 JH	119	static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
	120	{
	121	u32 reg, mask;
	122	int ret;
	123
77ea2bd7 JH	124	if (sc->collapse_mask) {
	125	reg = sc->collapse_ctrl;
	126	mask = sc->collapse_mask;
	127	} else {
	128	reg = sc->gdscr;
	129	mask = SW_COLLAPSE_MASK;
	130	}
e73cb852 JH	131
	132	ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
	133	if (ret)
	134	return ret;
	135
	136	return 0;
	137	}
	138
8b6af3b5 AO	139	static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
8b6af3b5 AO	140	bool wait)
45dd0e55 SB	141	{
45dd0e55 SB	142	int ret;
45dd0e55	143
37416e55 BA	144	if (status == GDSC_ON && sc->rsupply) {
	145	ret = regulator_enable(sc->rsupply);
	146	if (ret < 0)
	147	return ret;
	148	}
	149
e73cb852	150	ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
45dd0e55	151
a823bb9f	152	/* If disabling votable gdscs, don't poll on status */
8b6af3b5	153	if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {
a823bb9f RN	154	/*
	155	* Add a short delay here to ensure that an enable
	156	* right after it was disabled does not put it in an
	157	* unknown state
	158	*/
	159	udelay(TIMEOUT_US);
	160	return 0;
	161	}
	162
77b1067a	163	if (sc->gds_hw_ctrl) {
77b1067a RN	164	/*
	165	* The gds hw controller asserts/de-asserts the status bit soon
	166	* after it receives a power on/off request from a master.
	167	* The controller then takes around 8 xo cycles to start its
	168	* internal state machine and update the status bit. During
	169	* this time, the status bit does not reflect the true status
	170	* of the core.
	171	* Add a delay of 1 us between writing to the SW_COLLAPSE bit
	172	* and polling the status bit.
	173	*/
	174	udelay(1);
	175	}
45dd0e55	176
f02fba3a BA	177	ret = gdsc_poll_status(sc, status);
f02fba3a BA	178	WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
37416e55 BA	179
	180	if (!ret && status == GDSC_OFF && sc->rsupply) {
	181	ret = regulator_disable(sc->rsupply);
	182	if (ret < 0)
	183	return ret;
	184	}
	185
f02fba3a	186	return ret;
45dd0e55 SB	187	}
45dd0e55 SB	188
3c53f5e2 RN	189	static inline int gdsc_deassert_reset(struct gdsc *sc)
	190	{
	191	int i;
	192
	193	for (i = 0; i < sc->reset_count; i++)
	194	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	195	return 0;
	196	}
	197
	198	static inline int gdsc_assert_reset(struct gdsc *sc)
	199	{
	200	int i;
	201
	202	for (i = 0; i < sc->reset_count; i++)
	203	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	204	return 0;
	205	}
	206
014e193c RN	207	static inline void gdsc_force_mem_on(struct gdsc *sc)
	208	{
	209	int i;
785c02eb ADR	210	u32 mask = RETAIN_MEM;
	211
	212	if (!(sc->flags & NO_RET_PERIPH))
	213	mask \|= RETAIN_PERIPH;
014e193c RN	214
	215	for (i = 0; i < sc->cxc_count; i++)
	216	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	217	}
	218
	219	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	220	{
	221	int i;
785c02eb ADR	222	u32 mask = RETAIN_MEM;
	223
	224	if (!(sc->flags & NO_RET_PERIPH))
	225	mask \|= RETAIN_PERIPH;
014e193c RN	226
	227	for (i = 0; i < sc->cxc_count; i++)
	228	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	229	}
	230
e7cc455f RN	231	static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
	232	{
	233	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	234	GMEM_CLAMP_IO_MASK, 0);
	235	}
	236
	237	static inline void gdsc_assert_clamp_io(struct gdsc *sc)
	238	{
	239	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	240	GMEM_CLAMP_IO_MASK, 1);
	241	}
	242
44dbeebf AN	243	static inline void gdsc_assert_reset_aon(struct gdsc *sc)
	244	{
	245	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	246	GMEM_RESET_MASK, 1);
	247	udelay(1);
	248	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	249	GMEM_RESET_MASK, 0);
	250	}
17372299 TD	251
	252	static void gdsc_retain_ff_on(struct gdsc *sc)
	253	{
	254	u32 mask = GDSC_RETAIN_FF_ENABLE;
	255
	256	regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
	257	}
	258
4cc47e8a	259	static int gdsc_enable(struct generic_pm_domain *domain)
45dd0e55	260	{
4cc47e8a	261	struct gdsc *sc = domain_to_gdsc(domain);
45dd0e55 SB	262	int ret;
45dd0e55 SB	263
3c53f5e2 RN	264	if (sc->pwrsts == PWRSTS_ON)
	265	return gdsc_deassert_reset(sc);
	266
44dbeebf AN	267	if (sc->flags & SW_RESET) {
	268	gdsc_assert_reset(sc);
	269	udelay(1);
	270	gdsc_deassert_reset(sc);
	271	}
	272
	273	if (sc->flags & CLAMP_IO) {
	274	if (sc->flags & AON_RESET)
	275	gdsc_assert_reset_aon(sc);
e7cc455f	276	gdsc_deassert_clamp_io(sc);
44dbeebf	277	}
e7cc455f	278
8b6af3b5	279	ret = gdsc_toggle_logic(sc, GDSC_ON, false);
45dd0e55 SB	280	if (ret)
45dd0e55 SB	281	return ret;
014e193c RN	282
	283	if (sc->pwrsts & PWRSTS_OFF)
	284	gdsc_force_mem_on(sc);
	285
45dd0e55 SB	286	/*
	287	* If clocks to this power domain were already on, they will take an
	288	* additional 4 clock cycles to re-enable after the power domain is
	289	* enabled. Delay to account for this. A delay is also needed to ensure
	290	* clocks are not enabled within 400ns of enabling power to the
	291	* memories.
	292	*/
	293	udelay(1);
	294
25708f73 TD	295	if (sc->flags & RETAIN_FF_ENABLE)
	296	gdsc_retain_ff_on(sc);
	297
904bb4f5	298	/* Turn on HW trigger mode if supported */
843be1e7 RN	299	if (sc->flags & HW_CTRL) {
	300	ret = gdsc_hwctrl(sc, true);
	301	if (ret)
	302	return ret;
	303	/*
	304	* Wait for the GDSC to go through a power down and
	305	* up cycle. In case a firmware ends up polling status
	306	* bits for the gdsc, it might read an 'on' status before
	307	* the GDSC can finish the power cycle.
	308	* We wait 1us before returning to ensure the firmware
	309	* can't immediately poll the status bits.
	310	*/
	311	udelay(1);
	312	}
904bb4f5	313
45dd0e55 SB	314	return 0;
	315	}
	316
4cc47e8a	317	static int gdsc_disable(struct generic_pm_domain *domain)
45dd0e55 SB	318	{
45dd0e55 SB	319	struct gdsc *sc = domain_to_gdsc(domain);
e7cc455f	320	int ret;
45dd0e55	321
3c53f5e2 RN	322	if (sc->pwrsts == PWRSTS_ON)
	323	return gdsc_assert_reset(sc);
	324
904bb4f5 RN	325	/* Turn off HW trigger mode if supported */
	326	if (sc->flags & HW_CTRL) {
	327	ret = gdsc_hwctrl(sc, false);
	328	if (ret < 0)
	329	return ret;
843be1e7 RN	330	/*
	331	* Wait for the GDSC to go through a power down and
	332	* up cycle. In case we end up polling status
	333	* bits for the gdsc before the power cycle is completed
	334	* it might read an 'on' status wrongly.
	335	*/
	336	udelay(1);
	337
88051f55	338	ret = gdsc_poll_status(sc, GDSC_ON);
843be1e7 RN	339	if (ret)
843be1e7 RN	340	return ret;
904bb4f5 RN	341	}
904bb4f5 RN	342
014e193c RN	343	if (sc->pwrsts & PWRSTS_OFF)
	344	gdsc_clear_mem_on(sc);
	345
d3997239 RN	346	/*
	347	* If the GDSC supports only a Retention state, apart from ON,
	348	* leave it in ON state.
	349	* There is no SW control to transition the GDSC into
	350	* Retention state. This happens in HW when the parent
	351	* domain goes down to a Low power state
	352	*/
	353	if (sc->pwrsts == PWRSTS_RET_ON)
	354	return 0;
	355
8b6af3b5	356	ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);
e7cc455f RN	357	if (ret)
	358	return ret;
	359
	360	if (sc->flags & CLAMP_IO)
	361	gdsc_assert_clamp_io(sc);
	362
	363	return 0;
45dd0e55 SB	364	}
45dd0e55 SB	365
f7ccdaad JK	366	static int gdsc_set_hwmode(struct generic_pm_domain domain, struct device dev, bool mode)
	367	{
	368	struct gdsc *sc = domain_to_gdsc(domain);
	369	int ret;
	370
	371	ret = gdsc_hwctrl(sc, mode);
	372	if (ret)
	373	return ret;
	374
	375	/*
	376	* Wait for the GDSC to go through a power down and
	377	* up cycle. If we poll the status register before the
	378	* power cycle is finished we might read incorrect values.
	379	*/
	380	udelay(1);
	381
	382	/*
	383	* When the GDSC is switched to HW mode, HW can disable the GDSC.
	384	* When the GDSC is switched back to SW mode, the GDSC will be enabled
	385	* again, hence we need to poll for GDSC to complete the power up.
	386	*/
	387	if (!mode)
	388	return gdsc_poll_status(sc, GDSC_ON);
	389
	390	return 0;
	391	}
	392
	393	static bool gdsc_get_hwmode(struct generic_pm_domain domain, struct device dev)
	394	{
	395	struct gdsc *sc = domain_to_gdsc(domain);
	396	u32 val;
	397
	398	regmap_read(sc->regmap, sc->gdscr, &val);
	399
	400	return !!(val & HW_CONTROL_MASK);
	401	}
	402
45dd0e55 SB	403	static int gdsc_init(struct gdsc *sc)
	404	{
	405	u32 mask, val;
	406	int on, ret;
	407
	408	/*
	409	* Disable HW trigger: collapse/restore occur based on registers writes.
	410	* Disable SW override: Use hardware state-machine for sequencing.
	411	* Configure wait time between states.
	412	*/
	413	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	414	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
4e7c4d36 TD	415
	416	if (!sc->en_rest_wait_val)
	417	sc->en_rest_wait_val = EN_REST_WAIT_VAL;
	418	if (!sc->en_few_wait_val)
	419	sc->en_few_wait_val = EN_FEW_WAIT_VAL;
	420	if (!sc->clk_dis_wait_val)
	421	sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
	422
	423	val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT \|
	424	sc->en_few_wait_val << EN_FEW_WAIT_SHIFT \|
	425	sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
	426
45dd0e55 SB	427	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	428	if (ret)
	429	return ret;
	430
3c53f5e2 RN	431	/* Force gdsc ON if only ON state is supported */
3c53f5e2 RN	432	if (sc->pwrsts == PWRSTS_ON) {
8b6af3b5	433	ret = gdsc_toggle_logic(sc, GDSC_ON, false);
3c53f5e2 RN	434	if (ret)
	435	return ret;
	436	}
	437
88051f55	438	on = gdsc_check_status(sc, GDSC_ON);
45dd0e55 SB	439	if (on < 0)
	440	return on;
	441
9711759a BA	442	if (on) {
	443	/* The regulator must be on, sync the kernel state */
	444	if (sc->rsupply) {
	445	ret = regulator_enable(sc->rsupply);
	446	if (ret < 0)
	447	return ret;
	448	}
a823bb9f	449
9711759a BA	450	/*
	451	* Votable GDSCs can be ON due to Vote from other masters.
	452	* If a Votable GDSC is ON, make sure we have a Vote.
	453	*/
	454	if (sc->flags & VOTABLE) {
e73cb852	455	ret = gdsc_update_collapse_bit(sc, false);
9711759a	456	if (ret)
4cc47e8a	457	goto err_disable_supply;
9711759a BA	458	}
9711759a BA	459
9711759a BA	460	/*
	461	* Make sure the retain bit is set if the GDSC is already on,
	462	* otherwise we end up turning off the GDSC and destroying all
	463	* the register contents that we thought we were saving.
	464	*/
	465	if (sc->flags & RETAIN_FF_ENABLE)
	466	gdsc_retain_ff_on(sc);
25708f73 TD	467
	468	/* Turn on HW trigger mode if supported */
	469	if (sc->flags & HW_CTRL) {
	470	ret = gdsc_hwctrl(sc, true);
	471	if (ret < 0)
	472	goto err_disable_supply;
	473	}
	474
9711759a BA	475	} else if (sc->flags & ALWAYS_ON) {
	476	/* If ALWAYS_ON GDSCs are not ON, turn them ON */
	477	gdsc_enable(&sc->pd);
fb55bea1	478	on = true;
fb55bea1 RN	479	}
fb55bea1 RN	480
014e193c RN	481	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	482	gdsc_force_mem_on(sc);
	483	else
	484	gdsc_clear_mem_on(sc);
	485
9711759a BA	486	if (sc->flags & ALWAYS_ON)
9711759a BA	487	sc->pd.flags \|= GENPD_FLAG_ALWAYS_ON;
7895861a JC	488	if (!sc->pd.power_off)
	489	sc->pd.power_off = gdsc_disable;
	490	if (!sc->pd.power_on)
	491	sc->pd.power_on = gdsc_enable;
f7ccdaad JK	492	if (sc->flags & HW_CTRL_TRIGGER) {
	493	sc->pd.set_hwmode_dev = gdsc_set_hwmode;
	494	sc->pd.get_hwmode_dev = gdsc_get_hwmode;
	495	}
eab4c1eb JH	496
	497	ret = pm_genpd_init(&sc->pd, NULL, !on);
	498	if (ret)
4cc47e8a	499	goto err_disable_supply;
45dd0e55 SB	500
45dd0e55 SB	501	return 0;
eab4c1eb	502
eab4c1eb JH	503	err_disable_supply:
	504	if (on && sc->rsupply)
	505	regulator_disable(sc->rsupply);
	506
	507	return ret;
45dd0e55 SB	508	}
45dd0e55 SB	509
b489235b BD	510	static int gdsc_add_subdomain_list(struct dev_pm_domain_list *pd_list,
	511	struct generic_pm_domain *subdomain)
	512	{
	513	int i, ret;
	514
	515	for (i = 0; i < pd_list->num_pds; i++) {
	516	struct device *dev = pd_list->pd_devs[i];
	517	struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
	518
	519	ret = pm_genpd_add_subdomain(genpd, subdomain);
	520	if (ret)
	521	return ret;
	522	}
	523
	524	return 0;
	525	}
	526
	527	static void gdsc_remove_subdomain_list(struct dev_pm_domain_list *pd_list,
	528	struct generic_pm_domain *subdomain)
	529	{
	530	int i;
	531
	532	for (i = 0; i < pd_list->num_pds; i++) {
	533	struct device *dev = pd_list->pd_devs[i];
	534	struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
	535
	536	pm_genpd_remove_subdomain(genpd, subdomain);
	537	}
	538	}
	539
65a73346 BD	540	static void gdsc_pm_subdomain_remove(struct gdsc_desc *desc, size_t num)
	541	{
	542	struct device *dev = desc->dev;
	543	struct gdsc **scs = desc->scs;
	544	int i;
	545
	546	/* Remove subdomains */
	547	for (i = num - 1; i >= 0; i--) {
	548	if (!scs[i])
	549	continue;
	550	if (scs[i]->parent)
	551	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	552	else if (!IS_ERR_OR_NULL(dev->pm_domain))
	553	pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
b489235b BD	554	else if (desc->pd_list)
b489235b BD	555	gdsc_remove_subdomain_list(desc->pd_list, &scs[i]->pd);
65a73346 BD	556	}
	557	}
	558
c2c7f0a4	559	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	560	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	561	{
	562	int i, ret;
	563	struct genpd_onecell_data *data;
c2c7f0a4 RN	564	struct device *dev = desc->dev;
	565	struct gdsc **scs = desc->scs;
	566	size_t num = desc->num;
45dd0e55 SB	567
	568	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	569	if (!data)
	570	return -ENOMEM;
	571
	572	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	573	GFP_KERNEL);
	574	if (!data->domains)
	575	return -ENOMEM;
	576
37416e55 BA	577	for (i = 0; i < num; i++) {
	578	if (!scs[i] \|\| !scs[i]->supply)
	579	continue;
	580
6677196f JH	581	scs[i]->rsupply = devm_regulator_get_optional(dev, scs[i]->supply);
	582	if (IS_ERR(scs[i]->rsupply)) {
	583	ret = PTR_ERR(scs[i]->rsupply);
	584	if (ret != -ENODEV)
	585	return ret;
	586
	587	scs[i]->rsupply = NULL;
	588	}
37416e55 BA	589	}
37416e55 BA	590
45dd0e55 SB	591	data->num_domains = num;
	592	for (i = 0; i < num; i++) {
	593	if (!scs[i])
	594	continue;
	595	scs[i]->regmap = regmap;
3c53f5e2	596	scs[i]->rcdev = rcdev;
45dd0e55 SB	597	ret = gdsc_init(scs[i]);
	598	if (ret)
	599	return ret;
	600	data->domains[i] = &scs[i]->pd;
	601	}
	602
c2c7f0a4 RN	603	/* Add subdomains */
	604	for (i = 0; i < num; i++) {
	605	if (!scs[i])
	606	continue;
	607	if (scs[i]->parent)
65a73346	608	ret = pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
1b771839	609	else if (!IS_ERR_OR_NULL(dev->pm_domain))
65a73346	610	ret = pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
b489235b BD	611	else if (desc->pd_list)
	612	ret = gdsc_add_subdomain_list(desc->pd_list, &scs[i]->pd);
	613
65a73346 BD	614	if (ret)
65a73346 BD	615	goto err_pm_subdomain_remove;
c2c7f0a4 RN	616	}
c2c7f0a4 RN	617
45dd0e55	618	return of_genpd_add_provider_onecell(dev->of_node, data);
65a73346 BD	619
	620	err_pm_subdomain_remove:
	621	gdsc_pm_subdomain_remove(desc, i);
	622
	623	return ret;
45dd0e55 SB	624	}
45dd0e55 SB	625
c2c7f0a4	626	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	627	{
c2c7f0a4	628	struct device *dev = desc->dev;
c2c7f0a4 RN	629	size_t num = desc->num;
c2c7f0a4 RN	630
65a73346	631	gdsc_pm_subdomain_remove(desc, num);
45dd0e55 SB	632	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	633	}
0638226d JM	634
	635	/*
	636	* On SDM845+ the GPU GX domain is almost entirely controlled by the GMU
	637	* running in the CX domain so the CPU doesn't need to know anything about the
	638	* GX domain EXCEPT....
	639	*
	640	* Hardware constraints dictate that the GX be powered down before the CX. If
	641	* the GMU crashes it could leave the GX on. In order to successfully bring back
	642	* the device the CPU needs to disable the GX headswitch. There being no sane
	643	* way to reach in and touch that register from deep inside the GPU driver we
	644	* need to set up the infrastructure to be able to ensure that the GPU can
	645	* ensure that the GX is off during this super special case. We do this by
	646	* defining a GX gdsc with a dummy enable function and a "default" disable
	647	* function.
	648	*
	649	* This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
	650	* driver. During power up, nothing will happen from the CPU (and the GMU will
	651	* power up normally but during power down this will ensure that the GX domain
	652	* is really off - this gives us a semi standard way of doing what we need.
	653	*/
	654	int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
	655	{
9187ebb9 BA	656	struct gdsc *sc = domain_to_gdsc(domain);
	657	int ret = 0;
	658
	659	/* Enable the parent supply, when controlled through the regulator framework. */
	660	if (sc->rsupply)
	661	ret = regulator_enable(sc->rsupply);
	662
	663	/* Do nothing with the GDSC itself */
	664
	665	return ret;
0638226d	666	}
413d84b8	667	EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);