[linux-2.6-block.git] / drivers / clk / qcom / gdsc.c

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	(0x2 << 20)
#define EN_FEW_WAIT_VAL		(0x8 << 16)
#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define TIMEOUT_US		100

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

static int gdsc_is_enabled(struct gdsc *sc)
{
	u32 val;
	int ret;

	ret = regmap_read(sc->regmap, sc->gdscr, &val);
	if (ret)
		return ret;

	return !!(val & PWR_ON_MASK);
}

static int gdsc_toggle_logic(struct gdsc *sc, bool en)
{
	int ret;
	u32 val = en ? 0 : SW_COLLAPSE_MASK;
	u32 check = en ? PWR_ON_MASK : 0;
	unsigned long timeout;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	if (ret)
		return ret;

	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
	do {
		ret = regmap_read(sc->regmap, sc->gdscr, &val);
		if (ret)
			return ret;

		if ((val & PWR_ON_MASK) == check)
			return 0;
	} while (time_before(jiffies, timeout));

	ret = regmap_read(sc->regmap, sc->gdscr, &val);
	if (ret)
		return ret;

	if ((val & PWR_ON_MASK) == check)
		return 0;

	return -ETIMEDOUT;
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	ret = gdsc_toggle_logic(sc, true);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	return gdsc_toggle_logic(sc, false);
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, true);
		if (ret)
			return ret;
	}

	on = gdsc_is_enabled(sc);
	if (on < 0)
		return on;

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	sc->pd.power_off = gdsc_disable;
	sc->pd.power_on = gdsc_enable;
	pm_genpd_init(&sc->pd, NULL, !on);

	return 0;
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	int i;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	/* Remove subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	}
	of_genpd_del_provider(dev->of_node);
}
Commit	Line	Data
45dd0e55 SB	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/kernel.h>
	19	#include <linux/pm_domain.h>
	20	#include <linux/regmap.h>
3c53f5e2	21	#include <linux/reset-controller.h>
45dd0e55 SB	22	#include <linux/slab.h>
	23	#include "gdsc.h"
	24
	25	#define PWR_ON_MASK BIT(31)
	26	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	27	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	28	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	29	#define SW_OVERRIDE_MASK BIT(2)
	30	#define HW_CONTROL_MASK BIT(1)
	31	#define SW_COLLAPSE_MASK BIT(0)
	32
	33	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
	34	#define EN_REST_WAIT_VAL (0x2 << 20)
	35	#define EN_FEW_WAIT_VAL (0x8 << 16)
	36	#define CLK_DIS_WAIT_VAL (0x2 << 12)
	37
014e193c RN	38	#define RETAIN_MEM BIT(14)
	39	#define RETAIN_PERIPH BIT(13)
	40
45dd0e55 SB	41	#define TIMEOUT_US 100
	42
	43	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	44
	45	static int gdsc_is_enabled(struct gdsc *sc)
	46	{
	47	u32 val;
	48	int ret;
	49
	50	ret = regmap_read(sc->regmap, sc->gdscr, &val);
	51	if (ret)
	52	return ret;
	53
	54	return !!(val & PWR_ON_MASK);
	55	}
	56
	57	static int gdsc_toggle_logic(struct gdsc *sc, bool en)
	58	{
	59	int ret;
	60	u32 val = en ? 0 : SW_COLLAPSE_MASK;
	61	u32 check = en ? PWR_ON_MASK : 0;
	62	unsigned long timeout;
	63
	64	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	65	if (ret)
	66	return ret;
	67
	68	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
	69	do {
	70	ret = regmap_read(sc->regmap, sc->gdscr, &val);
	71	if (ret)
	72	return ret;
	73
	74	if ((val & PWR_ON_MASK) == check)
	75	return 0;
	76	} while (time_before(jiffies, timeout));
	77
	78	ret = regmap_read(sc->regmap, sc->gdscr, &val);
	79	if (ret)
	80	return ret;
	81
	82	if ((val & PWR_ON_MASK) == check)
	83	return 0;
	84
	85	return -ETIMEDOUT;
	86	}
	87
3c53f5e2 RN	88	static inline int gdsc_deassert_reset(struct gdsc *sc)
	89	{
	90	int i;
	91
	92	for (i = 0; i < sc->reset_count; i++)
	93	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	94	return 0;
	95	}
	96
	97	static inline int gdsc_assert_reset(struct gdsc *sc)
	98	{
	99	int i;
	100
	101	for (i = 0; i < sc->reset_count; i++)
	102	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	103	return 0;
	104	}
	105
014e193c RN	106	static inline void gdsc_force_mem_on(struct gdsc *sc)
	107	{
	108	int i;
	109	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	110
	111	for (i = 0; i < sc->cxc_count; i++)
	112	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	113	}
	114
	115	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	116	{
	117	int i;
	118	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	119
	120	for (i = 0; i < sc->cxc_count; i++)
	121	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	122	}
	123
45dd0e55 SB	124	static int gdsc_enable(struct generic_pm_domain *domain)
	125	{
	126	struct gdsc *sc = domain_to_gdsc(domain);
	127	int ret;
	128
3c53f5e2 RN	129	if (sc->pwrsts == PWRSTS_ON)
	130	return gdsc_deassert_reset(sc);
	131
45dd0e55 SB	132	ret = gdsc_toggle_logic(sc, true);
	133	if (ret)
	134	return ret;
014e193c RN	135
	136	if (sc->pwrsts & PWRSTS_OFF)
	137	gdsc_force_mem_on(sc);
	138
45dd0e55 SB	139	/*
	140	* If clocks to this power domain were already on, they will take an
	141	* additional 4 clock cycles to re-enable after the power domain is
	142	* enabled. Delay to account for this. A delay is also needed to ensure
	143	* clocks are not enabled within 400ns of enabling power to the
	144	* memories.
	145	*/
	146	udelay(1);
	147
	148	return 0;
	149	}
	150
	151	static int gdsc_disable(struct generic_pm_domain *domain)
	152	{
	153	struct gdsc *sc = domain_to_gdsc(domain);
	154
3c53f5e2 RN	155	if (sc->pwrsts == PWRSTS_ON)
	156	return gdsc_assert_reset(sc);
	157
014e193c RN	158	if (sc->pwrsts & PWRSTS_OFF)
	159	gdsc_clear_mem_on(sc);
	160
45dd0e55 SB	161	return gdsc_toggle_logic(sc, false);
	162	}
	163
	164	static int gdsc_init(struct gdsc *sc)
	165	{
	166	u32 mask, val;
	167	int on, ret;
	168
	169	/*
	170	* Disable HW trigger: collapse/restore occur based on registers writes.
	171	* Disable SW override: Use hardware state-machine for sequencing.
	172	* Configure wait time between states.
	173	*/
	174	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	175	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
	176	val = EN_REST_WAIT_VAL \| EN_FEW_WAIT_VAL \| CLK_DIS_WAIT_VAL;
	177	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	178	if (ret)
	179	return ret;
	180
3c53f5e2 RN	181	/* Force gdsc ON if only ON state is supported */
	182	if (sc->pwrsts == PWRSTS_ON) {
	183	ret = gdsc_toggle_logic(sc, true);
	184	if (ret)
	185	return ret;
	186	}
	187
45dd0e55 SB	188	on = gdsc_is_enabled(sc);
	189	if (on < 0)
	190	return on;
	191
014e193c RN	192	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	193	gdsc_force_mem_on(sc);
	194	else
	195	gdsc_clear_mem_on(sc);
	196
45dd0e55 SB	197	sc->pd.power_off = gdsc_disable;
	198	sc->pd.power_on = gdsc_enable;
	199	pm_genpd_init(&sc->pd, NULL, !on);
	200
	201	return 0;
	202	}
	203
c2c7f0a4	204	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	205	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	206	{
	207	int i, ret;
	208	struct genpd_onecell_data *data;
c2c7f0a4 RN	209	struct device *dev = desc->dev;
	210	struct gdsc **scs = desc->scs;
	211	size_t num = desc->num;
45dd0e55 SB	212
	213	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	214	if (!data)
	215	return -ENOMEM;
	216
	217	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	218	GFP_KERNEL);
	219	if (!data->domains)
	220	return -ENOMEM;
	221
	222	data->num_domains = num;
	223	for (i = 0; i < num; i++) {
	224	if (!scs[i])
	225	continue;
	226	scs[i]->regmap = regmap;
3c53f5e2	227	scs[i]->rcdev = rcdev;
45dd0e55 SB	228	ret = gdsc_init(scs[i]);
	229	if (ret)
	230	return ret;
	231	data->domains[i] = &scs[i]->pd;
	232	}
	233
c2c7f0a4 RN	234	/* Add subdomains */
	235	for (i = 0; i < num; i++) {
	236	if (!scs[i])
	237	continue;
	238	if (scs[i]->parent)
	239	pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	240	}
	241
45dd0e55 SB	242	return of_genpd_add_provider_onecell(dev->of_node, data);
	243	}
	244
c2c7f0a4	245	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	246	{
c2c7f0a4 RN	247	int i;
	248	struct device *dev = desc->dev;
	249	struct gdsc **scs = desc->scs;
	250	size_t num = desc->num;
	251
	252	/* Remove subdomains */
	253	for (i = 0; i < num; i++) {
	254	if (!scs[i])
	255	continue;
	256	if (scs[i]->parent)
	257	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	258	}
45dd0e55 SB	259	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	260	}