[linux-block.git] / drivers / clk / qcom / gdsc.c

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	(0x2 << 20)
#define EN_FEW_WAIT_VAL		(0x8 << 16)
#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define TIMEOUT_US		100

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
{
	u32 val;
	int ret;

	ret = regmap_read(sc->regmap, reg, &val);
	if (ret)
		return ret;

	return !!(val & PWR_ON_MASK);
}

static int gdsc_toggle_logic(struct gdsc *sc, bool en)
{
	int ret;
	u32 val = en ? 0 : SW_COLLAPSE_MASK;
	ktime_t start;
	unsigned int status_reg = sc->gdscr;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	if (ret)
		return ret;

	if (sc->gds_hw_ctrl) {
		status_reg = sc->gds_hw_ctrl;
		/*
		 * The gds hw controller asserts/de-asserts the status bit soon
		 * after it receives a power on/off request from a master.
		 * The controller then takes around 8 xo cycles to start its
		 * internal state machine and update the status bit. During
		 * this time, the status bit does not reflect the true status
		 * of the core.
		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
		 * and polling the status bit.
		 */
		udelay(1);
	}

	start = ktime_get();
	do {
		if (gdsc_is_enabled(sc, status_reg) == en)
			return 0;
	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

	if (gdsc_is_enabled(sc, status_reg) == en)
		return 0;

	return -ETIMEDOUT;
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	ret = gdsc_toggle_logic(sc, true);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	return gdsc_toggle_logic(sc, false);
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;
	unsigned int reg;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, true);
		if (ret)
			return ret;
	}

	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
	on = gdsc_is_enabled(sc, reg);
	if (on < 0)
		return on;

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	sc->pd.power_off = gdsc_disable;
	sc->pd.power_on = gdsc_enable;
	pm_genpd_init(&sc->pd, NULL, !on);

	return 0;
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	int i;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	/* Remove subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	}
	of_genpd_del_provider(dev->of_node);
}
Commit	Line	Data
45dd0e55 SB	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/kernel.h>
77b1067a	19	#include <linux/ktime.h>
45dd0e55 SB	20	#include <linux/pm_domain.h>
45dd0e55 SB	21	#include <linux/regmap.h>
3c53f5e2	22	#include <linux/reset-controller.h>
45dd0e55 SB	23	#include <linux/slab.h>
	24	#include "gdsc.h"
	25
	26	#define PWR_ON_MASK BIT(31)
	27	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	28	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	29	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	30	#define SW_OVERRIDE_MASK BIT(2)
	31	#define HW_CONTROL_MASK BIT(1)
	32	#define SW_COLLAPSE_MASK BIT(0)
	33
	34	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
	35	#define EN_REST_WAIT_VAL (0x2 << 20)
	36	#define EN_FEW_WAIT_VAL (0x8 << 16)
	37	#define CLK_DIS_WAIT_VAL (0x2 << 12)
	38
014e193c RN	39	#define RETAIN_MEM BIT(14)
	40	#define RETAIN_PERIPH BIT(13)
	41
45dd0e55 SB	42	#define TIMEOUT_US 100
	43
	44	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	45
77b1067a	46	static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
45dd0e55 SB	47	{
	48	u32 val;
	49	int ret;
	50
77b1067a	51	ret = regmap_read(sc->regmap, reg, &val);
45dd0e55 SB	52	if (ret)
	53	return ret;
	54
	55	return !!(val & PWR_ON_MASK);
	56	}
	57
	58	static int gdsc_toggle_logic(struct gdsc *sc, bool en)
	59	{
	60	int ret;
	61	u32 val = en ? 0 : SW_COLLAPSE_MASK;
77b1067a RN	62	ktime_t start;
77b1067a RN	63	unsigned int status_reg = sc->gdscr;
45dd0e55 SB	64
	65	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	66	if (ret)
	67	return ret;
	68
77b1067a RN	69	if (sc->gds_hw_ctrl) {
	70	status_reg = sc->gds_hw_ctrl;
	71	/*
	72	* The gds hw controller asserts/de-asserts the status bit soon
	73	* after it receives a power on/off request from a master.
	74	* The controller then takes around 8 xo cycles to start its
	75	* internal state machine and update the status bit. During
	76	* this time, the status bit does not reflect the true status
	77	* of the core.
	78	* Add a delay of 1 us between writing to the SW_COLLAPSE bit
	79	* and polling the status bit.
	80	*/
	81	udelay(1);
	82	}
45dd0e55	83
77b1067a RN	84	start = ktime_get();
	85	do {
	86	if (gdsc_is_enabled(sc, status_reg) == en)
45dd0e55	87	return 0;
77b1067a	88	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
45dd0e55	89
77b1067a	90	if (gdsc_is_enabled(sc, status_reg) == en)
45dd0e55 SB	91	return 0;
	92
	93	return -ETIMEDOUT;
	94	}
	95
3c53f5e2 RN	96	static inline int gdsc_deassert_reset(struct gdsc *sc)
	97	{
	98	int i;
	99
	100	for (i = 0; i < sc->reset_count; i++)
	101	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	102	return 0;
	103	}
	104
	105	static inline int gdsc_assert_reset(struct gdsc *sc)
	106	{
	107	int i;
	108
	109	for (i = 0; i < sc->reset_count; i++)
	110	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	111	return 0;
	112	}
	113
014e193c RN	114	static inline void gdsc_force_mem_on(struct gdsc *sc)
	115	{
	116	int i;
	117	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	118
	119	for (i = 0; i < sc->cxc_count; i++)
	120	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	121	}
	122
	123	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	124	{
	125	int i;
	126	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	127
	128	for (i = 0; i < sc->cxc_count; i++)
	129	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	130	}
	131
45dd0e55 SB	132	static int gdsc_enable(struct generic_pm_domain *domain)
	133	{
	134	struct gdsc *sc = domain_to_gdsc(domain);
	135	int ret;
	136
3c53f5e2 RN	137	if (sc->pwrsts == PWRSTS_ON)
	138	return gdsc_deassert_reset(sc);
	139
45dd0e55 SB	140	ret = gdsc_toggle_logic(sc, true);
	141	if (ret)
	142	return ret;
014e193c RN	143
	144	if (sc->pwrsts & PWRSTS_OFF)
	145	gdsc_force_mem_on(sc);
	146
45dd0e55 SB	147	/*
	148	* If clocks to this power domain were already on, they will take an
	149	* additional 4 clock cycles to re-enable after the power domain is
	150	* enabled. Delay to account for this. A delay is also needed to ensure
	151	* clocks are not enabled within 400ns of enabling power to the
	152	* memories.
	153	*/
	154	udelay(1);
	155
	156	return 0;
	157	}
	158
	159	static int gdsc_disable(struct generic_pm_domain *domain)
	160	{
	161	struct gdsc *sc = domain_to_gdsc(domain);
	162
3c53f5e2 RN	163	if (sc->pwrsts == PWRSTS_ON)
	164	return gdsc_assert_reset(sc);
	165
014e193c RN	166	if (sc->pwrsts & PWRSTS_OFF)
	167	gdsc_clear_mem_on(sc);
	168
45dd0e55 SB	169	return gdsc_toggle_logic(sc, false);
	170	}
	171
	172	static int gdsc_init(struct gdsc *sc)
	173	{
	174	u32 mask, val;
	175	int on, ret;
77b1067a	176	unsigned int reg;
45dd0e55 SB	177
	178	/*
	179	* Disable HW trigger: collapse/restore occur based on registers writes.
	180	* Disable SW override: Use hardware state-machine for sequencing.
	181	* Configure wait time between states.
	182	*/
	183	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	184	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
	185	val = EN_REST_WAIT_VAL \| EN_FEW_WAIT_VAL \| CLK_DIS_WAIT_VAL;
	186	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	187	if (ret)
	188	return ret;
	189
3c53f5e2 RN	190	/* Force gdsc ON if only ON state is supported */
	191	if (sc->pwrsts == PWRSTS_ON) {
	192	ret = gdsc_toggle_logic(sc, true);
	193	if (ret)
	194	return ret;
	195	}
	196
77b1067a RN	197	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
77b1067a RN	198	on = gdsc_is_enabled(sc, reg);
45dd0e55 SB	199	if (on < 0)
	200	return on;
	201
014e193c RN	202	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	203	gdsc_force_mem_on(sc);
	204	else
	205	gdsc_clear_mem_on(sc);
	206
45dd0e55 SB	207	sc->pd.power_off = gdsc_disable;
	208	sc->pd.power_on = gdsc_enable;
	209	pm_genpd_init(&sc->pd, NULL, !on);
	210
	211	return 0;
	212	}
	213
c2c7f0a4	214	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	215	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	216	{
	217	int i, ret;
	218	struct genpd_onecell_data *data;
c2c7f0a4 RN	219	struct device *dev = desc->dev;
	220	struct gdsc **scs = desc->scs;
	221	size_t num = desc->num;
45dd0e55 SB	222
	223	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	224	if (!data)
	225	return -ENOMEM;
	226
	227	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	228	GFP_KERNEL);
	229	if (!data->domains)
	230	return -ENOMEM;
	231
	232	data->num_domains = num;
	233	for (i = 0; i < num; i++) {
	234	if (!scs[i])
	235	continue;
	236	scs[i]->regmap = regmap;
3c53f5e2	237	scs[i]->rcdev = rcdev;
45dd0e55 SB	238	ret = gdsc_init(scs[i]);
	239	if (ret)
	240	return ret;
	241	data->domains[i] = &scs[i]->pd;
	242	}
	243
c2c7f0a4 RN	244	/* Add subdomains */
	245	for (i = 0; i < num; i++) {
	246	if (!scs[i])
	247	continue;
	248	if (scs[i]->parent)
	249	pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	250	}
	251
45dd0e55 SB	252	return of_genpd_add_provider_onecell(dev->of_node, data);
	253	}
	254
c2c7f0a4	255	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	256	{
c2c7f0a4 RN	257	int i;
	258	struct device *dev = desc->dev;
	259	struct gdsc **scs = desc->scs;
	260	size_t num = desc->num;
	261
	262	/* Remove subdomains */
	263	for (i = 0; i < num; i++) {
	264	if (!scs[i])
	265	continue;
	266	if (scs[i]->parent)
	267	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	268	}
45dd0e55 SB	269	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	270	}