[linux-2.6-block.git] / drivers / clk / qcom / gdsc.c

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)
#define GMEM_CLAMP_IO_MASK	BIT(0)

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	(0x2 << 20)
#define EN_FEW_WAIT_VAL		(0x8 << 16)
#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define TIMEOUT_US		100

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
{
	u32 val;
	int ret;

	ret = regmap_read(sc->regmap, reg, &val);
	if (ret)
		return ret;

	return !!(val & PWR_ON_MASK);
}

static int gdsc_hwctrl(struct gdsc *sc, bool en)
{
	u32 val = en ? HW_CONTROL_MASK : 0;

	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}

static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
{
	ktime_t start;

	start = ktime_get();
	do {
		if (gdsc_is_enabled(sc, reg) == en)
			return 0;
	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

	if (gdsc_is_enabled(sc, reg) == en)
		return 0;

	return -ETIMEDOUT;
}

static int gdsc_toggle_logic(struct gdsc *sc, bool en)
{
	int ret;
	u32 val = en ? 0 : SW_COLLAPSE_MASK;
	unsigned int status_reg = sc->gdscr;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	if (ret)
		return ret;

	/* If disabling votable gdscs, don't poll on status */
	if ((sc->flags & VOTABLE) && !en) {
		/*
		 * Add a short delay here to ensure that an enable
		 * right after it was disabled does not put it in an
		 * unknown state
		 */
		udelay(TIMEOUT_US);
		return 0;
	}

	if (sc->gds_hw_ctrl) {
		status_reg = sc->gds_hw_ctrl;
		/*
		 * The gds hw controller asserts/de-asserts the status bit soon
		 * after it receives a power on/off request from a master.
		 * The controller then takes around 8 xo cycles to start its
		 * internal state machine and update the status bit. During
		 * this time, the status bit does not reflect the true status
		 * of the core.
		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
		 * and polling the status bit.
		 */
		udelay(1);
	}

	return gdsc_poll_status(sc, status_reg, en);
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 0);
}

static inline void gdsc_assert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 1);
}

static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	if (sc->flags & CLAMP_IO)
		gdsc_deassert_clamp_io(sc);

	ret = gdsc_toggle_logic(sc, true);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	/* Turn on HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, true);
		if (ret)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case a firmware ends up polling status
		 * bits for the gdsc, it might read an 'on' status before
		 * the GDSC can finish the power cycle.
		 * We wait 1us before returning to ensure the firmware
		 * can't immediately poll the status bits.
		 */
		udelay(1);
	}

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	/* Turn off HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		unsigned int reg;

		ret = gdsc_hwctrl(sc, false);
		if (ret < 0)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case we end up polling status
		 * bits for the gdsc before the power cycle is completed
		 * it might read an 'on' status wrongly.
		 */
		udelay(1);

		reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
		ret = gdsc_poll_status(sc, reg, true);
		if (ret)
			return ret;
	}

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	ret = gdsc_toggle_logic(sc, false);
	if (ret)
		return ret;

	if (sc->flags & CLAMP_IO)
		gdsc_assert_clamp_io(sc);

	return 0;
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;
	unsigned int reg;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, true);
		if (ret)
			return ret;
	}

	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
	on = gdsc_is_enabled(sc, reg);
	if (on < 0)
		return on;

	/*
	 * Votable GDSCs can be ON due to Vote from other masters.
	 * If a Votable GDSC is ON, make sure we have a Vote.
	 */
	if ((sc->flags & VOTABLE) && on)
		gdsc_enable(&sc->pd);

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	sc->pd.power_off = gdsc_disable;
	sc->pd.power_on = gdsc_enable;
	pm_genpd_init(&sc->pd, NULL, !on);

	return 0;
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	int i;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	/* Remove subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	}
	of_genpd_del_provider(dev->of_node);
}
Commit	Line	Data
45dd0e55 SB	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/kernel.h>
77b1067a	19	#include <linux/ktime.h>
45dd0e55 SB	20	#include <linux/pm_domain.h>
45dd0e55 SB	21	#include <linux/regmap.h>
3c53f5e2	22	#include <linux/reset-controller.h>
45dd0e55 SB	23	#include <linux/slab.h>
	24	#include "gdsc.h"
	25
	26	#define PWR_ON_MASK BIT(31)
	27	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	28	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	29	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	30	#define SW_OVERRIDE_MASK BIT(2)
	31	#define HW_CONTROL_MASK BIT(1)
	32	#define SW_COLLAPSE_MASK BIT(0)
e7cc455f	33	#define GMEM_CLAMP_IO_MASK BIT(0)
45dd0e55 SB	34
	35	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
	36	#define EN_REST_WAIT_VAL (0x2 << 20)
	37	#define EN_FEW_WAIT_VAL (0x8 << 16)
	38	#define CLK_DIS_WAIT_VAL (0x2 << 12)
	39
014e193c RN	40	#define RETAIN_MEM BIT(14)
	41	#define RETAIN_PERIPH BIT(13)
	42
45dd0e55 SB	43	#define TIMEOUT_US 100
	44
	45	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	46
77b1067a	47	static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
45dd0e55 SB	48	{
	49	u32 val;
	50	int ret;
	51
77b1067a	52	ret = regmap_read(sc->regmap, reg, &val);
45dd0e55 SB	53	if (ret)
	54	return ret;
	55
	56	return !!(val & PWR_ON_MASK);
	57	}
	58
904bb4f5 RN	59	static int gdsc_hwctrl(struct gdsc *sc, bool en)
	60	{
	61	u32 val = en ? HW_CONTROL_MASK : 0;
	62
	63	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
	64	}
	65
843be1e7 RN	66	static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
	67	{
	68	ktime_t start;
	69
	70	start = ktime_get();
	71	do {
	72	if (gdsc_is_enabled(sc, reg) == en)
	73	return 0;
	74	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
	75
	76	if (gdsc_is_enabled(sc, reg) == en)
	77	return 0;
	78
	79	return -ETIMEDOUT;
	80	}
	81
45dd0e55 SB	82	static int gdsc_toggle_logic(struct gdsc *sc, bool en)
	83	{
	84	int ret;
	85	u32 val = en ? 0 : SW_COLLAPSE_MASK;
77b1067a	86	unsigned int status_reg = sc->gdscr;
45dd0e55 SB	87
	88	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	89	if (ret)
	90	return ret;
	91
a823bb9f RN	92	/* If disabling votable gdscs, don't poll on status */
	93	if ((sc->flags & VOTABLE) && !en) {
	94	/*
	95	* Add a short delay here to ensure that an enable
	96	* right after it was disabled does not put it in an
	97	* unknown state
	98	*/
	99	udelay(TIMEOUT_US);
	100	return 0;
	101	}
	102
77b1067a RN	103	if (sc->gds_hw_ctrl) {
	104	status_reg = sc->gds_hw_ctrl;
	105	/*
	106	* The gds hw controller asserts/de-asserts the status bit soon
	107	* after it receives a power on/off request from a master.
	108	* The controller then takes around 8 xo cycles to start its
	109	* internal state machine and update the status bit. During
	110	* this time, the status bit does not reflect the true status
	111	* of the core.
	112	* Add a delay of 1 us between writing to the SW_COLLAPSE bit
	113	* and polling the status bit.
	114	*/
	115	udelay(1);
	116	}
45dd0e55	117
843be1e7	118	return gdsc_poll_status(sc, status_reg, en);
45dd0e55 SB	119	}
45dd0e55 SB	120
3c53f5e2 RN	121	static inline int gdsc_deassert_reset(struct gdsc *sc)
	122	{
	123	int i;
	124
	125	for (i = 0; i < sc->reset_count; i++)
	126	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	127	return 0;
	128	}
	129
	130	static inline int gdsc_assert_reset(struct gdsc *sc)
	131	{
	132	int i;
	133
	134	for (i = 0; i < sc->reset_count; i++)
	135	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	136	return 0;
	137	}
	138
014e193c RN	139	static inline void gdsc_force_mem_on(struct gdsc *sc)
	140	{
	141	int i;
	142	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	143
	144	for (i = 0; i < sc->cxc_count; i++)
	145	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	146	}
	147
	148	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	149	{
	150	int i;
	151	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	152
	153	for (i = 0; i < sc->cxc_count; i++)
	154	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	155	}
	156
e7cc455f RN	157	static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
	158	{
	159	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	160	GMEM_CLAMP_IO_MASK, 0);
	161	}
	162
	163	static inline void gdsc_assert_clamp_io(struct gdsc *sc)
	164	{
	165	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	166	GMEM_CLAMP_IO_MASK, 1);
	167	}
	168
45dd0e55 SB	169	static int gdsc_enable(struct generic_pm_domain *domain)
	170	{
	171	struct gdsc *sc = domain_to_gdsc(domain);
	172	int ret;
	173
3c53f5e2 RN	174	if (sc->pwrsts == PWRSTS_ON)
	175	return gdsc_deassert_reset(sc);
	176
e7cc455f RN	177	if (sc->flags & CLAMP_IO)
	178	gdsc_deassert_clamp_io(sc);
	179
45dd0e55 SB	180	ret = gdsc_toggle_logic(sc, true);
	181	if (ret)
	182	return ret;
014e193c RN	183
	184	if (sc->pwrsts & PWRSTS_OFF)
	185	gdsc_force_mem_on(sc);
	186
45dd0e55 SB	187	/*
	188	* If clocks to this power domain were already on, they will take an
	189	* additional 4 clock cycles to re-enable after the power domain is
	190	* enabled. Delay to account for this. A delay is also needed to ensure
	191	* clocks are not enabled within 400ns of enabling power to the
	192	* memories.
	193	*/
	194	udelay(1);
	195
904bb4f5	196	/* Turn on HW trigger mode if supported */
843be1e7 RN	197	if (sc->flags & HW_CTRL) {
	198	ret = gdsc_hwctrl(sc, true);
	199	if (ret)
	200	return ret;
	201	/*
	202	* Wait for the GDSC to go through a power down and
	203	* up cycle. In case a firmware ends up polling status
	204	* bits for the gdsc, it might read an 'on' status before
	205	* the GDSC can finish the power cycle.
	206	* We wait 1us before returning to ensure the firmware
	207	* can't immediately poll the status bits.
	208	*/
	209	udelay(1);
	210	}
904bb4f5	211
45dd0e55 SB	212	return 0;
	213	}
	214
	215	static int gdsc_disable(struct generic_pm_domain *domain)
	216	{
	217	struct gdsc *sc = domain_to_gdsc(domain);
e7cc455f	218	int ret;
45dd0e55	219
3c53f5e2 RN	220	if (sc->pwrsts == PWRSTS_ON)
	221	return gdsc_assert_reset(sc);
	222
904bb4f5 RN	223	/* Turn off HW trigger mode if supported */
904bb4f5 RN	224	if (sc->flags & HW_CTRL) {
843be1e7 RN	225	unsigned int reg;
843be1e7 RN	226
904bb4f5 RN	227	ret = gdsc_hwctrl(sc, false);
	228	if (ret < 0)
	229	return ret;
843be1e7 RN	230	/*
	231	* Wait for the GDSC to go through a power down and
	232	* up cycle. In case we end up polling status
	233	* bits for the gdsc before the power cycle is completed
	234	* it might read an 'on' status wrongly.
	235	*/
	236	udelay(1);
	237
	238	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
	239	ret = gdsc_poll_status(sc, reg, true);
	240	if (ret)
	241	return ret;
904bb4f5 RN	242	}
904bb4f5 RN	243
014e193c RN	244	if (sc->pwrsts & PWRSTS_OFF)
	245	gdsc_clear_mem_on(sc);
	246
e7cc455f RN	247	ret = gdsc_toggle_logic(sc, false);
	248	if (ret)
	249	return ret;
	250
	251	if (sc->flags & CLAMP_IO)
	252	gdsc_assert_clamp_io(sc);
	253
	254	return 0;
45dd0e55 SB	255	}
	256
	257	static int gdsc_init(struct gdsc *sc)
	258	{
	259	u32 mask, val;
	260	int on, ret;
77b1067a	261	unsigned int reg;
45dd0e55 SB	262
	263	/*
	264	* Disable HW trigger: collapse/restore occur based on registers writes.
	265	* Disable SW override: Use hardware state-machine for sequencing.
	266	* Configure wait time between states.
	267	*/
	268	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	269	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
	270	val = EN_REST_WAIT_VAL \| EN_FEW_WAIT_VAL \| CLK_DIS_WAIT_VAL;
	271	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	272	if (ret)
	273	return ret;
	274
3c53f5e2 RN	275	/* Force gdsc ON if only ON state is supported */
	276	if (sc->pwrsts == PWRSTS_ON) {
	277	ret = gdsc_toggle_logic(sc, true);
	278	if (ret)
	279	return ret;
	280	}
	281
77b1067a RN	282	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
77b1067a RN	283	on = gdsc_is_enabled(sc, reg);
45dd0e55 SB	284	if (on < 0)
	285	return on;
	286
a823bb9f RN	287	/*
	288	* Votable GDSCs can be ON due to Vote from other masters.
	289	* If a Votable GDSC is ON, make sure we have a Vote.
	290	*/
	291	if ((sc->flags & VOTABLE) && on)
	292	gdsc_enable(&sc->pd);
	293
014e193c RN	294	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	295	gdsc_force_mem_on(sc);
	296	else
	297	gdsc_clear_mem_on(sc);
	298
45dd0e55 SB	299	sc->pd.power_off = gdsc_disable;
	300	sc->pd.power_on = gdsc_enable;
	301	pm_genpd_init(&sc->pd, NULL, !on);
	302
	303	return 0;
	304	}
	305
c2c7f0a4	306	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	307	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	308	{
	309	int i, ret;
	310	struct genpd_onecell_data *data;
c2c7f0a4 RN	311	struct device *dev = desc->dev;
	312	struct gdsc **scs = desc->scs;
	313	size_t num = desc->num;
45dd0e55 SB	314
	315	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	316	if (!data)
	317	return -ENOMEM;
	318
	319	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	320	GFP_KERNEL);
	321	if (!data->domains)
	322	return -ENOMEM;
	323
	324	data->num_domains = num;
	325	for (i = 0; i < num; i++) {
	326	if (!scs[i])
	327	continue;
	328	scs[i]->regmap = regmap;
3c53f5e2	329	scs[i]->rcdev = rcdev;
45dd0e55 SB	330	ret = gdsc_init(scs[i]);
	331	if (ret)
	332	return ret;
	333	data->domains[i] = &scs[i]->pd;
	334	}
	335
c2c7f0a4 RN	336	/* Add subdomains */
	337	for (i = 0; i < num; i++) {
	338	if (!scs[i])
	339	continue;
	340	if (scs[i]->parent)
	341	pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	342	}
	343
45dd0e55 SB	344	return of_genpd_add_provider_onecell(dev->of_node, data);
	345	}
	346
c2c7f0a4	347	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	348	{
c2c7f0a4 RN	349	int i;
	350	struct device *dev = desc->dev;
	351	struct gdsc **scs = desc->scs;
	352	size_t num = desc->num;
	353
	354	/* Remove subdomains */
	355	for (i = 0; i < num; i++) {
	356	if (!scs[i])
	357	continue;
	358	if (scs[i]->parent)
	359	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	360	}
45dd0e55 SB	361	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	362	}