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44c20c9e VA |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2020-2021, Linaro Limited | |
5 | */ | |
6 | ||
33aa94fd | 7 | #include <linux/clk-provider.h> |
44c20c9e VA |
8 | #include <linux/module.h> |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/regmap.h> | |
11 | ||
12 | #include <dt-bindings/clock/qcom,gcc-sm8350.h> | |
13 | ||
14 | #include "clk-alpha-pll.h" | |
15 | #include "clk-branch.h" | |
16 | #include "clk-rcg.h" | |
17 | #include "clk-regmap.h" | |
18 | #include "clk-regmap-divider.h" | |
19 | #include "clk-regmap-mux.h" | |
3fade948 | 20 | #include "gdsc.h" |
44c20c9e VA |
21 | #include "reset.h" |
22 | ||
23 | enum { | |
24 | P_BI_TCXO, | |
44c20c9e VA |
25 | P_GCC_GPLL0_OUT_EVEN, |
26 | P_GCC_GPLL0_OUT_MAIN, | |
27 | P_GCC_GPLL4_OUT_MAIN, | |
28 | P_GCC_GPLL9_OUT_MAIN, | |
29 | P_PCIE_0_PIPE_CLK, | |
30 | P_PCIE_1_PIPE_CLK, | |
31 | P_SLEEP_CLK, | |
32 | P_UFS_CARD_RX_SYMBOL_0_CLK, | |
33 | P_UFS_CARD_RX_SYMBOL_1_CLK, | |
34 | P_UFS_CARD_TX_SYMBOL_0_CLK, | |
35 | P_UFS_PHY_RX_SYMBOL_0_CLK, | |
36 | P_UFS_PHY_RX_SYMBOL_1_CLK, | |
37 | P_UFS_PHY_TX_SYMBOL_0_CLK, | |
38 | P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, | |
39 | P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, | |
40 | }; | |
41 | ||
42 | static struct clk_alpha_pll gcc_gpll0 = { | |
43 | .offset = 0x0, | |
44 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], | |
45 | .clkr = { | |
46 | .enable_reg = 0x52018, | |
47 | .enable_mask = BIT(0), | |
48 | .hw.init = &(struct clk_init_data){ | |
49 | .name = "gcc_gpll0", | |
50 | .parent_data = &(const struct clk_parent_data){ | |
51 | .fw_name = "bi_tcxo", | |
52 | }, | |
53 | .num_parents = 1, | |
54 | .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, | |
55 | }, | |
56 | }, | |
57 | }; | |
58 | ||
59 | static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { | |
60 | { 0x1, 2 }, | |
61 | { } | |
62 | }; | |
63 | ||
64 | static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { | |
65 | .offset = 0x0, | |
66 | .post_div_shift = 8, | |
67 | .post_div_table = post_div_table_gcc_gpll0_out_even, | |
68 | .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), | |
69 | .width = 4, | |
70 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], | |
71 | .clkr.hw.init = &(struct clk_init_data){ | |
72 | .name = "gcc_gpll0_out_even", | |
097a8888 DB |
73 | .parent_hws = (const struct clk_hw*[]){ |
74 | &gcc_gpll0.clkr.hw, | |
44c20c9e VA |
75 | }, |
76 | .num_parents = 1, | |
77 | .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, | |
78 | }, | |
79 | }; | |
80 | ||
81 | static struct clk_alpha_pll gcc_gpll4 = { | |
82 | .offset = 0x76000, | |
83 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], | |
84 | .clkr = { | |
85 | .enable_reg = 0x52018, | |
86 | .enable_mask = BIT(4), | |
87 | .hw.init = &(struct clk_init_data){ | |
88 | .name = "gcc_gpll4", | |
89 | .parent_data = &(const struct clk_parent_data){ | |
90 | .fw_name = "bi_tcxo", | |
91 | .name = "bi_tcxo", | |
92 | }, | |
93 | .num_parents = 1, | |
94 | .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, | |
95 | }, | |
96 | }, | |
97 | }; | |
98 | ||
99 | static struct clk_alpha_pll gcc_gpll9 = { | |
100 | .offset = 0x1c000, | |
101 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], | |
102 | .clkr = { | |
103 | .enable_reg = 0x52018, | |
104 | .enable_mask = BIT(9), | |
105 | .hw.init = &(struct clk_init_data){ | |
106 | .name = "gcc_gpll9", | |
107 | .parent_data = &(const struct clk_parent_data){ | |
108 | .fw_name = "bi_tcxo", | |
109 | .name = "bi_tcxo", | |
110 | }, | |
111 | .num_parents = 1, | |
112 | .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, | |
113 | }, | |
114 | }, | |
115 | }; | |
116 | ||
117 | static const struct parent_map gcc_parent_map_0[] = { | |
118 | { P_BI_TCXO, 0 }, | |
119 | { P_GCC_GPLL0_OUT_MAIN, 1 }, | |
120 | { P_GCC_GPLL0_OUT_EVEN, 6 }, | |
44c20c9e VA |
121 | }; |
122 | ||
123 | static const struct clk_parent_data gcc_parent_data_0[] = { | |
124 | { .fw_name = "bi_tcxo" }, | |
125 | { .hw = &gcc_gpll0.clkr.hw }, | |
126 | { .hw = &gcc_gpll0_out_even.clkr.hw }, | |
44c20c9e VA |
127 | }; |
128 | ||
129 | static const struct parent_map gcc_parent_map_1[] = { | |
130 | { P_BI_TCXO, 0 }, | |
131 | { P_GCC_GPLL0_OUT_MAIN, 1 }, | |
132 | { P_SLEEP_CLK, 5 }, | |
133 | { P_GCC_GPLL0_OUT_EVEN, 6 }, | |
44c20c9e VA |
134 | }; |
135 | ||
136 | static const struct clk_parent_data gcc_parent_data_1[] = { | |
137 | { .fw_name = "bi_tcxo" }, | |
138 | { .hw = &gcc_gpll0.clkr.hw }, | |
139 | { .fw_name = "sleep_clk" }, | |
140 | { .hw = &gcc_gpll0_out_even.clkr.hw }, | |
44c20c9e VA |
141 | }; |
142 | ||
143 | static const struct parent_map gcc_parent_map_2[] = { | |
144 | { P_BI_TCXO, 0 }, | |
145 | { P_SLEEP_CLK, 5 }, | |
44c20c9e VA |
146 | }; |
147 | ||
148 | static const struct clk_parent_data gcc_parent_data_2[] = { | |
149 | { .fw_name = "bi_tcxo" }, | |
150 | { .fw_name = "sleep_clk" }, | |
44c20c9e VA |
151 | }; |
152 | ||
153 | static const struct parent_map gcc_parent_map_3[] = { | |
154 | { P_BI_TCXO, 0 }, | |
44c20c9e VA |
155 | }; |
156 | ||
157 | static const struct clk_parent_data gcc_parent_data_3[] = { | |
158 | { .fw_name = "bi_tcxo" }, | |
44c20c9e VA |
159 | }; |
160 | ||
161 | static const struct parent_map gcc_parent_map_4[] = { | |
162 | { P_PCIE_0_PIPE_CLK, 0 }, | |
163 | { P_BI_TCXO, 2 }, | |
164 | }; | |
165 | ||
166 | static const struct clk_parent_data gcc_parent_data_4[] = { | |
167 | { .fw_name = "pcie_0_pipe_clk", }, | |
168 | { .fw_name = "bi_tcxo" }, | |
169 | }; | |
170 | ||
171 | static const struct parent_map gcc_parent_map_5[] = { | |
172 | { P_PCIE_1_PIPE_CLK, 0 }, | |
173 | { P_BI_TCXO, 2 }, | |
174 | }; | |
175 | ||
176 | static const struct clk_parent_data gcc_parent_data_5[] = { | |
177 | { .fw_name = "pcie_1_pipe_clk" }, | |
178 | { .fw_name = "bi_tcxo" }, | |
179 | }; | |
180 | ||
181 | static const struct parent_map gcc_parent_map_6[] = { | |
182 | { P_BI_TCXO, 0 }, | |
183 | { P_GCC_GPLL0_OUT_MAIN, 1 }, | |
184 | { P_GCC_GPLL9_OUT_MAIN, 2 }, | |
185 | { P_GCC_GPLL4_OUT_MAIN, 5 }, | |
186 | { P_GCC_GPLL0_OUT_EVEN, 6 }, | |
44c20c9e VA |
187 | }; |
188 | ||
189 | static const struct clk_parent_data gcc_parent_data_6[] = { | |
190 | { .fw_name = "bi_tcxo" }, | |
191 | { .hw = &gcc_gpll0.clkr.hw }, | |
192 | { .hw = &gcc_gpll9.clkr.hw }, | |
193 | { .hw = &gcc_gpll4.clkr.hw }, | |
194 | { .hw = &gcc_gpll0_out_even.clkr.hw }, | |
44c20c9e VA |
195 | }; |
196 | ||
197 | static const struct parent_map gcc_parent_map_7[] = { | |
198 | { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 }, | |
199 | { P_BI_TCXO, 2 }, | |
200 | }; | |
201 | ||
202 | static const struct clk_parent_data gcc_parent_data_7[] = { | |
203 | { .fw_name = "ufs_card_rx_symbol_0_clk" }, | |
204 | { .fw_name = "bi_tcxo" }, | |
205 | }; | |
206 | ||
207 | static const struct parent_map gcc_parent_map_8[] = { | |
208 | { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 }, | |
209 | { P_BI_TCXO, 2 }, | |
210 | }; | |
211 | ||
212 | static const struct clk_parent_data gcc_parent_data_8[] = { | |
213 | { .fw_name = "ufs_card_rx_symbol_1_clk" }, | |
214 | { .fw_name = "bi_tcxo" }, | |
215 | }; | |
216 | ||
217 | static const struct parent_map gcc_parent_map_9[] = { | |
218 | { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 }, | |
219 | { P_BI_TCXO, 2 }, | |
220 | }; | |
221 | ||
222 | static const struct clk_parent_data gcc_parent_data_9[] = { | |
223 | { .fw_name = "ufs_card_tx_symbol_0_clk" }, | |
224 | { .fw_name = "bi_tcxo" }, | |
225 | }; | |
226 | ||
227 | static const struct parent_map gcc_parent_map_10[] = { | |
228 | { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, | |
229 | { P_BI_TCXO, 2 }, | |
230 | }; | |
231 | ||
232 | static const struct clk_parent_data gcc_parent_data_10[] = { | |
233 | { .fw_name = "ufs_phy_rx_symbol_0_clk" }, | |
234 | { .fw_name = "bi_tcxo" }, | |
235 | }; | |
236 | ||
237 | static const struct parent_map gcc_parent_map_11[] = { | |
238 | { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, | |
239 | { P_BI_TCXO, 2 }, | |
240 | }; | |
241 | ||
242 | static const struct clk_parent_data gcc_parent_data_11[] = { | |
243 | { .fw_name = "ufs_phy_rx_symbol_1_clk" }, | |
244 | { .fw_name = "bi_tcxo" }, | |
245 | }; | |
246 | ||
247 | static const struct parent_map gcc_parent_map_12[] = { | |
248 | { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, | |
249 | { P_BI_TCXO, 2 }, | |
250 | }; | |
251 | ||
252 | static const struct clk_parent_data gcc_parent_data_12[] = { | |
253 | { .fw_name = "ufs_phy_tx_symbol_0_clk" }, | |
254 | { .fw_name = "bi_tcxo" }, | |
255 | }; | |
256 | ||
257 | static const struct parent_map gcc_parent_map_13[] = { | |
258 | { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, | |
44c20c9e VA |
259 | { P_BI_TCXO, 2 }, |
260 | }; | |
261 | ||
262 | static const struct clk_parent_data gcc_parent_data_13[] = { | |
263 | { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, | |
44c20c9e VA |
264 | { .fw_name = "bi_tcxo" }, |
265 | }; | |
266 | ||
267 | static const struct parent_map gcc_parent_map_14[] = { | |
268 | { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 }, | |
44c20c9e VA |
269 | { P_BI_TCXO, 2 }, |
270 | }; | |
271 | ||
272 | static const struct clk_parent_data gcc_parent_data_14[] = { | |
273 | { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" }, | |
44c20c9e VA |
274 | { .fw_name = "bi_tcxo" }, |
275 | }; | |
276 | ||
277 | static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { | |
278 | .reg = 0x6b054, | |
279 | .shift = 0, | |
280 | .width = 2, | |
281 | .parent_map = gcc_parent_map_4, | |
282 | .clkr = { | |
283 | .hw.init = &(struct clk_init_data){ | |
284 | .name = "gcc_pcie_0_pipe_clk_src", | |
285 | .parent_data = gcc_parent_data_4, | |
886fd9a4 | 286 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), |
44c20c9e VA |
287 | .ops = &clk_regmap_mux_closest_ops, |
288 | }, | |
289 | }, | |
290 | }; | |
291 | ||
292 | static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { | |
293 | .reg = 0x8d054, | |
294 | .shift = 0, | |
295 | .width = 2, | |
296 | .parent_map = gcc_parent_map_5, | |
297 | .clkr = { | |
298 | .hw.init = &(struct clk_init_data){ | |
299 | .name = "gcc_pcie_1_pipe_clk_src", | |
300 | .parent_data = gcc_parent_data_5, | |
886fd9a4 | 301 | .num_parents = ARRAY_SIZE(gcc_parent_data_5), |
44c20c9e VA |
302 | .ops = &clk_regmap_mux_closest_ops, |
303 | }, | |
304 | }, | |
305 | }; | |
306 | ||
307 | static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { | |
308 | .reg = 0x75058, | |
309 | .shift = 0, | |
310 | .width = 2, | |
311 | .parent_map = gcc_parent_map_7, | |
312 | .clkr = { | |
313 | .hw.init = &(struct clk_init_data){ | |
314 | .name = "gcc_ufs_card_rx_symbol_0_clk_src", | |
315 | .parent_data = gcc_parent_data_7, | |
886fd9a4 | 316 | .num_parents = ARRAY_SIZE(gcc_parent_data_7), |
44c20c9e VA |
317 | .ops = &clk_regmap_mux_closest_ops, |
318 | }, | |
319 | }, | |
320 | }; | |
321 | ||
322 | static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { | |
323 | .reg = 0x750c8, | |
324 | .shift = 0, | |
325 | .width = 2, | |
326 | .parent_map = gcc_parent_map_8, | |
327 | .clkr = { | |
328 | .hw.init = &(struct clk_init_data){ | |
329 | .name = "gcc_ufs_card_rx_symbol_1_clk_src", | |
330 | .parent_data = gcc_parent_data_8, | |
886fd9a4 | 331 | .num_parents = ARRAY_SIZE(gcc_parent_data_8), |
44c20c9e VA |
332 | .ops = &clk_regmap_mux_closest_ops, |
333 | }, | |
334 | }, | |
335 | }; | |
336 | ||
337 | static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { | |
338 | .reg = 0x75048, | |
339 | .shift = 0, | |
340 | .width = 2, | |
341 | .parent_map = gcc_parent_map_9, | |
342 | .clkr = { | |
343 | .hw.init = &(struct clk_init_data){ | |
344 | .name = "gcc_ufs_card_tx_symbol_0_clk_src", | |
345 | .parent_data = gcc_parent_data_9, | |
886fd9a4 | 346 | .num_parents = ARRAY_SIZE(gcc_parent_data_9), |
44c20c9e VA |
347 | .ops = &clk_regmap_mux_closest_ops, |
348 | }, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { | |
353 | .reg = 0x77058, | |
354 | .shift = 0, | |
355 | .width = 2, | |
356 | .parent_map = gcc_parent_map_10, | |
357 | .clkr = { | |
358 | .hw.init = &(struct clk_init_data){ | |
359 | .name = "gcc_ufs_phy_rx_symbol_0_clk_src", | |
360 | .parent_data = gcc_parent_data_10, | |
886fd9a4 | 361 | .num_parents = ARRAY_SIZE(gcc_parent_data_10), |
44c20c9e VA |
362 | .ops = &clk_regmap_mux_closest_ops, |
363 | }, | |
364 | }, | |
365 | }; | |
366 | ||
367 | static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { | |
368 | .reg = 0x770c8, | |
369 | .shift = 0, | |
370 | .width = 2, | |
371 | .parent_map = gcc_parent_map_11, | |
372 | .clkr = { | |
373 | .hw.init = &(struct clk_init_data){ | |
374 | .name = "gcc_ufs_phy_rx_symbol_1_clk_src", | |
375 | .parent_data = gcc_parent_data_11, | |
886fd9a4 | 376 | .num_parents = ARRAY_SIZE(gcc_parent_data_11), |
44c20c9e VA |
377 | .ops = &clk_regmap_mux_closest_ops, |
378 | }, | |
379 | }, | |
380 | }; | |
381 | ||
382 | static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { | |
383 | .reg = 0x77048, | |
384 | .shift = 0, | |
385 | .width = 2, | |
386 | .parent_map = gcc_parent_map_12, | |
387 | .clkr = { | |
388 | .hw.init = &(struct clk_init_data){ | |
389 | .name = "gcc_ufs_phy_tx_symbol_0_clk_src", | |
390 | .parent_data = gcc_parent_data_12, | |
886fd9a4 | 391 | .num_parents = ARRAY_SIZE(gcc_parent_data_12), |
44c20c9e VA |
392 | .ops = &clk_regmap_mux_closest_ops, |
393 | }, | |
394 | }, | |
395 | }; | |
396 | ||
397 | static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { | |
398 | .reg = 0xf060, | |
399 | .shift = 0, | |
400 | .width = 2, | |
401 | .parent_map = gcc_parent_map_13, | |
402 | .clkr = { | |
403 | .hw.init = &(struct clk_init_data){ | |
404 | .name = "gcc_usb3_prim_phy_pipe_clk_src", | |
405 | .parent_data = gcc_parent_data_13, | |
886fd9a4 | 406 | .num_parents = ARRAY_SIZE(gcc_parent_data_13), |
44c20c9e VA |
407 | .ops = &clk_regmap_mux_closest_ops, |
408 | }, | |
409 | }, | |
410 | }; | |
411 | ||
412 | static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { | |
413 | .reg = 0x10060, | |
414 | .shift = 0, | |
415 | .width = 2, | |
416 | .parent_map = gcc_parent_map_14, | |
417 | .clkr = { | |
418 | .hw.init = &(struct clk_init_data){ | |
419 | .name = "gcc_usb3_sec_phy_pipe_clk_src", | |
420 | .parent_data = gcc_parent_data_14, | |
886fd9a4 | 421 | .num_parents = ARRAY_SIZE(gcc_parent_data_14), |
44c20c9e VA |
422 | .ops = &clk_regmap_mux_closest_ops, |
423 | }, | |
424 | }, | |
425 | }; | |
426 | ||
427 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { | |
428 | F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), | |
429 | F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), | |
430 | F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), | |
431 | { } | |
432 | }; | |
433 | ||
434 | static struct clk_rcg2 gcc_gp1_clk_src = { | |
435 | .cmd_rcgr = 0x64004, | |
436 | .mnd_width = 8, | |
437 | .hid_width = 5, | |
438 | .parent_map = gcc_parent_map_1, | |
439 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
440 | .clkr.hw.init = &(struct clk_init_data){ | |
441 | .name = "gcc_gp1_clk_src", | |
442 | .parent_data = gcc_parent_data_1, | |
886fd9a4 | 443 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), |
44c20c9e VA |
444 | .flags = CLK_SET_RATE_PARENT, |
445 | .ops = &clk_rcg2_ops, | |
446 | }, | |
447 | }; | |
448 | ||
449 | static struct clk_rcg2 gcc_gp2_clk_src = { | |
450 | .cmd_rcgr = 0x65004, | |
451 | .mnd_width = 8, | |
452 | .hid_width = 5, | |
453 | .parent_map = gcc_parent_map_1, | |
454 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
455 | .clkr.hw.init = &(struct clk_init_data){ | |
456 | .name = "gcc_gp2_clk_src", | |
457 | .parent_data = gcc_parent_data_1, | |
886fd9a4 | 458 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), |
44c20c9e VA |
459 | .flags = CLK_SET_RATE_PARENT, |
460 | .ops = &clk_rcg2_ops, | |
461 | }, | |
462 | }; | |
463 | ||
464 | static struct clk_rcg2 gcc_gp3_clk_src = { | |
465 | .cmd_rcgr = 0x66004, | |
466 | .mnd_width = 8, | |
467 | .hid_width = 5, | |
468 | .parent_map = gcc_parent_map_1, | |
469 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
470 | .clkr.hw.init = &(struct clk_init_data){ | |
471 | .name = "gcc_gp3_clk_src", | |
472 | .parent_data = gcc_parent_data_1, | |
886fd9a4 | 473 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), |
44c20c9e VA |
474 | .flags = CLK_SET_RATE_PARENT, |
475 | .ops = &clk_rcg2_ops, | |
476 | }, | |
477 | }; | |
478 | ||
479 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { | |
480 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
481 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
482 | { } | |
483 | }; | |
484 | ||
485 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { | |
486 | .cmd_rcgr = 0x6b058, | |
487 | .mnd_width = 16, | |
488 | .hid_width = 5, | |
489 | .parent_map = gcc_parent_map_2, | |
490 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
491 | .clkr.hw.init = &(struct clk_init_data){ | |
492 | .name = "gcc_pcie_0_aux_clk_src", | |
493 | .parent_data = gcc_parent_data_2, | |
886fd9a4 | 494 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), |
44c20c9e VA |
495 | .flags = CLK_SET_RATE_PARENT, |
496 | .ops = &clk_rcg2_ops, | |
497 | }, | |
498 | }; | |
499 | ||
500 | static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { | |
501 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
502 | F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), | |
503 | { } | |
504 | }; | |
505 | ||
506 | static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { | |
507 | .cmd_rcgr = 0x6b03c, | |
508 | .mnd_width = 0, | |
509 | .hid_width = 5, | |
510 | .parent_map = gcc_parent_map_0, | |
511 | .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, | |
512 | .clkr.hw.init = &(struct clk_init_data){ | |
513 | .name = "gcc_pcie_0_phy_rchng_clk_src", | |
514 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 515 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
516 | .flags = CLK_SET_RATE_PARENT, |
517 | .ops = &clk_rcg2_ops, | |
518 | }, | |
519 | }; | |
520 | ||
521 | static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { | |
522 | .cmd_rcgr = 0x8d058, | |
523 | .mnd_width = 16, | |
524 | .hid_width = 5, | |
525 | .parent_map = gcc_parent_map_2, | |
526 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
527 | .clkr.hw.init = &(struct clk_init_data){ | |
528 | .name = "gcc_pcie_1_aux_clk_src", | |
529 | .parent_data = gcc_parent_data_2, | |
886fd9a4 | 530 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), |
44c20c9e VA |
531 | .flags = CLK_SET_RATE_PARENT, |
532 | .ops = &clk_rcg2_ops, | |
533 | }, | |
534 | }; | |
535 | ||
536 | static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { | |
537 | .cmd_rcgr = 0x8d03c, | |
538 | .mnd_width = 0, | |
539 | .hid_width = 5, | |
540 | .parent_map = gcc_parent_map_0, | |
541 | .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, | |
542 | .clkr.hw.init = &(struct clk_init_data){ | |
543 | .name = "gcc_pcie_1_phy_rchng_clk_src", | |
544 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 545 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
546 | .flags = CLK_SET_RATE_PARENT, |
547 | .ops = &clk_rcg2_ops, | |
548 | }, | |
549 | }; | |
550 | ||
551 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { | |
552 | F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), | |
553 | { } | |
554 | }; | |
555 | ||
556 | static struct clk_rcg2 gcc_pdm2_clk_src = { | |
557 | .cmd_rcgr = 0x33010, | |
558 | .mnd_width = 0, | |
559 | .hid_width = 5, | |
560 | .parent_map = gcc_parent_map_0, | |
561 | .freq_tbl = ftbl_gcc_pdm2_clk_src, | |
562 | .clkr.hw.init = &(struct clk_init_data){ | |
563 | .name = "gcc_pdm2_clk_src", | |
564 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 565 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
566 | .flags = CLK_SET_RATE_PARENT, |
567 | .ops = &clk_rcg2_ops, | |
568 | }, | |
569 | }; | |
570 | ||
571 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { | |
572 | F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), | |
573 | F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), | |
574 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
575 | F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), | |
576 | F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), | |
577 | F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), | |
578 | F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), | |
579 | F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), | |
580 | F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), | |
581 | F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), | |
582 | F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), | |
583 | { } | |
584 | }; | |
585 | ||
586 | static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { | |
587 | .name = "gcc_qupv3_wrap0_s0_clk_src", | |
588 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 589 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
590 | .flags = CLK_SET_RATE_PARENT, |
591 | .ops = &clk_rcg2_ops, | |
592 | }; | |
593 | ||
594 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { | |
595 | .cmd_rcgr = 0x17010, | |
596 | .mnd_width = 16, | |
597 | .hid_width = 5, | |
598 | .parent_map = gcc_parent_map_0, | |
599 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
600 | .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, | |
601 | }; | |
602 | ||
603 | static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { | |
604 | .name = "gcc_qupv3_wrap0_s1_clk_src", | |
605 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 606 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
607 | .flags = CLK_SET_RATE_PARENT, |
608 | .ops = &clk_rcg2_ops, | |
609 | }; | |
610 | ||
611 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { | |
612 | .cmd_rcgr = 0x17140, | |
613 | .mnd_width = 16, | |
614 | .hid_width = 5, | |
615 | .parent_map = gcc_parent_map_0, | |
616 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
617 | .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, | |
618 | }; | |
619 | ||
620 | static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { | |
621 | .name = "gcc_qupv3_wrap0_s2_clk_src", | |
622 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 623 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
624 | .flags = CLK_SET_RATE_PARENT, |
625 | .ops = &clk_rcg2_ops, | |
626 | }; | |
627 | ||
628 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { | |
629 | .cmd_rcgr = 0x17270, | |
630 | .mnd_width = 16, | |
631 | .hid_width = 5, | |
632 | .parent_map = gcc_parent_map_0, | |
633 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
634 | .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, | |
635 | }; | |
636 | ||
637 | static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { | |
638 | .name = "gcc_qupv3_wrap0_s3_clk_src", | |
639 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 640 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
641 | .flags = CLK_SET_RATE_PARENT, |
642 | .ops = &clk_rcg2_ops, | |
643 | }; | |
644 | ||
645 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { | |
646 | .cmd_rcgr = 0x173a0, | |
647 | .mnd_width = 16, | |
648 | .hid_width = 5, | |
649 | .parent_map = gcc_parent_map_0, | |
650 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
651 | .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, | |
652 | }; | |
653 | ||
654 | static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { | |
655 | .name = "gcc_qupv3_wrap0_s4_clk_src", | |
656 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 657 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
658 | .flags = CLK_SET_RATE_PARENT, |
659 | .ops = &clk_rcg2_ops, | |
660 | }; | |
661 | ||
662 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { | |
663 | .cmd_rcgr = 0x174d0, | |
664 | .mnd_width = 16, | |
665 | .hid_width = 5, | |
666 | .parent_map = gcc_parent_map_0, | |
667 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
668 | .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, | |
669 | }; | |
670 | ||
671 | static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { | |
672 | .name = "gcc_qupv3_wrap0_s5_clk_src", | |
673 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 674 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
675 | .flags = CLK_SET_RATE_PARENT, |
676 | .ops = &clk_rcg2_ops, | |
677 | }; | |
678 | ||
679 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { | |
680 | .cmd_rcgr = 0x17600, | |
681 | .mnd_width = 16, | |
682 | .hid_width = 5, | |
683 | .parent_map = gcc_parent_map_0, | |
684 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
685 | .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, | |
686 | }; | |
687 | ||
688 | static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { | |
689 | .name = "gcc_qupv3_wrap0_s6_clk_src", | |
690 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 691 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
692 | .flags = CLK_SET_RATE_PARENT, |
693 | .ops = &clk_rcg2_ops, | |
694 | }; | |
695 | ||
696 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { | |
697 | .cmd_rcgr = 0x17730, | |
698 | .mnd_width = 16, | |
699 | .hid_width = 5, | |
700 | .parent_map = gcc_parent_map_0, | |
701 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
702 | .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, | |
703 | }; | |
704 | ||
705 | static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { | |
706 | .name = "gcc_qupv3_wrap0_s7_clk_src", | |
707 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 708 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
709 | .flags = CLK_SET_RATE_PARENT, |
710 | .ops = &clk_rcg2_ops, | |
711 | }; | |
712 | ||
713 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { | |
714 | .cmd_rcgr = 0x17860, | |
715 | .mnd_width = 16, | |
716 | .hid_width = 5, | |
717 | .parent_map = gcc_parent_map_0, | |
718 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
719 | .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, | |
720 | }; | |
721 | ||
722 | static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { | |
723 | F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), | |
724 | F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), | |
725 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
726 | F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), | |
727 | F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), | |
728 | F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), | |
729 | F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), | |
730 | F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), | |
731 | F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), | |
732 | F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), | |
733 | F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), | |
734 | F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), | |
735 | F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), | |
736 | F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), | |
737 | F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), | |
738 | { } | |
739 | }; | |
740 | ||
741 | static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { | |
742 | .name = "gcc_qupv3_wrap1_s0_clk_src", | |
743 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 744 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
745 | .flags = CLK_SET_RATE_PARENT, |
746 | .ops = &clk_rcg2_ops, | |
747 | }; | |
748 | ||
749 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { | |
750 | .cmd_rcgr = 0x18010, | |
751 | .mnd_width = 16, | |
752 | .hid_width = 5, | |
753 | .parent_map = gcc_parent_map_0, | |
754 | .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, | |
755 | .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, | |
756 | }; | |
757 | ||
758 | static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { | |
759 | .name = "gcc_qupv3_wrap1_s1_clk_src", | |
760 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 761 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
762 | .flags = CLK_SET_RATE_PARENT, |
763 | .ops = &clk_rcg2_ops, | |
764 | }; | |
765 | ||
766 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { | |
767 | .cmd_rcgr = 0x18140, | |
768 | .mnd_width = 16, | |
769 | .hid_width = 5, | |
770 | .parent_map = gcc_parent_map_0, | |
771 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
772 | .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, | |
773 | }; | |
774 | ||
775 | static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { | |
776 | .name = "gcc_qupv3_wrap1_s2_clk_src", | |
777 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 778 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
779 | .flags = CLK_SET_RATE_PARENT, |
780 | .ops = &clk_rcg2_ops, | |
781 | }; | |
782 | ||
783 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { | |
784 | .cmd_rcgr = 0x18270, | |
785 | .mnd_width = 16, | |
786 | .hid_width = 5, | |
787 | .parent_map = gcc_parent_map_0, | |
788 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
789 | .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, | |
790 | }; | |
791 | ||
792 | static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { | |
793 | .name = "gcc_qupv3_wrap1_s3_clk_src", | |
794 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 795 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
796 | .flags = CLK_SET_RATE_PARENT, |
797 | .ops = &clk_rcg2_ops, | |
798 | }; | |
799 | ||
800 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { | |
801 | .cmd_rcgr = 0x183a0, | |
802 | .mnd_width = 16, | |
803 | .hid_width = 5, | |
804 | .parent_map = gcc_parent_map_0, | |
805 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
806 | .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, | |
807 | }; | |
808 | ||
809 | static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { | |
810 | .name = "gcc_qupv3_wrap1_s4_clk_src", | |
811 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 812 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
813 | .flags = CLK_SET_RATE_PARENT, |
814 | .ops = &clk_rcg2_ops, | |
815 | }; | |
816 | ||
817 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { | |
818 | .cmd_rcgr = 0x184d0, | |
819 | .mnd_width = 16, | |
820 | .hid_width = 5, | |
821 | .parent_map = gcc_parent_map_0, | |
822 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
823 | .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, | |
824 | }; | |
825 | ||
826 | static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { | |
827 | .name = "gcc_qupv3_wrap1_s5_clk_src", | |
828 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 829 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
830 | .flags = CLK_SET_RATE_PARENT, |
831 | .ops = &clk_rcg2_ops, | |
832 | }; | |
833 | ||
834 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { | |
835 | .cmd_rcgr = 0x18600, | |
836 | .mnd_width = 16, | |
837 | .hid_width = 5, | |
838 | .parent_map = gcc_parent_map_0, | |
839 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
840 | .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, | |
841 | }; | |
842 | ||
843 | static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { | |
844 | .name = "gcc_qupv3_wrap2_s0_clk_src", | |
845 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 846 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
847 | .flags = CLK_SET_RATE_PARENT, |
848 | .ops = &clk_rcg2_ops, | |
849 | }; | |
850 | ||
851 | static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { | |
852 | .cmd_rcgr = 0x1e010, | |
853 | .mnd_width = 16, | |
854 | .hid_width = 5, | |
855 | .parent_map = gcc_parent_map_0, | |
856 | .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, | |
857 | .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, | |
858 | }; | |
859 | ||
860 | static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { | |
861 | .name = "gcc_qupv3_wrap2_s1_clk_src", | |
862 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 863 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
864 | .flags = CLK_SET_RATE_PARENT, |
865 | .ops = &clk_rcg2_ops, | |
866 | }; | |
867 | ||
868 | static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { | |
869 | .cmd_rcgr = 0x1e140, | |
870 | .mnd_width = 16, | |
871 | .hid_width = 5, | |
872 | .parent_map = gcc_parent_map_0, | |
873 | .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, | |
874 | .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, | |
875 | }; | |
876 | ||
877 | static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { | |
878 | .name = "gcc_qupv3_wrap2_s2_clk_src", | |
879 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 880 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
881 | .flags = CLK_SET_RATE_PARENT, |
882 | .ops = &clk_rcg2_ops, | |
883 | }; | |
884 | ||
885 | static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { | |
886 | .cmd_rcgr = 0x1e270, | |
887 | .mnd_width = 16, | |
888 | .hid_width = 5, | |
889 | .parent_map = gcc_parent_map_0, | |
890 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
891 | .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, | |
892 | }; | |
893 | ||
894 | static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { | |
895 | .name = "gcc_qupv3_wrap2_s3_clk_src", | |
896 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 897 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
898 | .flags = CLK_SET_RATE_PARENT, |
899 | .ops = &clk_rcg2_ops, | |
900 | }; | |
901 | ||
902 | static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { | |
903 | .cmd_rcgr = 0x1e3a0, | |
904 | .mnd_width = 16, | |
905 | .hid_width = 5, | |
906 | .parent_map = gcc_parent_map_0, | |
907 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
908 | .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, | |
909 | }; | |
910 | ||
911 | static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { | |
912 | .name = "gcc_qupv3_wrap2_s4_clk_src", | |
913 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 914 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
915 | .flags = CLK_SET_RATE_PARENT, |
916 | .ops = &clk_rcg2_ops, | |
917 | }; | |
918 | ||
919 | static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { | |
920 | .cmd_rcgr = 0x1e4d0, | |
921 | .mnd_width = 16, | |
922 | .hid_width = 5, | |
923 | .parent_map = gcc_parent_map_0, | |
924 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
925 | .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, | |
926 | }; | |
927 | ||
928 | static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { | |
929 | .name = "gcc_qupv3_wrap2_s5_clk_src", | |
930 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 931 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
932 | .flags = CLK_SET_RATE_PARENT, |
933 | .ops = &clk_rcg2_ops, | |
934 | }; | |
935 | ||
936 | static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { | |
937 | .cmd_rcgr = 0x1e600, | |
938 | .mnd_width = 16, | |
939 | .hid_width = 5, | |
940 | .parent_map = gcc_parent_map_0, | |
941 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
942 | .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, | |
943 | }; | |
944 | ||
945 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { | |
946 | F(400000, P_BI_TCXO, 12, 1, 4), | |
947 | F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), | |
948 | F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), | |
949 | F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), | |
950 | F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), | |
951 | { } | |
952 | }; | |
953 | ||
954 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | |
955 | .cmd_rcgr = 0x1400c, | |
956 | .mnd_width = 8, | |
957 | .hid_width = 5, | |
958 | .parent_map = gcc_parent_map_6, | |
959 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, | |
960 | .clkr.hw.init = &(struct clk_init_data){ | |
961 | .name = "gcc_sdcc2_apps_clk_src", | |
962 | .parent_data = gcc_parent_data_6, | |
886fd9a4 | 963 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), |
44c20c9e VA |
964 | .flags = CLK_SET_RATE_PARENT, |
965 | .ops = &clk_rcg2_floor_ops, | |
966 | }, | |
967 | }; | |
968 | ||
969 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { | |
970 | F(400000, P_BI_TCXO, 12, 1, 4), | |
971 | F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), | |
972 | F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), | |
973 | { } | |
974 | }; | |
975 | ||
976 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { | |
977 | .cmd_rcgr = 0x1600c, | |
978 | .mnd_width = 8, | |
979 | .hid_width = 5, | |
980 | .parent_map = gcc_parent_map_0, | |
981 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, | |
982 | .clkr.hw.init = &(struct clk_init_data){ | |
983 | .name = "gcc_sdcc4_apps_clk_src", | |
984 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 985 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
986 | .flags = CLK_SET_RATE_PARENT, |
987 | .ops = &clk_rcg2_floor_ops, | |
988 | }, | |
989 | }; | |
990 | ||
991 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { | |
992 | F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), | |
993 | F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), | |
994 | F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), | |
995 | F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), | |
996 | { } | |
997 | }; | |
998 | ||
999 | static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { | |
1000 | .cmd_rcgr = 0x75024, | |
1001 | .mnd_width = 8, | |
1002 | .hid_width = 5, | |
1003 | .parent_map = gcc_parent_map_0, | |
1004 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, | |
1005 | .clkr.hw.init = &(struct clk_init_data){ | |
1006 | .name = "gcc_ufs_card_axi_clk_src", | |
1007 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1008 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1009 | .flags = CLK_SET_RATE_PARENT, |
1010 | .ops = &clk_rcg2_ops, | |
1011 | }, | |
1012 | }; | |
1013 | ||
1014 | static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { | |
1015 | F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), | |
1016 | F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), | |
1017 | F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), | |
1018 | { } | |
1019 | }; | |
1020 | ||
1021 | static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { | |
1022 | .cmd_rcgr = 0x7506c, | |
1023 | .mnd_width = 0, | |
1024 | .hid_width = 5, | |
1025 | .parent_map = gcc_parent_map_0, | |
1026 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
1027 | .clkr.hw.init = &(struct clk_init_data){ | |
1028 | .name = "gcc_ufs_card_ice_core_clk_src", | |
1029 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1030 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1031 | .flags = CLK_SET_RATE_PARENT, |
1032 | .ops = &clk_rcg2_ops, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { | |
1037 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1038 | { } | |
1039 | }; | |
1040 | ||
1041 | static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { | |
1042 | .cmd_rcgr = 0x750a0, | |
1043 | .mnd_width = 0, | |
1044 | .hid_width = 5, | |
1045 | .parent_map = gcc_parent_map_3, | |
1046 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1047 | .clkr.hw.init = &(struct clk_init_data){ | |
1048 | .name = "gcc_ufs_card_phy_aux_clk_src", | |
1049 | .parent_data = gcc_parent_data_3, | |
886fd9a4 | 1050 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), |
44c20c9e VA |
1051 | .flags = CLK_SET_RATE_PARENT, |
1052 | .ops = &clk_rcg2_ops, | |
1053 | }, | |
1054 | }; | |
1055 | ||
1056 | static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { | |
1057 | .cmd_rcgr = 0x75084, | |
1058 | .mnd_width = 0, | |
1059 | .hid_width = 5, | |
1060 | .parent_map = gcc_parent_map_0, | |
1061 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
1062 | .clkr.hw.init = &(struct clk_init_data){ | |
1063 | .name = "gcc_ufs_card_unipro_core_clk_src", | |
1064 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1065 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1066 | .flags = CLK_SET_RATE_PARENT, |
1067 | .ops = &clk_rcg2_ops, | |
1068 | }, | |
1069 | }; | |
1070 | ||
1071 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { | |
1072 | .cmd_rcgr = 0x77024, | |
1073 | .mnd_width = 8, | |
1074 | .hid_width = 5, | |
1075 | .parent_map = gcc_parent_map_0, | |
1076 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, | |
1077 | .clkr.hw.init = &(struct clk_init_data){ | |
1078 | .name = "gcc_ufs_phy_axi_clk_src", | |
1079 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1080 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1081 | .flags = CLK_SET_RATE_PARENT, |
1082 | .ops = &clk_rcg2_ops, | |
1083 | }, | |
1084 | }; | |
1085 | ||
1086 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { | |
1087 | .cmd_rcgr = 0x7706c, | |
1088 | .mnd_width = 0, | |
1089 | .hid_width = 5, | |
1090 | .parent_map = gcc_parent_map_0, | |
1091 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
1092 | .clkr.hw.init = &(struct clk_init_data){ | |
1093 | .name = "gcc_ufs_phy_ice_core_clk_src", | |
1094 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1095 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1096 | .flags = CLK_SET_RATE_PARENT, |
1097 | .ops = &clk_rcg2_ops, | |
1098 | }, | |
1099 | }; | |
1100 | ||
1101 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { | |
1102 | .cmd_rcgr = 0x770a0, | |
1103 | .mnd_width = 0, | |
1104 | .hid_width = 5, | |
1105 | .parent_map = gcc_parent_map_3, | |
1106 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
1107 | .clkr.hw.init = &(struct clk_init_data){ | |
1108 | .name = "gcc_ufs_phy_phy_aux_clk_src", | |
1109 | .parent_data = gcc_parent_data_3, | |
886fd9a4 | 1110 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), |
44c20c9e VA |
1111 | .flags = CLK_SET_RATE_PARENT, |
1112 | .ops = &clk_rcg2_ops, | |
1113 | }, | |
1114 | }; | |
1115 | ||
1116 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { | |
1117 | .cmd_rcgr = 0x77084, | |
1118 | .mnd_width = 0, | |
1119 | .hid_width = 5, | |
1120 | .parent_map = gcc_parent_map_0, | |
1121 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
1122 | .clkr.hw.init = &(struct clk_init_data){ | |
1123 | .name = "gcc_ufs_phy_unipro_core_clk_src", | |
1124 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1125 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1126 | .flags = CLK_SET_RATE_PARENT, |
1127 | .ops = &clk_rcg2_ops, | |
1128 | }, | |
1129 | }; | |
1130 | ||
1131 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { | |
1132 | F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), | |
1133 | F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), | |
1134 | F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), | |
1135 | F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
1136 | { } | |
1137 | }; | |
1138 | ||
1139 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { | |
1140 | .cmd_rcgr = 0xf020, | |
1141 | .mnd_width = 8, | |
1142 | .hid_width = 5, | |
1143 | .parent_map = gcc_parent_map_0, | |
1144 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1145 | .clkr.hw.init = &(struct clk_init_data){ | |
1146 | .name = "gcc_usb30_prim_master_clk_src", | |
1147 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1148 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1149 | .flags = CLK_SET_RATE_PARENT, |
1150 | .ops = &clk_rcg2_ops, | |
1151 | }, | |
1152 | }; | |
1153 | ||
1154 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { | |
1155 | .cmd_rcgr = 0xf038, | |
1156 | .mnd_width = 0, | |
1157 | .hid_width = 5, | |
1158 | .parent_map = gcc_parent_map_0, | |
1159 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1160 | .clkr.hw.init = &(struct clk_init_data){ | |
1161 | .name = "gcc_usb30_prim_mock_utmi_clk_src", | |
1162 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1163 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1164 | .flags = CLK_SET_RATE_PARENT, |
1165 | .ops = &clk_rcg2_ops, | |
1166 | }, | |
1167 | }; | |
1168 | ||
1169 | static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { | |
1170 | .cmd_rcgr = 0x10020, | |
1171 | .mnd_width = 8, | |
1172 | .hid_width = 5, | |
1173 | .parent_map = gcc_parent_map_0, | |
1174 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1175 | .clkr.hw.init = &(struct clk_init_data){ | |
1176 | .name = "gcc_usb30_sec_master_clk_src", | |
1177 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1178 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1179 | .flags = CLK_SET_RATE_PARENT, |
1180 | .ops = &clk_rcg2_ops, | |
1181 | }, | |
1182 | }; | |
1183 | ||
1184 | static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { | |
1185 | .cmd_rcgr = 0x10038, | |
1186 | .mnd_width = 0, | |
1187 | .hid_width = 5, | |
1188 | .parent_map = gcc_parent_map_0, | |
1189 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1190 | .clkr.hw.init = &(struct clk_init_data){ | |
1191 | .name = "gcc_usb30_sec_mock_utmi_clk_src", | |
1192 | .parent_data = gcc_parent_data_0, | |
886fd9a4 | 1193 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), |
44c20c9e VA |
1194 | .flags = CLK_SET_RATE_PARENT, |
1195 | .ops = &clk_rcg2_ops, | |
1196 | }, | |
1197 | }; | |
1198 | ||
1199 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { | |
1200 | .cmd_rcgr = 0xf064, | |
1201 | .mnd_width = 0, | |
1202 | .hid_width = 5, | |
1203 | .parent_map = gcc_parent_map_2, | |
1204 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1205 | .clkr.hw.init = &(struct clk_init_data){ | |
1206 | .name = "gcc_usb3_prim_phy_aux_clk_src", | |
1207 | .parent_data = gcc_parent_data_2, | |
886fd9a4 | 1208 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), |
44c20c9e VA |
1209 | .flags = CLK_SET_RATE_PARENT, |
1210 | .ops = &clk_rcg2_ops, | |
1211 | }, | |
1212 | }; | |
1213 | ||
1214 | static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { | |
1215 | .cmd_rcgr = 0x10064, | |
1216 | .mnd_width = 0, | |
1217 | .hid_width = 5, | |
1218 | .parent_map = gcc_parent_map_2, | |
1219 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1220 | .clkr.hw.init = &(struct clk_init_data){ | |
1221 | .name = "gcc_usb3_sec_phy_aux_clk_src", | |
1222 | .parent_data = gcc_parent_data_2, | |
886fd9a4 | 1223 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), |
44c20c9e VA |
1224 | .flags = CLK_SET_RATE_PARENT, |
1225 | .ops = &clk_rcg2_ops, | |
1226 | }, | |
1227 | }; | |
1228 | ||
1229 | static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { | |
1230 | .reg = 0xf050, | |
1231 | .shift = 0, | |
1232 | .width = 4, | |
1233 | .clkr.hw.init = &(struct clk_init_data) { | |
1234 | .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", | |
097a8888 DB |
1235 | .parent_hws = (const struct clk_hw*[]){ |
1236 | &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, | |
44c20c9e VA |
1237 | }, |
1238 | .num_parents = 1, | |
1239 | .flags = CLK_SET_RATE_PARENT, | |
1240 | .ops = &clk_regmap_div_ro_ops, | |
1241 | }, | |
1242 | }; | |
1243 | ||
1244 | static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { | |
1245 | .reg = 0x10050, | |
1246 | .shift = 0, | |
1247 | .width = 4, | |
1248 | .clkr.hw.init = &(struct clk_init_data) { | |
1249 | .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", | |
097a8888 DB |
1250 | .parent_hws = (const struct clk_hw*[]){ |
1251 | &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, | |
44c20c9e VA |
1252 | }, |
1253 | .num_parents = 1, | |
1254 | .flags = CLK_SET_RATE_PARENT, | |
1255 | .ops = &clk_regmap_div_ro_ops, | |
1256 | }, | |
1257 | }; | |
1258 | ||
1259 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1260 | static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { | |
1261 | .halt_reg = 0x6b080, | |
1262 | .halt_check = BRANCH_HALT_SKIP, | |
1263 | .clkr = { | |
1264 | .enable_reg = 0x52000, | |
1265 | .enable_mask = BIT(12), | |
1266 | .hw.init = &(struct clk_init_data){ | |
1267 | .name = "gcc_aggre_noc_pcie_0_axi_clk", | |
1268 | .ops = &clk_branch2_ops, | |
1269 | }, | |
1270 | }, | |
1271 | }; | |
1272 | ||
1273 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1274 | static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { | |
1275 | .halt_reg = 0x8d084, | |
1276 | .halt_check = BRANCH_HALT_SKIP, | |
1277 | .clkr = { | |
1278 | .enable_reg = 0x52000, | |
1279 | .enable_mask = BIT(11), | |
1280 | .hw.init = &(struct clk_init_data){ | |
1281 | .name = "gcc_aggre_noc_pcie_1_axi_clk", | |
1282 | .ops = &clk_branch2_ops, | |
1283 | }, | |
1284 | }, | |
1285 | }; | |
1286 | ||
1287 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { | |
1288 | .halt_reg = 0x9000c, | |
1289 | .halt_check = BRANCH_HALT_VOTED, | |
1290 | .hwcg_reg = 0x9000c, | |
1291 | .hwcg_bit = 1, | |
1292 | .clkr = { | |
1293 | .enable_reg = 0x52000, | |
1294 | .enable_mask = BIT(18), | |
1295 | .hw.init = &(struct clk_init_data){ | |
1296 | .name = "gcc_aggre_noc_pcie_tbu_clk", | |
1297 | .ops = &clk_branch2_ops, | |
1298 | }, | |
1299 | }, | |
1300 | }; | |
1301 | ||
1302 | static struct clk_branch gcc_aggre_ufs_card_axi_clk = { | |
1303 | .halt_reg = 0x750cc, | |
1304 | .halt_check = BRANCH_HALT_VOTED, | |
1305 | .hwcg_reg = 0x750cc, | |
1306 | .hwcg_bit = 1, | |
1307 | .clkr = { | |
1308 | .enable_reg = 0x750cc, | |
1309 | .enable_mask = BIT(0), | |
1310 | .hw.init = &(struct clk_init_data){ | |
1311 | .name = "gcc_aggre_ufs_card_axi_clk", | |
097a8888 DB |
1312 | .parent_hws = (const struct clk_hw*[]){ |
1313 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
44c20c9e VA |
1314 | }, |
1315 | .num_parents = 1, | |
1316 | .flags = CLK_SET_RATE_PARENT, | |
1317 | .ops = &clk_branch2_ops, | |
1318 | }, | |
1319 | }, | |
1320 | }; | |
1321 | ||
1322 | static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { | |
1323 | .halt_reg = 0x750cc, | |
1324 | .halt_check = BRANCH_HALT_VOTED, | |
1325 | .hwcg_reg = 0x750cc, | |
1326 | .hwcg_bit = 1, | |
1327 | .clkr = { | |
1328 | .enable_reg = 0x750cc, | |
1329 | .enable_mask = BIT(1), | |
1330 | .hw.init = &(struct clk_init_data){ | |
1331 | .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", | |
097a8888 DB |
1332 | .parent_hws = (const struct clk_hw*[]){ |
1333 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
44c20c9e VA |
1334 | }, |
1335 | .num_parents = 1, | |
1336 | .flags = CLK_SET_RATE_PARENT, | |
1337 | .ops = &clk_branch2_ops, | |
1338 | }, | |
1339 | }, | |
1340 | }; | |
1341 | ||
1342 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { | |
1343 | .halt_reg = 0x770cc, | |
1344 | .halt_check = BRANCH_HALT_VOTED, | |
1345 | .hwcg_reg = 0x770cc, | |
1346 | .hwcg_bit = 1, | |
1347 | .clkr = { | |
1348 | .enable_reg = 0x770cc, | |
1349 | .enable_mask = BIT(0), | |
1350 | .hw.init = &(struct clk_init_data){ | |
1351 | .name = "gcc_aggre_ufs_phy_axi_clk", | |
097a8888 DB |
1352 | .parent_hws = (const struct clk_hw*[]){ |
1353 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
44c20c9e VA |
1354 | }, |
1355 | .num_parents = 1, | |
1356 | .flags = CLK_SET_RATE_PARENT, | |
1357 | .ops = &clk_branch2_ops, | |
1358 | }, | |
1359 | }, | |
1360 | }; | |
1361 | ||
1362 | static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { | |
1363 | .halt_reg = 0x770cc, | |
1364 | .halt_check = BRANCH_HALT_VOTED, | |
1365 | .hwcg_reg = 0x770cc, | |
1366 | .hwcg_bit = 1, | |
1367 | .clkr = { | |
1368 | .enable_reg = 0x770cc, | |
1369 | .enable_mask = BIT(1), | |
1370 | .hw.init = &(struct clk_init_data){ | |
1371 | .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", | |
097a8888 DB |
1372 | .parent_hws = (const struct clk_hw*[]){ |
1373 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
44c20c9e VA |
1374 | }, |
1375 | .num_parents = 1, | |
1376 | .flags = CLK_SET_RATE_PARENT, | |
1377 | .ops = &clk_branch2_ops, | |
1378 | }, | |
1379 | }, | |
1380 | }; | |
1381 | ||
1382 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { | |
1383 | .halt_reg = 0xf080, | |
1384 | .halt_check = BRANCH_HALT_VOTED, | |
1385 | .hwcg_reg = 0xf080, | |
1386 | .hwcg_bit = 1, | |
1387 | .clkr = { | |
1388 | .enable_reg = 0xf080, | |
1389 | .enable_mask = BIT(0), | |
1390 | .hw.init = &(struct clk_init_data){ | |
1391 | .name = "gcc_aggre_usb3_prim_axi_clk", | |
097a8888 DB |
1392 | .parent_hws = (const struct clk_hw*[]){ |
1393 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
44c20c9e VA |
1394 | }, |
1395 | .num_parents = 1, | |
1396 | .flags = CLK_SET_RATE_PARENT, | |
1397 | .ops = &clk_branch2_ops, | |
1398 | }, | |
1399 | }, | |
1400 | }; | |
1401 | ||
1402 | static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { | |
1403 | .halt_reg = 0x10080, | |
1404 | .halt_check = BRANCH_HALT_VOTED, | |
1405 | .hwcg_reg = 0x10080, | |
1406 | .hwcg_bit = 1, | |
1407 | .clkr = { | |
1408 | .enable_reg = 0x10080, | |
1409 | .enable_mask = BIT(0), | |
1410 | .hw.init = &(struct clk_init_data){ | |
1411 | .name = "gcc_aggre_usb3_sec_axi_clk", | |
097a8888 DB |
1412 | .parent_hws = (const struct clk_hw*[]){ |
1413 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
44c20c9e VA |
1414 | }, |
1415 | .num_parents = 1, | |
1416 | .flags = CLK_SET_RATE_PARENT, | |
1417 | .ops = &clk_branch2_ops, | |
1418 | }, | |
1419 | }, | |
1420 | }; | |
1421 | ||
1422 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1423 | .halt_reg = 0x38004, | |
1424 | .halt_check = BRANCH_HALT_VOTED, | |
1425 | .hwcg_reg = 0x38004, | |
1426 | .hwcg_bit = 1, | |
1427 | .clkr = { | |
1428 | .enable_reg = 0x52000, | |
1429 | .enable_mask = BIT(10), | |
1430 | .hw.init = &(struct clk_init_data){ | |
1431 | .name = "gcc_boot_rom_ahb_clk", | |
1432 | .ops = &clk_branch2_ops, | |
1433 | }, | |
1434 | }, | |
1435 | }; | |
1436 | ||
1437 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1438 | static struct clk_branch gcc_camera_hf_axi_clk = { | |
1439 | .halt_reg = 0x26010, | |
1440 | .halt_check = BRANCH_HALT_SKIP, | |
1441 | .hwcg_reg = 0x26010, | |
1442 | .hwcg_bit = 1, | |
1443 | .clkr = { | |
1444 | .enable_reg = 0x26010, | |
1445 | .enable_mask = BIT(0), | |
1446 | .hw.init = &(struct clk_init_data){ | |
1447 | .name = "gcc_camera_hf_axi_clk", | |
1448 | .ops = &clk_branch2_ops, | |
1449 | }, | |
1450 | }, | |
1451 | }; | |
1452 | ||
1453 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1454 | static struct clk_branch gcc_camera_sf_axi_clk = { | |
1455 | .halt_reg = 0x26014, | |
1456 | .halt_check = BRANCH_HALT_SKIP, | |
1457 | .hwcg_reg = 0x26014, | |
1458 | .hwcg_bit = 1, | |
1459 | .clkr = { | |
1460 | .enable_reg = 0x26014, | |
1461 | .enable_mask = BIT(0), | |
1462 | .hw.init = &(struct clk_init_data){ | |
1463 | .name = "gcc_camera_sf_axi_clk", | |
1464 | .ops = &clk_branch2_ops, | |
1465 | }, | |
1466 | }, | |
1467 | }; | |
1468 | ||
1469 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { | |
1470 | .halt_reg = 0xf07c, | |
1471 | .halt_check = BRANCH_HALT_VOTED, | |
1472 | .hwcg_reg = 0xf07c, | |
1473 | .hwcg_bit = 1, | |
1474 | .clkr = { | |
1475 | .enable_reg = 0xf07c, | |
1476 | .enable_mask = BIT(0), | |
1477 | .hw.init = &(struct clk_init_data){ | |
1478 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", | |
097a8888 DB |
1479 | .parent_hws = (const struct clk_hw*[]){ |
1480 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
44c20c9e VA |
1481 | }, |
1482 | .num_parents = 1, | |
1483 | .flags = CLK_SET_RATE_PARENT, | |
1484 | .ops = &clk_branch2_ops, | |
1485 | }, | |
1486 | }, | |
1487 | }; | |
1488 | ||
1489 | static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { | |
1490 | .halt_reg = 0x1007c, | |
1491 | .halt_check = BRANCH_HALT_VOTED, | |
1492 | .hwcg_reg = 0x1007c, | |
1493 | .hwcg_bit = 1, | |
1494 | .clkr = { | |
1495 | .enable_reg = 0x1007c, | |
1496 | .enable_mask = BIT(0), | |
1497 | .hw.init = &(struct clk_init_data){ | |
1498 | .name = "gcc_cfg_noc_usb3_sec_axi_clk", | |
097a8888 DB |
1499 | .parent_hws = (const struct clk_hw*[]){ |
1500 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
44c20c9e VA |
1501 | }, |
1502 | .num_parents = 1, | |
1503 | .flags = CLK_SET_RATE_PARENT, | |
1504 | .ops = &clk_branch2_ops, | |
1505 | }, | |
1506 | }, | |
1507 | }; | |
1508 | ||
1509 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1510 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { | |
1511 | .halt_reg = 0x71154, | |
1512 | .halt_check = BRANCH_HALT_SKIP, | |
1513 | .hwcg_reg = 0x71154, | |
1514 | .hwcg_bit = 1, | |
1515 | .clkr = { | |
1516 | .enable_reg = 0x71154, | |
1517 | .enable_mask = BIT(0), | |
1518 | .hw.init = &(struct clk_init_data){ | |
1519 | .name = "gcc_ddrss_gpu_axi_clk", | |
1520 | .ops = &clk_branch2_aon_ops, | |
1521 | }, | |
1522 | }, | |
1523 | }; | |
1524 | ||
1525 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1526 | static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { | |
1527 | .halt_reg = 0x8d080, | |
1528 | .halt_check = BRANCH_HALT_SKIP, | |
1529 | .hwcg_reg = 0x8d080, | |
1530 | .hwcg_bit = 1, | |
1531 | .clkr = { | |
1532 | .enable_reg = 0x52000, | |
1533 | .enable_mask = BIT(19), | |
1534 | .hw.init = &(struct clk_init_data){ | |
1535 | .name = "gcc_ddrss_pcie_sf_tbu_clk", | |
1536 | .ops = &clk_branch2_ops, | |
1537 | }, | |
1538 | }, | |
1539 | }; | |
1540 | ||
1541 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1542 | static struct clk_branch gcc_disp_hf_axi_clk = { | |
1543 | .halt_reg = 0x2700c, | |
1544 | .halt_check = BRANCH_HALT_SKIP, | |
1545 | .hwcg_reg = 0x2700c, | |
1546 | .hwcg_bit = 1, | |
1547 | .clkr = { | |
1548 | .enable_reg = 0x2700c, | |
1549 | .enable_mask = BIT(0), | |
1550 | .hw.init = &(struct clk_init_data){ | |
1551 | .name = "gcc_disp_hf_axi_clk", | |
1552 | .ops = &clk_branch2_ops, | |
1553 | }, | |
1554 | }, | |
1555 | }; | |
1556 | ||
1557 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1558 | static struct clk_branch gcc_disp_sf_axi_clk = { | |
1559 | .halt_reg = 0x27014, | |
1560 | .halt_check = BRANCH_HALT_SKIP, | |
1561 | .hwcg_reg = 0x27014, | |
1562 | .hwcg_bit = 1, | |
1563 | .clkr = { | |
1564 | .enable_reg = 0x27014, | |
1565 | .enable_mask = BIT(0), | |
1566 | .hw.init = &(struct clk_init_data){ | |
1567 | .name = "gcc_disp_sf_axi_clk", | |
1568 | .ops = &clk_branch2_ops, | |
1569 | }, | |
1570 | }, | |
1571 | }; | |
1572 | ||
1573 | static struct clk_branch gcc_gp1_clk = { | |
1574 | .halt_reg = 0x64000, | |
1575 | .halt_check = BRANCH_HALT, | |
1576 | .clkr = { | |
1577 | .enable_reg = 0x64000, | |
1578 | .enable_mask = BIT(0), | |
1579 | .hw.init = &(struct clk_init_data){ | |
1580 | .name = "gcc_gp1_clk", | |
097a8888 DB |
1581 | .parent_hws = (const struct clk_hw*[]){ |
1582 | &gcc_gp1_clk_src.clkr.hw, | |
44c20c9e VA |
1583 | }, |
1584 | .num_parents = 1, | |
1585 | .flags = CLK_SET_RATE_PARENT, | |
1586 | .ops = &clk_branch2_ops, | |
1587 | }, | |
1588 | }, | |
1589 | }; | |
1590 | ||
1591 | static struct clk_branch gcc_gp2_clk = { | |
1592 | .halt_reg = 0x65000, | |
1593 | .halt_check = BRANCH_HALT, | |
1594 | .clkr = { | |
1595 | .enable_reg = 0x65000, | |
1596 | .enable_mask = BIT(0), | |
1597 | .hw.init = &(struct clk_init_data){ | |
1598 | .name = "gcc_gp2_clk", | |
097a8888 DB |
1599 | .parent_hws = (const struct clk_hw*[]){ |
1600 | &gcc_gp2_clk_src.clkr.hw, | |
44c20c9e VA |
1601 | }, |
1602 | .num_parents = 1, | |
1603 | .flags = CLK_SET_RATE_PARENT, | |
1604 | .ops = &clk_branch2_ops, | |
1605 | }, | |
1606 | }, | |
1607 | }; | |
1608 | ||
1609 | static struct clk_branch gcc_gp3_clk = { | |
1610 | .halt_reg = 0x66000, | |
1611 | .halt_check = BRANCH_HALT, | |
1612 | .clkr = { | |
1613 | .enable_reg = 0x66000, | |
1614 | .enable_mask = BIT(0), | |
1615 | .hw.init = &(struct clk_init_data){ | |
1616 | .name = "gcc_gp3_clk", | |
097a8888 DB |
1617 | .parent_hws = (const struct clk_hw*[]){ |
1618 | &gcc_gp3_clk_src.clkr.hw, | |
44c20c9e VA |
1619 | }, |
1620 | .num_parents = 1, | |
1621 | .flags = CLK_SET_RATE_PARENT, | |
1622 | .ops = &clk_branch2_ops, | |
1623 | }, | |
1624 | }, | |
1625 | }; | |
1626 | ||
1627 | /* Clock ON depends on external parent clock, so don't poll */ | |
1628 | static struct clk_branch gcc_gpu_gpll0_clk_src = { | |
1629 | .halt_check = BRANCH_HALT_DELAY, | |
1630 | .clkr = { | |
1631 | .enable_reg = 0x52000, | |
1632 | .enable_mask = BIT(15), | |
1633 | .hw.init = &(struct clk_init_data){ | |
1634 | .name = "gcc_gpu_gpll0_clk_src", | |
097a8888 DB |
1635 | .parent_hws = (const struct clk_hw*[]){ |
1636 | &gcc_gpll0.clkr.hw, | |
44c20c9e VA |
1637 | }, |
1638 | .num_parents = 1, | |
1639 | .flags = CLK_SET_RATE_PARENT, | |
1640 | .ops = &clk_branch2_ops, | |
1641 | }, | |
1642 | }, | |
1643 | }; | |
1644 | ||
1645 | /* Clock ON depends on external parent clock, so don't poll */ | |
1646 | static struct clk_branch gcc_gpu_gpll0_div_clk_src = { | |
1647 | .halt_check = BRANCH_HALT_DELAY, | |
1648 | .clkr = { | |
1649 | .enable_reg = 0x52000, | |
1650 | .enable_mask = BIT(16), | |
1651 | .hw.init = &(struct clk_init_data){ | |
1652 | .name = "gcc_gpu_gpll0_div_clk_src", | |
097a8888 DB |
1653 | .parent_hws = (const struct clk_hw*[]){ |
1654 | &gcc_gpll0_out_even.clkr.hw, | |
44c20c9e VA |
1655 | }, |
1656 | .num_parents = 1, | |
1657 | .flags = CLK_SET_RATE_PARENT, | |
1658 | .ops = &clk_branch2_ops, | |
1659 | }, | |
1660 | }, | |
1661 | }; | |
1662 | ||
1663 | static struct clk_branch gcc_gpu_iref_en = { | |
1664 | .halt_reg = 0x8c014, | |
1665 | .halt_check = BRANCH_HALT, | |
1666 | .clkr = { | |
1667 | .enable_reg = 0x8c014, | |
1668 | .enable_mask = BIT(0), | |
1669 | .hw.init = &(struct clk_init_data){ | |
1670 | .name = "gcc_gpu_iref_en", | |
1671 | .ops = &clk_branch2_ops, | |
1672 | }, | |
1673 | }, | |
1674 | }; | |
1675 | ||
1676 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { | |
1677 | .halt_reg = 0x7100c, | |
1678 | .halt_check = BRANCH_HALT_VOTED, | |
1679 | .hwcg_reg = 0x7100c, | |
1680 | .hwcg_bit = 1, | |
1681 | .clkr = { | |
1682 | .enable_reg = 0x7100c, | |
1683 | .enable_mask = BIT(0), | |
1684 | .hw.init = &(struct clk_init_data){ | |
1685 | .name = "gcc_gpu_memnoc_gfx_clk", | |
1686 | .ops = &clk_branch2_aon_ops, | |
1687 | }, | |
1688 | }, | |
1689 | }; | |
1690 | ||
1691 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { | |
1692 | .halt_reg = 0x71018, | |
1693 | .halt_check = BRANCH_HALT, | |
1694 | .clkr = { | |
1695 | .enable_reg = 0x71018, | |
1696 | .enable_mask = BIT(0), | |
1697 | .hw.init = &(struct clk_init_data){ | |
1698 | .name = "gcc_gpu_snoc_dvm_gfx_clk", | |
1699 | .ops = &clk_branch2_aon_ops, | |
1700 | }, | |
1701 | }, | |
1702 | }; | |
1703 | ||
1704 | static struct clk_branch gcc_pcie0_phy_rchng_clk = { | |
1705 | .halt_reg = 0x6b038, | |
1706 | .halt_check = BRANCH_HALT_VOTED, | |
1707 | .clkr = { | |
1708 | .enable_reg = 0x52000, | |
1709 | .enable_mask = BIT(22), | |
1710 | .hw.init = &(struct clk_init_data){ | |
1711 | .name = "gcc_pcie0_phy_rchng_clk", | |
097a8888 DB |
1712 | .parent_hws = (const struct clk_hw*[]){ |
1713 | &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, | |
44c20c9e VA |
1714 | }, |
1715 | .num_parents = 1, | |
1716 | .flags = CLK_SET_RATE_PARENT, | |
1717 | .ops = &clk_branch2_ops, | |
1718 | }, | |
1719 | }, | |
1720 | }; | |
1721 | ||
1722 | static struct clk_branch gcc_pcie1_phy_rchng_clk = { | |
1723 | .halt_reg = 0x8d038, | |
1724 | .halt_check = BRANCH_HALT_VOTED, | |
1725 | .clkr = { | |
1726 | .enable_reg = 0x52000, | |
1727 | .enable_mask = BIT(23), | |
1728 | .hw.init = &(struct clk_init_data){ | |
1729 | .name = "gcc_pcie1_phy_rchng_clk", | |
097a8888 DB |
1730 | .parent_hws = (const struct clk_hw*[]){ |
1731 | &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, | |
44c20c9e VA |
1732 | }, |
1733 | .num_parents = 1, | |
1734 | .flags = CLK_SET_RATE_PARENT, | |
1735 | .ops = &clk_branch2_ops, | |
1736 | }, | |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static struct clk_branch gcc_pcie_0_aux_clk = { | |
1741 | .halt_reg = 0x6b028, | |
1742 | .halt_check = BRANCH_HALT_VOTED, | |
1743 | .clkr = { | |
1744 | .enable_reg = 0x52008, | |
1745 | .enable_mask = BIT(3), | |
1746 | .hw.init = &(struct clk_init_data){ | |
1747 | .name = "gcc_pcie_0_aux_clk", | |
097a8888 DB |
1748 | .parent_hws = (const struct clk_hw*[]){ |
1749 | &gcc_pcie_0_aux_clk_src.clkr.hw, | |
44c20c9e VA |
1750 | }, |
1751 | .num_parents = 1, | |
1752 | .flags = CLK_SET_RATE_PARENT, | |
1753 | .ops = &clk_branch2_ops, | |
1754 | }, | |
1755 | }, | |
1756 | }; | |
1757 | ||
1758 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
1759 | .halt_reg = 0x6b024, | |
1760 | .halt_check = BRANCH_HALT_VOTED, | |
1761 | .hwcg_reg = 0x6b024, | |
1762 | .hwcg_bit = 1, | |
1763 | .clkr = { | |
1764 | .enable_reg = 0x52008, | |
1765 | .enable_mask = BIT(2), | |
1766 | .hw.init = &(struct clk_init_data){ | |
1767 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
1768 | .ops = &clk_branch2_ops, | |
1769 | }, | |
1770 | }, | |
1771 | }; | |
1772 | ||
1773 | static struct clk_branch gcc_pcie_0_clkref_en = { | |
1774 | .halt_reg = 0x8c004, | |
1775 | .halt_check = BRANCH_HALT, | |
1776 | .clkr = { | |
1777 | .enable_reg = 0x8c004, | |
1778 | .enable_mask = BIT(0), | |
1779 | .hw.init = &(struct clk_init_data){ | |
1780 | .name = "gcc_pcie_0_clkref_en", | |
1781 | .ops = &clk_branch2_ops, | |
1782 | }, | |
1783 | }, | |
1784 | }; | |
1785 | ||
1786 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1787 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
1788 | .halt_reg = 0x6b01c, | |
1789 | .halt_check = BRANCH_HALT_SKIP, | |
1790 | .hwcg_reg = 0x6b01c, | |
1791 | .hwcg_bit = 1, | |
1792 | .clkr = { | |
1793 | .enable_reg = 0x52008, | |
1794 | .enable_mask = BIT(1), | |
1795 | .hw.init = &(struct clk_init_data){ | |
1796 | .name = "gcc_pcie_0_mstr_axi_clk", | |
1797 | .ops = &clk_branch2_ops, | |
1798 | }, | |
1799 | }, | |
1800 | }; | |
1801 | ||
1802 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1803 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
1804 | .halt_reg = 0x6b030, | |
1805 | .halt_check = BRANCH_HALT_SKIP, | |
1806 | .clkr = { | |
1807 | .enable_reg = 0x52008, | |
1808 | .enable_mask = BIT(4), | |
1809 | .hw.init = &(struct clk_init_data){ | |
1810 | .name = "gcc_pcie_0_pipe_clk", | |
097a8888 DB |
1811 | .parent_hws = (const struct clk_hw*[]){ |
1812 | &gcc_pcie_0_pipe_clk_src.clkr.hw, | |
44c20c9e VA |
1813 | }, |
1814 | .num_parents = 1, | |
1815 | .flags = CLK_SET_RATE_PARENT, | |
1816 | .ops = &clk_branch2_ops, | |
1817 | }, | |
1818 | }, | |
1819 | }; | |
1820 | ||
1821 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
1822 | .halt_reg = 0x6b014, | |
1823 | .halt_check = BRANCH_HALT_VOTED, | |
1824 | .hwcg_reg = 0x6b014, | |
1825 | .hwcg_bit = 1, | |
1826 | .clkr = { | |
1827 | .enable_reg = 0x52008, | |
1828 | .enable_mask = BIT(0), | |
1829 | .hw.init = &(struct clk_init_data){ | |
1830 | .name = "gcc_pcie_0_slv_axi_clk", | |
1831 | .ops = &clk_branch2_ops, | |
1832 | }, | |
1833 | }, | |
1834 | }; | |
1835 | ||
1836 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { | |
1837 | .halt_reg = 0x6b010, | |
1838 | .halt_check = BRANCH_HALT_VOTED, | |
1839 | .clkr = { | |
1840 | .enable_reg = 0x52008, | |
1841 | .enable_mask = BIT(5), | |
1842 | .hw.init = &(struct clk_init_data){ | |
1843 | .name = "gcc_pcie_0_slv_q2a_axi_clk", | |
1844 | .ops = &clk_branch2_ops, | |
1845 | }, | |
1846 | }, | |
1847 | }; | |
1848 | ||
1849 | static struct clk_branch gcc_pcie_1_aux_clk = { | |
1850 | .halt_reg = 0x8d028, | |
1851 | .halt_check = BRANCH_HALT_VOTED, | |
1852 | .clkr = { | |
1853 | .enable_reg = 0x52000, | |
1854 | .enable_mask = BIT(29), | |
1855 | .hw.init = &(struct clk_init_data){ | |
1856 | .name = "gcc_pcie_1_aux_clk", | |
097a8888 DB |
1857 | .parent_hws = (const struct clk_hw*[]){ |
1858 | &gcc_pcie_1_aux_clk_src.clkr.hw, | |
44c20c9e VA |
1859 | }, |
1860 | .num_parents = 1, | |
1861 | .flags = CLK_SET_RATE_PARENT, | |
1862 | .ops = &clk_branch2_ops, | |
1863 | }, | |
1864 | }, | |
1865 | }; | |
1866 | ||
1867 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { | |
1868 | .halt_reg = 0x8d024, | |
1869 | .halt_check = BRANCH_HALT_VOTED, | |
1870 | .hwcg_reg = 0x8d024, | |
1871 | .hwcg_bit = 1, | |
1872 | .clkr = { | |
1873 | .enable_reg = 0x52000, | |
1874 | .enable_mask = BIT(28), | |
1875 | .hw.init = &(struct clk_init_data){ | |
1876 | .name = "gcc_pcie_1_cfg_ahb_clk", | |
1877 | .ops = &clk_branch2_ops, | |
1878 | }, | |
1879 | }, | |
1880 | }; | |
1881 | ||
1882 | static struct clk_branch gcc_pcie_1_clkref_en = { | |
1883 | .halt_reg = 0x8c008, | |
1884 | .halt_check = BRANCH_HALT, | |
1885 | .clkr = { | |
1886 | .enable_reg = 0x8c008, | |
1887 | .enable_mask = BIT(0), | |
1888 | .hw.init = &(struct clk_init_data){ | |
1889 | .name = "gcc_pcie_1_clkref_en", | |
1890 | .ops = &clk_branch2_ops, | |
1891 | }, | |
1892 | }, | |
1893 | }; | |
1894 | ||
1895 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1896 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { | |
1897 | .halt_reg = 0x8d01c, | |
1898 | .halt_check = BRANCH_HALT_SKIP, | |
1899 | .hwcg_reg = 0x8d01c, | |
1900 | .hwcg_bit = 1, | |
1901 | .clkr = { | |
1902 | .enable_reg = 0x52000, | |
1903 | .enable_mask = BIT(27), | |
1904 | .hw.init = &(struct clk_init_data){ | |
1905 | .name = "gcc_pcie_1_mstr_axi_clk", | |
1906 | .ops = &clk_branch2_ops, | |
1907 | }, | |
1908 | }, | |
1909 | }; | |
1910 | ||
1911 | /* external clocks so add BRANCH_HALT_SKIP */ | |
1912 | static struct clk_branch gcc_pcie_1_pipe_clk = { | |
1913 | .halt_reg = 0x8d030, | |
1914 | .halt_check = BRANCH_HALT_SKIP, | |
1915 | .clkr = { | |
1916 | .enable_reg = 0x52000, | |
1917 | .enable_mask = BIT(30), | |
1918 | .hw.init = &(struct clk_init_data){ | |
1919 | .name = "gcc_pcie_1_pipe_clk", | |
097a8888 DB |
1920 | .parent_hws = (const struct clk_hw*[]){ |
1921 | &gcc_pcie_1_pipe_clk_src.clkr.hw, | |
44c20c9e VA |
1922 | }, |
1923 | .num_parents = 1, | |
1924 | .flags = CLK_SET_RATE_PARENT, | |
1925 | .ops = &clk_branch2_ops, | |
1926 | }, | |
1927 | }, | |
1928 | }; | |
1929 | ||
1930 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { | |
1931 | .halt_reg = 0x8d014, | |
1932 | .halt_check = BRANCH_HALT_VOTED, | |
1933 | .hwcg_reg = 0x8d014, | |
1934 | .hwcg_bit = 1, | |
1935 | .clkr = { | |
1936 | .enable_reg = 0x52000, | |
1937 | .enable_mask = BIT(26), | |
1938 | .hw.init = &(struct clk_init_data){ | |
1939 | .name = "gcc_pcie_1_slv_axi_clk", | |
1940 | .ops = &clk_branch2_ops, | |
1941 | }, | |
1942 | }, | |
1943 | }; | |
1944 | ||
1945 | static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { | |
1946 | .halt_reg = 0x8d010, | |
1947 | .halt_check = BRANCH_HALT_VOTED, | |
1948 | .clkr = { | |
1949 | .enable_reg = 0x52000, | |
1950 | .enable_mask = BIT(25), | |
1951 | .hw.init = &(struct clk_init_data){ | |
1952 | .name = "gcc_pcie_1_slv_q2a_axi_clk", | |
1953 | .ops = &clk_branch2_ops, | |
1954 | }, | |
1955 | }, | |
1956 | }; | |
1957 | ||
1958 | static struct clk_branch gcc_pdm2_clk = { | |
1959 | .halt_reg = 0x3300c, | |
1960 | .halt_check = BRANCH_HALT, | |
1961 | .clkr = { | |
1962 | .enable_reg = 0x3300c, | |
1963 | .enable_mask = BIT(0), | |
1964 | .hw.init = &(struct clk_init_data){ | |
1965 | .name = "gcc_pdm2_clk", | |
097a8888 DB |
1966 | .parent_hws = (const struct clk_hw*[]){ |
1967 | &gcc_pdm2_clk_src.clkr.hw, | |
44c20c9e VA |
1968 | }, |
1969 | .num_parents = 1, | |
1970 | .flags = CLK_SET_RATE_PARENT, | |
1971 | .ops = &clk_branch2_ops, | |
1972 | }, | |
1973 | }, | |
1974 | }; | |
1975 | ||
1976 | static struct clk_branch gcc_pdm_ahb_clk = { | |
1977 | .halt_reg = 0x33004, | |
1978 | .halt_check = BRANCH_HALT_VOTED, | |
1979 | .hwcg_reg = 0x33004, | |
1980 | .hwcg_bit = 1, | |
1981 | .clkr = { | |
1982 | .enable_reg = 0x33004, | |
1983 | .enable_mask = BIT(0), | |
1984 | .hw.init = &(struct clk_init_data){ | |
1985 | .name = "gcc_pdm_ahb_clk", | |
1986 | .ops = &clk_branch2_ops, | |
1987 | }, | |
1988 | }, | |
1989 | }; | |
1990 | ||
1991 | static struct clk_branch gcc_pdm_xo4_clk = { | |
1992 | .halt_reg = 0x33008, | |
1993 | .halt_check = BRANCH_HALT, | |
1994 | .clkr = { | |
1995 | .enable_reg = 0x33008, | |
1996 | .enable_mask = BIT(0), | |
1997 | .hw.init = &(struct clk_init_data){ | |
1998 | .name = "gcc_pdm_xo4_clk", | |
1999 | .ops = &clk_branch2_ops, | |
2000 | }, | |
2001 | }, | |
2002 | }; | |
2003 | ||
2004 | static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { | |
2005 | .halt_reg = 0x26008, | |
2006 | .halt_check = BRANCH_HALT_VOTED, | |
2007 | .hwcg_reg = 0x26008, | |
2008 | .hwcg_bit = 1, | |
2009 | .clkr = { | |
2010 | .enable_reg = 0x26008, | |
2011 | .enable_mask = BIT(0), | |
2012 | .hw.init = &(struct clk_init_data){ | |
2013 | .name = "gcc_qmip_camera_nrt_ahb_clk", | |
2014 | .ops = &clk_branch2_ops, | |
2015 | }, | |
2016 | }, | |
2017 | }; | |
2018 | ||
2019 | static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { | |
2020 | .halt_reg = 0x2600c, | |
2021 | .halt_check = BRANCH_HALT_VOTED, | |
2022 | .hwcg_reg = 0x2600c, | |
2023 | .hwcg_bit = 1, | |
2024 | .clkr = { | |
2025 | .enable_reg = 0x2600c, | |
2026 | .enable_mask = BIT(0), | |
2027 | .hw.init = &(struct clk_init_data){ | |
2028 | .name = "gcc_qmip_camera_rt_ahb_clk", | |
2029 | .ops = &clk_branch2_ops, | |
2030 | }, | |
2031 | }, | |
2032 | }; | |
2033 | ||
2034 | static struct clk_branch gcc_qmip_disp_ahb_clk = { | |
2035 | .halt_reg = 0x27008, | |
2036 | .halt_check = BRANCH_HALT_VOTED, | |
2037 | .hwcg_reg = 0x27008, | |
2038 | .hwcg_bit = 1, | |
2039 | .clkr = { | |
2040 | .enable_reg = 0x27008, | |
2041 | .enable_mask = BIT(0), | |
2042 | .hw.init = &(struct clk_init_data){ | |
2043 | .name = "gcc_qmip_disp_ahb_clk", | |
2044 | .ops = &clk_branch2_ops, | |
2045 | }, | |
2046 | }, | |
2047 | }; | |
2048 | ||
2049 | static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { | |
2050 | .halt_reg = 0x28008, | |
2051 | .halt_check = BRANCH_HALT_VOTED, | |
2052 | .hwcg_reg = 0x28008, | |
2053 | .hwcg_bit = 1, | |
2054 | .clkr = { | |
2055 | .enable_reg = 0x28008, | |
2056 | .enable_mask = BIT(0), | |
2057 | .hw.init = &(struct clk_init_data){ | |
2058 | .name = "gcc_qmip_video_cvp_ahb_clk", | |
2059 | .ops = &clk_branch2_ops, | |
2060 | }, | |
2061 | }, | |
2062 | }; | |
2063 | ||
2064 | static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { | |
2065 | .halt_reg = 0x2800c, | |
2066 | .halt_check = BRANCH_HALT_VOTED, | |
2067 | .hwcg_reg = 0x2800c, | |
2068 | .hwcg_bit = 1, | |
2069 | .clkr = { | |
2070 | .enable_reg = 0x2800c, | |
2071 | .enable_mask = BIT(0), | |
2072 | .hw.init = &(struct clk_init_data){ | |
2073 | .name = "gcc_qmip_video_vcodec_ahb_clk", | |
2074 | .ops = &clk_branch2_ops, | |
2075 | }, | |
2076 | }, | |
2077 | }; | |
2078 | ||
2079 | static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { | |
2080 | .halt_reg = 0x23008, | |
2081 | .halt_check = BRANCH_HALT_VOTED, | |
2082 | .clkr = { | |
2083 | .enable_reg = 0x52008, | |
2084 | .enable_mask = BIT(9), | |
2085 | .hw.init = &(struct clk_init_data){ | |
2086 | .name = "gcc_qupv3_wrap0_core_2x_clk", | |
2087 | .ops = &clk_branch2_ops, | |
2088 | }, | |
2089 | }, | |
2090 | }; | |
2091 | ||
2092 | static struct clk_branch gcc_qupv3_wrap0_core_clk = { | |
2093 | .halt_reg = 0x23000, | |
2094 | .halt_check = BRANCH_HALT_VOTED, | |
2095 | .clkr = { | |
2096 | .enable_reg = 0x52008, | |
2097 | .enable_mask = BIT(8), | |
2098 | .hw.init = &(struct clk_init_data){ | |
2099 | .name = "gcc_qupv3_wrap0_core_clk", | |
2100 | .ops = &clk_branch2_ops, | |
2101 | }, | |
2102 | }, | |
2103 | }; | |
2104 | ||
2105 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { | |
2106 | .halt_reg = 0x1700c, | |
2107 | .halt_check = BRANCH_HALT_VOTED, | |
2108 | .clkr = { | |
2109 | .enable_reg = 0x52008, | |
2110 | .enable_mask = BIT(10), | |
2111 | .hw.init = &(struct clk_init_data){ | |
2112 | .name = "gcc_qupv3_wrap0_s0_clk", | |
097a8888 DB |
2113 | .parent_hws = (const struct clk_hw*[]){ |
2114 | &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, | |
44c20c9e VA |
2115 | }, |
2116 | .num_parents = 1, | |
2117 | .flags = CLK_SET_RATE_PARENT, | |
2118 | .ops = &clk_branch2_ops, | |
2119 | }, | |
2120 | }, | |
2121 | }; | |
2122 | ||
2123 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { | |
2124 | .halt_reg = 0x1713c, | |
2125 | .halt_check = BRANCH_HALT_VOTED, | |
2126 | .clkr = { | |
2127 | .enable_reg = 0x52008, | |
2128 | .enable_mask = BIT(11), | |
2129 | .hw.init = &(struct clk_init_data){ | |
2130 | .name = "gcc_qupv3_wrap0_s1_clk", | |
097a8888 DB |
2131 | .parent_hws = (const struct clk_hw*[]){ |
2132 | &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, | |
44c20c9e VA |
2133 | }, |
2134 | .num_parents = 1, | |
2135 | .flags = CLK_SET_RATE_PARENT, | |
2136 | .ops = &clk_branch2_ops, | |
2137 | }, | |
2138 | }, | |
2139 | }; | |
2140 | ||
2141 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { | |
2142 | .halt_reg = 0x1726c, | |
2143 | .halt_check = BRANCH_HALT_VOTED, | |
2144 | .clkr = { | |
2145 | .enable_reg = 0x52008, | |
2146 | .enable_mask = BIT(12), | |
2147 | .hw.init = &(struct clk_init_data){ | |
2148 | .name = "gcc_qupv3_wrap0_s2_clk", | |
097a8888 DB |
2149 | .parent_hws = (const struct clk_hw*[]){ |
2150 | &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, | |
44c20c9e VA |
2151 | }, |
2152 | .num_parents = 1, | |
2153 | .flags = CLK_SET_RATE_PARENT, | |
2154 | .ops = &clk_branch2_ops, | |
2155 | }, | |
2156 | }, | |
2157 | }; | |
2158 | ||
2159 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { | |
2160 | .halt_reg = 0x1739c, | |
2161 | .halt_check = BRANCH_HALT_VOTED, | |
2162 | .clkr = { | |
2163 | .enable_reg = 0x52008, | |
2164 | .enable_mask = BIT(13), | |
2165 | .hw.init = &(struct clk_init_data){ | |
2166 | .name = "gcc_qupv3_wrap0_s3_clk", | |
097a8888 DB |
2167 | .parent_hws = (const struct clk_hw*[]){ |
2168 | &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, | |
44c20c9e VA |
2169 | }, |
2170 | .num_parents = 1, | |
2171 | .flags = CLK_SET_RATE_PARENT, | |
2172 | .ops = &clk_branch2_ops, | |
2173 | }, | |
2174 | }, | |
2175 | }; | |
2176 | ||
2177 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { | |
2178 | .halt_reg = 0x174cc, | |
2179 | .halt_check = BRANCH_HALT_VOTED, | |
2180 | .clkr = { | |
2181 | .enable_reg = 0x52008, | |
2182 | .enable_mask = BIT(14), | |
2183 | .hw.init = &(struct clk_init_data){ | |
2184 | .name = "gcc_qupv3_wrap0_s4_clk", | |
097a8888 DB |
2185 | .parent_hws = (const struct clk_hw*[]){ |
2186 | &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, | |
44c20c9e VA |
2187 | }, |
2188 | .num_parents = 1, | |
2189 | .flags = CLK_SET_RATE_PARENT, | |
2190 | .ops = &clk_branch2_ops, | |
2191 | }, | |
2192 | }, | |
2193 | }; | |
2194 | ||
2195 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { | |
2196 | .halt_reg = 0x175fc, | |
2197 | .halt_check = BRANCH_HALT_VOTED, | |
2198 | .clkr = { | |
2199 | .enable_reg = 0x52008, | |
2200 | .enable_mask = BIT(15), | |
2201 | .hw.init = &(struct clk_init_data){ | |
2202 | .name = "gcc_qupv3_wrap0_s5_clk", | |
097a8888 DB |
2203 | .parent_hws = (const struct clk_hw*[]){ |
2204 | &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, | |
44c20c9e VA |
2205 | }, |
2206 | .num_parents = 1, | |
2207 | .flags = CLK_SET_RATE_PARENT, | |
2208 | .ops = &clk_branch2_ops, | |
2209 | }, | |
2210 | }, | |
2211 | }; | |
2212 | ||
2213 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { | |
2214 | .halt_reg = 0x1772c, | |
2215 | .halt_check = BRANCH_HALT_VOTED, | |
2216 | .clkr = { | |
2217 | .enable_reg = 0x52008, | |
2218 | .enable_mask = BIT(16), | |
2219 | .hw.init = &(struct clk_init_data){ | |
2220 | .name = "gcc_qupv3_wrap0_s6_clk", | |
097a8888 DB |
2221 | .parent_hws = (const struct clk_hw*[]){ |
2222 | &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, | |
44c20c9e VA |
2223 | }, |
2224 | .num_parents = 1, | |
2225 | .flags = CLK_SET_RATE_PARENT, | |
2226 | .ops = &clk_branch2_ops, | |
2227 | }, | |
2228 | }, | |
2229 | }; | |
2230 | ||
2231 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { | |
2232 | .halt_reg = 0x1785c, | |
2233 | .halt_check = BRANCH_HALT_VOTED, | |
2234 | .clkr = { | |
2235 | .enable_reg = 0x52008, | |
2236 | .enable_mask = BIT(17), | |
2237 | .hw.init = &(struct clk_init_data){ | |
2238 | .name = "gcc_qupv3_wrap0_s7_clk", | |
097a8888 DB |
2239 | .parent_hws = (const struct clk_hw*[]){ |
2240 | &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, | |
44c20c9e VA |
2241 | }, |
2242 | .num_parents = 1, | |
2243 | .flags = CLK_SET_RATE_PARENT, | |
2244 | .ops = &clk_branch2_ops, | |
2245 | }, | |
2246 | }, | |
2247 | }; | |
2248 | ||
2249 | static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { | |
2250 | .halt_reg = 0x23140, | |
2251 | .halt_check = BRANCH_HALT_VOTED, | |
2252 | .clkr = { | |
2253 | .enable_reg = 0x52008, | |
2254 | .enable_mask = BIT(18), | |
2255 | .hw.init = &(struct clk_init_data){ | |
2256 | .name = "gcc_qupv3_wrap1_core_2x_clk", | |
2257 | .ops = &clk_branch2_ops, | |
2258 | }, | |
2259 | }, | |
2260 | }; | |
2261 | ||
2262 | static struct clk_branch gcc_qupv3_wrap1_core_clk = { | |
2263 | .halt_reg = 0x23138, | |
2264 | .halt_check = BRANCH_HALT_VOTED, | |
2265 | .clkr = { | |
2266 | .enable_reg = 0x52008, | |
2267 | .enable_mask = BIT(19), | |
2268 | .hw.init = &(struct clk_init_data){ | |
2269 | .name = "gcc_qupv3_wrap1_core_clk", | |
2270 | .ops = &clk_branch2_ops, | |
2271 | }, | |
2272 | }, | |
2273 | }; | |
2274 | ||
2275 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { | |
2276 | .halt_reg = 0x18004, | |
2277 | .halt_check = BRANCH_HALT_VOTED, | |
2278 | .hwcg_reg = 0x18004, | |
2279 | .hwcg_bit = 1, | |
2280 | .clkr = { | |
2281 | .enable_reg = 0x52008, | |
2282 | .enable_mask = BIT(20), | |
2283 | .hw.init = &(struct clk_init_data){ | |
2284 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", | |
2285 | .ops = &clk_branch2_ops, | |
2286 | }, | |
2287 | }, | |
2288 | }; | |
2289 | ||
2290 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { | |
2291 | .halt_reg = 0x18008, | |
2292 | .halt_check = BRANCH_HALT_VOTED, | |
2293 | .hwcg_reg = 0x18008, | |
2294 | .hwcg_bit = 1, | |
2295 | .clkr = { | |
2296 | .enable_reg = 0x52008, | |
2297 | .enable_mask = BIT(21), | |
2298 | .hw.init = &(struct clk_init_data){ | |
2299 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", | |
2300 | .ops = &clk_branch2_ops, | |
2301 | }, | |
2302 | }, | |
2303 | }; | |
2304 | ||
2305 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { | |
2306 | .halt_reg = 0x1800c, | |
2307 | .halt_check = BRANCH_HALT_VOTED, | |
2308 | .clkr = { | |
2309 | .enable_reg = 0x52008, | |
2310 | .enable_mask = BIT(22), | |
2311 | .hw.init = &(struct clk_init_data){ | |
2312 | .name = "gcc_qupv3_wrap1_s0_clk", | |
097a8888 DB |
2313 | .parent_hws = (const struct clk_hw*[]){ |
2314 | &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, | |
44c20c9e VA |
2315 | }, |
2316 | .num_parents = 1, | |
2317 | .flags = CLK_SET_RATE_PARENT, | |
2318 | .ops = &clk_branch2_ops, | |
2319 | }, | |
2320 | }, | |
2321 | }; | |
2322 | ||
2323 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { | |
2324 | .halt_reg = 0x1813c, | |
2325 | .halt_check = BRANCH_HALT_VOTED, | |
2326 | .clkr = { | |
2327 | .enable_reg = 0x52008, | |
2328 | .enable_mask = BIT(23), | |
2329 | .hw.init = &(struct clk_init_data){ | |
2330 | .name = "gcc_qupv3_wrap1_s1_clk", | |
097a8888 DB |
2331 | .parent_hws = (const struct clk_hw*[]){ |
2332 | &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, | |
44c20c9e VA |
2333 | }, |
2334 | .num_parents = 1, | |
2335 | .flags = CLK_SET_RATE_PARENT, | |
2336 | .ops = &clk_branch2_ops, | |
2337 | }, | |
2338 | }, | |
2339 | }; | |
2340 | ||
2341 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { | |
2342 | .halt_reg = 0x1826c, | |
2343 | .halt_check = BRANCH_HALT_VOTED, | |
2344 | .clkr = { | |
2345 | .enable_reg = 0x52008, | |
2346 | .enable_mask = BIT(24), | |
2347 | .hw.init = &(struct clk_init_data){ | |
2348 | .name = "gcc_qupv3_wrap1_s2_clk", | |
097a8888 DB |
2349 | .parent_hws = (const struct clk_hw*[]){ |
2350 | &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, | |
44c20c9e VA |
2351 | }, |
2352 | .num_parents = 1, | |
2353 | .flags = CLK_SET_RATE_PARENT, | |
2354 | .ops = &clk_branch2_ops, | |
2355 | }, | |
2356 | }, | |
2357 | }; | |
2358 | ||
2359 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { | |
2360 | .halt_reg = 0x1839c, | |
2361 | .halt_check = BRANCH_HALT_VOTED, | |
2362 | .clkr = { | |
2363 | .enable_reg = 0x52008, | |
2364 | .enable_mask = BIT(25), | |
2365 | .hw.init = &(struct clk_init_data){ | |
2366 | .name = "gcc_qupv3_wrap1_s3_clk", | |
097a8888 DB |
2367 | .parent_hws = (const struct clk_hw*[]){ |
2368 | &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, | |
44c20c9e VA |
2369 | }, |
2370 | .num_parents = 1, | |
2371 | .flags = CLK_SET_RATE_PARENT, | |
2372 | .ops = &clk_branch2_ops, | |
2373 | }, | |
2374 | }, | |
2375 | }; | |
2376 | ||
2377 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { | |
2378 | .halt_reg = 0x184cc, | |
2379 | .halt_check = BRANCH_HALT_VOTED, | |
2380 | .clkr = { | |
2381 | .enable_reg = 0x52008, | |
2382 | .enable_mask = BIT(26), | |
2383 | .hw.init = &(struct clk_init_data){ | |
2384 | .name = "gcc_qupv3_wrap1_s4_clk", | |
097a8888 DB |
2385 | .parent_hws = (const struct clk_hw*[]){ |
2386 | &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, | |
44c20c9e VA |
2387 | }, |
2388 | .num_parents = 1, | |
2389 | .flags = CLK_SET_RATE_PARENT, | |
2390 | .ops = &clk_branch2_ops, | |
2391 | }, | |
2392 | }, | |
2393 | }; | |
2394 | ||
2395 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { | |
2396 | .halt_reg = 0x185fc, | |
2397 | .halt_check = BRANCH_HALT_VOTED, | |
2398 | .clkr = { | |
2399 | .enable_reg = 0x52008, | |
2400 | .enable_mask = BIT(27), | |
2401 | .hw.init = &(struct clk_init_data){ | |
2402 | .name = "gcc_qupv3_wrap1_s5_clk", | |
097a8888 DB |
2403 | .parent_hws = (const struct clk_hw*[]){ |
2404 | &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, | |
44c20c9e VA |
2405 | }, |
2406 | .num_parents = 1, | |
2407 | .flags = CLK_SET_RATE_PARENT, | |
2408 | .ops = &clk_branch2_ops, | |
2409 | }, | |
2410 | }, | |
2411 | }; | |
2412 | ||
2413 | static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { | |
2414 | .halt_reg = 0x23278, | |
2415 | .halt_check = BRANCH_HALT_VOTED, | |
2416 | .clkr = { | |
2417 | .enable_reg = 0x52010, | |
2418 | .enable_mask = BIT(3), | |
2419 | .hw.init = &(struct clk_init_data){ | |
2420 | .name = "gcc_qupv3_wrap2_core_2x_clk", | |
2421 | .ops = &clk_branch2_ops, | |
2422 | }, | |
2423 | }, | |
2424 | }; | |
2425 | ||
2426 | static struct clk_branch gcc_qupv3_wrap2_core_clk = { | |
2427 | .halt_reg = 0x23270, | |
2428 | .halt_check = BRANCH_HALT_VOTED, | |
2429 | .clkr = { | |
2430 | .enable_reg = 0x52010, | |
2431 | .enable_mask = BIT(0), | |
2432 | .hw.init = &(struct clk_init_data){ | |
2433 | .name = "gcc_qupv3_wrap2_core_clk", | |
2434 | .ops = &clk_branch2_ops, | |
2435 | }, | |
2436 | }, | |
2437 | }; | |
2438 | ||
2439 | static struct clk_branch gcc_qupv3_wrap2_s0_clk = { | |
2440 | .halt_reg = 0x1e00c, | |
2441 | .halt_check = BRANCH_HALT_VOTED, | |
2442 | .clkr = { | |
2443 | .enable_reg = 0x52010, | |
2444 | .enable_mask = BIT(4), | |
2445 | .hw.init = &(struct clk_init_data){ | |
2446 | .name = "gcc_qupv3_wrap2_s0_clk", | |
097a8888 DB |
2447 | .parent_hws = (const struct clk_hw*[]){ |
2448 | &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, | |
44c20c9e VA |
2449 | }, |
2450 | .num_parents = 1, | |
2451 | .flags = CLK_SET_RATE_PARENT, | |
2452 | .ops = &clk_branch2_ops, | |
2453 | }, | |
2454 | }, | |
2455 | }; | |
2456 | ||
2457 | static struct clk_branch gcc_qupv3_wrap2_s1_clk = { | |
2458 | .halt_reg = 0x1e13c, | |
2459 | .halt_check = BRANCH_HALT_VOTED, | |
2460 | .clkr = { | |
2461 | .enable_reg = 0x52010, | |
2462 | .enable_mask = BIT(5), | |
2463 | .hw.init = &(struct clk_init_data){ | |
2464 | .name = "gcc_qupv3_wrap2_s1_clk", | |
097a8888 DB |
2465 | .parent_hws = (const struct clk_hw*[]){ |
2466 | &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, | |
44c20c9e VA |
2467 | }, |
2468 | .num_parents = 1, | |
2469 | .flags = CLK_SET_RATE_PARENT, | |
2470 | .ops = &clk_branch2_ops, | |
2471 | }, | |
2472 | }, | |
2473 | }; | |
2474 | ||
2475 | static struct clk_branch gcc_qupv3_wrap2_s2_clk = { | |
2476 | .halt_reg = 0x1e26c, | |
2477 | .halt_check = BRANCH_HALT_VOTED, | |
2478 | .clkr = { | |
2479 | .enable_reg = 0x52010, | |
2480 | .enable_mask = BIT(6), | |
2481 | .hw.init = &(struct clk_init_data){ | |
2482 | .name = "gcc_qupv3_wrap2_s2_clk", | |
097a8888 DB |
2483 | .parent_hws = (const struct clk_hw*[]){ |
2484 | &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, | |
44c20c9e VA |
2485 | }, |
2486 | .num_parents = 1, | |
2487 | .flags = CLK_SET_RATE_PARENT, | |
2488 | .ops = &clk_branch2_ops, | |
2489 | }, | |
2490 | }, | |
2491 | }; | |
2492 | ||
2493 | static struct clk_branch gcc_qupv3_wrap2_s3_clk = { | |
2494 | .halt_reg = 0x1e39c, | |
2495 | .halt_check = BRANCH_HALT_VOTED, | |
2496 | .clkr = { | |
2497 | .enable_reg = 0x52010, | |
2498 | .enable_mask = BIT(7), | |
2499 | .hw.init = &(struct clk_init_data){ | |
2500 | .name = "gcc_qupv3_wrap2_s3_clk", | |
097a8888 DB |
2501 | .parent_hws = (const struct clk_hw*[]){ |
2502 | &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, | |
44c20c9e VA |
2503 | }, |
2504 | .num_parents = 1, | |
2505 | .flags = CLK_SET_RATE_PARENT, | |
2506 | .ops = &clk_branch2_ops, | |
2507 | }, | |
2508 | }, | |
2509 | }; | |
2510 | ||
2511 | static struct clk_branch gcc_qupv3_wrap2_s4_clk = { | |
2512 | .halt_reg = 0x1e4cc, | |
2513 | .halt_check = BRANCH_HALT_VOTED, | |
2514 | .clkr = { | |
2515 | .enable_reg = 0x52010, | |
2516 | .enable_mask = BIT(8), | |
2517 | .hw.init = &(struct clk_init_data){ | |
2518 | .name = "gcc_qupv3_wrap2_s4_clk", | |
097a8888 DB |
2519 | .parent_hws = (const struct clk_hw*[]){ |
2520 | &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, | |
44c20c9e VA |
2521 | }, |
2522 | .num_parents = 1, | |
2523 | .flags = CLK_SET_RATE_PARENT, | |
2524 | .ops = &clk_branch2_ops, | |
2525 | }, | |
2526 | }, | |
2527 | }; | |
2528 | ||
2529 | static struct clk_branch gcc_qupv3_wrap2_s5_clk = { | |
2530 | .halt_reg = 0x1e5fc, | |
2531 | .halt_check = BRANCH_HALT_VOTED, | |
2532 | .clkr = { | |
2533 | .enable_reg = 0x52010, | |
2534 | .enable_mask = BIT(9), | |
2535 | .hw.init = &(struct clk_init_data){ | |
2536 | .name = "gcc_qupv3_wrap2_s5_clk", | |
097a8888 DB |
2537 | .parent_hws = (const struct clk_hw*[]){ |
2538 | &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, | |
44c20c9e VA |
2539 | }, |
2540 | .num_parents = 1, | |
2541 | .flags = CLK_SET_RATE_PARENT, | |
2542 | .ops = &clk_branch2_ops, | |
2543 | }, | |
2544 | }, | |
2545 | }; | |
2546 | ||
2547 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { | |
2548 | .halt_reg = 0x17004, | |
2549 | .halt_check = BRANCH_HALT_VOTED, | |
2550 | .hwcg_reg = 0x17004, | |
2551 | .hwcg_bit = 1, | |
2552 | .clkr = { | |
2553 | .enable_reg = 0x52008, | |
2554 | .enable_mask = BIT(6), | |
2555 | .hw.init = &(struct clk_init_data){ | |
2556 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", | |
2557 | .ops = &clk_branch2_ops, | |
2558 | }, | |
2559 | }, | |
2560 | }; | |
2561 | ||
2562 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { | |
2563 | .halt_reg = 0x17008, | |
2564 | .halt_check = BRANCH_HALT_VOTED, | |
2565 | .hwcg_reg = 0x17008, | |
2566 | .hwcg_bit = 1, | |
2567 | .clkr = { | |
2568 | .enable_reg = 0x52008, | |
2569 | .enable_mask = BIT(7), | |
2570 | .hw.init = &(struct clk_init_data){ | |
2571 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", | |
2572 | .ops = &clk_branch2_ops, | |
2573 | }, | |
2574 | }, | |
2575 | }; | |
2576 | ||
2577 | static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { | |
2578 | .halt_reg = 0x1e004, | |
2579 | .halt_check = BRANCH_HALT_VOTED, | |
2580 | .hwcg_reg = 0x1e004, | |
2581 | .hwcg_bit = 1, | |
2582 | .clkr = { | |
2583 | .enable_reg = 0x52010, | |
2584 | .enable_mask = BIT(2), | |
2585 | .hw.init = &(struct clk_init_data){ | |
2586 | .name = "gcc_qupv3_wrap_2_m_ahb_clk", | |
2587 | .ops = &clk_branch2_ops, | |
2588 | }, | |
2589 | }, | |
2590 | }; | |
2591 | ||
2592 | static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { | |
2593 | .halt_reg = 0x1e008, | |
2594 | .halt_check = BRANCH_HALT_VOTED, | |
2595 | .hwcg_reg = 0x1e008, | |
2596 | .hwcg_bit = 1, | |
2597 | .clkr = { | |
2598 | .enable_reg = 0x52010, | |
2599 | .enable_mask = BIT(1), | |
2600 | .hw.init = &(struct clk_init_data){ | |
2601 | .name = "gcc_qupv3_wrap_2_s_ahb_clk", | |
2602 | .ops = &clk_branch2_ops, | |
2603 | }, | |
2604 | }, | |
2605 | }; | |
2606 | ||
2607 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
2608 | .halt_reg = 0x14008, | |
2609 | .halt_check = BRANCH_HALT, | |
2610 | .clkr = { | |
2611 | .enable_reg = 0x14008, | |
2612 | .enable_mask = BIT(0), | |
2613 | .hw.init = &(struct clk_init_data){ | |
2614 | .name = "gcc_sdcc2_ahb_clk", | |
2615 | .ops = &clk_branch2_ops, | |
2616 | }, | |
2617 | }, | |
2618 | }; | |
2619 | ||
2620 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2621 | .halt_reg = 0x14004, | |
2622 | .halt_check = BRANCH_HALT, | |
2623 | .clkr = { | |
2624 | .enable_reg = 0x14004, | |
2625 | .enable_mask = BIT(0), | |
2626 | .hw.init = &(struct clk_init_data){ | |
2627 | .name = "gcc_sdcc2_apps_clk", | |
097a8888 DB |
2628 | .parent_hws = (const struct clk_hw*[]){ |
2629 | &gcc_sdcc2_apps_clk_src.clkr.hw, | |
44c20c9e VA |
2630 | }, |
2631 | .num_parents = 1, | |
2632 | .flags = CLK_SET_RATE_PARENT, | |
2633 | .ops = &clk_branch2_ops, | |
2634 | }, | |
2635 | }, | |
2636 | }; | |
2637 | ||
2638 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2639 | .halt_reg = 0x16008, | |
2640 | .halt_check = BRANCH_HALT, | |
2641 | .clkr = { | |
2642 | .enable_reg = 0x16008, | |
2643 | .enable_mask = BIT(0), | |
2644 | .hw.init = &(struct clk_init_data){ | |
2645 | .name = "gcc_sdcc4_ahb_clk", | |
2646 | .ops = &clk_branch2_ops, | |
2647 | }, | |
2648 | }, | |
2649 | }; | |
2650 | ||
2651 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2652 | .halt_reg = 0x16004, | |
2653 | .halt_check = BRANCH_HALT, | |
2654 | .clkr = { | |
2655 | .enable_reg = 0x16004, | |
2656 | .enable_mask = BIT(0), | |
2657 | .hw.init = &(struct clk_init_data){ | |
2658 | .name = "gcc_sdcc4_apps_clk", | |
097a8888 DB |
2659 | .parent_hws = (const struct clk_hw*[]){ |
2660 | &gcc_sdcc4_apps_clk_src.clkr.hw, | |
44c20c9e VA |
2661 | }, |
2662 | .num_parents = 1, | |
2663 | .flags = CLK_SET_RATE_PARENT, | |
2664 | .ops = &clk_branch2_ops, | |
2665 | }, | |
2666 | }, | |
2667 | }; | |
2668 | ||
2669 | static struct clk_branch gcc_throttle_pcie_ahb_clk = { | |
2670 | .halt_reg = 0x9044, | |
2671 | .halt_check = BRANCH_HALT, | |
2672 | .clkr = { | |
2673 | .enable_reg = 0x9044, | |
2674 | .enable_mask = BIT(0), | |
2675 | .hw.init = &(struct clk_init_data){ | |
2676 | .name = "gcc_throttle_pcie_ahb_clk", | |
2677 | .ops = &clk_branch2_ops, | |
2678 | }, | |
2679 | }, | |
2680 | }; | |
2681 | ||
2682 | static struct clk_branch gcc_ufs_1_clkref_en = { | |
2683 | .halt_reg = 0x8c000, | |
2684 | .halt_check = BRANCH_HALT, | |
2685 | .clkr = { | |
2686 | .enable_reg = 0x8c000, | |
2687 | .enable_mask = BIT(0), | |
2688 | .hw.init = &(struct clk_init_data){ | |
2689 | .name = "gcc_ufs_1_clkref_en", | |
2690 | .ops = &clk_branch2_ops, | |
2691 | }, | |
2692 | }, | |
2693 | }; | |
2694 | ||
2695 | static struct clk_branch gcc_ufs_card_ahb_clk = { | |
2696 | .halt_reg = 0x75018, | |
2697 | .halt_check = BRANCH_HALT_VOTED, | |
2698 | .hwcg_reg = 0x75018, | |
2699 | .hwcg_bit = 1, | |
2700 | .clkr = { | |
2701 | .enable_reg = 0x75018, | |
2702 | .enable_mask = BIT(0), | |
2703 | .hw.init = &(struct clk_init_data){ | |
2704 | .name = "gcc_ufs_card_ahb_clk", | |
2705 | .ops = &clk_branch2_ops, | |
2706 | }, | |
2707 | }, | |
2708 | }; | |
2709 | ||
2710 | static struct clk_branch gcc_ufs_card_axi_clk = { | |
2711 | .halt_reg = 0x75010, | |
2712 | .halt_check = BRANCH_HALT_VOTED, | |
2713 | .hwcg_reg = 0x75010, | |
2714 | .hwcg_bit = 1, | |
2715 | .clkr = { | |
2716 | .enable_reg = 0x75010, | |
2717 | .enable_mask = BIT(0), | |
2718 | .hw.init = &(struct clk_init_data){ | |
2719 | .name = "gcc_ufs_card_axi_clk", | |
097a8888 DB |
2720 | .parent_hws = (const struct clk_hw*[]){ |
2721 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
44c20c9e VA |
2722 | }, |
2723 | .num_parents = 1, | |
2724 | .flags = CLK_SET_RATE_PARENT, | |
2725 | .ops = &clk_branch2_ops, | |
2726 | }, | |
2727 | }, | |
2728 | }; | |
2729 | ||
2730 | static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { | |
2731 | .halt_reg = 0x75010, | |
2732 | .halt_check = BRANCH_HALT_VOTED, | |
2733 | .hwcg_reg = 0x75010, | |
2734 | .hwcg_bit = 1, | |
2735 | .clkr = { | |
2736 | .enable_reg = 0x75010, | |
2737 | .enable_mask = BIT(1), | |
2738 | .hw.init = &(struct clk_init_data){ | |
2739 | .name = "gcc_ufs_card_axi_hw_ctl_clk", | |
097a8888 DB |
2740 | .parent_hws = (const struct clk_hw*[]){ |
2741 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
44c20c9e VA |
2742 | }, |
2743 | .num_parents = 1, | |
2744 | .flags = CLK_SET_RATE_PARENT, | |
2745 | .ops = &clk_branch2_ops, | |
2746 | }, | |
2747 | }, | |
2748 | }; | |
2749 | ||
2750 | static struct clk_branch gcc_ufs_card_ice_core_clk = { | |
2751 | .halt_reg = 0x75064, | |
2752 | .halt_check = BRANCH_HALT_VOTED, | |
2753 | .hwcg_reg = 0x75064, | |
2754 | .hwcg_bit = 1, | |
2755 | .clkr = { | |
2756 | .enable_reg = 0x75064, | |
2757 | .enable_mask = BIT(0), | |
2758 | .hw.init = &(struct clk_init_data){ | |
2759 | .name = "gcc_ufs_card_ice_core_clk", | |
097a8888 DB |
2760 | .parent_hws = (const struct clk_hw*[]){ |
2761 | &gcc_ufs_card_ice_core_clk_src.clkr.hw, | |
44c20c9e VA |
2762 | }, |
2763 | .num_parents = 1, | |
2764 | .flags = CLK_SET_RATE_PARENT, | |
2765 | .ops = &clk_branch2_ops, | |
2766 | }, | |
2767 | }, | |
2768 | }; | |
2769 | ||
2770 | static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { | |
2771 | .halt_reg = 0x75064, | |
2772 | .halt_check = BRANCH_HALT_VOTED, | |
2773 | .hwcg_reg = 0x75064, | |
2774 | .hwcg_bit = 1, | |
2775 | .clkr = { | |
2776 | .enable_reg = 0x75064, | |
2777 | .enable_mask = BIT(1), | |
2778 | .hw.init = &(struct clk_init_data){ | |
2779 | .name = "gcc_ufs_card_ice_core_hw_ctl_clk", | |
097a8888 DB |
2780 | .parent_hws = (const struct clk_hw*[]){ |
2781 | &gcc_ufs_card_ice_core_clk_src.clkr.hw, | |
44c20c9e VA |
2782 | }, |
2783 | .num_parents = 1, | |
2784 | .flags = CLK_SET_RATE_PARENT, | |
2785 | .ops = &clk_branch2_ops, | |
2786 | }, | |
2787 | }, | |
2788 | }; | |
2789 | ||
2790 | static struct clk_branch gcc_ufs_card_phy_aux_clk = { | |
2791 | .halt_reg = 0x7509c, | |
2792 | .halt_check = BRANCH_HALT_VOTED, | |
2793 | .hwcg_reg = 0x7509c, | |
2794 | .hwcg_bit = 1, | |
2795 | .clkr = { | |
2796 | .enable_reg = 0x7509c, | |
2797 | .enable_mask = BIT(0), | |
2798 | .hw.init = &(struct clk_init_data){ | |
2799 | .name = "gcc_ufs_card_phy_aux_clk", | |
097a8888 DB |
2800 | .parent_hws = (const struct clk_hw*[]){ |
2801 | &gcc_ufs_card_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
2802 | }, |
2803 | .num_parents = 1, | |
2804 | .flags = CLK_SET_RATE_PARENT, | |
2805 | .ops = &clk_branch2_ops, | |
2806 | }, | |
2807 | }, | |
2808 | }; | |
2809 | ||
2810 | static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { | |
2811 | .halt_reg = 0x7509c, | |
2812 | .halt_check = BRANCH_HALT_VOTED, | |
2813 | .hwcg_reg = 0x7509c, | |
2814 | .hwcg_bit = 1, | |
2815 | .clkr = { | |
2816 | .enable_reg = 0x7509c, | |
2817 | .enable_mask = BIT(1), | |
2818 | .hw.init = &(struct clk_init_data){ | |
2819 | .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", | |
097a8888 DB |
2820 | .parent_hws = (const struct clk_hw*[]){ |
2821 | &gcc_ufs_card_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
2822 | }, |
2823 | .num_parents = 1, | |
2824 | .flags = CLK_SET_RATE_PARENT, | |
2825 | .ops = &clk_branch2_ops, | |
2826 | }, | |
2827 | }, | |
2828 | }; | |
2829 | ||
2830 | /* Clock ON depends on external parent clock, so don't poll */ | |
2831 | static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { | |
2832 | .halt_reg = 0x75020, | |
2833 | .halt_check = BRANCH_HALT_DELAY, | |
2834 | .clkr = { | |
2835 | .enable_reg = 0x75020, | |
2836 | .enable_mask = BIT(0), | |
2837 | .hw.init = &(struct clk_init_data){ | |
2838 | .name = "gcc_ufs_card_rx_symbol_0_clk", | |
097a8888 DB |
2839 | .parent_hws = (const struct clk_hw*[]){ |
2840 | &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, | |
44c20c9e VA |
2841 | }, |
2842 | .num_parents = 1, | |
2843 | .flags = CLK_SET_RATE_PARENT, | |
2844 | .ops = &clk_branch2_ops, | |
2845 | }, | |
2846 | }, | |
2847 | }; | |
2848 | ||
2849 | /* Clock ON depends on external parent clock, so don't poll */ | |
2850 | static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { | |
2851 | .halt_reg = 0x750b8, | |
2852 | .halt_check = BRANCH_HALT_DELAY, | |
2853 | .clkr = { | |
2854 | .enable_reg = 0x750b8, | |
2855 | .enable_mask = BIT(0), | |
2856 | .hw.init = &(struct clk_init_data){ | |
2857 | .name = "gcc_ufs_card_rx_symbol_1_clk", | |
097a8888 DB |
2858 | .parent_hws = (const struct clk_hw*[]){ |
2859 | &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, | |
44c20c9e VA |
2860 | }, |
2861 | .num_parents = 1, | |
2862 | .flags = CLK_SET_RATE_PARENT, | |
2863 | .ops = &clk_branch2_ops, | |
2864 | }, | |
2865 | }, | |
2866 | }; | |
2867 | ||
2868 | /* Clock ON depends on external parent clock, so don't poll */ | |
2869 | static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { | |
2870 | .halt_reg = 0x7501c, | |
2871 | .halt_check = BRANCH_HALT_DELAY, | |
2872 | .clkr = { | |
2873 | .enable_reg = 0x7501c, | |
2874 | .enable_mask = BIT(0), | |
2875 | .hw.init = &(struct clk_init_data){ | |
2876 | .name = "gcc_ufs_card_tx_symbol_0_clk", | |
097a8888 DB |
2877 | .parent_hws = (const struct clk_hw*[]){ |
2878 | &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, | |
44c20c9e VA |
2879 | }, |
2880 | .num_parents = 1, | |
2881 | .flags = CLK_SET_RATE_PARENT, | |
2882 | .ops = &clk_branch2_ops, | |
2883 | }, | |
2884 | }, | |
2885 | }; | |
2886 | ||
2887 | static struct clk_branch gcc_ufs_card_unipro_core_clk = { | |
2888 | .halt_reg = 0x7505c, | |
2889 | .halt_check = BRANCH_HALT_VOTED, | |
2890 | .hwcg_reg = 0x7505c, | |
2891 | .hwcg_bit = 1, | |
2892 | .clkr = { | |
2893 | .enable_reg = 0x7505c, | |
2894 | .enable_mask = BIT(0), | |
2895 | .hw.init = &(struct clk_init_data){ | |
2896 | .name = "gcc_ufs_card_unipro_core_clk", | |
097a8888 DB |
2897 | .parent_hws = (const struct clk_hw*[]){ |
2898 | &gcc_ufs_card_unipro_core_clk_src.clkr.hw, | |
44c20c9e VA |
2899 | }, |
2900 | .num_parents = 1, | |
2901 | .flags = CLK_SET_RATE_PARENT, | |
2902 | .ops = &clk_branch2_ops, | |
2903 | }, | |
2904 | }, | |
2905 | }; | |
2906 | ||
2907 | static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { | |
2908 | .halt_reg = 0x7505c, | |
2909 | .halt_check = BRANCH_HALT_VOTED, | |
2910 | .hwcg_reg = 0x7505c, | |
2911 | .hwcg_bit = 1, | |
2912 | .clkr = { | |
2913 | .enable_reg = 0x7505c, | |
2914 | .enable_mask = BIT(1), | |
2915 | .hw.init = &(struct clk_init_data){ | |
2916 | .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", | |
097a8888 DB |
2917 | .parent_hws = (const struct clk_hw*[]){ |
2918 | &gcc_ufs_card_unipro_core_clk_src.clkr.hw, | |
44c20c9e VA |
2919 | }, |
2920 | .num_parents = 1, | |
2921 | .flags = CLK_SET_RATE_PARENT, | |
2922 | .ops = &clk_branch2_ops, | |
2923 | }, | |
2924 | }, | |
2925 | }; | |
2926 | ||
2927 | static struct clk_branch gcc_ufs_phy_ahb_clk = { | |
2928 | .halt_reg = 0x77018, | |
2929 | .halt_check = BRANCH_HALT_VOTED, | |
2930 | .hwcg_reg = 0x77018, | |
2931 | .hwcg_bit = 1, | |
2932 | .clkr = { | |
2933 | .enable_reg = 0x77018, | |
2934 | .enable_mask = BIT(0), | |
2935 | .hw.init = &(struct clk_init_data){ | |
2936 | .name = "gcc_ufs_phy_ahb_clk", | |
2937 | .ops = &clk_branch2_ops, | |
2938 | }, | |
2939 | }, | |
2940 | }; | |
2941 | ||
2942 | static struct clk_branch gcc_ufs_phy_axi_clk = { | |
2943 | .halt_reg = 0x77010, | |
2944 | .halt_check = BRANCH_HALT_VOTED, | |
2945 | .hwcg_reg = 0x77010, | |
2946 | .hwcg_bit = 1, | |
2947 | .clkr = { | |
2948 | .enable_reg = 0x77010, | |
2949 | .enable_mask = BIT(0), | |
2950 | .hw.init = &(struct clk_init_data){ | |
2951 | .name = "gcc_ufs_phy_axi_clk", | |
097a8888 DB |
2952 | .parent_hws = (const struct clk_hw*[]){ |
2953 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
44c20c9e VA |
2954 | }, |
2955 | .num_parents = 1, | |
2956 | .flags = CLK_SET_RATE_PARENT, | |
2957 | .ops = &clk_branch2_ops, | |
2958 | }, | |
2959 | }, | |
2960 | }; | |
2961 | ||
2962 | static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { | |
2963 | .halt_reg = 0x77010, | |
2964 | .halt_check = BRANCH_HALT_VOTED, | |
2965 | .hwcg_reg = 0x77010, | |
2966 | .hwcg_bit = 1, | |
2967 | .clkr = { | |
2968 | .enable_reg = 0x77010, | |
2969 | .enable_mask = BIT(1), | |
2970 | .hw.init = &(struct clk_init_data){ | |
2971 | .name = "gcc_ufs_phy_axi_hw_ctl_clk", | |
097a8888 DB |
2972 | .parent_hws = (const struct clk_hw*[]){ |
2973 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
44c20c9e VA |
2974 | }, |
2975 | .num_parents = 1, | |
2976 | .flags = CLK_SET_RATE_PARENT, | |
2977 | .ops = &clk_branch2_ops, | |
2978 | }, | |
2979 | }, | |
2980 | }; | |
2981 | ||
2982 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { | |
2983 | .halt_reg = 0x77064, | |
2984 | .halt_check = BRANCH_HALT_VOTED, | |
2985 | .hwcg_reg = 0x77064, | |
2986 | .hwcg_bit = 1, | |
2987 | .clkr = { | |
2988 | .enable_reg = 0x77064, | |
2989 | .enable_mask = BIT(0), | |
2990 | .hw.init = &(struct clk_init_data){ | |
2991 | .name = "gcc_ufs_phy_ice_core_clk", | |
097a8888 DB |
2992 | .parent_hws = (const struct clk_hw*[]){ |
2993 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw, | |
44c20c9e VA |
2994 | }, |
2995 | .num_parents = 1, | |
2996 | .flags = CLK_SET_RATE_PARENT, | |
2997 | .ops = &clk_branch2_ops, | |
2998 | }, | |
2999 | }, | |
3000 | }; | |
3001 | ||
3002 | static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { | |
3003 | .halt_reg = 0x77064, | |
3004 | .halt_check = BRANCH_HALT_VOTED, | |
3005 | .hwcg_reg = 0x77064, | |
3006 | .hwcg_bit = 1, | |
3007 | .clkr = { | |
3008 | .enable_reg = 0x77064, | |
3009 | .enable_mask = BIT(1), | |
3010 | .hw.init = &(struct clk_init_data){ | |
3011 | .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", | |
097a8888 DB |
3012 | .parent_hws = (const struct clk_hw*[]){ |
3013 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw, | |
44c20c9e VA |
3014 | }, |
3015 | .num_parents = 1, | |
3016 | .flags = CLK_SET_RATE_PARENT, | |
3017 | .ops = &clk_branch2_ops, | |
3018 | }, | |
3019 | }, | |
3020 | }; | |
3021 | ||
3022 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { | |
3023 | .halt_reg = 0x7709c, | |
3024 | .halt_check = BRANCH_HALT_VOTED, | |
3025 | .hwcg_reg = 0x7709c, | |
3026 | .hwcg_bit = 1, | |
3027 | .clkr = { | |
3028 | .enable_reg = 0x7709c, | |
3029 | .enable_mask = BIT(0), | |
3030 | .hw.init = &(struct clk_init_data){ | |
3031 | .name = "gcc_ufs_phy_phy_aux_clk", | |
097a8888 DB |
3032 | .parent_hws = (const struct clk_hw*[]){ |
3033 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3034 | }, |
3035 | .num_parents = 1, | |
3036 | .flags = CLK_SET_RATE_PARENT, | |
3037 | .ops = &clk_branch2_ops, | |
3038 | }, | |
3039 | }, | |
3040 | }; | |
3041 | ||
3042 | static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { | |
3043 | .halt_reg = 0x7709c, | |
3044 | .halt_check = BRANCH_HALT_VOTED, | |
3045 | .hwcg_reg = 0x7709c, | |
3046 | .hwcg_bit = 1, | |
3047 | .clkr = { | |
3048 | .enable_reg = 0x7709c, | |
3049 | .enable_mask = BIT(1), | |
3050 | .hw.init = &(struct clk_init_data){ | |
3051 | .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", | |
097a8888 DB |
3052 | .parent_hws = (const struct clk_hw*[]){ |
3053 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3054 | }, |
3055 | .num_parents = 1, | |
3056 | .flags = CLK_SET_RATE_PARENT, | |
3057 | .ops = &clk_branch2_ops, | |
3058 | }, | |
3059 | }, | |
3060 | }; | |
3061 | ||
3062 | /* Clock ON depends on external parent clock, so don't poll */ | |
3063 | static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { | |
3064 | .halt_reg = 0x77020, | |
3065 | .halt_check = BRANCH_HALT_DELAY, | |
3066 | .clkr = { | |
3067 | .enable_reg = 0x77020, | |
3068 | .enable_mask = BIT(0), | |
3069 | .hw.init = &(struct clk_init_data){ | |
3070 | .name = "gcc_ufs_phy_rx_symbol_0_clk", | |
097a8888 DB |
3071 | .parent_hws = (const struct clk_hw*[]){ |
3072 | &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, | |
44c20c9e VA |
3073 | }, |
3074 | .num_parents = 1, | |
3075 | .flags = CLK_SET_RATE_PARENT, | |
3076 | .ops = &clk_branch2_ops, | |
3077 | }, | |
3078 | }, | |
3079 | }; | |
3080 | ||
3081 | /* Clock ON depends on external parent clock, so don't poll */ | |
3082 | static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { | |
3083 | .halt_reg = 0x770b8, | |
3084 | .halt_check = BRANCH_HALT_DELAY, | |
3085 | .clkr = { | |
3086 | .enable_reg = 0x770b8, | |
3087 | .enable_mask = BIT(0), | |
3088 | .hw.init = &(struct clk_init_data){ | |
3089 | .name = "gcc_ufs_phy_rx_symbol_1_clk", | |
097a8888 DB |
3090 | .parent_hws = (const struct clk_hw*[]){ |
3091 | &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, | |
44c20c9e VA |
3092 | }, |
3093 | .num_parents = 1, | |
3094 | .flags = CLK_SET_RATE_PARENT, | |
3095 | .ops = &clk_branch2_ops, | |
3096 | }, | |
3097 | }, | |
3098 | }; | |
3099 | ||
3100 | /* Clock ON depends on external parent clock, so don't poll */ | |
3101 | static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { | |
3102 | .halt_reg = 0x7701c, | |
3103 | .halt_check = BRANCH_HALT_DELAY, | |
3104 | .clkr = { | |
3105 | .enable_reg = 0x7701c, | |
3106 | .enable_mask = BIT(0), | |
3107 | .hw.init = &(struct clk_init_data){ | |
3108 | .name = "gcc_ufs_phy_tx_symbol_0_clk", | |
097a8888 DB |
3109 | .parent_hws = (const struct clk_hw*[]){ |
3110 | &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, | |
44c20c9e VA |
3111 | }, |
3112 | .num_parents = 1, | |
3113 | .flags = CLK_SET_RATE_PARENT, | |
3114 | .ops = &clk_branch2_ops, | |
3115 | }, | |
3116 | }, | |
3117 | }; | |
3118 | ||
3119 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { | |
3120 | .halt_reg = 0x7705c, | |
3121 | .halt_check = BRANCH_HALT_VOTED, | |
3122 | .hwcg_reg = 0x7705c, | |
3123 | .hwcg_bit = 1, | |
3124 | .clkr = { | |
3125 | .enable_reg = 0x7705c, | |
3126 | .enable_mask = BIT(0), | |
3127 | .hw.init = &(struct clk_init_data){ | |
3128 | .name = "gcc_ufs_phy_unipro_core_clk", | |
097a8888 DB |
3129 | .parent_hws = (const struct clk_hw*[]){ |
3130 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, | |
44c20c9e VA |
3131 | }, |
3132 | .num_parents = 1, | |
3133 | .flags = CLK_SET_RATE_PARENT, | |
3134 | .ops = &clk_branch2_ops, | |
3135 | }, | |
3136 | }, | |
3137 | }; | |
3138 | ||
3139 | static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { | |
3140 | .halt_reg = 0x7705c, | |
3141 | .halt_check = BRANCH_HALT_VOTED, | |
3142 | .hwcg_reg = 0x7705c, | |
3143 | .hwcg_bit = 1, | |
3144 | .clkr = { | |
3145 | .enable_reg = 0x7705c, | |
3146 | .enable_mask = BIT(1), | |
3147 | .hw.init = &(struct clk_init_data){ | |
3148 | .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", | |
097a8888 DB |
3149 | .parent_hws = (const struct clk_hw*[]){ |
3150 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, | |
44c20c9e VA |
3151 | }, |
3152 | .num_parents = 1, | |
3153 | .flags = CLK_SET_RATE_PARENT, | |
3154 | .ops = &clk_branch2_ops, | |
3155 | }, | |
3156 | }, | |
3157 | }; | |
3158 | ||
3159 | static struct clk_branch gcc_usb30_prim_master_clk = { | |
3160 | .halt_reg = 0xf010, | |
3161 | .halt_check = BRANCH_HALT, | |
3162 | .clkr = { | |
3163 | .enable_reg = 0xf010, | |
3164 | .enable_mask = BIT(0), | |
3165 | .hw.init = &(struct clk_init_data){ | |
3166 | .name = "gcc_usb30_prim_master_clk", | |
097a8888 DB |
3167 | .parent_hws = (const struct clk_hw*[]){ |
3168 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
44c20c9e VA |
3169 | }, |
3170 | .num_parents = 1, | |
3171 | .flags = CLK_SET_RATE_PARENT, | |
3172 | .ops = &clk_branch2_ops, | |
3173 | }, | |
3174 | }, | |
3175 | }; | |
3176 | ||
3177 | static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = { | |
3178 | .halt_reg = 0xf010, | |
3179 | .halt_check = BRANCH_HALT, | |
3180 | .clkr = { | |
3181 | .enable_reg = 0xf010, | |
3182 | .enable_mask = BIT(14), | |
3183 | .hw.init = &(struct clk_init_data){ | |
3184 | .name = "gcc_usb30_prim_master_clk__force_mem_core_on", | |
3185 | .ops = &clk_branch_simple_ops, | |
3186 | }, | |
3187 | }, | |
3188 | }; | |
3189 | ||
3190 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { | |
3191 | .halt_reg = 0xf01c, | |
3192 | .halt_check = BRANCH_HALT, | |
3193 | .clkr = { | |
3194 | .enable_reg = 0xf01c, | |
3195 | .enable_mask = BIT(0), | |
3196 | .hw.init = &(struct clk_init_data){ | |
3197 | .name = "gcc_usb30_prim_mock_utmi_clk", | |
097a8888 DB |
3198 | .parent_hws = (const struct clk_hw*[]){ |
3199 | &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, | |
44c20c9e VA |
3200 | }, |
3201 | .num_parents = 1, | |
3202 | .flags = CLK_SET_RATE_PARENT, | |
3203 | .ops = &clk_branch2_ops, | |
3204 | }, | |
3205 | }, | |
3206 | }; | |
3207 | ||
3208 | static struct clk_branch gcc_usb30_prim_sleep_clk = { | |
3209 | .halt_reg = 0xf018, | |
3210 | .halt_check = BRANCH_HALT, | |
3211 | .clkr = { | |
3212 | .enable_reg = 0xf018, | |
3213 | .enable_mask = BIT(0), | |
3214 | .hw.init = &(struct clk_init_data){ | |
3215 | .name = "gcc_usb30_prim_sleep_clk", | |
3216 | .ops = &clk_branch2_ops, | |
3217 | }, | |
3218 | }, | |
3219 | }; | |
3220 | ||
3221 | static struct clk_branch gcc_usb30_sec_master_clk = { | |
3222 | .halt_reg = 0x10010, | |
3223 | .halt_check = BRANCH_HALT, | |
3224 | .clkr = { | |
3225 | .enable_reg = 0x10010, | |
3226 | .enable_mask = BIT(0), | |
3227 | .hw.init = &(struct clk_init_data){ | |
3228 | .name = "gcc_usb30_sec_master_clk", | |
097a8888 DB |
3229 | .parent_hws = (const struct clk_hw*[]){ |
3230 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
44c20c9e VA |
3231 | }, |
3232 | .num_parents = 1, | |
3233 | .flags = CLK_SET_RATE_PARENT, | |
3234 | .ops = &clk_branch2_ops, | |
3235 | }, | |
3236 | }, | |
3237 | }; | |
3238 | ||
3239 | static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = { | |
3240 | .halt_reg = 0x10010, | |
3241 | .halt_check = BRANCH_HALT, | |
3242 | .clkr = { | |
3243 | .enable_reg = 0x10010, | |
3244 | .enable_mask = BIT(14), | |
3245 | .hw.init = &(struct clk_init_data){ | |
3246 | .name = "gcc_usb30_sec_master_clk__force_mem_core_on", | |
3247 | .ops = &clk_branch_simple_ops, | |
3248 | }, | |
3249 | }, | |
3250 | }; | |
3251 | ||
3252 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { | |
3253 | .halt_reg = 0x1001c, | |
3254 | .halt_check = BRANCH_HALT, | |
3255 | .clkr = { | |
3256 | .enable_reg = 0x1001c, | |
3257 | .enable_mask = BIT(0), | |
3258 | .hw.init = &(struct clk_init_data){ | |
3259 | .name = "gcc_usb30_sec_mock_utmi_clk", | |
097a8888 DB |
3260 | .parent_hws = (const struct clk_hw*[]){ |
3261 | &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, | |
44c20c9e VA |
3262 | }, |
3263 | .num_parents = 1, | |
3264 | .flags = CLK_SET_RATE_PARENT, | |
3265 | .ops = &clk_branch2_ops, | |
3266 | }, | |
3267 | }, | |
3268 | }; | |
3269 | ||
3270 | static struct clk_branch gcc_usb30_sec_sleep_clk = { | |
3271 | .halt_reg = 0x10018, | |
3272 | .halt_check = BRANCH_HALT, | |
3273 | .clkr = { | |
3274 | .enable_reg = 0x10018, | |
3275 | .enable_mask = BIT(0), | |
3276 | .hw.init = &(struct clk_init_data){ | |
3277 | .name = "gcc_usb30_sec_sleep_clk", | |
3278 | .ops = &clk_branch2_ops, | |
3279 | }, | |
3280 | }, | |
3281 | }; | |
3282 | ||
3283 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { | |
3284 | .halt_reg = 0xf054, | |
3285 | .halt_check = BRANCH_HALT, | |
3286 | .clkr = { | |
3287 | .enable_reg = 0xf054, | |
3288 | .enable_mask = BIT(0), | |
3289 | .hw.init = &(struct clk_init_data){ | |
3290 | .name = "gcc_usb3_prim_phy_aux_clk", | |
097a8888 DB |
3291 | .parent_hws = (const struct clk_hw*[]){ |
3292 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3293 | }, |
3294 | .num_parents = 1, | |
3295 | .flags = CLK_SET_RATE_PARENT, | |
3296 | .ops = &clk_branch2_ops, | |
3297 | }, | |
3298 | }, | |
3299 | }; | |
3300 | ||
3301 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { | |
3302 | .halt_reg = 0xf058, | |
3303 | .halt_check = BRANCH_HALT, | |
3304 | .clkr = { | |
3305 | .enable_reg = 0xf058, | |
3306 | .enable_mask = BIT(0), | |
3307 | .hw.init = &(struct clk_init_data){ | |
3308 | .name = "gcc_usb3_prim_phy_com_aux_clk", | |
097a8888 DB |
3309 | .parent_hws = (const struct clk_hw*[]){ |
3310 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3311 | }, |
3312 | .num_parents = 1, | |
3313 | .flags = CLK_SET_RATE_PARENT, | |
3314 | .ops = &clk_branch2_ops, | |
3315 | }, | |
3316 | }, | |
3317 | }; | |
3318 | ||
3319 | /* Clock ON depends on external parent clock, so don't poll */ | |
3320 | static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { | |
3321 | .halt_reg = 0xf05c, | |
3322 | .halt_check = BRANCH_HALT_DELAY, | |
3323 | .hwcg_reg = 0xf05c, | |
3324 | .hwcg_bit = 1, | |
3325 | .clkr = { | |
3326 | .enable_reg = 0xf05c, | |
3327 | .enable_mask = BIT(0), | |
3328 | .hw.init = &(struct clk_init_data){ | |
3329 | .name = "gcc_usb3_prim_phy_pipe_clk", | |
097a8888 DB |
3330 | .parent_hws = (const struct clk_hw*[]){ |
3331 | &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, | |
44c20c9e VA |
3332 | }, |
3333 | .num_parents = 1, | |
3334 | .flags = CLK_SET_RATE_PARENT, | |
3335 | .ops = &clk_branch2_ops, | |
3336 | }, | |
3337 | }, | |
3338 | }; | |
3339 | ||
3340 | static struct clk_branch gcc_usb3_sec_clkref_en = { | |
3341 | .halt_reg = 0x8c010, | |
3342 | .halt_check = BRANCH_HALT, | |
3343 | .clkr = { | |
3344 | .enable_reg = 0x8c010, | |
3345 | .enable_mask = BIT(0), | |
3346 | .hw.init = &(struct clk_init_data){ | |
3347 | .name = "gcc_usb3_sec_clkref_en", | |
3348 | .ops = &clk_branch2_ops, | |
3349 | }, | |
3350 | }, | |
3351 | }; | |
3352 | ||
3353 | static struct clk_branch gcc_usb3_sec_phy_aux_clk = { | |
3354 | .halt_reg = 0x10054, | |
3355 | .halt_check = BRANCH_HALT, | |
3356 | .clkr = { | |
3357 | .enable_reg = 0x10054, | |
3358 | .enable_mask = BIT(0), | |
3359 | .hw.init = &(struct clk_init_data){ | |
3360 | .name = "gcc_usb3_sec_phy_aux_clk", | |
097a8888 DB |
3361 | .parent_hws = (const struct clk_hw*[]){ |
3362 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3363 | }, |
3364 | .num_parents = 1, | |
3365 | .flags = CLK_SET_RATE_PARENT, | |
3366 | .ops = &clk_branch2_ops, | |
3367 | }, | |
3368 | }, | |
3369 | }; | |
3370 | ||
3371 | static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { | |
3372 | .halt_reg = 0x10058, | |
3373 | .halt_check = BRANCH_HALT, | |
3374 | .clkr = { | |
3375 | .enable_reg = 0x10058, | |
3376 | .enable_mask = BIT(0), | |
3377 | .hw.init = &(struct clk_init_data){ | |
3378 | .name = "gcc_usb3_sec_phy_com_aux_clk", | |
097a8888 DB |
3379 | .parent_hws = (const struct clk_hw*[]){ |
3380 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, | |
44c20c9e VA |
3381 | }, |
3382 | .num_parents = 1, | |
3383 | .flags = CLK_SET_RATE_PARENT, | |
3384 | .ops = &clk_branch2_ops, | |
3385 | }, | |
3386 | }, | |
3387 | }; | |
3388 | ||
3389 | /* Clock ON depends on external parent clock, so don't poll */ | |
3390 | static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { | |
3391 | .halt_reg = 0x1005c, | |
3392 | .halt_check = BRANCH_HALT_DELAY, | |
3393 | .clkr = { | |
3394 | .enable_reg = 0x1005c, | |
3395 | .enable_mask = BIT(0), | |
3396 | .hw.init = &(struct clk_init_data){ | |
3397 | .name = "gcc_usb3_sec_phy_pipe_clk", | |
097a8888 DB |
3398 | .parent_hws = (const struct clk_hw*[]){ |
3399 | &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, | |
44c20c9e VA |
3400 | }, |
3401 | .num_parents = 1, | |
3402 | .flags = CLK_SET_RATE_PARENT, | |
3403 | .ops = &clk_branch2_ops, | |
3404 | }, | |
3405 | }, | |
3406 | }; | |
3407 | ||
3408 | /* external clocks so add BRANCH_HALT_SKIP */ | |
3409 | static struct clk_branch gcc_video_axi0_clk = { | |
3410 | .halt_reg = 0x28010, | |
3411 | .halt_check = BRANCH_HALT_SKIP, | |
3412 | .hwcg_reg = 0x28010, | |
3413 | .hwcg_bit = 1, | |
3414 | .clkr = { | |
3415 | .enable_reg = 0x28010, | |
3416 | .enable_mask = BIT(0), | |
3417 | .hw.init = &(struct clk_init_data){ | |
3418 | .name = "gcc_video_axi0_clk", | |
3419 | .ops = &clk_branch2_ops, | |
3420 | }, | |
3421 | }, | |
3422 | }; | |
3423 | ||
3424 | /* external clocks so add BRANCH_HALT_SKIP */ | |
3425 | static struct clk_branch gcc_video_axi1_clk = { | |
3426 | .halt_reg = 0x28018, | |
3427 | .halt_check = BRANCH_HALT_SKIP, | |
3428 | .hwcg_reg = 0x28018, | |
3429 | .hwcg_bit = 1, | |
3430 | .clkr = { | |
3431 | .enable_reg = 0x28018, | |
3432 | .enable_mask = BIT(0), | |
3433 | .hw.init = &(struct clk_init_data){ | |
3434 | .name = "gcc_video_axi1_clk", | |
3435 | .ops = &clk_branch2_ops, | |
3436 | }, | |
3437 | }, | |
3438 | }; | |
3439 | ||
3fade948 VK |
3440 | static struct gdsc pcie_0_gdsc = { |
3441 | .gdscr = 0x6b004, | |
3442 | .pd = { | |
3443 | .name = "pcie_0_gdsc", | |
3444 | }, | |
3445 | .pwrsts = PWRSTS_OFF_ON, | |
3446 | }; | |
3447 | ||
3448 | static struct gdsc pcie_1_gdsc = { | |
3449 | .gdscr = 0x8d004, | |
3450 | .pd = { | |
3451 | .name = "pcie_1_gdsc", | |
3452 | }, | |
3453 | .pwrsts = PWRSTS_OFF_ON, | |
3454 | }; | |
3455 | ||
3456 | static struct gdsc ufs_card_gdsc = { | |
3457 | .gdscr = 0x75004, | |
3458 | .pd = { | |
3459 | .name = "ufs_card_gdsc", | |
3460 | }, | |
3461 | .pwrsts = PWRSTS_OFF_ON, | |
3462 | }; | |
3463 | ||
3464 | static struct gdsc ufs_phy_gdsc = { | |
3465 | .gdscr = 0x77004, | |
3466 | .pd = { | |
3467 | .name = "ufs_phy_gdsc", | |
3468 | }, | |
3469 | .pwrsts = PWRSTS_OFF_ON, | |
3470 | }; | |
3471 | ||
3472 | static struct gdsc usb30_prim_gdsc = { | |
3473 | .gdscr = 0xf004, | |
3474 | .pd = { | |
3475 | .name = "usb30_prim_gdsc", | |
3476 | }, | |
3477 | .pwrsts = PWRSTS_OFF_ON, | |
3478 | }; | |
3479 | ||
3480 | static struct gdsc usb30_sec_gdsc = { | |
3481 | .gdscr = 0x10004, | |
3482 | .pd = { | |
3483 | .name = "usb30_sec_gdsc", | |
3484 | }, | |
3485 | .pwrsts = PWRSTS_OFF_ON, | |
3486 | }; | |
3487 | ||
3488 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { | |
3489 | .gdscr = 0x7d050, | |
3490 | .pd = { | |
3491 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", | |
3492 | }, | |
3493 | .pwrsts = PWRSTS_OFF_ON, | |
3494 | .flags = VOTABLE, | |
3495 | }; | |
3496 | ||
3497 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { | |
3498 | .gdscr = 0x7d058, | |
3499 | .pd = { | |
3500 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", | |
3501 | }, | |
3502 | .pwrsts = PWRSTS_OFF_ON, | |
3503 | .flags = VOTABLE, | |
3504 | }; | |
3505 | ||
3506 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { | |
3507 | .gdscr = 0x7d054, | |
3508 | .pd = { | |
3509 | .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", | |
3510 | }, | |
3511 | .pwrsts = PWRSTS_OFF_ON, | |
3512 | .flags = VOTABLE, | |
3513 | }; | |
3514 | ||
3515 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { | |
3516 | .gdscr = 0x7d06c, | |
3517 | .pd = { | |
3518 | .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", | |
3519 | }, | |
3520 | .pwrsts = PWRSTS_OFF_ON, | |
3521 | .flags = VOTABLE, | |
3522 | }; | |
3523 | ||
44c20c9e VA |
3524 | static struct clk_regmap *gcc_sm8350_clocks[] = { |
3525 | [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, | |
3526 | [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, | |
3527 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, | |
3528 | [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, | |
3529 | [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, | |
3530 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, | |
3531 | [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, | |
3532 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, | |
3533 | [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, | |
3534 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3535 | [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, | |
3536 | [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, | |
3537 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
3538 | [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, | |
3539 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, | |
3540 | [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, | |
3541 | [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, | |
3542 | [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, | |
3543 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3544 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
3545 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3546 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
3547 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3548 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
3549 | [GCC_GPLL0] = &gcc_gpll0.clkr, | |
3550 | [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, | |
3551 | [GCC_GPLL4] = &gcc_gpll4.clkr, | |
3552 | [GCC_GPLL9] = &gcc_gpll9.clkr, | |
3553 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, | |
3554 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, | |
3555 | [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, | |
3556 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
3557 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
3558 | [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, | |
3559 | [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, | |
3560 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, | |
3561 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, | |
3562 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
3563 | [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, | |
3564 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
3565 | [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, | |
3566 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
3567 | [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, | |
3568 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
3569 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, | |
3570 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, | |
3571 | [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, | |
3572 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, | |
3573 | [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, | |
3574 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, | |
3575 | [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, | |
3576 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, | |
3577 | [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, | |
3578 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, | |
3579 | [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, | |
3580 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3581 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
3582 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3583 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
3584 | [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, | |
3585 | [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, | |
3586 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, | |
3587 | [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, | |
3588 | [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, | |
3589 | [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, | |
3590 | [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, | |
3591 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
3592 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
3593 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
3594 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
3595 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
3596 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
3597 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
3598 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
3599 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
3600 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
3601 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
3602 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
3603 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, | |
3604 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, | |
3605 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, | |
3606 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, | |
3607 | [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, | |
3608 | [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, | |
3609 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
3610 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
3611 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
3612 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
3613 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
3614 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
3615 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
3616 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
3617 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
3618 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
3619 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
3620 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
3621 | [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, | |
3622 | [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, | |
3623 | [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, | |
3624 | [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, | |
3625 | [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, | |
3626 | [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, | |
3627 | [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, | |
3628 | [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, | |
3629 | [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, | |
3630 | [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, | |
3631 | [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, | |
3632 | [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, | |
3633 | [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, | |
3634 | [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, | |
3635 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
3636 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
3637 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
3638 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
3639 | [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, | |
3640 | [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, | |
3641 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3642 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3643 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
3644 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3645 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
3646 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, | |
3647 | [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr, | |
3648 | [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, | |
3649 | [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, | |
3650 | [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, | |
3651 | [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, | |
3652 | [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, | |
3653 | [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, | |
3654 | [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, | |
3655 | [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, | |
3656 | [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, | |
3657 | [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, | |
3658 | [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, | |
3659 | [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, | |
3660 | [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr, | |
3661 | [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, | |
3662 | [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr, | |
3663 | [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, | |
3664 | [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr, | |
3665 | [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, | |
3666 | [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, | |
3667 | [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, | |
3668 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
3669 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
3670 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
3671 | [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, | |
3672 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
3673 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
3674 | [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, | |
3675 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
3676 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
3677 | [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, | |
3678 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, | |
3679 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, | |
3680 | [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, | |
3681 | [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, | |
3682 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, | |
3683 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, | |
3684 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
3685 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
3686 | [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, | |
3687 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
3688 | [GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] = | |
3689 | &gcc_usb30_prim_master_clk__force_mem_core_on.clkr, | |
3690 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
3691 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
3692 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
3693 | [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, | |
3694 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
3695 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, | |
3696 | [GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] = | |
3697 | &gcc_usb30_sec_master_clk__force_mem_core_on.clkr, | |
3698 | [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, | |
3699 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, | |
3700 | [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, | |
3701 | [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, | |
3702 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, | |
3703 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, | |
3704 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
3705 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
3706 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, | |
3707 | [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, | |
3708 | [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr, | |
3709 | [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, | |
3710 | [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, | |
3711 | [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, | |
3712 | [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, | |
3713 | [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, | |
3714 | [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, | |
3715 | [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, | |
3716 | }; | |
3717 | ||
3fade948 VK |
3718 | static struct gdsc *gcc_sm8350_gdscs[] = { |
3719 | [PCIE_0_GDSC] = &pcie_0_gdsc, | |
3720 | [PCIE_1_GDSC] = &pcie_1_gdsc, | |
3721 | [UFS_CARD_GDSC] = &ufs_card_gdsc, | |
3722 | [UFS_PHY_GDSC] = &ufs_phy_gdsc, | |
3723 | [USB30_PRIM_GDSC] = &usb30_prim_gdsc, | |
3724 | [USB30_SEC_GDSC] = &usb30_sec_gdsc, | |
3725 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, | |
3726 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, | |
3727 | [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, | |
3728 | [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, | |
3729 | }; | |
3730 | ||
44c20c9e VA |
3731 | static const struct qcom_reset_map gcc_sm8350_resets[] = { |
3732 | [GCC_CAMERA_BCR] = { 0x26000 }, | |
3733 | [GCC_DISPLAY_BCR] = { 0x27000 }, | |
3734 | [GCC_GPU_BCR] = { 0x71000 }, | |
3735 | [GCC_MMSS_BCR] = { 0xb000 }, | |
3736 | [GCC_PCIE_0_BCR] = { 0x6b000 }, | |
3737 | [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, | |
3738 | [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, | |
3739 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, | |
3740 | [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, | |
3741 | [GCC_PCIE_1_BCR] = { 0x8d000 }, | |
3742 | [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, | |
3743 | [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, | |
3744 | [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, | |
3745 | [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, | |
3746 | [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, | |
3747 | [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, | |
3748 | [GCC_PDM_BCR] = { 0x33000 }, | |
3749 | [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, | |
3750 | [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, | |
3751 | [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, | |
3752 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, | |
3753 | [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, | |
3754 | [GCC_SDCC2_BCR] = { 0x14000 }, | |
3755 | [GCC_SDCC4_BCR] = { 0x16000 }, | |
3756 | [GCC_UFS_CARD_BCR] = { 0x75000 }, | |
3757 | [GCC_UFS_PHY_BCR] = { 0x77000 }, | |
3758 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, | |
3759 | [GCC_USB30_SEC_BCR] = { 0x10000 }, | |
3760 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, | |
3761 | [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, | |
3762 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, | |
3763 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, | |
3764 | [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, | |
3765 | [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, | |
3766 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, | |
3767 | [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 }, | |
3768 | [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 }, | |
3769 | [GCC_VIDEO_BCR] = { 0x28000 }, | |
3770 | }; | |
3771 | ||
3772 | static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { | |
3773 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), | |
3774 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), | |
3775 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), | |
3776 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), | |
3777 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), | |
3778 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), | |
3779 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), | |
3780 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), | |
3781 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), | |
3782 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), | |
3783 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), | |
3784 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), | |
3785 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), | |
3786 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), | |
3787 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), | |
3788 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), | |
3789 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), | |
3790 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), | |
3791 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), | |
3792 | DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), | |
3793 | }; | |
3794 | ||
3795 | static const struct regmap_config gcc_sm8350_regmap_config = { | |
3796 | .reg_bits = 32, | |
3797 | .reg_stride = 4, | |
3798 | .val_bits = 32, | |
3799 | .max_register = 0x9c100, | |
3800 | .fast_io = true, | |
3801 | }; | |
3802 | ||
3803 | static const struct qcom_cc_desc gcc_sm8350_desc = { | |
3804 | .config = &gcc_sm8350_regmap_config, | |
3805 | .clks = gcc_sm8350_clocks, | |
3806 | .num_clks = ARRAY_SIZE(gcc_sm8350_clocks), | |
3807 | .resets = gcc_sm8350_resets, | |
3808 | .num_resets = ARRAY_SIZE(gcc_sm8350_resets), | |
3fade948 VK |
3809 | .gdscs = gcc_sm8350_gdscs, |
3810 | .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs), | |
44c20c9e VA |
3811 | }; |
3812 | ||
3813 | static const struct of_device_id gcc_sm8350_match_table[] = { | |
3814 | { .compatible = "qcom,gcc-sm8350" }, | |
3815 | { } | |
3816 | }; | |
3817 | MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table); | |
3818 | ||
3819 | static int gcc_sm8350_probe(struct platform_device *pdev) | |
3820 | { | |
3821 | struct regmap *regmap; | |
3822 | int ret; | |
3823 | ||
3824 | regmap = qcom_cc_map(pdev, &gcc_sm8350_desc); | |
3825 | if (IS_ERR(regmap)) { | |
3826 | dev_err(&pdev->dev, "Failed to map gcc registers\n"); | |
3827 | return PTR_ERR(regmap); | |
3828 | } | |
3829 | ||
3830 | /* | |
3831 | * Keep the critical clock always-On | |
3832 | * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, | |
3833 | * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK | |
3834 | */ | |
3835 | regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); | |
3836 | regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); | |
3837 | regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); | |
3838 | regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); | |
3839 | regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); | |
3840 | regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); | |
3841 | regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); | |
3842 | ||
3843 | ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); | |
3844 | if (ret) | |
3845 | return ret; | |
3846 | ||
3847 | /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ | |
3848 | regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); | |
3849 | ||
3850 | return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap); | |
3851 | } | |
3852 | ||
3853 | static struct platform_driver gcc_sm8350_driver = { | |
3854 | .probe = gcc_sm8350_probe, | |
3855 | .driver = { | |
3856 | .name = "sm8350-gcc", | |
3857 | .of_match_table = gcc_sm8350_match_table, | |
3858 | }, | |
3859 | }; | |
3860 | ||
3861 | static int __init gcc_sm8350_init(void) | |
3862 | { | |
3863 | return platform_driver_register(&gcc_sm8350_driver); | |
3864 | } | |
3865 | subsys_initcall(gcc_sm8350_init); | |
3866 | ||
3867 | static void __exit gcc_sm8350_exit(void) | |
3868 | { | |
3869 | platform_driver_unregister(&gcc_sm8350_driver); | |
3870 | } | |
3871 | module_exit(gcc_sm8350_exit); | |
3872 | ||
3873 | MODULE_DESCRIPTION("QTI GCC SM8350 Driver"); | |
3874 | MODULE_LICENSE("GPL v2"); |