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2a1d7eb8 DK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. | |
3 | ||
4 | #include <linux/kernel.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/err.h> | |
7 | #include <linux/platform_device.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/of_device.h> | |
11 | #include <linux/clk-provider.h> | |
12 | #include <linux/regmap.h> | |
13 | #include <linux/reset-controller.h> | |
14 | ||
15 | #include <dt-bindings/clock/qcom,gcc-sm8150.h> | |
16 | ||
17 | #include "common.h" | |
18 | #include "clk-alpha-pll.h" | |
19 | #include "clk-branch.h" | |
20 | #include "clk-pll.h" | |
21 | #include "clk-rcg.h" | |
22 | #include "clk-regmap.h" | |
23 | #include "reset.h" | |
24 | ||
25 | enum { | |
26 | P_BI_TCXO, | |
27 | P_AUD_REF_CLK, | |
28 | P_CORE_BI_PLL_TEST_SE, | |
29 | P_GPLL0_OUT_EVEN, | |
30 | P_GPLL0_OUT_MAIN, | |
31 | P_GPLL7_OUT_MAIN, | |
32 | P_GPLL9_OUT_MAIN, | |
33 | P_SLEEP_CLK, | |
34 | }; | |
35 | ||
36 | static const struct pll_vco trion_vco[] = { | |
37 | { 249600000, 2000000000, 0 }, | |
38 | }; | |
39 | ||
40 | static struct clk_alpha_pll gpll0 = { | |
41 | .offset = 0x0, | |
42 | .vco_table = trion_vco, | |
43 | .num_vco = ARRAY_SIZE(trion_vco), | |
44 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], | |
45 | .clkr = { | |
46 | .enable_reg = 0x52000, | |
47 | .enable_mask = BIT(0), | |
48 | .hw.init = &(struct clk_init_data){ | |
49 | .name = "gpll0", | |
50 | .parent_data = &(const struct clk_parent_data){ | |
51 | .fw_name = "bi_tcxo", | |
52 | .name = "bi_tcxo", | |
53 | }, | |
54 | .num_parents = 1, | |
55 | .ops = &clk_trion_fixed_pll_ops, | |
56 | }, | |
57 | }, | |
58 | }; | |
59 | ||
60 | static const struct clk_div_table post_div_table_trion_even[] = { | |
61 | { 0x0, 1 }, | |
62 | { 0x1, 2 }, | |
63 | { 0x3, 4 }, | |
64 | { 0x7, 8 }, | |
65 | { } | |
66 | }; | |
67 | ||
68 | static struct clk_alpha_pll_postdiv gpll0_out_even = { | |
69 | .offset = 0x0, | |
70 | .post_div_shift = 8, | |
71 | .post_div_table = post_div_table_trion_even, | |
72 | .num_post_div = ARRAY_SIZE(post_div_table_trion_even), | |
73 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], | |
74 | .width = 4, | |
75 | .clkr.hw.init = &(struct clk_init_data){ | |
76 | .name = "gpll0_out_even", | |
77 | .parent_data = &(const struct clk_parent_data){ | |
78 | .fw_name = "bi_tcxo", | |
79 | .name = "bi_tcxo", | |
80 | }, | |
81 | .num_parents = 1, | |
82 | .ops = &clk_trion_pll_postdiv_ops, | |
83 | }, | |
84 | }; | |
85 | ||
86 | static struct clk_alpha_pll gpll7 = { | |
87 | .offset = 0x1a000, | |
88 | .vco_table = trion_vco, | |
89 | .num_vco = ARRAY_SIZE(trion_vco), | |
90 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], | |
91 | .clkr = { | |
92 | .enable_reg = 0x52000, | |
93 | .enable_mask = BIT(7), | |
94 | .hw.init = &(struct clk_init_data){ | |
95 | .name = "gpll7", | |
96 | .parent_data = &(const struct clk_parent_data){ | |
97 | .fw_name = "bi_tcxo", | |
98 | .name = "bi_tcxo", | |
99 | }, | |
100 | .num_parents = 1, | |
101 | .ops = &clk_trion_fixed_pll_ops, | |
102 | }, | |
103 | }, | |
104 | }; | |
105 | ||
106 | static struct clk_alpha_pll gpll9 = { | |
107 | .offset = 0x1c000, | |
108 | .vco_table = trion_vco, | |
109 | .num_vco = ARRAY_SIZE(trion_vco), | |
110 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], | |
111 | .clkr = { | |
112 | .enable_reg = 0x52000, | |
113 | .enable_mask = BIT(9), | |
114 | .hw.init = &(struct clk_init_data){ | |
115 | .name = "gpll9", | |
116 | .parent_data = &(const struct clk_parent_data){ | |
117 | .fw_name = "bi_tcxo", | |
118 | .name = "bi_tcxo", | |
119 | }, | |
120 | .num_parents = 1, | |
121 | .ops = &clk_trion_fixed_pll_ops, | |
122 | }, | |
123 | }, | |
124 | }; | |
125 | ||
126 | static const struct parent_map gcc_parent_map_0[] = { | |
127 | { P_BI_TCXO, 0 }, | |
128 | { P_GPLL0_OUT_MAIN, 1 }, | |
129 | { P_GPLL0_OUT_EVEN, 6 }, | |
130 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
131 | }; | |
132 | ||
133 | static const struct clk_parent_data gcc_parents_0[] = { | |
134 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
135 | { .hw = &gpll0.clkr.hw }, | |
136 | { .hw = &gpll0_out_even.clkr.hw }, | |
137 | { .fw_name = "core_bi_pll_test_se" }, | |
138 | }; | |
139 | ||
140 | static const struct parent_map gcc_parent_map_1[] = { | |
141 | { P_BI_TCXO, 0 }, | |
142 | { P_GPLL0_OUT_MAIN, 1 }, | |
143 | { P_SLEEP_CLK, 5 }, | |
144 | { P_GPLL0_OUT_EVEN, 6 }, | |
145 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
146 | }; | |
147 | ||
148 | static const struct clk_parent_data gcc_parents_1[] = { | |
149 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
150 | { .hw = &gpll0.clkr.hw }, | |
151 | { .fw_name = "sleep_clk", .name = "sleep_clk" }, | |
152 | { .hw = &gpll0_out_even.clkr.hw }, | |
153 | { .fw_name = "core_bi_pll_test_se" }, | |
154 | }; | |
155 | ||
156 | static const struct parent_map gcc_parent_map_2[] = { | |
157 | { P_BI_TCXO, 0 }, | |
158 | { P_SLEEP_CLK, 5 }, | |
159 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
160 | }; | |
161 | ||
162 | static const struct clk_parent_data gcc_parents_2[] = { | |
163 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
164 | { .fw_name = "sleep_clk", .name = "sleep_clk" }, | |
165 | { .fw_name = "core_bi_pll_test_se" }, | |
166 | }; | |
167 | ||
168 | static const struct parent_map gcc_parent_map_3[] = { | |
169 | { P_BI_TCXO, 0 }, | |
170 | { P_GPLL0_OUT_MAIN, 1 }, | |
171 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
172 | }; | |
173 | ||
174 | static const struct clk_parent_data gcc_parents_3[] = { | |
175 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
176 | { .hw = &gpll0.clkr.hw }, | |
177 | { .fw_name = "core_bi_pll_test_se"}, | |
178 | }; | |
179 | ||
180 | static const struct parent_map gcc_parent_map_4[] = { | |
181 | { P_BI_TCXO, 0 }, | |
182 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
183 | }; | |
184 | ||
185 | static const struct clk_parent_data gcc_parents_4[] = { | |
186 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
187 | { .fw_name = "core_bi_pll_test_se" }, | |
188 | }; | |
189 | ||
190 | static const struct parent_map gcc_parent_map_5[] = { | |
191 | { P_BI_TCXO, 0 }, | |
192 | { P_GPLL0_OUT_MAIN, 1 }, | |
193 | { P_GPLL7_OUT_MAIN, 3 }, | |
194 | { P_GPLL0_OUT_EVEN, 6 }, | |
195 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
196 | }; | |
197 | ||
198 | static const struct clk_parent_data gcc_parents_5[] = { | |
199 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
200 | { .hw = &gpll0.clkr.hw }, | |
201 | { .hw = &gpll7.clkr.hw }, | |
202 | { .hw = &gpll0_out_even.clkr.hw }, | |
203 | { .fw_name = "core_bi_pll_test_se" }, | |
204 | }; | |
205 | ||
206 | static const struct parent_map gcc_parent_map_6[] = { | |
207 | { P_BI_TCXO, 0 }, | |
208 | { P_GPLL0_OUT_MAIN, 1 }, | |
209 | { P_GPLL9_OUT_MAIN, 2 }, | |
210 | { P_GPLL0_OUT_EVEN, 6 }, | |
211 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
212 | }; | |
213 | ||
214 | static const struct clk_parent_data gcc_parents_6[] = { | |
215 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
216 | { .hw = &gpll0.clkr.hw }, | |
217 | { .hw = &gpll9.clkr.hw }, | |
218 | { .hw = &gpll0_out_even.clkr.hw }, | |
219 | { .fw_name = "core_bi_pll_test_se" }, | |
220 | }; | |
221 | ||
222 | static const struct parent_map gcc_parent_map_7[] = { | |
223 | { P_BI_TCXO, 0 }, | |
224 | { P_GPLL0_OUT_MAIN, 1 }, | |
225 | { P_AUD_REF_CLK, 2 }, | |
226 | { P_GPLL0_OUT_EVEN, 6 }, | |
227 | { P_CORE_BI_PLL_TEST_SE, 7 }, | |
228 | }; | |
229 | ||
230 | static const struct clk_parent_data gcc_parents_7[] = { | |
231 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
232 | { .hw = &gpll0.clkr.hw }, | |
233 | { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, | |
234 | { .hw = &gpll0_out_even.clkr.hw }, | |
235 | { .fw_name = "core_bi_pll_test_se" }, | |
236 | }; | |
237 | ||
238 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { | |
239 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
240 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
241 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
242 | { } | |
243 | }; | |
244 | ||
245 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { | |
246 | .cmd_rcgr = 0x48014, | |
247 | .mnd_width = 0, | |
248 | .hid_width = 5, | |
249 | .parent_map = gcc_parent_map_0, | |
250 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, | |
251 | .clkr.hw.init = &(struct clk_init_data){ | |
252 | .name = "gcc_cpuss_ahb_clk_src", | |
253 | .parent_data = gcc_parents_0, | |
254 | .num_parents = 4, | |
255 | .flags = CLK_SET_RATE_PARENT, | |
256 | .ops = &clk_rcg2_ops, | |
257 | }, | |
258 | }; | |
259 | ||
260 | static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { | |
261 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
262 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
263 | F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), | |
264 | F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), | |
265 | { } | |
266 | }; | |
267 | ||
268 | static struct clk_rcg2 gcc_emac_ptp_clk_src = { | |
269 | .cmd_rcgr = 0x6038, | |
270 | .mnd_width = 0, | |
271 | .hid_width = 5, | |
272 | .parent_map = gcc_parent_map_5, | |
273 | .freq_tbl = ftbl_gcc_emac_ptp_clk_src, | |
274 | .clkr.hw.init = &(struct clk_init_data){ | |
275 | .name = "gcc_emac_ptp_clk_src", | |
276 | .parent_data = gcc_parents_5, | |
277 | .num_parents = 5, | |
278 | .flags = CLK_SET_RATE_PARENT, | |
279 | .ops = &clk_rcg2_ops, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { | |
284 | F(2500000, P_BI_TCXO, 1, 25, 192), | |
285 | F(5000000, P_BI_TCXO, 1, 25, 96), | |
286 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
287 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
288 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
289 | F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), | |
290 | F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), | |
291 | { } | |
292 | }; | |
293 | ||
294 | static struct clk_rcg2 gcc_emac_rgmii_clk_src = { | |
295 | .cmd_rcgr = 0x601c, | |
296 | .mnd_width = 8, | |
297 | .hid_width = 5, | |
298 | .parent_map = gcc_parent_map_5, | |
299 | .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, | |
300 | .clkr.hw.init = &(struct clk_init_data){ | |
301 | .name = "gcc_emac_rgmii_clk_src", | |
302 | .parent_data = gcc_parents_5, | |
303 | .num_parents = 5, | |
304 | .flags = CLK_SET_RATE_PARENT, | |
305 | .ops = &clk_rcg2_ops, | |
306 | }, | |
307 | }; | |
308 | ||
309 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { | |
310 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
311 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
312 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
313 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
314 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
315 | { } | |
316 | }; | |
317 | ||
318 | static struct clk_rcg2 gcc_gp1_clk_src = { | |
319 | .cmd_rcgr = 0x64004, | |
320 | .mnd_width = 8, | |
321 | .hid_width = 5, | |
322 | .parent_map = gcc_parent_map_1, | |
323 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
324 | .clkr.hw.init = &(struct clk_init_data){ | |
325 | .name = "gcc_gp1_clk_src", | |
326 | .parent_data = gcc_parents_1, | |
327 | .num_parents = 5, | |
328 | .flags = CLK_SET_RATE_PARENT, | |
329 | .ops = &clk_rcg2_ops, | |
330 | }, | |
331 | }; | |
332 | ||
333 | static struct clk_rcg2 gcc_gp2_clk_src = { | |
334 | .cmd_rcgr = 0x65004, | |
335 | .mnd_width = 8, | |
336 | .hid_width = 5, | |
337 | .parent_map = gcc_parent_map_1, | |
338 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
339 | .clkr.hw.init = &(struct clk_init_data){ | |
340 | .name = "gcc_gp2_clk_src", | |
341 | .parent_data = gcc_parents_1, | |
342 | .num_parents = 5, | |
343 | .flags = CLK_SET_RATE_PARENT, | |
344 | .ops = &clk_rcg2_ops, | |
345 | }, | |
346 | }; | |
347 | ||
348 | static struct clk_rcg2 gcc_gp3_clk_src = { | |
349 | .cmd_rcgr = 0x66004, | |
350 | .mnd_width = 8, | |
351 | .hid_width = 5, | |
352 | .parent_map = gcc_parent_map_1, | |
353 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
354 | .clkr.hw.init = &(struct clk_init_data){ | |
355 | .name = "gcc_gp3_clk_src", | |
356 | .parent_data = gcc_parents_1, | |
357 | .num_parents = 5, | |
358 | .flags = CLK_SET_RATE_PARENT, | |
359 | .ops = &clk_rcg2_ops, | |
360 | }, | |
361 | }; | |
362 | ||
363 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { | |
364 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
365 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
366 | { } | |
367 | }; | |
368 | ||
369 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { | |
370 | .cmd_rcgr = 0x6b02c, | |
371 | .mnd_width = 16, | |
372 | .hid_width = 5, | |
373 | .parent_map = gcc_parent_map_2, | |
374 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
375 | .clkr.hw.init = &(struct clk_init_data){ | |
376 | .name = "gcc_pcie_0_aux_clk_src", | |
377 | .parent_data = gcc_parents_2, | |
378 | .num_parents = 3, | |
379 | .flags = CLK_SET_RATE_PARENT, | |
380 | .ops = &clk_rcg2_ops, | |
381 | }, | |
382 | }; | |
383 | ||
384 | static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { | |
385 | .cmd_rcgr = 0x8d02c, | |
386 | .mnd_width = 16, | |
387 | .hid_width = 5, | |
388 | .parent_map = gcc_parent_map_2, | |
389 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
390 | .clkr.hw.init = &(struct clk_init_data){ | |
391 | .name = "gcc_pcie_1_aux_clk_src", | |
392 | .parent_data = gcc_parents_2, | |
393 | .num_parents = 3, | |
394 | .flags = CLK_SET_RATE_PARENT, | |
395 | .ops = &clk_rcg2_ops, | |
396 | }, | |
397 | }; | |
398 | ||
399 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { | |
400 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
401 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
402 | { } | |
403 | }; | |
404 | ||
405 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { | |
406 | .cmd_rcgr = 0x6f014, | |
407 | .mnd_width = 0, | |
408 | .hid_width = 5, | |
409 | .parent_map = gcc_parent_map_0, | |
410 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, | |
411 | .clkr.hw.init = &(struct clk_init_data){ | |
412 | .name = "gcc_pcie_phy_refgen_clk_src", | |
413 | .parent_data = gcc_parents_0, | |
414 | .num_parents = 4, | |
415 | .flags = CLK_SET_RATE_PARENT, | |
416 | .ops = &clk_rcg2_ops, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { | |
421 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
422 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
423 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), | |
424 | { } | |
425 | }; | |
426 | ||
427 | static struct clk_rcg2 gcc_pdm2_clk_src = { | |
428 | .cmd_rcgr = 0x33010, | |
429 | .mnd_width = 0, | |
430 | .hid_width = 5, | |
431 | .parent_map = gcc_parent_map_0, | |
432 | .freq_tbl = ftbl_gcc_pdm2_clk_src, | |
433 | .clkr.hw.init = &(struct clk_init_data){ | |
434 | .name = "gcc_pdm2_clk_src", | |
435 | .parent_data = gcc_parents_0, | |
436 | .num_parents = 4, | |
437 | .flags = CLK_SET_RATE_PARENT, | |
438 | .ops = &clk_rcg2_ops, | |
439 | }, | |
440 | }; | |
441 | ||
442 | static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { | |
443 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
444 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
445 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
446 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
447 | { } | |
448 | }; | |
449 | ||
450 | static struct clk_rcg2 gcc_qspi_core_clk_src = { | |
451 | .cmd_rcgr = 0x4b008, | |
452 | .mnd_width = 0, | |
453 | .hid_width = 5, | |
454 | .parent_map = gcc_parent_map_0, | |
455 | .freq_tbl = ftbl_gcc_qspi_core_clk_src, | |
456 | .clkr.hw.init = &(struct clk_init_data){ | |
457 | .name = "gcc_qspi_core_clk_src", | |
458 | .parent_data = gcc_parents_0, | |
459 | .num_parents = 4, | |
460 | .flags = CLK_SET_RATE_PARENT, | |
461 | .ops = &clk_rcg2_ops, | |
462 | }, | |
463 | }; | |
464 | ||
465 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { | |
466 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), | |
467 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), | |
468 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
469 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), | |
470 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), | |
471 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), | |
472 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), | |
473 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), | |
474 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), | |
475 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), | |
476 | F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), | |
477 | F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), | |
478 | F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), | |
479 | F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), | |
480 | F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), | |
481 | { } | |
482 | }; | |
483 | ||
484 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { | |
485 | .cmd_rcgr = 0x17148, | |
486 | .mnd_width = 16, | |
487 | .hid_width = 5, | |
488 | .parent_map = gcc_parent_map_0, | |
489 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
490 | .clkr.hw.init = &(struct clk_init_data){ | |
491 | .name = "gcc_qupv3_wrap0_s0_clk_src", | |
492 | .parent_data = gcc_parents_0, | |
493 | .num_parents = 4, | |
494 | .flags = CLK_SET_RATE_PARENT, | |
495 | .ops = &clk_rcg2_ops, | |
496 | }, | |
497 | }; | |
498 | ||
499 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { | |
500 | .cmd_rcgr = 0x17278, | |
501 | .mnd_width = 16, | |
502 | .hid_width = 5, | |
503 | .parent_map = gcc_parent_map_0, | |
504 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
505 | .clkr.hw.init = &(struct clk_init_data){ | |
506 | .name = "gcc_qupv3_wrap0_s1_clk_src", | |
507 | .parent_data = gcc_parents_0, | |
508 | .num_parents = 4, | |
509 | .flags = CLK_SET_RATE_PARENT, | |
510 | .ops = &clk_rcg2_ops, | |
511 | }, | |
512 | }; | |
513 | ||
514 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { | |
515 | .cmd_rcgr = 0x173a8, | |
516 | .mnd_width = 16, | |
517 | .hid_width = 5, | |
518 | .parent_map = gcc_parent_map_0, | |
519 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
520 | .clkr.hw.init = &(struct clk_init_data){ | |
521 | .name = "gcc_qupv3_wrap0_s2_clk_src", | |
522 | .parent_data = gcc_parents_0, | |
523 | .num_parents = 4, | |
524 | .flags = CLK_SET_RATE_PARENT, | |
525 | .ops = &clk_rcg2_ops, | |
526 | }, | |
527 | }; | |
528 | ||
529 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { | |
530 | .cmd_rcgr = 0x174d8, | |
531 | .mnd_width = 16, | |
532 | .hid_width = 5, | |
533 | .parent_map = gcc_parent_map_0, | |
534 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
535 | .clkr.hw.init = &(struct clk_init_data){ | |
536 | .name = "gcc_qupv3_wrap0_s3_clk_src", | |
537 | .parent_data = gcc_parents_0, | |
538 | .num_parents = 4, | |
539 | .flags = CLK_SET_RATE_PARENT, | |
540 | .ops = &clk_rcg2_ops, | |
541 | }, | |
542 | }; | |
543 | ||
544 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { | |
545 | .cmd_rcgr = 0x17608, | |
546 | .mnd_width = 16, | |
547 | .hid_width = 5, | |
548 | .parent_map = gcc_parent_map_0, | |
549 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
550 | .clkr.hw.init = &(struct clk_init_data){ | |
551 | .name = "gcc_qupv3_wrap0_s4_clk_src", | |
552 | .parent_data = gcc_parents_0, | |
553 | .num_parents = 4, | |
554 | .flags = CLK_SET_RATE_PARENT, | |
555 | .ops = &clk_rcg2_ops, | |
556 | }, | |
557 | }; | |
558 | ||
559 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { | |
560 | .cmd_rcgr = 0x17738, | |
561 | .mnd_width = 16, | |
562 | .hid_width = 5, | |
563 | .parent_map = gcc_parent_map_0, | |
564 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
565 | .clkr.hw.init = &(struct clk_init_data){ | |
566 | .name = "gcc_qupv3_wrap0_s5_clk_src", | |
567 | .parent_data = gcc_parents_0, | |
568 | .num_parents = 4, | |
569 | .flags = CLK_SET_RATE_PARENT, | |
570 | .ops = &clk_rcg2_ops, | |
571 | }, | |
572 | }; | |
573 | ||
574 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { | |
575 | .cmd_rcgr = 0x17868, | |
576 | .mnd_width = 16, | |
577 | .hid_width = 5, | |
578 | .parent_map = gcc_parent_map_0, | |
579 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
580 | .clkr.hw.init = &(struct clk_init_data){ | |
581 | .name = "gcc_qupv3_wrap0_s6_clk_src", | |
582 | .parent_data = gcc_parents_0, | |
583 | .num_parents = 4, | |
584 | .flags = CLK_SET_RATE_PARENT, | |
585 | .ops = &clk_rcg2_ops, | |
586 | }, | |
587 | }; | |
588 | ||
589 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { | |
590 | .cmd_rcgr = 0x17998, | |
591 | .mnd_width = 16, | |
592 | .hid_width = 5, | |
593 | .parent_map = gcc_parent_map_0, | |
594 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
595 | .clkr.hw.init = &(struct clk_init_data){ | |
596 | .name = "gcc_qupv3_wrap0_s7_clk_src", | |
597 | .parent_data = gcc_parents_0, | |
598 | .num_parents = 4, | |
599 | .flags = CLK_SET_RATE_PARENT, | |
600 | .ops = &clk_rcg2_ops, | |
601 | }, | |
602 | }; | |
603 | ||
604 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { | |
605 | .cmd_rcgr = 0x18148, | |
606 | .mnd_width = 16, | |
607 | .hid_width = 5, | |
608 | .parent_map = gcc_parent_map_0, | |
609 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
610 | .clkr.hw.init = &(struct clk_init_data){ | |
611 | .name = "gcc_qupv3_wrap1_s0_clk_src", | |
612 | .parent_data = gcc_parents_0, | |
613 | .num_parents = 4, | |
614 | .flags = CLK_SET_RATE_PARENT, | |
615 | .ops = &clk_rcg2_ops, | |
616 | }, | |
617 | }; | |
618 | ||
619 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { | |
620 | .cmd_rcgr = 0x18278, | |
621 | .mnd_width = 16, | |
622 | .hid_width = 5, | |
623 | .parent_map = gcc_parent_map_0, | |
624 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
625 | .clkr.hw.init = &(struct clk_init_data){ | |
626 | .name = "gcc_qupv3_wrap1_s1_clk_src", | |
627 | .parent_data = gcc_parents_0, | |
628 | .num_parents = 4, | |
629 | .flags = CLK_SET_RATE_PARENT, | |
630 | .ops = &clk_rcg2_ops, | |
631 | }, | |
632 | }; | |
633 | ||
634 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { | |
635 | .cmd_rcgr = 0x183a8, | |
636 | .mnd_width = 16, | |
637 | .hid_width = 5, | |
638 | .parent_map = gcc_parent_map_0, | |
639 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
640 | .clkr.hw.init = &(struct clk_init_data){ | |
641 | .name = "gcc_qupv3_wrap1_s2_clk_src", | |
642 | .parent_data = gcc_parents_0, | |
643 | .num_parents = 4, | |
644 | .flags = CLK_SET_RATE_PARENT, | |
645 | .ops = &clk_rcg2_ops, | |
646 | }, | |
647 | }; | |
648 | ||
649 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { | |
650 | .cmd_rcgr = 0x184d8, | |
651 | .mnd_width = 16, | |
652 | .hid_width = 5, | |
653 | .parent_map = gcc_parent_map_0, | |
654 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
655 | .clkr.hw.init = &(struct clk_init_data){ | |
656 | .name = "gcc_qupv3_wrap1_s3_clk_src", | |
657 | .parent_data = gcc_parents_0, | |
658 | .num_parents = 4, | |
659 | .flags = CLK_SET_RATE_PARENT, | |
660 | .ops = &clk_rcg2_ops, | |
661 | }, | |
662 | }; | |
663 | ||
664 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { | |
665 | .cmd_rcgr = 0x18608, | |
666 | .mnd_width = 16, | |
667 | .hid_width = 5, | |
668 | .parent_map = gcc_parent_map_0, | |
669 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
670 | .clkr.hw.init = &(struct clk_init_data){ | |
671 | .name = "gcc_qupv3_wrap1_s4_clk_src", | |
672 | .parent_data = gcc_parents_0, | |
673 | .num_parents = 4, | |
674 | .flags = CLK_SET_RATE_PARENT, | |
675 | .ops = &clk_rcg2_ops, | |
676 | }, | |
677 | }; | |
678 | ||
679 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { | |
680 | .cmd_rcgr = 0x18738, | |
681 | .mnd_width = 16, | |
682 | .hid_width = 5, | |
683 | .parent_map = gcc_parent_map_0, | |
684 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
685 | .clkr.hw.init = &(struct clk_init_data){ | |
686 | .name = "gcc_qupv3_wrap1_s5_clk_src", | |
687 | .parent_data = gcc_parents_0, | |
688 | .num_parents = 4, | |
689 | .flags = CLK_SET_RATE_PARENT, | |
690 | .ops = &clk_rcg2_ops, | |
691 | }, | |
692 | }; | |
693 | ||
694 | static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { | |
695 | .cmd_rcgr = 0x1e148, | |
696 | .mnd_width = 16, | |
697 | .hid_width = 5, | |
698 | .parent_map = gcc_parent_map_0, | |
699 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
700 | .clkr.hw.init = &(struct clk_init_data){ | |
701 | .name = "gcc_qupv3_wrap2_s0_clk_src", | |
702 | .parent_data = gcc_parents_0, | |
703 | .num_parents = 4, | |
704 | .flags = CLK_SET_RATE_PARENT, | |
705 | .ops = &clk_rcg2_ops, | |
706 | }, | |
707 | }; | |
708 | ||
709 | static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { | |
710 | .cmd_rcgr = 0x1e278, | |
711 | .mnd_width = 16, | |
712 | .hid_width = 5, | |
713 | .parent_map = gcc_parent_map_0, | |
714 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
715 | .clkr.hw.init = &(struct clk_init_data){ | |
716 | .name = "gcc_qupv3_wrap2_s1_clk_src", | |
717 | .parent_data = gcc_parents_0, | |
718 | .num_parents = 4, | |
719 | .flags = CLK_SET_RATE_PARENT, | |
720 | .ops = &clk_rcg2_ops, | |
721 | }, | |
722 | }; | |
723 | ||
724 | static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { | |
725 | .cmd_rcgr = 0x1e3a8, | |
726 | .mnd_width = 16, | |
727 | .hid_width = 5, | |
728 | .parent_map = gcc_parent_map_0, | |
729 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
730 | .clkr.hw.init = &(struct clk_init_data){ | |
731 | .name = "gcc_qupv3_wrap2_s2_clk_src", | |
732 | .parent_data = gcc_parents_0, | |
733 | .num_parents = 4, | |
734 | .flags = CLK_SET_RATE_PARENT, | |
735 | .ops = &clk_rcg2_ops, | |
736 | }, | |
737 | }; | |
738 | ||
739 | static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { | |
740 | .cmd_rcgr = 0x1e4d8, | |
741 | .mnd_width = 16, | |
742 | .hid_width = 5, | |
743 | .parent_map = gcc_parent_map_0, | |
744 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
745 | .clkr.hw.init = &(struct clk_init_data){ | |
746 | .name = "gcc_qupv3_wrap2_s3_clk_src", | |
747 | .parent_data = gcc_parents_0, | |
748 | .num_parents = 4, | |
749 | .flags = CLK_SET_RATE_PARENT, | |
750 | .ops = &clk_rcg2_ops, | |
751 | }, | |
752 | }; | |
753 | ||
754 | static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { | |
755 | .cmd_rcgr = 0x1e608, | |
756 | .mnd_width = 16, | |
757 | .hid_width = 5, | |
758 | .parent_map = gcc_parent_map_0, | |
759 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
760 | .clkr.hw.init = &(struct clk_init_data){ | |
761 | .name = "gcc_qupv3_wrap2_s4_clk_src", | |
762 | .parent_data = gcc_parents_0, | |
763 | .num_parents = 4, | |
764 | .flags = CLK_SET_RATE_PARENT, | |
765 | .ops = &clk_rcg2_ops, | |
766 | }, | |
767 | }; | |
768 | ||
769 | static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { | |
770 | .cmd_rcgr = 0x1e738, | |
771 | .mnd_width = 16, | |
772 | .hid_width = 5, | |
773 | .parent_map = gcc_parent_map_0, | |
774 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
775 | .clkr.hw.init = &(struct clk_init_data){ | |
776 | .name = "gcc_qupv3_wrap2_s5_clk_src", | |
777 | .parent_data = gcc_parents_0, | |
778 | .num_parents = 4, | |
779 | .flags = CLK_SET_RATE_PARENT, | |
780 | .ops = &clk_rcg2_ops, | |
781 | }, | |
782 | }; | |
783 | ||
784 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { | |
785 | F(400000, P_BI_TCXO, 12, 1, 4), | |
786 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
787 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
788 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), | |
789 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
790 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
791 | F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), | |
792 | { } | |
793 | }; | |
794 | ||
795 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | |
796 | .cmd_rcgr = 0x1400c, | |
797 | .mnd_width = 8, | |
798 | .hid_width = 5, | |
799 | .parent_map = gcc_parent_map_6, | |
800 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, | |
801 | .clkr.hw.init = &(struct clk_init_data){ | |
802 | .name = "gcc_sdcc2_apps_clk_src", | |
803 | .parent_data = gcc_parents_6, | |
804 | .num_parents = 5, | |
805 | .flags = CLK_SET_RATE_PARENT, | |
806 | .ops = &clk_rcg2_ops, | |
807 | }, | |
808 | }; | |
809 | ||
810 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { | |
811 | F(400000, P_BI_TCXO, 12, 1, 4), | |
812 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
813 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
814 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), | |
815 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
816 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
817 | { } | |
818 | }; | |
819 | ||
820 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { | |
821 | .cmd_rcgr = 0x1600c, | |
822 | .mnd_width = 8, | |
823 | .hid_width = 5, | |
824 | .parent_map = gcc_parent_map_3, | |
825 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, | |
826 | .clkr.hw.init = &(struct clk_init_data){ | |
827 | .name = "gcc_sdcc4_apps_clk_src", | |
828 | .parent_data = gcc_parents_3, | |
829 | .num_parents = 3, | |
830 | .flags = CLK_SET_RATE_PARENT, | |
831 | .ops = &clk_rcg2_ops, | |
832 | }, | |
833 | }; | |
834 | ||
835 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { | |
836 | F(105495, P_BI_TCXO, 2, 1, 91), | |
837 | { } | |
838 | }; | |
839 | ||
840 | static struct clk_rcg2 gcc_tsif_ref_clk_src = { | |
841 | .cmd_rcgr = 0x36010, | |
842 | .mnd_width = 8, | |
843 | .hid_width = 5, | |
844 | .parent_map = gcc_parent_map_7, | |
845 | .freq_tbl = ftbl_gcc_tsif_ref_clk_src, | |
846 | .clkr.hw.init = &(struct clk_init_data){ | |
847 | .name = "gcc_tsif_ref_clk_src", | |
848 | .parent_data = gcc_parents_7, | |
849 | .num_parents = 5, | |
850 | .flags = CLK_SET_RATE_PARENT, | |
851 | .ops = &clk_rcg2_ops, | |
852 | }, | |
853 | }; | |
854 | ||
855 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { | |
856 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
857 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
858 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
859 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
860 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
861 | { } | |
862 | }; | |
863 | ||
864 | static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { | |
865 | .cmd_rcgr = 0x75020, | |
866 | .mnd_width = 8, | |
867 | .hid_width = 5, | |
868 | .parent_map = gcc_parent_map_0, | |
869 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, | |
870 | .clkr.hw.init = &(struct clk_init_data){ | |
871 | .name = "gcc_ufs_card_axi_clk_src", | |
872 | .parent_data = gcc_parents_0, | |
873 | .num_parents = 4, | |
874 | .flags = CLK_SET_RATE_PARENT, | |
875 | .ops = &clk_rcg2_ops, | |
876 | }, | |
877 | }; | |
878 | ||
879 | static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { | |
880 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
881 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
882 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
883 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
884 | { } | |
885 | }; | |
886 | ||
887 | static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { | |
888 | .cmd_rcgr = 0x75060, | |
889 | .mnd_width = 0, | |
890 | .hid_width = 5, | |
891 | .parent_map = gcc_parent_map_0, | |
892 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
893 | .clkr.hw.init = &(struct clk_init_data){ | |
894 | .name = "gcc_ufs_card_ice_core_clk_src", | |
895 | .parent_data = gcc_parents_0, | |
896 | .num_parents = 4, | |
897 | .flags = CLK_SET_RATE_PARENT, | |
898 | .ops = &clk_rcg2_ops, | |
899 | }, | |
900 | }; | |
901 | ||
902 | static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { | |
903 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
904 | { } | |
905 | }; | |
906 | ||
907 | static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { | |
908 | .cmd_rcgr = 0x75094, | |
909 | .mnd_width = 0, | |
910 | .hid_width = 5, | |
911 | .parent_map = gcc_parent_map_4, | |
912 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
913 | .clkr.hw.init = &(struct clk_init_data){ | |
914 | .name = "gcc_ufs_card_phy_aux_clk_src", | |
915 | .parent_data = gcc_parents_4, | |
916 | .num_parents = 2, | |
917 | .flags = CLK_SET_RATE_PARENT, | |
918 | .ops = &clk_rcg2_ops, | |
919 | }, | |
920 | }; | |
921 | ||
922 | static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { | |
923 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
924 | F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), | |
925 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
926 | { } | |
927 | }; | |
928 | ||
929 | static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { | |
930 | .cmd_rcgr = 0x75078, | |
931 | .mnd_width = 0, | |
932 | .hid_width = 5, | |
933 | .parent_map = gcc_parent_map_0, | |
934 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, | |
935 | .clkr.hw.init = &(struct clk_init_data){ | |
936 | .name = "gcc_ufs_card_unipro_core_clk_src", | |
937 | .parent_data = gcc_parents_0, | |
938 | .num_parents = 4, | |
939 | .flags = CLK_SET_RATE_PARENT, | |
940 | .ops = &clk_rcg2_ops, | |
941 | }, | |
942 | }; | |
943 | ||
944 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { | |
945 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
946 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
947 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
948 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
949 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
950 | { } | |
951 | }; | |
952 | ||
953 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { | |
954 | .cmd_rcgr = 0x77020, | |
955 | .mnd_width = 8, | |
956 | .hid_width = 5, | |
957 | .parent_map = gcc_parent_map_0, | |
958 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, | |
959 | .clkr.hw.init = &(struct clk_init_data){ | |
960 | .name = "gcc_ufs_phy_axi_clk_src", | |
961 | .parent_data = gcc_parents_0, | |
962 | .num_parents = 4, | |
963 | .flags = CLK_SET_RATE_PARENT, | |
964 | .ops = &clk_rcg2_ops, | |
965 | }, | |
966 | }; | |
967 | ||
968 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { | |
969 | .cmd_rcgr = 0x77060, | |
970 | .mnd_width = 0, | |
971 | .hid_width = 5, | |
972 | .parent_map = gcc_parent_map_0, | |
973 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
974 | .clkr.hw.init = &(struct clk_init_data){ | |
975 | .name = "gcc_ufs_phy_ice_core_clk_src", | |
976 | .parent_data = gcc_parents_0, | |
977 | .num_parents = 4, | |
978 | .flags = CLK_SET_RATE_PARENT, | |
979 | .ops = &clk_rcg2_ops, | |
980 | }, | |
981 | }; | |
982 | ||
983 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { | |
984 | .cmd_rcgr = 0x77094, | |
985 | .mnd_width = 0, | |
986 | .hid_width = 5, | |
987 | .parent_map = gcc_parent_map_4, | |
988 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
989 | .clkr.hw.init = &(struct clk_init_data){ | |
990 | .name = "gcc_ufs_phy_phy_aux_clk_src", | |
991 | .parent_data = gcc_parents_4, | |
992 | .num_parents = 2, | |
993 | .flags = CLK_SET_RATE_PARENT, | |
994 | .ops = &clk_rcg2_ops, | |
995 | }, | |
996 | }; | |
997 | ||
998 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { | |
999 | .cmd_rcgr = 0x77078, | |
1000 | .mnd_width = 0, | |
1001 | .hid_width = 5, | |
1002 | .parent_map = gcc_parent_map_0, | |
1003 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
1004 | .clkr.hw.init = &(struct clk_init_data){ | |
1005 | .name = "gcc_ufs_phy_unipro_core_clk_src", | |
1006 | .parent_data = gcc_parents_0, | |
1007 | .num_parents = 4, | |
1008 | .flags = CLK_SET_RATE_PARENT, | |
1009 | .ops = &clk_rcg2_ops, | |
1010 | }, | |
1011 | }; | |
1012 | ||
1013 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { | |
1014 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), | |
1015 | F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), | |
1016 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), | |
1017 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
1018 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
1019 | { } | |
1020 | }; | |
1021 | ||
1022 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { | |
1023 | .cmd_rcgr = 0xf01c, | |
1024 | .mnd_width = 8, | |
1025 | .hid_width = 5, | |
1026 | .parent_map = gcc_parent_map_0, | |
1027 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1028 | .clkr.hw.init = &(struct clk_init_data){ | |
1029 | .name = "gcc_usb30_prim_master_clk_src", | |
1030 | .parent_data = gcc_parents_0, | |
1031 | .num_parents = 4, | |
1032 | .flags = CLK_SET_RATE_PARENT, | |
1033 | .ops = &clk_rcg2_ops, | |
1034 | }, | |
1035 | }; | |
1036 | ||
1037 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { | |
1038 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1039 | F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), | |
1040 | F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), | |
1041 | { } | |
1042 | }; | |
1043 | ||
1044 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { | |
1045 | .cmd_rcgr = 0xf034, | |
1046 | .mnd_width = 0, | |
1047 | .hid_width = 5, | |
1048 | .parent_map = gcc_parent_map_0, | |
1049 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
1050 | .clkr.hw.init = &(struct clk_init_data){ | |
1051 | .name = "gcc_usb30_prim_mock_utmi_clk_src", | |
1052 | .parent_data = gcc_parents_0, | |
1053 | .num_parents = 4, | |
1054 | .flags = CLK_SET_RATE_PARENT, | |
1055 | .ops = &clk_rcg2_ops, | |
1056 | }, | |
1057 | }; | |
1058 | ||
1059 | static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { | |
1060 | .cmd_rcgr = 0x1001c, | |
1061 | .mnd_width = 8, | |
1062 | .hid_width = 5, | |
1063 | .parent_map = gcc_parent_map_0, | |
1064 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1065 | .clkr.hw.init = &(struct clk_init_data){ | |
1066 | .name = "gcc_usb30_sec_master_clk_src", | |
1067 | .parent_data = gcc_parents_0, | |
1068 | .num_parents = 4, | |
1069 | .flags = CLK_SET_RATE_PARENT, | |
1070 | .ops = &clk_rcg2_ops, | |
1071 | }, | |
1072 | }; | |
1073 | ||
1074 | static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { | |
1075 | .cmd_rcgr = 0x10034, | |
1076 | .mnd_width = 0, | |
1077 | .hid_width = 5, | |
1078 | .parent_map = gcc_parent_map_0, | |
1079 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
1080 | .clkr.hw.init = &(struct clk_init_data){ | |
1081 | .name = "gcc_usb30_sec_mock_utmi_clk_src", | |
1082 | .parent_data = gcc_parents_0, | |
1083 | .num_parents = 4, | |
1084 | .flags = CLK_SET_RATE_PARENT, | |
1085 | .ops = &clk_rcg2_ops, | |
1086 | }, | |
1087 | }; | |
1088 | ||
1089 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { | |
1090 | .cmd_rcgr = 0xf060, | |
1091 | .mnd_width = 0, | |
1092 | .hid_width = 5, | |
1093 | .parent_map = gcc_parent_map_2, | |
1094 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1095 | .clkr.hw.init = &(struct clk_init_data){ | |
1096 | .name = "gcc_usb3_prim_phy_aux_clk_src", | |
1097 | .parent_data = gcc_parents_2, | |
1098 | .num_parents = 3, | |
1099 | .flags = CLK_SET_RATE_PARENT, | |
1100 | .ops = &clk_rcg2_ops, | |
1101 | }, | |
1102 | }; | |
1103 | ||
1104 | static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { | |
1105 | .cmd_rcgr = 0x10060, | |
1106 | .mnd_width = 0, | |
1107 | .hid_width = 5, | |
1108 | .parent_map = gcc_parent_map_2, | |
1109 | .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, | |
1110 | .clkr.hw.init = &(struct clk_init_data){ | |
1111 | .name = "gcc_usb3_sec_phy_aux_clk_src", | |
1112 | .parent_data = gcc_parents_2, | |
1113 | .num_parents = 3, | |
1114 | .flags = CLK_SET_RATE_PARENT, | |
1115 | .ops = &clk_rcg2_ops, | |
1116 | }, | |
1117 | }; | |
1118 | ||
1119 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { | |
1120 | .halt_reg = 0x90018, | |
1121 | .halt_check = BRANCH_HALT, | |
1122 | .clkr = { | |
1123 | .enable_reg = 0x90018, | |
1124 | .enable_mask = BIT(0), | |
1125 | .hw.init = &(struct clk_init_data){ | |
1126 | .name = "gcc_aggre_noc_pcie_tbu_clk", | |
1127 | .ops = &clk_branch2_ops, | |
1128 | }, | |
1129 | }, | |
1130 | }; | |
1131 | ||
1132 | static struct clk_branch gcc_aggre_ufs_card_axi_clk = { | |
1133 | .halt_reg = 0x750c0, | |
1134 | .halt_check = BRANCH_HALT, | |
1135 | .hwcg_reg = 0x750c0, | |
1136 | .hwcg_bit = 1, | |
1137 | .clkr = { | |
1138 | .enable_reg = 0x750c0, | |
1139 | .enable_mask = BIT(0), | |
1140 | .hw.init = &(struct clk_init_data){ | |
1141 | .name = "gcc_aggre_ufs_card_axi_clk", | |
1142 | .parent_hws = (const struct clk_hw *[]){ | |
1143 | &gcc_ufs_card_axi_clk_src.clkr.hw }, | |
1144 | .num_parents = 1, | |
1145 | .flags = CLK_SET_RATE_PARENT, | |
1146 | .ops = &clk_branch2_ops, | |
1147 | }, | |
1148 | }, | |
1149 | }; | |
1150 | ||
1151 | static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { | |
1152 | .halt_reg = 0x750c0, | |
1153 | .halt_check = BRANCH_HALT, | |
1154 | .hwcg_reg = 0x750c0, | |
1155 | .hwcg_bit = 1, | |
1156 | .clkr = { | |
1157 | .enable_reg = 0x750c0, | |
1158 | .enable_mask = BIT(1), | |
1159 | .hw.init = &(struct clk_init_data){ | |
1160 | .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", | |
1161 | .parent_hws = (const struct clk_hw *[]){ | |
1162 | &gcc_aggre_ufs_card_axi_clk.clkr.hw }, | |
1163 | .num_parents = 1, | |
1164 | .flags = CLK_SET_RATE_PARENT, | |
1165 | .ops = &clk_branch_simple_ops, | |
1166 | }, | |
1167 | }, | |
1168 | }; | |
1169 | ||
1170 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { | |
1171 | .halt_reg = 0x770c0, | |
1172 | .halt_check = BRANCH_HALT, | |
1173 | .hwcg_reg = 0x770c0, | |
1174 | .hwcg_bit = 1, | |
1175 | .clkr = { | |
1176 | .enable_reg = 0x770c0, | |
1177 | .enable_mask = BIT(0), | |
1178 | .hw.init = &(struct clk_init_data){ | |
1179 | .name = "gcc_aggre_ufs_phy_axi_clk", | |
1180 | .parent_hws = (const struct clk_hw *[]){ | |
1181 | &gcc_ufs_phy_axi_clk_src.clkr.hw }, | |
1182 | .num_parents = 1, | |
1183 | .flags = CLK_SET_RATE_PARENT, | |
1184 | .ops = &clk_branch2_ops, | |
1185 | }, | |
1186 | }, | |
1187 | }; | |
1188 | ||
1189 | static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { | |
1190 | .halt_reg = 0x770c0, | |
1191 | .halt_check = BRANCH_HALT, | |
1192 | .hwcg_reg = 0x770c0, | |
1193 | .hwcg_bit = 1, | |
1194 | .clkr = { | |
1195 | .enable_reg = 0x770c0, | |
1196 | .enable_mask = BIT(1), | |
1197 | .hw.init = &(struct clk_init_data){ | |
1198 | .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", | |
1199 | .parent_hws = (const struct clk_hw *[]){ | |
1200 | &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, | |
1201 | .num_parents = 1, | |
1202 | .flags = CLK_SET_RATE_PARENT, | |
1203 | .ops = &clk_branch_simple_ops, | |
1204 | }, | |
1205 | }, | |
1206 | }; | |
1207 | ||
1208 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { | |
1209 | .halt_reg = 0xf07c, | |
1210 | .halt_check = BRANCH_HALT, | |
1211 | .clkr = { | |
1212 | .enable_reg = 0xf07c, | |
1213 | .enable_mask = BIT(0), | |
1214 | .hw.init = &(struct clk_init_data){ | |
1215 | .name = "gcc_aggre_usb3_prim_axi_clk", | |
1216 | .parent_hws = (const struct clk_hw *[]){ | |
1217 | &gcc_usb30_prim_master_clk_src.clkr.hw }, | |
1218 | .num_parents = 1, | |
1219 | .flags = CLK_SET_RATE_PARENT, | |
1220 | .ops = &clk_branch2_ops, | |
1221 | }, | |
1222 | }, | |
1223 | }; | |
1224 | ||
1225 | static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { | |
1226 | .halt_reg = 0x1007c, | |
1227 | .halt_check = BRANCH_HALT, | |
1228 | .clkr = { | |
1229 | .enable_reg = 0x1007c, | |
1230 | .enable_mask = BIT(0), | |
1231 | .hw.init = &(struct clk_init_data){ | |
1232 | .name = "gcc_aggre_usb3_sec_axi_clk", | |
1233 | .parent_hws = (const struct clk_hw *[]){ | |
1234 | &gcc_usb30_sec_master_clk_src.clkr.hw }, | |
1235 | .num_parents = 1, | |
1236 | .flags = CLK_SET_RATE_PARENT, | |
1237 | .ops = &clk_branch2_ops, | |
1238 | }, | |
1239 | }, | |
1240 | }; | |
1241 | ||
1242 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1243 | .halt_reg = 0x38004, | |
1244 | .halt_check = BRANCH_HALT_VOTED, | |
1245 | .hwcg_reg = 0x38004, | |
1246 | .hwcg_bit = 1, | |
1247 | .clkr = { | |
1248 | .enable_reg = 0x52004, | |
1249 | .enable_mask = BIT(10), | |
1250 | .hw.init = &(struct clk_init_data){ | |
1251 | .name = "gcc_boot_rom_ahb_clk", | |
1252 | .ops = &clk_branch2_ops, | |
1253 | }, | |
1254 | }, | |
1255 | }; | |
1256 | ||
1257 | /* | |
1258 | * Clock ON depends on external parent 'config noc', so cant poll | |
1259 | * delay and also mark as crtitical for camss boot | |
1260 | */ | |
1261 | static struct clk_branch gcc_camera_ahb_clk = { | |
1262 | .halt_reg = 0xb008, | |
1263 | .halt_check = BRANCH_HALT_DELAY, | |
1264 | .hwcg_reg = 0xb008, | |
1265 | .hwcg_bit = 1, | |
1266 | .clkr = { | |
1267 | .enable_reg = 0xb008, | |
1268 | .enable_mask = BIT(0), | |
1269 | .hw.init = &(struct clk_init_data){ | |
1270 | .name = "gcc_camera_ahb_clk", | |
1271 | .flags = CLK_IS_CRITICAL, | |
1272 | .ops = &clk_branch2_ops, | |
1273 | }, | |
1274 | }, | |
1275 | }; | |
1276 | ||
1277 | static struct clk_branch gcc_camera_hf_axi_clk = { | |
1278 | .halt_reg = 0xb030, | |
1279 | .halt_check = BRANCH_HALT, | |
1280 | .clkr = { | |
1281 | .enable_reg = 0xb030, | |
1282 | .enable_mask = BIT(0), | |
1283 | .hw.init = &(struct clk_init_data){ | |
1284 | .name = "gcc_camera_hf_axi_clk", | |
1285 | .ops = &clk_branch2_ops, | |
1286 | }, | |
1287 | }, | |
1288 | }; | |
1289 | ||
1290 | static struct clk_branch gcc_camera_sf_axi_clk = { | |
1291 | .halt_reg = 0xb034, | |
1292 | .halt_check = BRANCH_HALT, | |
1293 | .clkr = { | |
1294 | .enable_reg = 0xb034, | |
1295 | .enable_mask = BIT(0), | |
1296 | .hw.init = &(struct clk_init_data){ | |
1297 | .name = "gcc_camera_sf_axi_clk", | |
1298 | .ops = &clk_branch2_ops, | |
1299 | }, | |
1300 | }, | |
1301 | }; | |
1302 | ||
1303 | /* XO critical input to camss, so no need to poll */ | |
1304 | static struct clk_branch gcc_camera_xo_clk = { | |
1305 | .halt_reg = 0xb044, | |
1306 | .halt_check = BRANCH_HALT_DELAY, | |
1307 | .clkr = { | |
1308 | .enable_reg = 0xb044, | |
1309 | .enable_mask = BIT(0), | |
1310 | .hw.init = &(struct clk_init_data){ | |
1311 | .name = "gcc_camera_xo_clk", | |
1312 | .flags = CLK_IS_CRITICAL, | |
1313 | .ops = &clk_branch2_ops, | |
1314 | }, | |
1315 | }, | |
1316 | }; | |
1317 | ||
1318 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { | |
1319 | .halt_reg = 0xf078, | |
1320 | .halt_check = BRANCH_HALT, | |
1321 | .clkr = { | |
1322 | .enable_reg = 0xf078, | |
1323 | .enable_mask = BIT(0), | |
1324 | .hw.init = &(struct clk_init_data){ | |
1325 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", | |
1326 | .parent_hws = (const struct clk_hw *[]){ | |
1327 | &gcc_usb30_prim_master_clk_src.clkr.hw }, | |
1328 | .num_parents = 1, | |
1329 | .flags = CLK_SET_RATE_PARENT, | |
1330 | .ops = &clk_branch2_ops, | |
1331 | }, | |
1332 | }, | |
1333 | }; | |
1334 | ||
1335 | static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { | |
1336 | .halt_reg = 0x10078, | |
1337 | .halt_check = BRANCH_HALT, | |
1338 | .clkr = { | |
1339 | .enable_reg = 0x10078, | |
1340 | .enable_mask = BIT(0), | |
1341 | .hw.init = &(struct clk_init_data){ | |
1342 | .name = "gcc_cfg_noc_usb3_sec_axi_clk", | |
1343 | .parent_hws = (const struct clk_hw *[]){ | |
1344 | &gcc_usb30_sec_master_clk_src.clkr.hw }, | |
1345 | .num_parents = 1, | |
1346 | .flags = CLK_SET_RATE_PARENT, | |
1347 | .ops = &clk_branch2_ops, | |
1348 | }, | |
1349 | }, | |
1350 | }; | |
1351 | ||
1352 | static struct clk_branch gcc_cpuss_ahb_clk = { | |
1353 | .halt_reg = 0x48000, | |
1354 | .halt_check = BRANCH_HALT_VOTED, | |
1355 | .clkr = { | |
1356 | .enable_reg = 0x52004, | |
1357 | .enable_mask = BIT(21), | |
1358 | .hw.init = &(struct clk_init_data){ | |
1359 | .name = "gcc_cpuss_ahb_clk", | |
1360 | .parent_hws = (const struct clk_hw *[]){ | |
1361 | &gcc_cpuss_ahb_clk_src.clkr.hw }, | |
1362 | .num_parents = 1, | |
1363 | /* required for cpuss */ | |
1364 | .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, | |
1365 | .ops = &clk_branch2_ops, | |
1366 | }, | |
1367 | }, | |
1368 | }; | |
1369 | ||
1370 | static struct clk_branch gcc_cpuss_dvm_bus_clk = { | |
1371 | .halt_reg = 0x48190, | |
1372 | .halt_check = BRANCH_HALT, | |
1373 | .clkr = { | |
1374 | .enable_reg = 0x48190, | |
1375 | .enable_mask = BIT(0), | |
1376 | .hw.init = &(struct clk_init_data){ | |
1377 | .name = "gcc_cpuss_dvm_bus_clk", | |
1378 | /* required for cpuss */ | |
1379 | .flags = CLK_IS_CRITICAL, | |
1380 | .ops = &clk_branch2_ops, | |
1381 | }, | |
1382 | }, | |
1383 | }; | |
1384 | ||
1385 | static struct clk_branch gcc_cpuss_gnoc_clk = { | |
1386 | .halt_reg = 0x48004, | |
1387 | .halt_check = BRANCH_HALT_VOTED, | |
1388 | .hwcg_reg = 0x48004, | |
1389 | .hwcg_bit = 1, | |
1390 | .clkr = { | |
1391 | .enable_reg = 0x52004, | |
1392 | .enable_mask = BIT(22), | |
1393 | .hw.init = &(struct clk_init_data){ | |
1394 | .name = "gcc_cpuss_gnoc_clk", | |
1395 | /* required for cpuss */ | |
1396 | .flags = CLK_IS_CRITICAL, | |
1397 | .ops = &clk_branch2_ops, | |
1398 | }, | |
1399 | }, | |
1400 | }; | |
1401 | ||
1402 | static struct clk_branch gcc_cpuss_rbcpr_clk = { | |
1403 | .halt_reg = 0x48008, | |
1404 | .halt_check = BRANCH_HALT, | |
1405 | .clkr = { | |
1406 | .enable_reg = 0x48008, | |
1407 | .enable_mask = BIT(0), | |
1408 | .hw.init = &(struct clk_init_data){ | |
1409 | .name = "gcc_cpuss_rbcpr_clk", | |
1410 | .ops = &clk_branch2_ops, | |
1411 | }, | |
1412 | }, | |
1413 | }; | |
1414 | ||
1415 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { | |
1416 | .halt_reg = 0x71154, | |
1417 | .halt_check = BRANCH_VOTED, | |
1418 | .clkr = { | |
1419 | .enable_reg = 0x71154, | |
1420 | .enable_mask = BIT(0), | |
1421 | .hw.init = &(struct clk_init_data){ | |
1422 | .name = "gcc_ddrss_gpu_axi_clk", | |
1423 | .ops = &clk_branch2_ops, | |
1424 | }, | |
1425 | }, | |
1426 | }; | |
1427 | ||
1428 | /* | |
1429 | * Clock ON depends on external parent 'config noc', so cant poll | |
1430 | * delay and also mark as crtitical for disp boot | |
1431 | */ | |
1432 | static struct clk_branch gcc_disp_ahb_clk = { | |
1433 | .halt_reg = 0xb00c, | |
1434 | .halt_check = BRANCH_HALT_DELAY, | |
1435 | .hwcg_reg = 0xb00c, | |
1436 | .hwcg_bit = 1, | |
1437 | .clkr = { | |
1438 | .enable_reg = 0xb00c, | |
1439 | .enable_mask = BIT(0), | |
1440 | .hw.init = &(struct clk_init_data){ | |
1441 | .name = "gcc_disp_ahb_clk", | |
1442 | .flags = CLK_IS_CRITICAL, | |
1443 | .ops = &clk_branch2_ops, | |
1444 | }, | |
1445 | }, | |
1446 | }; | |
1447 | ||
1448 | static struct clk_branch gcc_disp_hf_axi_clk = { | |
1449 | .halt_reg = 0xb038, | |
1450 | .halt_check = BRANCH_HALT, | |
1451 | .clkr = { | |
1452 | .enable_reg = 0xb038, | |
1453 | .enable_mask = BIT(0), | |
1454 | .hw.init = &(struct clk_init_data){ | |
1455 | .name = "gcc_disp_hf_axi_clk", | |
1456 | .ops = &clk_branch2_ops, | |
1457 | }, | |
1458 | }, | |
1459 | }; | |
1460 | ||
1461 | static struct clk_branch gcc_disp_sf_axi_clk = { | |
1462 | .halt_reg = 0xb03c, | |
1463 | .halt_check = BRANCH_HALT, | |
1464 | .clkr = { | |
1465 | .enable_reg = 0xb03c, | |
1466 | .enable_mask = BIT(0), | |
1467 | .hw.init = &(struct clk_init_data){ | |
1468 | .name = "gcc_disp_sf_axi_clk", | |
1469 | .ops = &clk_branch2_ops, | |
1470 | }, | |
1471 | }, | |
1472 | }; | |
1473 | ||
1474 | /* XO critical input to disp, so no need to poll */ | |
1475 | static struct clk_branch gcc_disp_xo_clk = { | |
1476 | .halt_reg = 0xb048, | |
1477 | .halt_check = BRANCH_HALT_DELAY, | |
1478 | .clkr = { | |
1479 | .enable_reg = 0xb048, | |
1480 | .enable_mask = BIT(0), | |
1481 | .hw.init = &(struct clk_init_data){ | |
1482 | .name = "gcc_disp_xo_clk", | |
1483 | .flags = CLK_IS_CRITICAL, | |
1484 | .ops = &clk_branch2_ops, | |
1485 | }, | |
1486 | }, | |
1487 | }; | |
1488 | ||
1489 | static struct clk_branch gcc_emac_axi_clk = { | |
1490 | .halt_reg = 0x6010, | |
1491 | .halt_check = BRANCH_HALT, | |
1492 | .clkr = { | |
1493 | .enable_reg = 0x6010, | |
1494 | .enable_mask = BIT(0), | |
1495 | .hw.init = &(struct clk_init_data){ | |
1496 | .name = "gcc_emac_axi_clk", | |
1497 | .ops = &clk_branch2_ops, | |
1498 | }, | |
1499 | }, | |
1500 | }; | |
1501 | ||
1502 | static struct clk_branch gcc_emac_ptp_clk = { | |
1503 | .halt_reg = 0x6034, | |
1504 | .halt_check = BRANCH_HALT, | |
1505 | .clkr = { | |
1506 | .enable_reg = 0x6034, | |
1507 | .enable_mask = BIT(0), | |
1508 | .hw.init = &(struct clk_init_data){ | |
1509 | .name = "gcc_emac_ptp_clk", | |
1510 | .parent_hws = (const struct clk_hw *[]){ | |
1511 | &gcc_emac_ptp_clk_src.clkr.hw }, | |
1512 | .num_parents = 1, | |
1513 | .flags = CLK_SET_RATE_PARENT, | |
1514 | .ops = &clk_branch2_ops, | |
1515 | }, | |
1516 | }, | |
1517 | }; | |
1518 | ||
1519 | static struct clk_branch gcc_emac_rgmii_clk = { | |
1520 | .halt_reg = 0x6018, | |
1521 | .halt_check = BRANCH_HALT, | |
1522 | .clkr = { | |
1523 | .enable_reg = 0x6018, | |
1524 | .enable_mask = BIT(0), | |
1525 | .hw.init = &(struct clk_init_data){ | |
1526 | .name = "gcc_emac_rgmii_clk", | |
1527 | .parent_hws = (const struct clk_hw *[]){ | |
1528 | &gcc_emac_rgmii_clk_src.clkr.hw }, | |
1529 | .num_parents = 1, | |
1530 | .flags = CLK_SET_RATE_PARENT, | |
1531 | .ops = &clk_branch2_ops, | |
1532 | }, | |
1533 | }, | |
1534 | }; | |
1535 | ||
1536 | static struct clk_branch gcc_emac_slv_ahb_clk = { | |
1537 | .halt_reg = 0x6014, | |
1538 | .halt_check = BRANCH_HALT, | |
1539 | .hwcg_reg = 0x6014, | |
1540 | .hwcg_bit = 1, | |
1541 | .clkr = { | |
1542 | .enable_reg = 0x6014, | |
1543 | .enable_mask = BIT(0), | |
1544 | .hw.init = &(struct clk_init_data){ | |
1545 | .name = "gcc_emac_slv_ahb_clk", | |
1546 | .ops = &clk_branch2_ops, | |
1547 | }, | |
1548 | }, | |
1549 | }; | |
1550 | ||
1551 | static struct clk_branch gcc_gp1_clk = { | |
1552 | .halt_reg = 0x64000, | |
1553 | .halt_check = BRANCH_HALT, | |
1554 | .clkr = { | |
1555 | .enable_reg = 0x64000, | |
1556 | .enable_mask = BIT(0), | |
1557 | .hw.init = &(struct clk_init_data){ | |
1558 | .name = "gcc_gp1_clk", | |
1559 | .parent_hws = (const struct clk_hw *[]){ | |
1560 | &gcc_gp1_clk_src.clkr.hw }, | |
1561 | .num_parents = 1, | |
1562 | .flags = CLK_SET_RATE_PARENT, | |
1563 | .ops = &clk_branch2_ops, | |
1564 | }, | |
1565 | }, | |
1566 | }; | |
1567 | ||
1568 | static struct clk_branch gcc_gp2_clk = { | |
1569 | .halt_reg = 0x65000, | |
1570 | .halt_check = BRANCH_HALT, | |
1571 | .clkr = { | |
1572 | .enable_reg = 0x65000, | |
1573 | .enable_mask = BIT(0), | |
1574 | .hw.init = &(struct clk_init_data){ | |
1575 | .name = "gcc_gp2_clk", | |
1576 | .parent_hws = (const struct clk_hw *[]){ | |
1577 | &gcc_gp2_clk_src.clkr.hw }, | |
1578 | .num_parents = 1, | |
1579 | .flags = CLK_SET_RATE_PARENT, | |
1580 | .ops = &clk_branch2_ops, | |
1581 | }, | |
1582 | }, | |
1583 | }; | |
1584 | ||
1585 | static struct clk_branch gcc_gp3_clk = { | |
1586 | .halt_reg = 0x66000, | |
1587 | .halt_check = BRANCH_HALT, | |
1588 | .clkr = { | |
1589 | .enable_reg = 0x66000, | |
1590 | .enable_mask = BIT(0), | |
1591 | .hw.init = &(struct clk_init_data){ | |
1592 | .name = "gcc_gp3_clk", | |
1593 | .parent_hws = (const struct clk_hw *[]){ | |
1594 | &gcc_gp3_clk_src.clkr.hw }, | |
1595 | .num_parents = 1, | |
1596 | .flags = CLK_SET_RATE_PARENT, | |
1597 | .ops = &clk_branch2_ops, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
1602 | static struct clk_branch gcc_gpu_cfg_ahb_clk = { | |
1603 | .halt_reg = 0x71004, | |
1604 | .halt_check = BRANCH_HALT, | |
1605 | .hwcg_reg = 0x71004, | |
1606 | .hwcg_bit = 1, | |
1607 | .clkr = { | |
1608 | .enable_reg = 0x71004, | |
1609 | .enable_mask = BIT(0), | |
1610 | .hw.init = &(struct clk_init_data){ | |
1611 | .name = "gcc_gpu_cfg_ahb_clk", | |
1612 | /* required for gpu */ | |
1613 | .flags = CLK_IS_CRITICAL, | |
1614 | .ops = &clk_branch2_ops, | |
1615 | }, | |
1616 | }, | |
1617 | }; | |
1618 | ||
1619 | static struct clk_branch gcc_gpu_iref_clk = { | |
1620 | .halt_reg = 0x8c010, | |
1621 | .halt_check = BRANCH_HALT, | |
1622 | .clkr = { | |
1623 | .enable_reg = 0x8c010, | |
1624 | .enable_mask = BIT(0), | |
1625 | .hw.init = &(struct clk_init_data){ | |
1626 | .name = "gcc_gpu_iref_clk", | |
1627 | .ops = &clk_branch2_ops, | |
1628 | }, | |
1629 | }, | |
1630 | }; | |
1631 | ||
1632 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { | |
1633 | .halt_reg = 0x7100c, | |
1634 | .halt_check = BRANCH_VOTED, | |
1635 | .clkr = { | |
1636 | .enable_reg = 0x7100c, | |
1637 | .enable_mask = BIT(0), | |
1638 | .hw.init = &(struct clk_init_data){ | |
1639 | .name = "gcc_gpu_memnoc_gfx_clk", | |
1640 | .ops = &clk_branch2_ops, | |
1641 | }, | |
1642 | }, | |
1643 | }; | |
1644 | ||
1645 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { | |
1646 | .halt_reg = 0x71018, | |
1647 | .halt_check = BRANCH_HALT, | |
1648 | .clkr = { | |
1649 | .enable_reg = 0x71018, | |
1650 | .enable_mask = BIT(0), | |
1651 | .hw.init = &(struct clk_init_data){ | |
1652 | .name = "gcc_gpu_snoc_dvm_gfx_clk", | |
1653 | .ops = &clk_branch2_ops, | |
1654 | }, | |
1655 | }, | |
1656 | }; | |
1657 | ||
1658 | static struct clk_branch gcc_npu_at_clk = { | |
1659 | .halt_reg = 0x4d010, | |
1660 | .halt_check = BRANCH_VOTED, | |
1661 | .clkr = { | |
1662 | .enable_reg = 0x4d010, | |
1663 | .enable_mask = BIT(0), | |
1664 | .hw.init = &(struct clk_init_data){ | |
1665 | .name = "gcc_npu_at_clk", | |
1666 | .ops = &clk_branch2_ops, | |
1667 | }, | |
1668 | }, | |
1669 | }; | |
1670 | ||
1671 | static struct clk_branch gcc_npu_axi_clk = { | |
1672 | .halt_reg = 0x4d008, | |
1673 | .halt_check = BRANCH_VOTED, | |
1674 | .clkr = { | |
1675 | .enable_reg = 0x4d008, | |
1676 | .enable_mask = BIT(0), | |
1677 | .hw.init = &(struct clk_init_data){ | |
1678 | .name = "gcc_npu_axi_clk", | |
1679 | .ops = &clk_branch2_ops, | |
1680 | }, | |
1681 | }, | |
1682 | }; | |
1683 | ||
1684 | static struct clk_branch gcc_npu_cfg_ahb_clk = { | |
1685 | .halt_reg = 0x4d004, | |
1686 | .halt_check = BRANCH_HALT, | |
1687 | .hwcg_reg = 0x4d004, | |
1688 | .hwcg_bit = 1, | |
1689 | .clkr = { | |
1690 | .enable_reg = 0x4d004, | |
1691 | .enable_mask = BIT(0), | |
1692 | .hw.init = &(struct clk_init_data){ | |
1693 | .name = "gcc_npu_cfg_ahb_clk", | |
1694 | /* required for npu */ | |
1695 | .flags = CLK_IS_CRITICAL, | |
1696 | .ops = &clk_branch2_ops, | |
1697 | }, | |
1698 | }, | |
1699 | }; | |
1700 | ||
1701 | static struct clk_branch gcc_npu_trig_clk = { | |
1702 | .halt_reg = 0x4d00c, | |
1703 | .halt_check = BRANCH_VOTED, | |
1704 | .clkr = { | |
1705 | .enable_reg = 0x4d00c, | |
1706 | .enable_mask = BIT(0), | |
1707 | .hw.init = &(struct clk_init_data){ | |
1708 | .name = "gcc_npu_trig_clk", | |
1709 | .ops = &clk_branch2_ops, | |
1710 | }, | |
1711 | }, | |
1712 | }; | |
1713 | ||
1714 | static struct clk_branch gcc_pcie0_phy_refgen_clk = { | |
1715 | .halt_reg = 0x6f02c, | |
1716 | .halt_check = BRANCH_HALT, | |
1717 | .clkr = { | |
1718 | .enable_reg = 0x6f02c, | |
1719 | .enable_mask = BIT(0), | |
1720 | .hw.init = &(struct clk_init_data){ | |
1721 | .name = "gcc_pcie0_phy_refgen_clk", | |
1722 | .parent_hws = (const struct clk_hw *[]){ | |
1723 | &gcc_pcie_phy_refgen_clk_src.clkr.hw }, | |
1724 | .num_parents = 1, | |
1725 | .flags = CLK_SET_RATE_PARENT, | |
1726 | .ops = &clk_branch2_ops, | |
1727 | }, | |
1728 | }, | |
1729 | }; | |
1730 | ||
1731 | static struct clk_branch gcc_pcie1_phy_refgen_clk = { | |
1732 | .halt_reg = 0x6f030, | |
1733 | .halt_check = BRANCH_HALT, | |
1734 | .clkr = { | |
1735 | .enable_reg = 0x6f030, | |
1736 | .enable_mask = BIT(0), | |
1737 | .hw.init = &(struct clk_init_data){ | |
1738 | .name = "gcc_pcie1_phy_refgen_clk", | |
1739 | .parent_hws = (const struct clk_hw *[]){ | |
1740 | &gcc_pcie_phy_refgen_clk_src.clkr.hw }, | |
1741 | .num_parents = 1, | |
1742 | .flags = CLK_SET_RATE_PARENT, | |
1743 | .ops = &clk_branch2_ops, | |
1744 | }, | |
1745 | }, | |
1746 | }; | |
1747 | ||
1748 | static struct clk_branch gcc_pcie_0_aux_clk = { | |
1749 | .halt_reg = 0x6b020, | |
1750 | .halt_check = BRANCH_HALT_VOTED, | |
1751 | .clkr = { | |
1752 | .enable_reg = 0x5200c, | |
1753 | .enable_mask = BIT(3), | |
1754 | .hw.init = &(struct clk_init_data){ | |
1755 | .name = "gcc_pcie_0_aux_clk", | |
1756 | .parent_hws = (const struct clk_hw *[]){ | |
1757 | &gcc_pcie_0_aux_clk_src.clkr.hw }, | |
1758 | .num_parents = 1, | |
1759 | .flags = CLK_SET_RATE_PARENT, | |
1760 | .ops = &clk_branch2_ops, | |
1761 | }, | |
1762 | }, | |
1763 | }; | |
1764 | ||
1765 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
1766 | .halt_reg = 0x6b01c, | |
1767 | .halt_check = BRANCH_HALT_VOTED, | |
1768 | .hwcg_reg = 0x6b01c, | |
1769 | .hwcg_bit = 1, | |
1770 | .clkr = { | |
1771 | .enable_reg = 0x5200c, | |
1772 | .enable_mask = BIT(2), | |
1773 | .hw.init = &(struct clk_init_data){ | |
1774 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
1775 | .ops = &clk_branch2_ops, | |
1776 | }, | |
1777 | }, | |
1778 | }; | |
1779 | ||
1780 | static struct clk_branch gcc_pcie_0_clkref_clk = { | |
1781 | .halt_reg = 0x8c00c, | |
1782 | .halt_check = BRANCH_HALT, | |
1783 | .clkr = { | |
1784 | .enable_reg = 0x8c00c, | |
1785 | .enable_mask = BIT(0), | |
1786 | .hw.init = &(struct clk_init_data){ | |
1787 | .name = "gcc_pcie_0_clkref_clk", | |
1788 | .ops = &clk_branch2_ops, | |
1789 | }, | |
1790 | }, | |
1791 | }; | |
1792 | ||
1793 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
1794 | .halt_reg = 0x6b018, | |
1795 | .halt_check = BRANCH_HALT_VOTED, | |
1796 | .clkr = { | |
1797 | .enable_reg = 0x5200c, | |
1798 | .enable_mask = BIT(1), | |
1799 | .hw.init = &(struct clk_init_data){ | |
1800 | .name = "gcc_pcie_0_mstr_axi_clk", | |
1801 | .ops = &clk_branch2_ops, | |
1802 | }, | |
1803 | }, | |
1804 | }; | |
1805 | ||
1806 | /* Clock ON depends on external parent 'PIPE' clock, so dont poll */ | |
1807 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
1808 | .halt_reg = 0x6b024, | |
1809 | .halt_check = BRANCH_HALT_DELAY, | |
1810 | .clkr = { | |
1811 | .enable_reg = 0x5200c, | |
1812 | .enable_mask = BIT(4), | |
1813 | .hw.init = &(struct clk_init_data){ | |
1814 | .name = "gcc_pcie_0_pipe_clk", | |
1815 | .ops = &clk_branch2_ops, | |
1816 | }, | |
1817 | }, | |
1818 | }; | |
1819 | ||
1820 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
1821 | .halt_reg = 0x6b014, | |
1822 | .halt_check = BRANCH_HALT_VOTED, | |
1823 | .hwcg_reg = 0x6b014, | |
1824 | .hwcg_bit = 1, | |
1825 | .clkr = { | |
1826 | .enable_reg = 0x5200c, | |
1827 | .enable_mask = BIT(0), | |
1828 | .hw.init = &(struct clk_init_data){ | |
1829 | .name = "gcc_pcie_0_slv_axi_clk", | |
1830 | .ops = &clk_branch2_ops, | |
1831 | }, | |
1832 | }, | |
1833 | }; | |
1834 | ||
1835 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { | |
1836 | .halt_reg = 0x6b010, | |
1837 | .halt_check = BRANCH_HALT_VOTED, | |
1838 | .clkr = { | |
1839 | .enable_reg = 0x5200c, | |
1840 | .enable_mask = BIT(5), | |
1841 | .hw.init = &(struct clk_init_data){ | |
1842 | .name = "gcc_pcie_0_slv_q2a_axi_clk", | |
1843 | .ops = &clk_branch2_ops, | |
1844 | }, | |
1845 | }, | |
1846 | }; | |
1847 | ||
1848 | static struct clk_branch gcc_pcie_1_aux_clk = { | |
1849 | .halt_reg = 0x8d020, | |
1850 | .halt_check = BRANCH_HALT_VOTED, | |
1851 | .clkr = { | |
1852 | .enable_reg = 0x52004, | |
1853 | .enable_mask = BIT(29), | |
1854 | .hw.init = &(struct clk_init_data){ | |
1855 | .name = "gcc_pcie_1_aux_clk", | |
1856 | .parent_hws = (const struct clk_hw *[]){ | |
1857 | &gcc_pcie_1_aux_clk_src.clkr.hw }, | |
1858 | .num_parents = 1, | |
1859 | .flags = CLK_SET_RATE_PARENT, | |
1860 | .ops = &clk_branch2_ops, | |
1861 | }, | |
1862 | }, | |
1863 | }; | |
1864 | ||
1865 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { | |
1866 | .halt_reg = 0x8d01c, | |
1867 | .halt_check = BRANCH_HALT_VOTED, | |
1868 | .hwcg_reg = 0x8d01c, | |
1869 | .hwcg_bit = 1, | |
1870 | .clkr = { | |
1871 | .enable_reg = 0x52004, | |
1872 | .enable_mask = BIT(28), | |
1873 | .hw.init = &(struct clk_init_data){ | |
1874 | .name = "gcc_pcie_1_cfg_ahb_clk", | |
1875 | .ops = &clk_branch2_ops, | |
1876 | }, | |
1877 | }, | |
1878 | }; | |
1879 | ||
1880 | static struct clk_branch gcc_pcie_1_clkref_clk = { | |
1881 | .halt_reg = 0x8c02c, | |
1882 | .halt_check = BRANCH_HALT, | |
1883 | .clkr = { | |
1884 | .enable_reg = 0x8c02c, | |
1885 | .enable_mask = BIT(0), | |
1886 | .hw.init = &(struct clk_init_data){ | |
1887 | .name = "gcc_pcie_1_clkref_clk", | |
1888 | .ops = &clk_branch2_ops, | |
1889 | }, | |
1890 | }, | |
1891 | }; | |
1892 | ||
1893 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { | |
1894 | .halt_reg = 0x8d018, | |
1895 | .halt_check = BRANCH_HALT_VOTED, | |
1896 | .clkr = { | |
1897 | .enable_reg = 0x52004, | |
1898 | .enable_mask = BIT(27), | |
1899 | .hw.init = &(struct clk_init_data){ | |
1900 | .name = "gcc_pcie_1_mstr_axi_clk", | |
1901 | .ops = &clk_branch2_ops, | |
1902 | }, | |
1903 | }, | |
1904 | }; | |
1905 | ||
1906 | /* Clock ON depends on external parent 'PIPE' clock, so dont poll */ | |
1907 | static struct clk_branch gcc_pcie_1_pipe_clk = { | |
1908 | .halt_reg = 0x8d024, | |
1909 | .halt_check = BRANCH_HALT_DELAY, | |
1910 | .clkr = { | |
1911 | .enable_reg = 0x52004, | |
1912 | .enable_mask = BIT(30), | |
1913 | .hw.init = &(struct clk_init_data){ | |
1914 | .name = "gcc_pcie_1_pipe_clk", | |
1915 | .ops = &clk_branch2_ops, | |
1916 | }, | |
1917 | }, | |
1918 | }; | |
1919 | ||
1920 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { | |
1921 | .halt_reg = 0x8d014, | |
1922 | .halt_check = BRANCH_HALT_VOTED, | |
1923 | .hwcg_reg = 0x8d014, | |
1924 | .hwcg_bit = 1, | |
1925 | .clkr = { | |
1926 | .enable_reg = 0x52004, | |
1927 | .enable_mask = BIT(26), | |
1928 | .hw.init = &(struct clk_init_data){ | |
1929 | .name = "gcc_pcie_1_slv_axi_clk", | |
1930 | .ops = &clk_branch2_ops, | |
1931 | }, | |
1932 | }, | |
1933 | }; | |
1934 | ||
1935 | static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { | |
1936 | .halt_reg = 0x8d010, | |
1937 | .halt_check = BRANCH_HALT_VOTED, | |
1938 | .clkr = { | |
1939 | .enable_reg = 0x52004, | |
1940 | .enable_mask = BIT(25), | |
1941 | .hw.init = &(struct clk_init_data){ | |
1942 | .name = "gcc_pcie_1_slv_q2a_axi_clk", | |
1943 | .ops = &clk_branch2_ops, | |
1944 | }, | |
1945 | }, | |
1946 | }; | |
1947 | ||
1948 | static struct clk_branch gcc_pcie_phy_aux_clk = { | |
1949 | .halt_reg = 0x6f004, | |
1950 | .halt_check = BRANCH_HALT, | |
1951 | .clkr = { | |
1952 | .enable_reg = 0x6f004, | |
1953 | .enable_mask = BIT(0), | |
1954 | .hw.init = &(struct clk_init_data){ | |
1955 | .name = "gcc_pcie_phy_aux_clk", | |
1956 | .parent_hws = (const struct clk_hw *[]){ | |
1957 | &gcc_pcie_0_aux_clk_src.clkr.hw }, | |
1958 | .num_parents = 1, | |
1959 | .flags = CLK_SET_RATE_PARENT, | |
1960 | .ops = &clk_branch2_ops, | |
1961 | }, | |
1962 | }, | |
1963 | }; | |
1964 | ||
1965 | static struct clk_branch gcc_pdm2_clk = { | |
1966 | .halt_reg = 0x3300c, | |
1967 | .halt_check = BRANCH_HALT, | |
1968 | .clkr = { | |
1969 | .enable_reg = 0x3300c, | |
1970 | .enable_mask = BIT(0), | |
1971 | .hw.init = &(struct clk_init_data){ | |
1972 | .name = "gcc_pdm2_clk", | |
1973 | .parent_hws = (const struct clk_hw *[]){ | |
1974 | &gcc_pdm2_clk_src.clkr.hw }, | |
1975 | .num_parents = 1, | |
1976 | .flags = CLK_SET_RATE_PARENT, | |
1977 | .ops = &clk_branch2_ops, | |
1978 | }, | |
1979 | }, | |
1980 | }; | |
1981 | ||
1982 | static struct clk_branch gcc_pdm_ahb_clk = { | |
1983 | .halt_reg = 0x33004, | |
1984 | .halt_check = BRANCH_HALT, | |
1985 | .hwcg_reg = 0x33004, | |
1986 | .hwcg_bit = 1, | |
1987 | .clkr = { | |
1988 | .enable_reg = 0x33004, | |
1989 | .enable_mask = BIT(0), | |
1990 | .hw.init = &(struct clk_init_data){ | |
1991 | .name = "gcc_pdm_ahb_clk", | |
1992 | .ops = &clk_branch2_ops, | |
1993 | }, | |
1994 | }, | |
1995 | }; | |
1996 | ||
1997 | static struct clk_branch gcc_pdm_xo4_clk = { | |
1998 | .halt_reg = 0x33008, | |
1999 | .halt_check = BRANCH_HALT, | |
2000 | .clkr = { | |
2001 | .enable_reg = 0x33008, | |
2002 | .enable_mask = BIT(0), | |
2003 | .hw.init = &(struct clk_init_data){ | |
2004 | .name = "gcc_pdm_xo4_clk", | |
2005 | .ops = &clk_branch2_ops, | |
2006 | }, | |
2007 | }, | |
2008 | }; | |
2009 | ||
2010 | static struct clk_branch gcc_prng_ahb_clk = { | |
2011 | .halt_reg = 0x34004, | |
2012 | .halt_check = BRANCH_HALT_VOTED, | |
2013 | .clkr = { | |
2014 | .enable_reg = 0x52004, | |
2015 | .enable_mask = BIT(13), | |
2016 | .hw.init = &(struct clk_init_data){ | |
2017 | .name = "gcc_prng_ahb_clk", | |
2018 | .ops = &clk_branch2_ops, | |
2019 | }, | |
2020 | }, | |
2021 | }; | |
2022 | ||
2023 | static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { | |
2024 | .halt_reg = 0xb018, | |
2025 | .halt_check = BRANCH_HALT, | |
2026 | .hwcg_reg = 0xb018, | |
2027 | .hwcg_bit = 1, | |
2028 | .clkr = { | |
2029 | .enable_reg = 0xb018, | |
2030 | .enable_mask = BIT(0), | |
2031 | .hw.init = &(struct clk_init_data){ | |
2032 | .name = "gcc_qmip_camera_nrt_ahb_clk", | |
2033 | .ops = &clk_branch2_ops, | |
2034 | }, | |
2035 | }, | |
2036 | }; | |
2037 | ||
2038 | static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { | |
2039 | .halt_reg = 0xb01c, | |
2040 | .halt_check = BRANCH_HALT, | |
2041 | .hwcg_reg = 0xb01c, | |
2042 | .hwcg_bit = 1, | |
2043 | .clkr = { | |
2044 | .enable_reg = 0xb01c, | |
2045 | .enable_mask = BIT(0), | |
2046 | .hw.init = &(struct clk_init_data){ | |
2047 | .name = "gcc_qmip_camera_rt_ahb_clk", | |
2048 | .ops = &clk_branch2_ops, | |
2049 | }, | |
2050 | }, | |
2051 | }; | |
2052 | ||
2053 | static struct clk_branch gcc_qmip_disp_ahb_clk = { | |
2054 | .halt_reg = 0xb020, | |
2055 | .halt_check = BRANCH_HALT, | |
2056 | .hwcg_reg = 0xb020, | |
2057 | .hwcg_bit = 1, | |
2058 | .clkr = { | |
2059 | .enable_reg = 0xb020, | |
2060 | .enable_mask = BIT(0), | |
2061 | .hw.init = &(struct clk_init_data){ | |
2062 | .name = "gcc_qmip_disp_ahb_clk", | |
2063 | .ops = &clk_branch2_ops, | |
2064 | }, | |
2065 | }, | |
2066 | }; | |
2067 | ||
2068 | static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { | |
2069 | .halt_reg = 0xb010, | |
2070 | .halt_check = BRANCH_HALT, | |
2071 | .hwcg_reg = 0xb010, | |
2072 | .hwcg_bit = 1, | |
2073 | .clkr = { | |
2074 | .enable_reg = 0xb010, | |
2075 | .enable_mask = BIT(0), | |
2076 | .hw.init = &(struct clk_init_data){ | |
2077 | .name = "gcc_qmip_video_cvp_ahb_clk", | |
2078 | .ops = &clk_branch2_ops, | |
2079 | }, | |
2080 | }, | |
2081 | }; | |
2082 | ||
2083 | static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { | |
2084 | .halt_reg = 0xb014, | |
2085 | .halt_check = BRANCH_HALT, | |
2086 | .hwcg_reg = 0xb014, | |
2087 | .hwcg_bit = 1, | |
2088 | .clkr = { | |
2089 | .enable_reg = 0xb014, | |
2090 | .enable_mask = BIT(0), | |
2091 | .hw.init = &(struct clk_init_data){ | |
2092 | .name = "gcc_qmip_video_vcodec_ahb_clk", | |
2093 | .ops = &clk_branch2_ops, | |
2094 | }, | |
2095 | }, | |
2096 | }; | |
2097 | ||
2098 | static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { | |
2099 | .halt_reg = 0x4b000, | |
2100 | .halt_check = BRANCH_HALT, | |
2101 | .clkr = { | |
2102 | .enable_reg = 0x4b000, | |
2103 | .enable_mask = BIT(0), | |
2104 | .hw.init = &(struct clk_init_data){ | |
2105 | .name = "gcc_qspi_cnoc_periph_ahb_clk", | |
2106 | .ops = &clk_branch2_ops, | |
2107 | }, | |
2108 | }, | |
2109 | }; | |
2110 | ||
2111 | static struct clk_branch gcc_qspi_core_clk = { | |
2112 | .halt_reg = 0x4b004, | |
2113 | .halt_check = BRANCH_HALT, | |
2114 | .clkr = { | |
2115 | .enable_reg = 0x4b004, | |
2116 | .enable_mask = BIT(0), | |
2117 | .hw.init = &(struct clk_init_data){ | |
2118 | .name = "gcc_qspi_core_clk", | |
2119 | .parent_hws = (const struct clk_hw *[]){ | |
2120 | &gcc_qspi_core_clk_src.clkr.hw }, | |
2121 | .num_parents = 1, | |
2122 | .flags = CLK_SET_RATE_PARENT, | |
2123 | .ops = &clk_branch2_ops, | |
2124 | }, | |
2125 | }, | |
2126 | }; | |
2127 | ||
2128 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { | |
2129 | .halt_reg = 0x17144, | |
2130 | .halt_check = BRANCH_HALT_VOTED, | |
2131 | .clkr = { | |
2132 | .enable_reg = 0x5200c, | |
2133 | .enable_mask = BIT(10), | |
2134 | .hw.init = &(struct clk_init_data){ | |
2135 | .name = "gcc_qupv3_wrap0_s0_clk", | |
2136 | .parent_hws = (const struct clk_hw *[]){ | |
2137 | &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, | |
2138 | .num_parents = 1, | |
2139 | .flags = CLK_SET_RATE_PARENT, | |
2140 | .ops = &clk_branch2_ops, | |
2141 | }, | |
2142 | }, | |
2143 | }; | |
2144 | ||
2145 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { | |
2146 | .halt_reg = 0x17274, | |
2147 | .halt_check = BRANCH_HALT_VOTED, | |
2148 | .clkr = { | |
2149 | .enable_reg = 0x5200c, | |
2150 | .enable_mask = BIT(11), | |
2151 | .hw.init = &(struct clk_init_data){ | |
2152 | .name = "gcc_qupv3_wrap0_s1_clk", | |
2153 | .parent_hws = (const struct clk_hw *[]){ | |
2154 | &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, | |
2155 | .num_parents = 1, | |
2156 | .flags = CLK_SET_RATE_PARENT, | |
2157 | .ops = &clk_branch2_ops, | |
2158 | }, | |
2159 | }, | |
2160 | }; | |
2161 | ||
2162 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { | |
2163 | .halt_reg = 0x173a4, | |
2164 | .halt_check = BRANCH_HALT_VOTED, | |
2165 | .clkr = { | |
2166 | .enable_reg = 0x5200c, | |
2167 | .enable_mask = BIT(12), | |
2168 | .hw.init = &(struct clk_init_data){ | |
2169 | .name = "gcc_qupv3_wrap0_s2_clk", | |
2170 | .parent_hws = (const struct clk_hw *[]){ | |
2171 | &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, | |
2172 | .num_parents = 1, | |
2173 | .flags = CLK_SET_RATE_PARENT, | |
2174 | .ops = &clk_branch2_ops, | |
2175 | }, | |
2176 | }, | |
2177 | }; | |
2178 | ||
2179 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { | |
2180 | .halt_reg = 0x174d4, | |
2181 | .halt_check = BRANCH_HALT_VOTED, | |
2182 | .clkr = { | |
2183 | .enable_reg = 0x5200c, | |
2184 | .enable_mask = BIT(13), | |
2185 | .hw.init = &(struct clk_init_data){ | |
2186 | .name = "gcc_qupv3_wrap0_s3_clk", | |
2187 | .parent_hws = (const struct clk_hw *[]){ | |
2188 | &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, | |
2189 | .num_parents = 1, | |
2190 | .flags = CLK_SET_RATE_PARENT, | |
2191 | .ops = &clk_branch2_ops, | |
2192 | }, | |
2193 | }, | |
2194 | }; | |
2195 | ||
2196 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { | |
2197 | .halt_reg = 0x17604, | |
2198 | .halt_check = BRANCH_HALT_VOTED, | |
2199 | .clkr = { | |
2200 | .enable_reg = 0x5200c, | |
2201 | .enable_mask = BIT(14), | |
2202 | .hw.init = &(struct clk_init_data){ | |
2203 | .name = "gcc_qupv3_wrap0_s4_clk", | |
2204 | .parent_hws = (const struct clk_hw *[]){ | |
2205 | &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, | |
2206 | .num_parents = 1, | |
2207 | .flags = CLK_SET_RATE_PARENT, | |
2208 | .ops = &clk_branch2_ops, | |
2209 | }, | |
2210 | }, | |
2211 | }; | |
2212 | ||
2213 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { | |
2214 | .halt_reg = 0x17734, | |
2215 | .halt_check = BRANCH_HALT_VOTED, | |
2216 | .clkr = { | |
2217 | .enable_reg = 0x5200c, | |
2218 | .enable_mask = BIT(15), | |
2219 | .hw.init = &(struct clk_init_data){ | |
2220 | .name = "gcc_qupv3_wrap0_s5_clk", | |
2221 | .parent_hws = (const struct clk_hw *[]){ | |
2222 | &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, | |
2223 | .num_parents = 1, | |
2224 | .flags = CLK_SET_RATE_PARENT, | |
2225 | .ops = &clk_branch2_ops, | |
2226 | }, | |
2227 | }, | |
2228 | }; | |
2229 | ||
2230 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { | |
2231 | .halt_reg = 0x17864, | |
2232 | .halt_check = BRANCH_HALT_VOTED, | |
2233 | .clkr = { | |
2234 | .enable_reg = 0x5200c, | |
2235 | .enable_mask = BIT(16), | |
2236 | .hw.init = &(struct clk_init_data){ | |
2237 | .name = "gcc_qupv3_wrap0_s6_clk", | |
2238 | .parent_hws = (const struct clk_hw *[]){ | |
2239 | &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, | |
2240 | .num_parents = 1, | |
2241 | .flags = CLK_SET_RATE_PARENT, | |
2242 | .ops = &clk_branch2_ops, | |
2243 | }, | |
2244 | }, | |
2245 | }; | |
2246 | ||
2247 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { | |
2248 | .halt_reg = 0x17994, | |
2249 | .halt_check = BRANCH_HALT_VOTED, | |
2250 | .clkr = { | |
2251 | .enable_reg = 0x5200c, | |
2252 | .enable_mask = BIT(17), | |
2253 | .hw.init = &(struct clk_init_data){ | |
2254 | .name = "gcc_qupv3_wrap0_s7_clk", | |
2255 | .parent_hws = (const struct clk_hw *[]){ | |
2256 | &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, | |
2257 | .num_parents = 1, | |
2258 | .flags = CLK_SET_RATE_PARENT, | |
2259 | .ops = &clk_branch2_ops, | |
2260 | }, | |
2261 | }, | |
2262 | }; | |
2263 | ||
2264 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { | |
2265 | .halt_reg = 0x18144, | |
2266 | .halt_check = BRANCH_HALT_VOTED, | |
2267 | .clkr = { | |
2268 | .enable_reg = 0x5200c, | |
2269 | .enable_mask = BIT(22), | |
2270 | .hw.init = &(struct clk_init_data){ | |
2271 | .name = "gcc_qupv3_wrap1_s0_clk", | |
2272 | .parent_hws = (const struct clk_hw *[]){ | |
2273 | &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, | |
2274 | .num_parents = 1, | |
2275 | .flags = CLK_SET_RATE_PARENT, | |
2276 | .ops = &clk_branch2_ops, | |
2277 | }, | |
2278 | }, | |
2279 | }; | |
2280 | ||
2281 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { | |
2282 | .halt_reg = 0x18274, | |
2283 | .halt_check = BRANCH_HALT_VOTED, | |
2284 | .clkr = { | |
2285 | .enable_reg = 0x5200c, | |
2286 | .enable_mask = BIT(23), | |
2287 | .hw.init = &(struct clk_init_data){ | |
2288 | .name = "gcc_qupv3_wrap1_s1_clk", | |
2289 | .parent_hws = (const struct clk_hw *[]){ | |
2290 | &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, | |
2291 | .num_parents = 1, | |
2292 | .flags = CLK_SET_RATE_PARENT, | |
2293 | .ops = &clk_branch2_ops, | |
2294 | }, | |
2295 | }, | |
2296 | }; | |
2297 | ||
2298 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { | |
2299 | .halt_reg = 0x183a4, | |
2300 | .halt_check = BRANCH_HALT_VOTED, | |
2301 | .clkr = { | |
2302 | .enable_reg = 0x5200c, | |
2303 | .enable_mask = BIT(24), | |
2304 | .hw.init = &(struct clk_init_data){ | |
2305 | .name = "gcc_qupv3_wrap1_s2_clk", | |
2306 | .parent_hws = (const struct clk_hw *[]){ | |
2307 | &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, | |
2308 | .num_parents = 1, | |
2309 | .flags = CLK_SET_RATE_PARENT, | |
2310 | .ops = &clk_branch2_ops, | |
2311 | }, | |
2312 | }, | |
2313 | }; | |
2314 | ||
2315 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { | |
2316 | .halt_reg = 0x184d4, | |
2317 | .halt_check = BRANCH_HALT_VOTED, | |
2318 | .clkr = { | |
2319 | .enable_reg = 0x5200c, | |
2320 | .enable_mask = BIT(25), | |
2321 | .hw.init = &(struct clk_init_data){ | |
2322 | .name = "gcc_qupv3_wrap1_s3_clk", | |
2323 | .parent_hws = (const struct clk_hw *[]){ | |
2324 | &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, | |
2325 | .num_parents = 1, | |
2326 | .flags = CLK_SET_RATE_PARENT, | |
2327 | .ops = &clk_branch2_ops, | |
2328 | }, | |
2329 | }, | |
2330 | }; | |
2331 | ||
2332 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { | |
2333 | .halt_reg = 0x18604, | |
2334 | .halt_check = BRANCH_HALT_VOTED, | |
2335 | .clkr = { | |
2336 | .enable_reg = 0x5200c, | |
2337 | .enable_mask = BIT(26), | |
2338 | .hw.init = &(struct clk_init_data){ | |
2339 | .name = "gcc_qupv3_wrap1_s4_clk", | |
2340 | .parent_hws = (const struct clk_hw *[]){ | |
2341 | &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, | |
2342 | .num_parents = 1, | |
2343 | .flags = CLK_SET_RATE_PARENT, | |
2344 | .ops = &clk_branch2_ops, | |
2345 | }, | |
2346 | }, | |
2347 | }; | |
2348 | ||
2349 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { | |
2350 | .halt_reg = 0x18734, | |
2351 | .halt_check = BRANCH_HALT_VOTED, | |
2352 | .clkr = { | |
2353 | .enable_reg = 0x5200c, | |
2354 | .enable_mask = BIT(27), | |
2355 | .hw.init = &(struct clk_init_data){ | |
2356 | .name = "gcc_qupv3_wrap1_s5_clk", | |
2357 | .parent_hws = (const struct clk_hw *[]){ | |
2358 | &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, | |
2359 | .num_parents = 1, | |
2360 | .flags = CLK_SET_RATE_PARENT, | |
2361 | .ops = &clk_branch2_ops, | |
2362 | }, | |
2363 | }, | |
2364 | }; | |
2365 | ||
2366 | static struct clk_branch gcc_qupv3_wrap2_s0_clk = { | |
2367 | .halt_reg = 0x1e144, | |
2368 | .halt_check = BRANCH_HALT_VOTED, | |
2369 | .clkr = { | |
2370 | .enable_reg = 0x52014, | |
2371 | .enable_mask = BIT(4), | |
2372 | .hw.init = &(struct clk_init_data){ | |
2373 | .name = "gcc_qupv3_wrap2_s0_clk", | |
2374 | .parent_hws = (const struct clk_hw *[]){ | |
2375 | &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, | |
2376 | .num_parents = 1, | |
2377 | .flags = CLK_SET_RATE_PARENT, | |
2378 | .ops = &clk_branch2_ops, | |
2379 | }, | |
2380 | }, | |
2381 | }; | |
2382 | ||
2383 | static struct clk_branch gcc_qupv3_wrap2_s1_clk = { | |
2384 | .halt_reg = 0x1e274, | |
2385 | .halt_check = BRANCH_HALT_VOTED, | |
2386 | .clkr = { | |
2387 | .enable_reg = 0x52014, | |
2388 | .enable_mask = BIT(5), | |
2389 | .hw.init = &(struct clk_init_data){ | |
2390 | .name = "gcc_qupv3_wrap2_s1_clk", | |
2391 | .parent_hws = (const struct clk_hw *[]){ | |
2392 | &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, | |
2393 | .num_parents = 1, | |
2394 | .flags = CLK_SET_RATE_PARENT, | |
2395 | .ops = &clk_branch2_ops, | |
2396 | }, | |
2397 | }, | |
2398 | }; | |
2399 | ||
2400 | static struct clk_branch gcc_qupv3_wrap2_s2_clk = { | |
2401 | .halt_reg = 0x1e3a4, | |
2402 | .halt_check = BRANCH_HALT_VOTED, | |
2403 | .clkr = { | |
2404 | .enable_reg = 0x52014, | |
2405 | .enable_mask = BIT(6), | |
2406 | .hw.init = &(struct clk_init_data){ | |
2407 | .name = "gcc_qupv3_wrap2_s2_clk", | |
2408 | .parent_hws = (const struct clk_hw *[]){ | |
2409 | &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, | |
2410 | .num_parents = 1, | |
2411 | .flags = CLK_SET_RATE_PARENT, | |
2412 | .ops = &clk_branch2_ops, | |
2413 | }, | |
2414 | }, | |
2415 | }; | |
2416 | ||
2417 | static struct clk_branch gcc_qupv3_wrap2_s3_clk = { | |
2418 | .halt_reg = 0x1e4d4, | |
2419 | .halt_check = BRANCH_HALT_VOTED, | |
2420 | .clkr = { | |
2421 | .enable_reg = 0x52014, | |
2422 | .enable_mask = BIT(7), | |
2423 | .hw.init = &(struct clk_init_data){ | |
2424 | .name = "gcc_qupv3_wrap2_s3_clk", | |
2425 | .parent_hws = (const struct clk_hw *[]){ | |
2426 | &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, | |
2427 | .num_parents = 1, | |
2428 | .flags = CLK_SET_RATE_PARENT, | |
2429 | .ops = &clk_branch2_ops, | |
2430 | }, | |
2431 | }, | |
2432 | }; | |
2433 | ||
2434 | static struct clk_branch gcc_qupv3_wrap2_s4_clk = { | |
2435 | .halt_reg = 0x1e604, | |
2436 | .halt_check = BRANCH_HALT_VOTED, | |
2437 | .clkr = { | |
2438 | .enable_reg = 0x52014, | |
2439 | .enable_mask = BIT(8), | |
2440 | .hw.init = &(struct clk_init_data){ | |
2441 | .name = "gcc_qupv3_wrap2_s4_clk", | |
2442 | .parent_hws = (const struct clk_hw *[]){ | |
2443 | &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, | |
2444 | .num_parents = 1, | |
2445 | .flags = CLK_SET_RATE_PARENT, | |
2446 | .ops = &clk_branch2_ops, | |
2447 | }, | |
2448 | }, | |
2449 | }; | |
2450 | ||
2451 | static struct clk_branch gcc_qupv3_wrap2_s5_clk = { | |
2452 | .halt_reg = 0x1e734, | |
2453 | .halt_check = BRANCH_HALT_VOTED, | |
2454 | .clkr = { | |
2455 | .enable_reg = 0x52014, | |
2456 | .enable_mask = BIT(9), | |
2457 | .hw.init = &(struct clk_init_data){ | |
2458 | .name = "gcc_qupv3_wrap2_s5_clk", | |
2459 | .parent_hws = (const struct clk_hw *[]){ | |
2460 | &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, | |
2461 | .num_parents = 1, | |
2462 | .flags = CLK_SET_RATE_PARENT, | |
2463 | .ops = &clk_branch2_ops, | |
2464 | }, | |
2465 | }, | |
2466 | }; | |
2467 | ||
2468 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { | |
2469 | .halt_reg = 0x17004, | |
2470 | .halt_check = BRANCH_HALT_VOTED, | |
2471 | .clkr = { | |
2472 | .enable_reg = 0x5200c, | |
2473 | .enable_mask = BIT(6), | |
2474 | .hw.init = &(struct clk_init_data){ | |
2475 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", | |
2476 | .ops = &clk_branch2_ops, | |
2477 | }, | |
2478 | }, | |
2479 | }; | |
2480 | ||
2481 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { | |
2482 | .halt_reg = 0x17008, | |
2483 | .halt_check = BRANCH_HALT_VOTED, | |
2484 | .hwcg_reg = 0x17008, | |
2485 | .hwcg_bit = 1, | |
2486 | .clkr = { | |
2487 | .enable_reg = 0x5200c, | |
2488 | .enable_mask = BIT(7), | |
2489 | .hw.init = &(struct clk_init_data){ | |
2490 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", | |
2491 | .ops = &clk_branch2_ops, | |
2492 | }, | |
2493 | }, | |
2494 | }; | |
2495 | ||
2496 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { | |
2497 | .halt_reg = 0x18004, | |
2498 | .halt_check = BRANCH_HALT_VOTED, | |
2499 | .clkr = { | |
2500 | .enable_reg = 0x5200c, | |
2501 | .enable_mask = BIT(20), | |
2502 | .hw.init = &(struct clk_init_data){ | |
2503 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", | |
2504 | .ops = &clk_branch2_ops, | |
2505 | }, | |
2506 | }, | |
2507 | }; | |
2508 | ||
2509 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { | |
2510 | .halt_reg = 0x18008, | |
2511 | .halt_check = BRANCH_HALT_VOTED, | |
2512 | .hwcg_reg = 0x18008, | |
2513 | .hwcg_bit = 1, | |
2514 | .clkr = { | |
2515 | .enable_reg = 0x5200c, | |
2516 | .enable_mask = BIT(21), | |
2517 | .hw.init = &(struct clk_init_data){ | |
2518 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", | |
2519 | .ops = &clk_branch2_ops, | |
2520 | }, | |
2521 | }, | |
2522 | }; | |
2523 | ||
2524 | static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { | |
2525 | .halt_reg = 0x1e004, | |
2526 | .halt_check = BRANCH_HALT_VOTED, | |
2527 | .clkr = { | |
2528 | .enable_reg = 0x52014, | |
2529 | .enable_mask = BIT(2), | |
2530 | .hw.init = &(struct clk_init_data){ | |
2531 | .name = "gcc_qupv3_wrap_2_m_ahb_clk", | |
2532 | .ops = &clk_branch2_ops, | |
2533 | }, | |
2534 | }, | |
2535 | }; | |
2536 | ||
2537 | static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { | |
2538 | .halt_reg = 0x1e008, | |
2539 | .halt_check = BRANCH_HALT_VOTED, | |
2540 | .hwcg_reg = 0x1e008, | |
2541 | .hwcg_bit = 1, | |
2542 | .clkr = { | |
2543 | .enable_reg = 0x52014, | |
2544 | .enable_mask = BIT(1), | |
2545 | .hw.init = &(struct clk_init_data){ | |
2546 | .name = "gcc_qupv3_wrap_2_s_ahb_clk", | |
2547 | .ops = &clk_branch2_ops, | |
2548 | }, | |
2549 | }, | |
2550 | }; | |
2551 | ||
2552 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
2553 | .halt_reg = 0x14008, | |
2554 | .halt_check = BRANCH_HALT, | |
2555 | .clkr = { | |
2556 | .enable_reg = 0x14008, | |
2557 | .enable_mask = BIT(0), | |
2558 | .hw.init = &(struct clk_init_data){ | |
2559 | .name = "gcc_sdcc2_ahb_clk", | |
2560 | .ops = &clk_branch2_ops, | |
2561 | }, | |
2562 | }, | |
2563 | }; | |
2564 | ||
2565 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2566 | .halt_reg = 0x14004, | |
2567 | .halt_check = BRANCH_HALT, | |
2568 | .clkr = { | |
2569 | .enable_reg = 0x14004, | |
2570 | .enable_mask = BIT(0), | |
2571 | .hw.init = &(struct clk_init_data){ | |
2572 | .name = "gcc_sdcc2_apps_clk", | |
2573 | .parent_hws = (const struct clk_hw *[]){ | |
2574 | &gcc_sdcc2_apps_clk_src.clkr.hw }, | |
2575 | .num_parents = 1, | |
2576 | .flags = CLK_SET_RATE_PARENT, | |
2577 | .ops = &clk_branch2_ops, | |
2578 | }, | |
2579 | }, | |
2580 | }; | |
2581 | ||
2582 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2583 | .halt_reg = 0x16008, | |
2584 | .halt_check = BRANCH_HALT, | |
2585 | .clkr = { | |
2586 | .enable_reg = 0x16008, | |
2587 | .enable_mask = BIT(0), | |
2588 | .hw.init = &(struct clk_init_data){ | |
2589 | .name = "gcc_sdcc4_ahb_clk", | |
2590 | .ops = &clk_branch2_ops, | |
2591 | }, | |
2592 | }, | |
2593 | }; | |
2594 | ||
2595 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2596 | .halt_reg = 0x16004, | |
2597 | .halt_check = BRANCH_HALT, | |
2598 | .clkr = { | |
2599 | .enable_reg = 0x16004, | |
2600 | .enable_mask = BIT(0), | |
2601 | .hw.init = &(struct clk_init_data){ | |
2602 | .name = "gcc_sdcc4_apps_clk", | |
2603 | .parent_hws = (const struct clk_hw *[]){ | |
2604 | &gcc_sdcc4_apps_clk_src.clkr.hw }, | |
2605 | .num_parents = 1, | |
2606 | .flags = CLK_SET_RATE_PARENT, | |
2607 | .ops = &clk_branch2_ops, | |
2608 | }, | |
2609 | }, | |
2610 | }; | |
2611 | ||
2612 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { | |
2613 | .halt_reg = 0x4819c, | |
2614 | .halt_check = BRANCH_HALT_VOTED, | |
2615 | .clkr = { | |
2616 | .enable_reg = 0x52004, | |
2617 | .enable_mask = BIT(0), | |
2618 | .hw.init = &(struct clk_init_data){ | |
2619 | .name = "gcc_sys_noc_cpuss_ahb_clk", | |
2620 | .parent_hws = (const struct clk_hw *[]){ | |
2621 | &gcc_cpuss_ahb_clk_src.clkr.hw }, | |
2622 | .num_parents = 1, | |
2623 | /* required for cpuss */ | |
2624 | .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, | |
2625 | .ops = &clk_branch2_ops, | |
2626 | }, | |
2627 | }, | |
2628 | }; | |
2629 | ||
2630 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2631 | .halt_reg = 0x36004, | |
2632 | .halt_check = BRANCH_HALT, | |
2633 | .clkr = { | |
2634 | .enable_reg = 0x36004, | |
2635 | .enable_mask = BIT(0), | |
2636 | .hw.init = &(struct clk_init_data){ | |
2637 | .name = "gcc_tsif_ahb_clk", | |
2638 | .ops = &clk_branch2_ops, | |
2639 | }, | |
2640 | }, | |
2641 | }; | |
2642 | ||
2643 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { | |
2644 | .halt_reg = 0x3600c, | |
2645 | .halt_check = BRANCH_HALT, | |
2646 | .clkr = { | |
2647 | .enable_reg = 0x3600c, | |
2648 | .enable_mask = BIT(0), | |
2649 | .hw.init = &(struct clk_init_data){ | |
2650 | .name = "gcc_tsif_inactivity_timers_clk", | |
2651 | .ops = &clk_branch2_ops, | |
2652 | }, | |
2653 | }, | |
2654 | }; | |
2655 | ||
2656 | static struct clk_branch gcc_tsif_ref_clk = { | |
2657 | .halt_reg = 0x36008, | |
2658 | .halt_check = BRANCH_HALT, | |
2659 | .clkr = { | |
2660 | .enable_reg = 0x36008, | |
2661 | .enable_mask = BIT(0), | |
2662 | .hw.init = &(struct clk_init_data){ | |
2663 | .name = "gcc_tsif_ref_clk", | |
2664 | .parent_hws = (const struct clk_hw *[]){ | |
2665 | &gcc_tsif_ref_clk_src.clkr.hw }, | |
2666 | .num_parents = 1, | |
2667 | .flags = CLK_SET_RATE_PARENT, | |
2668 | .ops = &clk_branch2_ops, | |
2669 | }, | |
2670 | }, | |
2671 | }; | |
2672 | ||
2673 | static struct clk_branch gcc_ufs_card_ahb_clk = { | |
2674 | .halt_reg = 0x75014, | |
2675 | .halt_check = BRANCH_HALT, | |
2676 | .hwcg_reg = 0x75014, | |
2677 | .hwcg_bit = 1, | |
2678 | .clkr = { | |
2679 | .enable_reg = 0x75014, | |
2680 | .enable_mask = BIT(0), | |
2681 | .hw.init = &(struct clk_init_data){ | |
2682 | .name = "gcc_ufs_card_ahb_clk", | |
2683 | .ops = &clk_branch2_ops, | |
2684 | }, | |
2685 | }, | |
2686 | }; | |
2687 | ||
2688 | static struct clk_branch gcc_ufs_card_axi_clk = { | |
2689 | .halt_reg = 0x75010, | |
2690 | .halt_check = BRANCH_HALT, | |
2691 | .hwcg_reg = 0x75010, | |
2692 | .hwcg_bit = 1, | |
2693 | .clkr = { | |
2694 | .enable_reg = 0x75010, | |
2695 | .enable_mask = BIT(0), | |
2696 | .hw.init = &(struct clk_init_data){ | |
2697 | .name = "gcc_ufs_card_axi_clk", | |
2698 | .parent_hws = (const struct clk_hw *[]){ | |
2699 | &gcc_ufs_card_axi_clk_src.clkr.hw }, | |
2700 | .num_parents = 1, | |
2701 | .flags = CLK_SET_RATE_PARENT, | |
2702 | .ops = &clk_branch2_ops, | |
2703 | }, | |
2704 | }, | |
2705 | }; | |
2706 | ||
2707 | static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { | |
2708 | .halt_reg = 0x75010, | |
2709 | .halt_check = BRANCH_HALT, | |
2710 | .hwcg_reg = 0x75010, | |
2711 | .hwcg_bit = 1, | |
2712 | .clkr = { | |
2713 | .enable_reg = 0x75010, | |
2714 | .enable_mask = BIT(1), | |
2715 | .hw.init = &(struct clk_init_data){ | |
2716 | .name = "gcc_ufs_card_axi_hw_ctl_clk", | |
2717 | .parent_hws = (const struct clk_hw *[]){ | |
2718 | &gcc_ufs_card_axi_clk.clkr.hw }, | |
2719 | .num_parents = 1, | |
2720 | .flags = CLK_SET_RATE_PARENT, | |
2721 | .ops = &clk_branch_simple_ops, | |
2722 | }, | |
2723 | }, | |
2724 | }; | |
2725 | ||
2726 | static struct clk_branch gcc_ufs_card_clkref_clk = { | |
2727 | .halt_reg = 0x8c004, | |
2728 | .halt_check = BRANCH_HALT, | |
2729 | .clkr = { | |
2730 | .enable_reg = 0x8c004, | |
2731 | .enable_mask = BIT(0), | |
2732 | .hw.init = &(struct clk_init_data){ | |
2733 | .name = "gcc_ufs_card_clkref_clk", | |
2734 | .ops = &clk_branch2_ops, | |
2735 | }, | |
2736 | }, | |
2737 | }; | |
2738 | ||
2739 | static struct clk_branch gcc_ufs_card_ice_core_clk = { | |
2740 | .halt_reg = 0x7505c, | |
2741 | .halt_check = BRANCH_HALT, | |
2742 | .hwcg_reg = 0x7505c, | |
2743 | .hwcg_bit = 1, | |
2744 | .clkr = { | |
2745 | .enable_reg = 0x7505c, | |
2746 | .enable_mask = BIT(0), | |
2747 | .hw.init = &(struct clk_init_data){ | |
2748 | .name = "gcc_ufs_card_ice_core_clk", | |
2749 | .parent_hws = (const struct clk_hw *[]){ | |
2750 | &gcc_ufs_card_ice_core_clk_src.clkr.hw }, | |
2751 | .num_parents = 1, | |
2752 | .flags = CLK_SET_RATE_PARENT, | |
2753 | .ops = &clk_branch2_ops, | |
2754 | }, | |
2755 | }, | |
2756 | }; | |
2757 | ||
2758 | static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { | |
2759 | .halt_reg = 0x7505c, | |
2760 | .halt_check = BRANCH_HALT, | |
2761 | .hwcg_reg = 0x7505c, | |
2762 | .hwcg_bit = 1, | |
2763 | .clkr = { | |
2764 | .enable_reg = 0x7505c, | |
2765 | .enable_mask = BIT(1), | |
2766 | .hw.init = &(struct clk_init_data){ | |
2767 | .name = "gcc_ufs_card_ice_core_hw_ctl_clk", | |
2768 | .parent_hws = (const struct clk_hw *[]){ | |
2769 | &gcc_ufs_card_ice_core_clk.clkr.hw }, | |
2770 | .num_parents = 1, | |
2771 | .flags = CLK_SET_RATE_PARENT, | |
2772 | .ops = &clk_branch_simple_ops, | |
2773 | }, | |
2774 | }, | |
2775 | }; | |
2776 | ||
2777 | static struct clk_branch gcc_ufs_card_phy_aux_clk = { | |
2778 | .halt_reg = 0x75090, | |
2779 | .halt_check = BRANCH_HALT, | |
2780 | .hwcg_reg = 0x75090, | |
2781 | .hwcg_bit = 1, | |
2782 | .clkr = { | |
2783 | .enable_reg = 0x75090, | |
2784 | .enable_mask = BIT(0), | |
2785 | .hw.init = &(struct clk_init_data){ | |
2786 | .name = "gcc_ufs_card_phy_aux_clk", | |
2787 | .parent_hws = (const struct clk_hw *[]){ | |
2788 | &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, | |
2789 | .num_parents = 1, | |
2790 | .flags = CLK_SET_RATE_PARENT, | |
2791 | .ops = &clk_branch2_ops, | |
2792 | }, | |
2793 | }, | |
2794 | }; | |
2795 | ||
2796 | static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { | |
2797 | .halt_reg = 0x75090, | |
2798 | .halt_check = BRANCH_HALT, | |
2799 | .hwcg_reg = 0x75090, | |
2800 | .hwcg_bit = 1, | |
2801 | .clkr = { | |
2802 | .enable_reg = 0x75090, | |
2803 | .enable_mask = BIT(1), | |
2804 | .hw.init = &(struct clk_init_data){ | |
2805 | .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", | |
2806 | .parent_hws = (const struct clk_hw *[]){ | |
2807 | &gcc_ufs_card_phy_aux_clk.clkr.hw }, | |
2808 | .num_parents = 1, | |
2809 | .flags = CLK_SET_RATE_PARENT, | |
2810 | .ops = &clk_branch_simple_ops, | |
2811 | }, | |
2812 | }, | |
2813 | }; | |
2814 | ||
2815 | static struct clk_branch gcc_ufs_card_unipro_core_clk = { | |
2816 | .halt_reg = 0x75058, | |
2817 | .halt_check = BRANCH_HALT, | |
2818 | .hwcg_reg = 0x75058, | |
2819 | .hwcg_bit = 1, | |
2820 | .clkr = { | |
2821 | .enable_reg = 0x75058, | |
2822 | .enable_mask = BIT(0), | |
2823 | .hw.init = &(struct clk_init_data){ | |
2824 | .name = "gcc_ufs_card_unipro_core_clk", | |
2825 | .parent_hws = (const struct clk_hw *[]){ | |
2826 | &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, | |
2827 | .num_parents = 1, | |
2828 | .flags = CLK_SET_RATE_PARENT, | |
2829 | .ops = &clk_branch2_ops, | |
2830 | }, | |
2831 | }, | |
2832 | }; | |
2833 | ||
2834 | static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { | |
2835 | .halt_reg = 0x75058, | |
2836 | .halt_check = BRANCH_HALT, | |
2837 | .hwcg_reg = 0x75058, | |
2838 | .hwcg_bit = 1, | |
2839 | .clkr = { | |
2840 | .enable_reg = 0x75058, | |
2841 | .enable_mask = BIT(1), | |
2842 | .hw.init = &(struct clk_init_data){ | |
2843 | .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", | |
2844 | .parent_hws = (const struct clk_hw *[]){ | |
2845 | &gcc_ufs_card_unipro_core_clk.clkr.hw }, | |
2846 | .num_parents = 1, | |
2847 | .flags = CLK_SET_RATE_PARENT, | |
2848 | .ops = &clk_branch_simple_ops, | |
2849 | }, | |
2850 | }, | |
2851 | }; | |
2852 | ||
2853 | static struct clk_branch gcc_ufs_mem_clkref_clk = { | |
2854 | .halt_reg = 0x8c000, | |
2855 | .halt_check = BRANCH_HALT, | |
2856 | .clkr = { | |
2857 | .enable_reg = 0x8c000, | |
2858 | .enable_mask = BIT(0), | |
2859 | .hw.init = &(struct clk_init_data){ | |
2860 | .name = "gcc_ufs_mem_clkref_clk", | |
2861 | .ops = &clk_branch2_ops, | |
2862 | }, | |
2863 | }, | |
2864 | }; | |
2865 | ||
2866 | static struct clk_branch gcc_ufs_phy_ahb_clk = { | |
2867 | .halt_reg = 0x77014, | |
2868 | .halt_check = BRANCH_HALT, | |
2869 | .hwcg_reg = 0x77014, | |
2870 | .hwcg_bit = 1, | |
2871 | .clkr = { | |
2872 | .enable_reg = 0x77014, | |
2873 | .enable_mask = BIT(0), | |
2874 | .hw.init = &(struct clk_init_data){ | |
2875 | .name = "gcc_ufs_phy_ahb_clk", | |
2876 | .ops = &clk_branch2_ops, | |
2877 | }, | |
2878 | }, | |
2879 | }; | |
2880 | ||
2881 | static struct clk_branch gcc_ufs_phy_axi_clk = { | |
2882 | .halt_reg = 0x77010, | |
2883 | .halt_check = BRANCH_HALT, | |
2884 | .hwcg_reg = 0x77010, | |
2885 | .hwcg_bit = 1, | |
2886 | .clkr = { | |
2887 | .enable_reg = 0x77010, | |
2888 | .enable_mask = BIT(0), | |
2889 | .hw.init = &(struct clk_init_data){ | |
2890 | .name = "gcc_ufs_phy_axi_clk", | |
2891 | .parent_hws = (const struct clk_hw *[]){ | |
2892 | &gcc_ufs_phy_axi_clk_src.clkr.hw }, | |
2893 | .num_parents = 1, | |
2894 | .flags = CLK_SET_RATE_PARENT, | |
2895 | .ops = &clk_branch2_ops, | |
2896 | }, | |
2897 | }, | |
2898 | }; | |
2899 | ||
2900 | static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { | |
2901 | .halt_reg = 0x77010, | |
2902 | .halt_check = BRANCH_HALT, | |
2903 | .hwcg_reg = 0x77010, | |
2904 | .hwcg_bit = 1, | |
2905 | .clkr = { | |
2906 | .enable_reg = 0x77010, | |
2907 | .enable_mask = BIT(1), | |
2908 | .hw.init = &(struct clk_init_data){ | |
2909 | .name = "gcc_ufs_phy_axi_hw_ctl_clk", | |
2910 | .parent_hws = (const struct clk_hw *[]){ | |
2911 | &gcc_ufs_phy_axi_clk.clkr.hw }, | |
2912 | .num_parents = 1, | |
2913 | .flags = CLK_SET_RATE_PARENT, | |
2914 | .ops = &clk_branch_simple_ops, | |
2915 | }, | |
2916 | }, | |
2917 | }; | |
2918 | ||
2919 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { | |
2920 | .halt_reg = 0x7705c, | |
2921 | .halt_check = BRANCH_HALT, | |
2922 | .hwcg_reg = 0x7705c, | |
2923 | .hwcg_bit = 1, | |
2924 | .clkr = { | |
2925 | .enable_reg = 0x7705c, | |
2926 | .enable_mask = BIT(0), | |
2927 | .hw.init = &(struct clk_init_data){ | |
2928 | .name = "gcc_ufs_phy_ice_core_clk", | |
2929 | .parent_hws = (const struct clk_hw *[]){ | |
2930 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, | |
2931 | .num_parents = 1, | |
2932 | .flags = CLK_SET_RATE_PARENT, | |
2933 | .ops = &clk_branch2_ops, | |
2934 | }, | |
2935 | }, | |
2936 | }; | |
2937 | ||
2938 | static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { | |
2939 | .halt_reg = 0x7705c, | |
2940 | .halt_check = BRANCH_HALT, | |
2941 | .hwcg_reg = 0x7705c, | |
2942 | .hwcg_bit = 1, | |
2943 | .clkr = { | |
2944 | .enable_reg = 0x7705c, | |
2945 | .enable_mask = BIT(1), | |
2946 | .hw.init = &(struct clk_init_data){ | |
2947 | .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", | |
2948 | .parent_hws = (const struct clk_hw *[]){ | |
2949 | &gcc_ufs_phy_ice_core_clk.clkr.hw }, | |
2950 | .num_parents = 1, | |
2951 | .flags = CLK_SET_RATE_PARENT, | |
2952 | .ops = &clk_branch_simple_ops, | |
2953 | }, | |
2954 | }, | |
2955 | }; | |
2956 | ||
2957 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { | |
2958 | .halt_reg = 0x77090, | |
2959 | .halt_check = BRANCH_HALT, | |
2960 | .hwcg_reg = 0x77090, | |
2961 | .hwcg_bit = 1, | |
2962 | .clkr = { | |
2963 | .enable_reg = 0x77090, | |
2964 | .enable_mask = BIT(0), | |
2965 | .hw.init = &(struct clk_init_data){ | |
2966 | .name = "gcc_ufs_phy_phy_aux_clk", | |
2967 | .parent_hws = (const struct clk_hw *[]){ | |
2968 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, | |
2969 | .num_parents = 1, | |
2970 | .flags = CLK_SET_RATE_PARENT, | |
2971 | .ops = &clk_branch2_ops, | |
2972 | }, | |
2973 | }, | |
2974 | }; | |
2975 | ||
2976 | static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { | |
2977 | .halt_reg = 0x77090, | |
2978 | .halt_check = BRANCH_HALT, | |
2979 | .hwcg_reg = 0x77090, | |
2980 | .hwcg_bit = 1, | |
2981 | .clkr = { | |
2982 | .enable_reg = 0x77090, | |
2983 | .enable_mask = BIT(1), | |
2984 | .hw.init = &(struct clk_init_data){ | |
2985 | .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", | |
2986 | .parent_hws = (const struct clk_hw *[]){ | |
2987 | &gcc_ufs_phy_phy_aux_clk.clkr.hw }, | |
2988 | .num_parents = 1, | |
2989 | .flags = CLK_SET_RATE_PARENT, | |
2990 | .ops = &clk_branch_simple_ops, | |
2991 | }, | |
2992 | }, | |
2993 | }; | |
2994 | ||
2995 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { | |
2996 | .halt_reg = 0x77058, | |
2997 | .halt_check = BRANCH_HALT, | |
2998 | .hwcg_reg = 0x77058, | |
2999 | .hwcg_bit = 1, | |
3000 | .clkr = { | |
3001 | .enable_reg = 0x77058, | |
3002 | .enable_mask = BIT(0), | |
3003 | .hw.init = &(struct clk_init_data){ | |
3004 | .name = "gcc_ufs_phy_unipro_core_clk", | |
3005 | .parent_hws = (const struct clk_hw *[]){ | |
3006 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, | |
3007 | .num_parents = 1, | |
3008 | .flags = CLK_SET_RATE_PARENT, | |
3009 | .ops = &clk_branch2_ops, | |
3010 | }, | |
3011 | }, | |
3012 | }; | |
3013 | ||
3014 | static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { | |
3015 | .halt_reg = 0x77058, | |
3016 | .halt_check = BRANCH_HALT, | |
3017 | .hwcg_reg = 0x77058, | |
3018 | .hwcg_bit = 1, | |
3019 | .clkr = { | |
3020 | .enable_reg = 0x77058, | |
3021 | .enable_mask = BIT(1), | |
3022 | .hw.init = &(struct clk_init_data){ | |
3023 | .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", | |
3024 | .parent_hws = (const struct clk_hw *[]){ | |
3025 | &gcc_ufs_phy_unipro_core_clk.clkr.hw }, | |
3026 | .num_parents = 1, | |
3027 | .flags = CLK_SET_RATE_PARENT, | |
3028 | .ops = &clk_branch_simple_ops, | |
3029 | }, | |
3030 | }, | |
3031 | }; | |
3032 | ||
3033 | static struct clk_branch gcc_usb30_prim_master_clk = { | |
3034 | .halt_reg = 0xf010, | |
3035 | .halt_check = BRANCH_HALT, | |
3036 | .clkr = { | |
3037 | .enable_reg = 0xf010, | |
3038 | .enable_mask = BIT(0), | |
3039 | .hw.init = &(struct clk_init_data){ | |
3040 | .name = "gcc_usb30_prim_master_clk", | |
3041 | .parent_hws = (const struct clk_hw *[]){ | |
3042 | &gcc_usb30_prim_master_clk_src.clkr.hw }, | |
3043 | .num_parents = 1, | |
3044 | .flags = CLK_SET_RATE_PARENT, | |
3045 | .ops = &clk_branch2_ops, | |
3046 | }, | |
3047 | }, | |
3048 | }; | |
3049 | ||
3050 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { | |
3051 | .halt_reg = 0xf018, | |
3052 | .halt_check = BRANCH_HALT, | |
3053 | .clkr = { | |
3054 | .enable_reg = 0xf018, | |
3055 | .enable_mask = BIT(0), | |
3056 | .hw.init = &(struct clk_init_data){ | |
3057 | .name = "gcc_usb30_prim_mock_utmi_clk", | |
3058 | .parent_hws = (const struct clk_hw *[]){ | |
3059 | &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, | |
3060 | .num_parents = 1, | |
3061 | .flags = CLK_SET_RATE_PARENT, | |
3062 | .ops = &clk_branch2_ops, | |
3063 | }, | |
3064 | }, | |
3065 | }; | |
3066 | ||
3067 | static struct clk_branch gcc_usb30_prim_sleep_clk = { | |
3068 | .halt_reg = 0xf014, | |
3069 | .halt_check = BRANCH_HALT, | |
3070 | .clkr = { | |
3071 | .enable_reg = 0xf014, | |
3072 | .enable_mask = BIT(0), | |
3073 | .hw.init = &(struct clk_init_data){ | |
3074 | .name = "gcc_usb30_prim_sleep_clk", | |
3075 | .ops = &clk_branch2_ops, | |
3076 | }, | |
3077 | }, | |
3078 | }; | |
3079 | ||
3080 | static struct clk_branch gcc_usb30_sec_master_clk = { | |
3081 | .halt_reg = 0x10010, | |
3082 | .halt_check = BRANCH_HALT, | |
3083 | .clkr = { | |
3084 | .enable_reg = 0x10010, | |
3085 | .enable_mask = BIT(0), | |
3086 | .hw.init = &(struct clk_init_data){ | |
3087 | .name = "gcc_usb30_sec_master_clk", | |
3088 | .parent_hws = (const struct clk_hw *[]){ | |
3089 | &gcc_usb30_sec_master_clk_src.clkr.hw }, | |
3090 | .num_parents = 1, | |
3091 | .flags = CLK_SET_RATE_PARENT, | |
3092 | .ops = &clk_branch2_ops, | |
3093 | }, | |
3094 | }, | |
3095 | }; | |
3096 | ||
3097 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { | |
3098 | .halt_reg = 0x10018, | |
3099 | .halt_check = BRANCH_HALT, | |
3100 | .clkr = { | |
3101 | .enable_reg = 0x10018, | |
3102 | .enable_mask = BIT(0), | |
3103 | .hw.init = &(struct clk_init_data){ | |
3104 | .name = "gcc_usb30_sec_mock_utmi_clk", | |
3105 | .parent_hws = (const struct clk_hw *[]){ | |
3106 | &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, | |
3107 | .num_parents = 1, | |
3108 | .flags = CLK_SET_RATE_PARENT, | |
3109 | .ops = &clk_branch2_ops, | |
3110 | }, | |
3111 | }, | |
3112 | }; | |
3113 | ||
3114 | static struct clk_branch gcc_usb30_sec_sleep_clk = { | |
3115 | .halt_reg = 0x10014, | |
3116 | .halt_check = BRANCH_HALT, | |
3117 | .clkr = { | |
3118 | .enable_reg = 0x10014, | |
3119 | .enable_mask = BIT(0), | |
3120 | .hw.init = &(struct clk_init_data){ | |
3121 | .name = "gcc_usb30_sec_sleep_clk", | |
3122 | .ops = &clk_branch2_ops, | |
3123 | }, | |
3124 | }, | |
3125 | }; | |
3126 | ||
3127 | static struct clk_branch gcc_usb3_prim_clkref_clk = { | |
3128 | .halt_reg = 0x8c008, | |
3129 | .halt_check = BRANCH_HALT, | |
3130 | .clkr = { | |
3131 | .enable_reg = 0x8c008, | |
3132 | .enable_mask = BIT(0), | |
3133 | .hw.init = &(struct clk_init_data){ | |
3134 | .name = "gcc_usb3_prim_clkref_clk", | |
3135 | .ops = &clk_branch2_ops, | |
3136 | }, | |
3137 | }, | |
3138 | }; | |
3139 | ||
3140 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { | |
3141 | .halt_reg = 0xf050, | |
3142 | .halt_check = BRANCH_HALT, | |
3143 | .clkr = { | |
3144 | .enable_reg = 0xf050, | |
3145 | .enable_mask = BIT(0), | |
3146 | .hw.init = &(struct clk_init_data){ | |
3147 | .name = "gcc_usb3_prim_phy_aux_clk", | |
3148 | .parent_hws = (const struct clk_hw *[]){ | |
3149 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, | |
3150 | .num_parents = 1, | |
3151 | .flags = CLK_SET_RATE_PARENT, | |
3152 | .ops = &clk_branch2_ops, | |
3153 | }, | |
3154 | }, | |
3155 | }; | |
3156 | ||
3157 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { | |
3158 | .halt_reg = 0xf054, | |
3159 | .halt_check = BRANCH_HALT, | |
3160 | .clkr = { | |
3161 | .enable_reg = 0xf054, | |
3162 | .enable_mask = BIT(0), | |
3163 | .hw.init = &(struct clk_init_data){ | |
3164 | .name = "gcc_usb3_prim_phy_com_aux_clk", | |
3165 | .parent_hws = (const struct clk_hw *[]){ | |
3166 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, | |
3167 | .num_parents = 1, | |
3168 | .flags = CLK_SET_RATE_PARENT, | |
3169 | .ops = &clk_branch2_ops, | |
3170 | }, | |
3171 | }, | |
3172 | }; | |
3173 | ||
3174 | static struct clk_branch gcc_usb3_sec_clkref_clk = { | |
3175 | .halt_reg = 0x8c028, | |
3176 | .halt_check = BRANCH_HALT, | |
3177 | .clkr = { | |
3178 | .enable_reg = 0x8c028, | |
3179 | .enable_mask = BIT(0), | |
3180 | .hw.init = &(struct clk_init_data){ | |
3181 | .name = "gcc_usb3_sec_clkref_clk", | |
3182 | .ops = &clk_branch2_ops, | |
3183 | }, | |
3184 | }, | |
3185 | }; | |
3186 | ||
3187 | static struct clk_branch gcc_usb3_sec_phy_aux_clk = { | |
3188 | .halt_reg = 0x10050, | |
3189 | .halt_check = BRANCH_HALT, | |
3190 | .clkr = { | |
3191 | .enable_reg = 0x10050, | |
3192 | .enable_mask = BIT(0), | |
3193 | .hw.init = &(struct clk_init_data){ | |
3194 | .name = "gcc_usb3_sec_phy_aux_clk", | |
3195 | .parent_hws = (const struct clk_hw *[]){ | |
3196 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, | |
3197 | .num_parents = 1, | |
3198 | .flags = CLK_SET_RATE_PARENT, | |
3199 | .ops = &clk_branch2_ops, | |
3200 | }, | |
3201 | }, | |
3202 | }; | |
3203 | ||
3204 | static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { | |
3205 | .halt_reg = 0x10054, | |
3206 | .halt_check = BRANCH_HALT, | |
3207 | .clkr = { | |
3208 | .enable_reg = 0x10054, | |
3209 | .enable_mask = BIT(0), | |
3210 | .hw.init = &(struct clk_init_data){ | |
3211 | .name = "gcc_usb3_sec_phy_com_aux_clk", | |
3212 | .parent_hws = (const struct clk_hw *[]){ | |
3213 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, | |
3214 | .num_parents = 1, | |
3215 | .flags = CLK_SET_RATE_PARENT, | |
3216 | .ops = &clk_branch2_ops, | |
3217 | }, | |
3218 | }, | |
3219 | }; | |
3220 | ||
3221 | /* | |
3222 | * Clock ON depends on external parent 'config noc', so cant poll | |
3223 | * delay and also mark as crtitical for video boot | |
3224 | */ | |
3225 | static struct clk_branch gcc_video_ahb_clk = { | |
3226 | .halt_reg = 0xb004, | |
3227 | .halt_check = BRANCH_HALT_DELAY, | |
3228 | .hwcg_reg = 0xb004, | |
3229 | .hwcg_bit = 1, | |
3230 | .clkr = { | |
3231 | .enable_reg = 0xb004, | |
3232 | .enable_mask = BIT(0), | |
3233 | .hw.init = &(struct clk_init_data){ | |
3234 | .name = "gcc_video_ahb_clk", | |
3235 | .flags = CLK_IS_CRITICAL, | |
3236 | .ops = &clk_branch2_ops, | |
3237 | }, | |
3238 | }, | |
3239 | }; | |
3240 | ||
3241 | static struct clk_branch gcc_video_axi0_clk = { | |
3242 | .halt_reg = 0xb024, | |
3243 | .halt_check = BRANCH_HALT, | |
3244 | .clkr = { | |
3245 | .enable_reg = 0xb024, | |
3246 | .enable_mask = BIT(0), | |
3247 | .hw.init = &(struct clk_init_data){ | |
3248 | .name = "gcc_video_axi0_clk", | |
3249 | .ops = &clk_branch2_ops, | |
3250 | }, | |
3251 | }, | |
3252 | }; | |
3253 | ||
3254 | static struct clk_branch gcc_video_axi1_clk = { | |
3255 | .halt_reg = 0xb028, | |
3256 | .halt_check = BRANCH_HALT, | |
3257 | .clkr = { | |
3258 | .enable_reg = 0xb028, | |
3259 | .enable_mask = BIT(0), | |
3260 | .hw.init = &(struct clk_init_data){ | |
3261 | .name = "gcc_video_axi1_clk", | |
3262 | .ops = &clk_branch2_ops, | |
3263 | }, | |
3264 | }, | |
3265 | }; | |
3266 | ||
3267 | static struct clk_branch gcc_video_axic_clk = { | |
3268 | .halt_reg = 0xb02c, | |
3269 | .halt_check = BRANCH_HALT, | |
3270 | .clkr = { | |
3271 | .enable_reg = 0xb02c, | |
3272 | .enable_mask = BIT(0), | |
3273 | .hw.init = &(struct clk_init_data){ | |
3274 | .name = "gcc_video_axic_clk", | |
3275 | .ops = &clk_branch2_ops, | |
3276 | }, | |
3277 | }, | |
3278 | }; | |
3279 | ||
3280 | /* XO critical input to video, so no need to poll */ | |
3281 | static struct clk_branch gcc_video_xo_clk = { | |
3282 | .halt_reg = 0xb040, | |
3283 | .halt_check = BRANCH_HALT_DELAY, | |
3284 | .clkr = { | |
3285 | .enable_reg = 0xb040, | |
3286 | .enable_mask = BIT(0), | |
3287 | .hw.init = &(struct clk_init_data){ | |
3288 | .name = "gcc_video_xo_clk", | |
3289 | .flags = CLK_IS_CRITICAL, | |
3290 | .ops = &clk_branch2_ops, | |
3291 | }, | |
3292 | }, | |
3293 | }; | |
3294 | ||
3295 | static struct clk_regmap *gcc_sm8150_clocks[] = { | |
3296 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, | |
3297 | [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, | |
3298 | [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = | |
3299 | &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, | |
3300 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, | |
3301 | [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = | |
3302 | &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, | |
3303 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, | |
3304 | [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, | |
3305 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3306 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, | |
3307 | [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, | |
3308 | [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, | |
3309 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, | |
3310 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
3311 | [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, | |
3312 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, | |
3313 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, | |
3314 | [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, | |
3315 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, | |
3316 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, | |
3317 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, | |
3318 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, | |
3319 | [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, | |
3320 | [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, | |
3321 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, | |
3322 | [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, | |
3323 | [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, | |
3324 | [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, | |
3325 | [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, | |
3326 | [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, | |
3327 | [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, | |
3328 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3329 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
3330 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3331 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
3332 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3333 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
3334 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, | |
3335 | [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, | |
3336 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
3337 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
3338 | [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, | |
3339 | [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, | |
3340 | [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, | |
3341 | [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, | |
3342 | [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, | |
3343 | [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, | |
3344 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, | |
3345 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, | |
3346 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
3347 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, | |
3348 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
3349 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
3350 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
3351 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, | |
3352 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, | |
3353 | [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, | |
3354 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, | |
3355 | [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, | |
3356 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, | |
3357 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, | |
3358 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, | |
3359 | [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, | |
3360 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, | |
3361 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, | |
3362 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3363 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
3364 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3365 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
3366 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
3367 | [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, | |
3368 | [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, | |
3369 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, | |
3370 | [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, | |
3371 | [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, | |
3372 | [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, | |
3373 | [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, | |
3374 | [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, | |
3375 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
3376 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
3377 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
3378 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
3379 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
3380 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
3381 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
3382 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
3383 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
3384 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
3385 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
3386 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
3387 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, | |
3388 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, | |
3389 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, | |
3390 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, | |
3391 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
3392 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
3393 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
3394 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
3395 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
3396 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
3397 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
3398 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
3399 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
3400 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
3401 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
3402 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
3403 | [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, | |
3404 | [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, | |
3405 | [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, | |
3406 | [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, | |
3407 | [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, | |
3408 | [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, | |
3409 | [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, | |
3410 | [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, | |
3411 | [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, | |
3412 | [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, | |
3413 | [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, | |
3414 | [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, | |
3415 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
3416 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
3417 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
3418 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
3419 | [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, | |
3420 | [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, | |
3421 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3422 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3423 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
3424 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3425 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
3426 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, | |
3427 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, | |
3428 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
3429 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, | |
3430 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
3431 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, | |
3432 | [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, | |
3433 | [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, | |
3434 | [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, | |
3435 | [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, | |
3436 | [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, | |
3437 | [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, | |
3438 | [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, | |
3439 | [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = | |
3440 | &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, | |
3441 | [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, | |
3442 | [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, | |
3443 | [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = | |
3444 | &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, | |
3445 | [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, | |
3446 | [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = | |
3447 | &gcc_ufs_card_unipro_core_clk_src.clkr, | |
3448 | [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = | |
3449 | &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, | |
3450 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, | |
3451 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
3452 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
3453 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
3454 | [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, | |
3455 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
3456 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
3457 | [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = | |
3458 | &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, | |
3459 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
3460 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
3461 | [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, | |
3462 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
3463 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = | |
3464 | &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
3465 | [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = | |
3466 | &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, | |
3467 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
3468 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
3469 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
3470 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = | |
3471 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
3472 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
3473 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, | |
3474 | [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, | |
3475 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, | |
3476 | [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = | |
3477 | &gcc_usb30_sec_mock_utmi_clk_src.clkr, | |
3478 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, | |
3479 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, | |
3480 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, | |
3481 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
3482 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
3483 | [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, | |
3484 | [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, | |
3485 | [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, | |
3486 | [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, | |
3487 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, | |
3488 | [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, | |
3489 | [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, | |
3490 | [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, | |
3491 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, | |
3492 | [GPLL0] = &gpll0.clkr, | |
3493 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, | |
3494 | [GPLL7] = &gpll7.clkr, | |
3495 | [GPLL9] = &gpll9.clkr, | |
3496 | }; | |
3497 | ||
3498 | static const struct qcom_reset_map gcc_sm8150_resets[] = { | |
3499 | [GCC_EMAC_BCR] = { 0x6000 }, | |
3500 | [GCC_GPU_BCR] = { 0x71000 }, | |
3501 | [GCC_MMSS_BCR] = { 0xb000 }, | |
3502 | [GCC_NPU_BCR] = { 0x4d000 }, | |
3503 | [GCC_PCIE_0_BCR] = { 0x6b000 }, | |
3504 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, | |
3505 | [GCC_PCIE_1_BCR] = { 0x8d000 }, | |
3506 | [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, | |
3507 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, | |
3508 | [GCC_PDM_BCR] = { 0x33000 }, | |
3509 | [GCC_PRNG_BCR] = { 0x34000 }, | |
3510 | [GCC_QSPI_BCR] = { 0x24008 }, | |
3511 | [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, | |
3512 | [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, | |
3513 | [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, | |
3514 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, | |
3515 | [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, | |
3516 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, | |
3517 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, | |
3518 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, | |
3519 | [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, | |
3520 | [GCC_SDCC2_BCR] = { 0x14000 }, | |
3521 | [GCC_SDCC4_BCR] = { 0x16000 }, | |
3522 | [GCC_TSIF_BCR] = { 0x36000 }, | |
3523 | [GCC_UFS_CARD_BCR] = { 0x75000 }, | |
3524 | [GCC_UFS_PHY_BCR] = { 0x77000 }, | |
3525 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, | |
3526 | [GCC_USB30_SEC_BCR] = { 0x10000 }, | |
3527 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, | |
3528 | }; | |
3529 | ||
3530 | static const struct regmap_config gcc_sm8150_regmap_config = { | |
3531 | .reg_bits = 32, | |
3532 | .reg_stride = 4, | |
3533 | .val_bits = 32, | |
3534 | .max_register = 0x9c040, | |
3535 | .fast_io = true, | |
3536 | }; | |
3537 | ||
3538 | static const struct qcom_cc_desc gcc_sm8150_desc = { | |
3539 | .config = &gcc_sm8150_regmap_config, | |
3540 | .clks = gcc_sm8150_clocks, | |
3541 | .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), | |
3542 | .resets = gcc_sm8150_resets, | |
3543 | .num_resets = ARRAY_SIZE(gcc_sm8150_resets), | |
3544 | }; | |
3545 | ||
3546 | static const struct of_device_id gcc_sm8150_match_table[] = { | |
3547 | { .compatible = "qcom,gcc-sm8150" }, | |
3548 | { } | |
3549 | }; | |
3550 | MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); | |
3551 | ||
3552 | static int gcc_sm8150_probe(struct platform_device *pdev) | |
3553 | { | |
3554 | struct regmap *regmap; | |
3555 | ||
3556 | regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); | |
3557 | if (IS_ERR(regmap)) | |
3558 | return PTR_ERR(regmap); | |
3559 | ||
3560 | /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ | |
3561 | regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); | |
3562 | regmap_update_bits(regmap, 0x71028, 0x3, 0x3); | |
3563 | ||
3564 | return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); | |
3565 | } | |
3566 | ||
3567 | static struct platform_driver gcc_sm8150_driver = { | |
3568 | .probe = gcc_sm8150_probe, | |
3569 | .driver = { | |
3570 | .name = "gcc-sm8150", | |
3571 | .of_match_table = gcc_sm8150_match_table, | |
3572 | }, | |
3573 | }; | |
3574 | ||
3575 | static int __init gcc_sm8150_init(void) | |
3576 | { | |
3577 | return platform_driver_register(&gcc_sm8150_driver); | |
3578 | } | |
3579 | subsys_initcall(gcc_sm8150_init); | |
3580 | ||
3581 | static void __exit gcc_sm8150_exit(void) | |
3582 | { | |
3583 | platform_driver_unregister(&gcc_sm8150_driver); | |
3584 | } | |
3585 | module_exit(gcc_sm8150_exit); | |
3586 | ||
3587 | MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); | |
3588 | MODULE_LICENSE("GPL v2"); |