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a808d58d DT |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> | |
5 | * Copyright (c) 2023, David Wronek <davidwronek@gmail.com> | |
6 | */ | |
7 | ||
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_device.h> | |
14 | #include <linux/regmap.h> | |
15 | ||
16 | #include <dt-bindings/clock/qcom,sm7150-gcc.h> | |
17 | ||
18 | #include "clk-alpha-pll.h" | |
19 | #include "clk-branch.h" | |
20 | #include "clk-rcg.h" | |
21 | #include "clk-regmap.h" | |
22 | #include "common.h" | |
23 | #include "gdsc.h" | |
24 | #include "reset.h" | |
25 | ||
26 | enum { | |
27 | DT_BI_TCXO, | |
28 | DT_BI_TCXO_AO, | |
29 | DT_SLEEP_CLK | |
30 | }; | |
31 | ||
32 | enum { | |
33 | P_BI_TCXO, | |
34 | P_GPLL0_OUT_EVEN, | |
35 | P_GPLL0_OUT_MAIN, | |
36 | P_GPLL6_OUT_MAIN, | |
37 | P_GPLL7_OUT_MAIN, | |
38 | P_SLEEP_CLK, | |
39 | }; | |
40 | ||
41 | static struct clk_alpha_pll gpll0 = { | |
42 | .offset = 0x0, | |
43 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
44 | .clkr = { | |
45 | .enable_reg = 0x52000, | |
46 | .enable_mask = BIT(0), | |
47 | .hw.init = &(struct clk_init_data){ | |
48 | .name = "gpll0", | |
49 | .parent_data = &(const struct clk_parent_data){ | |
50 | .index = DT_BI_TCXO, | |
51 | }, | |
52 | .num_parents = 1, | |
53 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
54 | }, | |
55 | }, | |
56 | }; | |
57 | ||
58 | static const struct clk_div_table post_div_table_fabia_even[] = { | |
59 | { 0x0, 1 }, | |
60 | { 0x1, 2 }, | |
61 | { 0x3, 4 }, | |
62 | { 0x7, 8 }, | |
63 | { } | |
64 | }; | |
65 | ||
66 | static struct clk_alpha_pll_postdiv gpll0_out_even = { | |
67 | .offset = 0x0, | |
68 | .post_div_shift = 8, | |
69 | .post_div_table = post_div_table_fabia_even, | |
70 | .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), | |
71 | .width = 4, | |
72 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
73 | .clkr.hw.init = &(struct clk_init_data){ | |
74 | .name = "gpll0_out_even", | |
75 | .parent_hws = (const struct clk_hw*[]){ | |
76 | &gpll0.clkr.hw, | |
77 | }, | |
78 | .num_parents = 1, | |
79 | .ops = &clk_alpha_pll_postdiv_fabia_ops, | |
80 | }, | |
81 | }; | |
82 | ||
83 | static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { | |
84 | .mult = 1, | |
85 | .div = 2, | |
86 | .hw.init = &(struct clk_init_data){ | |
87 | .name = "gcc_pll0_main_div_cdiv", | |
88 | .parent_hws = (const struct clk_hw*[]){ | |
89 | &gpll0.clkr.hw, | |
90 | }, | |
91 | .num_parents = 1, | |
92 | .ops = &clk_fixed_factor_ops, | |
93 | }, | |
94 | }; | |
95 | ||
96 | static struct clk_alpha_pll gpll6 = { | |
97 | .offset = 0x13000, | |
98 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
99 | .clkr = { | |
100 | .enable_reg = 0x52000, | |
101 | .enable_mask = BIT(6), | |
102 | .hw.init = &(struct clk_init_data){ | |
103 | .name = "gpll6", | |
104 | .parent_data = &(const struct clk_parent_data){ | |
105 | .index = DT_BI_TCXO, | |
106 | }, | |
107 | .num_parents = 1, | |
108 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
109 | }, | |
110 | }, | |
111 | }; | |
112 | ||
113 | static struct clk_alpha_pll gpll7 = { | |
114 | .offset = 0x27000, | |
115 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
116 | .clkr = { | |
117 | .enable_reg = 0x52000, | |
118 | .enable_mask = BIT(7), | |
119 | .hw.init = &(struct clk_init_data){ | |
120 | .name = "gpll7", | |
121 | .parent_data = &(const struct clk_parent_data){ | |
122 | .index = DT_BI_TCXO, | |
123 | }, | |
124 | .num_parents = 1, | |
125 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
126 | }, | |
127 | }, | |
128 | }; | |
129 | ||
130 | static const struct parent_map gcc_parent_map_0[] = { | |
131 | { P_BI_TCXO, 0 }, | |
132 | { P_GPLL0_OUT_MAIN, 1 }, | |
133 | { P_GPLL0_OUT_EVEN, 6 }, | |
134 | }; | |
135 | ||
136 | static const struct clk_parent_data gcc_parent_data_0[] = { | |
137 | { .index = DT_BI_TCXO }, | |
138 | { .hw = &gpll0.clkr.hw }, | |
139 | { .hw = &gpll0_out_even.clkr.hw }, | |
140 | }; | |
141 | static const struct clk_parent_data gcc_parent_data_0_ao[] = { | |
142 | { .index = DT_BI_TCXO_AO }, | |
143 | { .hw = &gpll0.clkr.hw }, | |
144 | { .hw = &gpll0_out_even.clkr.hw }, | |
145 | }; | |
146 | ||
147 | static const struct parent_map gcc_parent_map_1[] = { | |
148 | { P_BI_TCXO, 0 }, | |
149 | { P_GPLL0_OUT_MAIN, 1 }, | |
150 | { P_SLEEP_CLK, 5 }, | |
151 | { P_GPLL0_OUT_EVEN, 6 }, | |
152 | }; | |
153 | ||
154 | static const struct clk_parent_data gcc_parent_data_1[] = { | |
155 | { .index = DT_BI_TCXO }, | |
156 | { .hw = &gpll0.clkr.hw }, | |
157 | { .index = DT_SLEEP_CLK }, | |
158 | { .hw = &gpll0_out_even.clkr.hw }, | |
159 | }; | |
160 | ||
161 | static const struct parent_map gcc_parent_map_2[] = { | |
162 | { P_BI_TCXO, 0 }, | |
163 | { P_GPLL0_OUT_MAIN, 1 }, | |
164 | }; | |
165 | ||
166 | static const struct clk_parent_data gcc_parent_data_2[] = { | |
167 | { .index = DT_BI_TCXO }, | |
168 | { .hw = &gpll0.clkr.hw }, | |
169 | }; | |
170 | ||
171 | static const struct clk_parent_data gcc_parent_data_2_ao[] = { | |
172 | { .index = DT_BI_TCXO_AO }, | |
173 | { .hw = &gpll0.clkr.hw }, | |
174 | }; | |
175 | ||
176 | static const struct parent_map gcc_parent_map_3[] = { | |
177 | { P_BI_TCXO, 0 }, | |
178 | { P_SLEEP_CLK, 5 }, | |
179 | }; | |
180 | ||
181 | static const struct clk_parent_data gcc_parent_data_3[] = { | |
182 | { .index = DT_BI_TCXO }, | |
183 | { .index = DT_SLEEP_CLK }, | |
184 | }; | |
185 | ||
186 | static const struct parent_map gcc_parent_map_4[] = { | |
187 | { P_BI_TCXO, 0 }, | |
188 | }; | |
189 | ||
190 | static const struct clk_parent_data gcc_parent_data_4[] = { | |
191 | { .index = DT_BI_TCXO }, | |
192 | }; | |
193 | ||
194 | static const struct parent_map gcc_parent_map_5[] = { | |
195 | { P_BI_TCXO, 0 }, | |
196 | { P_GPLL0_OUT_MAIN, 1 }, | |
197 | { P_GPLL6_OUT_MAIN, 2 }, | |
198 | { P_GPLL0_OUT_EVEN, 6 }, | |
199 | }; | |
200 | ||
201 | static const struct clk_parent_data gcc_parent_data_5[] = { | |
202 | { .index = DT_BI_TCXO }, | |
203 | { .hw = &gpll0.clkr.hw }, | |
204 | { .hw = &gpll6.clkr.hw }, | |
205 | { .hw = &gpll0_out_even.clkr.hw }, | |
206 | }; | |
207 | ||
208 | static const struct parent_map gcc_parent_map_6[] = { | |
209 | { P_BI_TCXO, 0 }, | |
210 | { P_GPLL0_OUT_MAIN, 1 }, | |
211 | { P_GPLL7_OUT_MAIN, 3 }, | |
212 | { P_GPLL0_OUT_EVEN, 6 }, | |
213 | }; | |
214 | ||
215 | static const struct clk_parent_data gcc_parent_data_6[] = { | |
216 | { .index = DT_BI_TCXO }, | |
217 | { .hw = &gpll0.clkr.hw }, | |
218 | { .hw = &gpll7.clkr.hw }, | |
219 | { .hw = &gpll0_out_even.clkr.hw }, | |
220 | }; | |
221 | ||
222 | static const struct parent_map gcc_parent_map_7[] = { | |
223 | { P_BI_TCXO, 0 }, | |
224 | { P_GPLL0_OUT_MAIN, 1 }, | |
225 | { P_GPLL0_OUT_EVEN, 6 }, | |
226 | }; | |
227 | ||
228 | static const struct clk_parent_data gcc_parent_data_7[] = { | |
229 | { .index = DT_BI_TCXO }, | |
230 | { .hw = &gpll0.clkr.hw }, | |
231 | { .hw = &gpll0_out_even.clkr.hw }, | |
232 | }; | |
233 | ||
234 | static const struct parent_map gcc_parent_map_8[] = { | |
235 | { P_BI_TCXO, 0 }, | |
236 | { P_GPLL0_OUT_MAIN, 1 }, | |
237 | }; | |
238 | ||
239 | static const struct clk_parent_data gcc_parent_data_8[] = { | |
240 | { .index = DT_BI_TCXO }, | |
241 | { .hw = &gpll0.clkr.hw }, | |
242 | }; | |
243 | ||
244 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { | |
245 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
246 | { } | |
247 | }; | |
248 | ||
249 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { | |
250 | .cmd_rcgr = 0x48014, | |
251 | .mnd_width = 0, | |
252 | .hid_width = 5, | |
253 | .parent_map = gcc_parent_map_0, | |
254 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, | |
255 | .clkr.hw.init = &(struct clk_init_data){ | |
256 | .name = "gcc_cpuss_ahb_clk_src", | |
257 | .parent_data = gcc_parent_data_0_ao, | |
258 | .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), | |
259 | .flags = CLK_SET_RATE_PARENT, | |
260 | .ops = &clk_rcg2_ops, | |
261 | }, | |
262 | }; | |
263 | ||
264 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { | |
265 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
266 | { } | |
267 | }; | |
268 | ||
269 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { | |
270 | .cmd_rcgr = 0x4815c, | |
271 | .mnd_width = 0, | |
272 | .hid_width = 5, | |
273 | .parent_map = gcc_parent_map_2, | |
274 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
275 | .clkr.hw.init = &(struct clk_init_data){ | |
276 | .name = "gcc_cpuss_rbcpr_clk_src", | |
277 | .parent_data = gcc_parent_data_2_ao, | |
278 | .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), | |
279 | .ops = &clk_rcg2_ops, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { | |
284 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
285 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
286 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
287 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
288 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
289 | { } | |
290 | }; | |
291 | ||
292 | static struct clk_rcg2 gcc_gp1_clk_src = { | |
293 | .cmd_rcgr = 0x64004, | |
294 | .mnd_width = 8, | |
295 | .hid_width = 5, | |
296 | .parent_map = gcc_parent_map_1, | |
297 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
298 | .clkr.hw.init = &(struct clk_init_data){ | |
299 | .name = "gcc_gp1_clk_src", | |
300 | .parent_data = gcc_parent_data_1, | |
301 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
302 | .ops = &clk_rcg2_ops, | |
303 | }, | |
304 | }; | |
305 | ||
306 | static struct clk_rcg2 gcc_gp2_clk_src = { | |
307 | .cmd_rcgr = 0x65004, | |
308 | .mnd_width = 8, | |
309 | .hid_width = 5, | |
310 | .parent_map = gcc_parent_map_1, | |
311 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
312 | .clkr.hw.init = &(struct clk_init_data){ | |
313 | .name = "gcc_gp2_clk_src", | |
314 | .parent_data = gcc_parent_data_1, | |
315 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
316 | .ops = &clk_rcg2_ops, | |
317 | }, | |
318 | }; | |
319 | ||
320 | static struct clk_rcg2 gcc_gp3_clk_src = { | |
321 | .cmd_rcgr = 0x66004, | |
322 | .mnd_width = 8, | |
323 | .hid_width = 5, | |
324 | .parent_map = gcc_parent_map_1, | |
325 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
326 | .clkr.hw.init = &(struct clk_init_data){ | |
327 | .name = "gcc_gp3_clk_src", | |
328 | .parent_data = gcc_parent_data_1, | |
329 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
330 | .ops = &clk_rcg2_ops, | |
331 | }, | |
332 | }; | |
333 | ||
334 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { | |
335 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
336 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
337 | { } | |
338 | }; | |
339 | ||
340 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { | |
341 | .cmd_rcgr = 0x6b028, | |
342 | .mnd_width = 16, | |
343 | .hid_width = 5, | |
344 | .parent_map = gcc_parent_map_3, | |
345 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
346 | .clkr.hw.init = &(struct clk_init_data){ | |
347 | .name = "gcc_pcie_0_aux_clk_src", | |
348 | .parent_data = gcc_parent_data_3, | |
349 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
350 | .ops = &clk_rcg2_ops, | |
351 | }, | |
352 | }; | |
353 | ||
354 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { | |
355 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
356 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
357 | { } | |
358 | }; | |
359 | ||
360 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { | |
361 | .cmd_rcgr = 0x6f014, | |
362 | .mnd_width = 0, | |
363 | .hid_width = 5, | |
364 | .parent_map = gcc_parent_map_0, | |
365 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, | |
366 | .clkr.hw.init = &(struct clk_init_data){ | |
367 | .name = "gcc_pcie_phy_refgen_clk_src", | |
368 | .parent_data = gcc_parent_data_0, | |
369 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
370 | .ops = &clk_rcg2_ops, | |
371 | }, | |
372 | }; | |
373 | ||
374 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { | |
375 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
376 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), | |
377 | { } | |
378 | }; | |
379 | ||
380 | static struct clk_rcg2 gcc_pdm2_clk_src = { | |
381 | .cmd_rcgr = 0x33010, | |
382 | .mnd_width = 0, | |
383 | .hid_width = 5, | |
384 | .parent_map = gcc_parent_map_0, | |
385 | .freq_tbl = ftbl_gcc_pdm2_clk_src, | |
386 | .clkr.hw.init = &(struct clk_init_data){ | |
387 | .name = "gcc_pdm2_clk_src", | |
388 | .parent_data = gcc_parent_data_0, | |
389 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
390 | .ops = &clk_rcg2_ops, | |
391 | }, | |
392 | }; | |
393 | ||
394 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { | |
395 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), | |
396 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), | |
397 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
398 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), | |
399 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), | |
400 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), | |
401 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), | |
402 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), | |
403 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), | |
404 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), | |
405 | F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), | |
406 | F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), | |
407 | F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), | |
408 | F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), | |
409 | F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), | |
410 | { } | |
411 | }; | |
412 | ||
413 | static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { | |
414 | .name = "gcc_qupv3_wrap0_s0_clk_src", | |
415 | .parent_data = gcc_parent_data_0, | |
416 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
417 | .ops = &clk_rcg2_ops, | |
418 | }; | |
419 | ||
420 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { | |
421 | .cmd_rcgr = 0x17034, | |
422 | .mnd_width = 16, | |
423 | .hid_width = 5, | |
424 | .parent_map = gcc_parent_map_0, | |
425 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
426 | .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, | |
427 | }; | |
428 | ||
429 | static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { | |
430 | .name = "gcc_qupv3_wrap0_s1_clk_src", | |
431 | .parent_data = gcc_parent_data_0, | |
432 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
433 | .ops = &clk_rcg2_ops, | |
434 | }; | |
435 | ||
436 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { | |
437 | .cmd_rcgr = 0x17164, | |
438 | .mnd_width = 16, | |
439 | .hid_width = 5, | |
440 | .parent_map = gcc_parent_map_0, | |
441 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
442 | .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, | |
443 | }; | |
444 | ||
445 | static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { | |
446 | .name = "gcc_qupv3_wrap0_s2_clk_src", | |
447 | .parent_data = gcc_parent_data_0, | |
448 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
449 | .ops = &clk_rcg2_ops, | |
450 | }; | |
451 | ||
452 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { | |
453 | .cmd_rcgr = 0x17294, | |
454 | .mnd_width = 16, | |
455 | .hid_width = 5, | |
456 | .parent_map = gcc_parent_map_0, | |
457 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
458 | .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, | |
459 | }; | |
460 | ||
461 | static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { | |
462 | .name = "gcc_qupv3_wrap0_s3_clk_src", | |
463 | .parent_data = gcc_parent_data_0, | |
464 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
465 | .ops = &clk_rcg2_ops, | |
466 | }; | |
467 | ||
468 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { | |
469 | .cmd_rcgr = 0x173c4, | |
470 | .mnd_width = 16, | |
471 | .hid_width = 5, | |
472 | .parent_map = gcc_parent_map_0, | |
473 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
474 | .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, | |
475 | }; | |
476 | ||
477 | static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { | |
478 | .name = "gcc_qupv3_wrap0_s4_clk_src", | |
479 | .parent_data = gcc_parent_data_0, | |
480 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
481 | .ops = &clk_rcg2_ops, | |
482 | }; | |
483 | ||
484 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { | |
485 | .cmd_rcgr = 0x174f4, | |
486 | .mnd_width = 16, | |
487 | .hid_width = 5, | |
488 | .parent_map = gcc_parent_map_0, | |
489 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
490 | .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, | |
491 | }; | |
492 | ||
493 | static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { | |
494 | .name = "gcc_qupv3_wrap0_s5_clk_src", | |
495 | .parent_data = gcc_parent_data_0, | |
496 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
497 | .ops = &clk_rcg2_ops, | |
498 | }; | |
499 | ||
500 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { | |
501 | .cmd_rcgr = 0x17624, | |
502 | .mnd_width = 16, | |
503 | .hid_width = 5, | |
504 | .parent_map = gcc_parent_map_0, | |
505 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
506 | .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, | |
507 | }; | |
508 | ||
509 | static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { | |
510 | .name = "gcc_qupv3_wrap0_s6_clk_src", | |
511 | .parent_data = gcc_parent_data_0, | |
512 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
513 | .flags = CLK_SET_RATE_PARENT, | |
514 | .ops = &clk_rcg2_ops, | |
515 | }; | |
516 | ||
517 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { | |
518 | .cmd_rcgr = 0x17754, | |
519 | .mnd_width = 16, | |
520 | .hid_width = 5, | |
521 | .parent_map = gcc_parent_map_0, | |
522 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
523 | .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, | |
524 | }; | |
525 | ||
526 | static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { | |
527 | .name = "gcc_qupv3_wrap0_s7_clk_src", | |
528 | .parent_data = gcc_parent_data_0, | |
529 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
530 | .flags = CLK_SET_RATE_PARENT, | |
531 | .ops = &clk_rcg2_ops, | |
532 | }; | |
533 | ||
534 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { | |
535 | .cmd_rcgr = 0x17884, | |
536 | .mnd_width = 16, | |
537 | .hid_width = 5, | |
538 | .parent_map = gcc_parent_map_0, | |
539 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
540 | .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, | |
541 | }; | |
542 | ||
543 | static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { | |
544 | .name = "gcc_qupv3_wrap1_s0_clk_src", | |
545 | .parent_data = gcc_parent_data_0, | |
546 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
547 | .ops = &clk_rcg2_ops, | |
548 | }; | |
549 | ||
550 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { | |
551 | .cmd_rcgr = 0x18018, | |
552 | .mnd_width = 16, | |
553 | .hid_width = 5, | |
554 | .parent_map = gcc_parent_map_0, | |
555 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
556 | .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, | |
557 | }; | |
558 | ||
559 | static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { | |
560 | .name = "gcc_qupv3_wrap1_s1_clk_src", | |
561 | .parent_data = gcc_parent_data_0, | |
562 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
563 | .ops = &clk_rcg2_ops, | |
564 | }; | |
565 | ||
566 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { | |
567 | .cmd_rcgr = 0x18148, | |
568 | .mnd_width = 16, | |
569 | .hid_width = 5, | |
570 | .parent_map = gcc_parent_map_0, | |
571 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
572 | .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, | |
573 | }; | |
574 | ||
575 | static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { | |
576 | .name = "gcc_qupv3_wrap1_s2_clk_src", | |
577 | .parent_data = gcc_parent_data_0, | |
578 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
579 | .ops = &clk_rcg2_ops, | |
580 | }; | |
581 | ||
582 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { | |
583 | .cmd_rcgr = 0x18278, | |
584 | .mnd_width = 16, | |
585 | .hid_width = 5, | |
586 | .parent_map = gcc_parent_map_0, | |
587 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
588 | .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, | |
589 | }; | |
590 | ||
591 | static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { | |
592 | .name = "gcc_qupv3_wrap1_s3_clk_src", | |
593 | .parent_data = gcc_parent_data_0, | |
594 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
595 | .ops = &clk_rcg2_ops, | |
596 | }; | |
597 | ||
598 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { | |
599 | .cmd_rcgr = 0x183a8, | |
600 | .mnd_width = 16, | |
601 | .hid_width = 5, | |
602 | .parent_map = gcc_parent_map_0, | |
603 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
604 | .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, | |
605 | }; | |
606 | ||
607 | static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { | |
608 | .name = "gcc_qupv3_wrap1_s4_clk_src", | |
609 | .parent_data = gcc_parent_data_0, | |
610 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
611 | .ops = &clk_rcg2_ops, | |
612 | }; | |
613 | ||
614 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { | |
615 | .cmd_rcgr = 0x184d8, | |
616 | .mnd_width = 16, | |
617 | .hid_width = 5, | |
618 | .parent_map = gcc_parent_map_0, | |
619 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
620 | .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, | |
621 | }; | |
622 | ||
623 | static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { | |
624 | .name = "gcc_qupv3_wrap1_s5_clk_src", | |
625 | .parent_data = gcc_parent_data_0, | |
626 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
627 | .ops = &clk_rcg2_ops, | |
628 | }; | |
629 | ||
630 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { | |
631 | .cmd_rcgr = 0x18608, | |
632 | .mnd_width = 16, | |
633 | .hid_width = 5, | |
634 | .parent_map = gcc_parent_map_0, | |
635 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
636 | .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, | |
637 | }; | |
638 | ||
639 | static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { | |
640 | .name = "gcc_qupv3_wrap1_s6_clk_src", | |
641 | .parent_data = gcc_parent_data_0, | |
642 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
643 | .ops = &clk_rcg2_ops, | |
644 | }; | |
645 | ||
646 | static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { | |
647 | .cmd_rcgr = 0x18738, | |
648 | .mnd_width = 16, | |
649 | .hid_width = 5, | |
650 | .parent_map = gcc_parent_map_0, | |
651 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
652 | .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, | |
653 | }; | |
654 | ||
655 | static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { | |
656 | .name = "gcc_qupv3_wrap1_s7_clk_src", | |
657 | .parent_data = gcc_parent_data_0, | |
658 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
659 | .ops = &clk_rcg2_ops, | |
660 | }; | |
661 | ||
662 | static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { | |
663 | .cmd_rcgr = 0x18868, | |
664 | .mnd_width = 16, | |
665 | .hid_width = 5, | |
666 | .parent_map = gcc_parent_map_0, | |
667 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
668 | .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, | |
669 | }; | |
670 | ||
671 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { | |
672 | F(144000, P_BI_TCXO, 16, 3, 25), | |
673 | F(400000, P_BI_TCXO, 12, 1, 4), | |
674 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
675 | F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), | |
676 | F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), | |
677 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
678 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), | |
679 | F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), | |
680 | F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), | |
681 | { } | |
682 | }; | |
683 | ||
684 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { | |
685 | .cmd_rcgr = 0x12028, | |
686 | .mnd_width = 8, | |
687 | .hid_width = 5, | |
688 | .parent_map = gcc_parent_map_5, | |
689 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, | |
690 | .clkr.hw.init = &(struct clk_init_data){ | |
691 | .name = "gcc_sdcc1_apps_clk_src", | |
692 | .parent_data = gcc_parent_data_5, | |
693 | .num_parents = ARRAY_SIZE(gcc_parent_data_5), | |
694 | .ops = &clk_rcg2_floor_ops, | |
695 | }, | |
696 | }; | |
697 | ||
698 | static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { | |
699 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
700 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
701 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
702 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
703 | { } | |
704 | }; | |
705 | ||
706 | static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { | |
707 | .cmd_rcgr = 0x12010, | |
708 | .mnd_width = 0, | |
709 | .hid_width = 5, | |
710 | .parent_map = gcc_parent_map_0, | |
711 | .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, | |
712 | .clkr.hw.init = &(struct clk_init_data){ | |
713 | .name = "gcc_sdcc1_ice_core_clk_src", | |
714 | .parent_data = gcc_parent_data_0, | |
715 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
716 | .ops = &clk_rcg2_ops, | |
717 | }, | |
718 | }; | |
719 | ||
720 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { | |
721 | F(400000, P_BI_TCXO, 12, 1, 4), | |
722 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
723 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
724 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
725 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
726 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
727 | F(208000000, P_GPLL7_OUT_MAIN, 4, 0, 0), | |
728 | { } | |
729 | }; | |
730 | ||
731 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | |
732 | .cmd_rcgr = 0x1400c, | |
733 | .mnd_width = 8, | |
734 | .hid_width = 5, | |
735 | .parent_map = gcc_parent_map_6, | |
736 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, | |
737 | .clkr.hw.init = &(struct clk_init_data){ | |
738 | .name = "gcc_sdcc2_apps_clk_src", | |
739 | .parent_data = gcc_parent_data_6, | |
740 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), | |
741 | .ops = &clk_rcg2_floor_ops, | |
742 | }, | |
743 | }; | |
744 | ||
745 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { | |
746 | F(400000, P_BI_TCXO, 12, 1, 4), | |
747 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
748 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
749 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
750 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), | |
751 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
752 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
753 | { } | |
754 | }; | |
755 | ||
756 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { | |
757 | .cmd_rcgr = 0x1600c, | |
758 | .mnd_width = 8, | |
759 | .hid_width = 5, | |
760 | .parent_map = gcc_parent_map_0, | |
761 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, | |
762 | .clkr.hw.init = &(struct clk_init_data){ | |
763 | .name = "gcc_sdcc4_apps_clk_src", | |
764 | .parent_data = gcc_parent_data_0, | |
765 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
766 | .ops = &clk_rcg2_floor_ops, | |
767 | }, | |
768 | }; | |
769 | ||
770 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { | |
771 | F(105495, P_BI_TCXO, 2, 1, 91), | |
772 | { } | |
773 | }; | |
774 | ||
775 | static struct clk_rcg2 gcc_tsif_ref_clk_src = { | |
776 | .cmd_rcgr = 0x36010, | |
777 | .mnd_width = 8, | |
778 | .hid_width = 5, | |
779 | .parent_map = gcc_parent_map_7, | |
780 | .freq_tbl = ftbl_gcc_tsif_ref_clk_src, | |
781 | .clkr.hw.init = &(struct clk_init_data){ | |
782 | .name = "gcc_tsif_ref_clk_src", | |
783 | .parent_data = gcc_parent_data_7, | |
784 | .num_parents = ARRAY_SIZE(gcc_parent_data_7), | |
785 | .ops = &clk_rcg2_ops, | |
786 | }, | |
787 | }; | |
788 | ||
789 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { | |
790 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
791 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
792 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
793 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
794 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
795 | { } | |
796 | }; | |
797 | ||
798 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { | |
799 | .cmd_rcgr = 0x77020, | |
800 | .mnd_width = 8, | |
801 | .hid_width = 5, | |
802 | .parent_map = gcc_parent_map_0, | |
803 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, | |
804 | .clkr.hw.init = &(struct clk_init_data){ | |
805 | .name = "gcc_ufs_phy_axi_clk_src", | |
806 | .parent_data = gcc_parent_data_0, | |
807 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
808 | .ops = &clk_rcg2_ops, | |
809 | }, | |
810 | }; | |
811 | ||
812 | static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { | |
813 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
814 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
815 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
816 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
817 | { } | |
818 | }; | |
819 | ||
820 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { | |
821 | .cmd_rcgr = 0x77048, | |
822 | .mnd_width = 0, | |
823 | .hid_width = 5, | |
824 | .parent_map = gcc_parent_map_0, | |
825 | .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, | |
826 | .clkr.hw.init = &(struct clk_init_data){ | |
827 | .name = "gcc_ufs_phy_ice_core_clk_src", | |
828 | .parent_data = gcc_parent_data_0, | |
829 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
830 | .ops = &clk_rcg2_ops, | |
831 | }, | |
832 | }; | |
833 | ||
834 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { | |
835 | .cmd_rcgr = 0x77098, | |
836 | .mnd_width = 0, | |
837 | .hid_width = 5, | |
838 | .parent_map = gcc_parent_map_4, | |
839 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
840 | .clkr.hw.init = &(struct clk_init_data){ | |
841 | .name = "gcc_ufs_phy_phy_aux_clk_src", | |
842 | .parent_data = gcc_parent_data_4, | |
843 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
844 | .ops = &clk_rcg2_ops, | |
845 | }, | |
846 | }; | |
847 | ||
848 | static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { | |
849 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
850 | F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), | |
851 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
852 | { } | |
853 | }; | |
854 | ||
855 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { | |
856 | .cmd_rcgr = 0x77060, | |
857 | .mnd_width = 0, | |
858 | .hid_width = 5, | |
859 | .parent_map = gcc_parent_map_0, | |
860 | .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, | |
861 | .clkr.hw.init = &(struct clk_init_data){ | |
862 | .name = "gcc_ufs_phy_unipro_core_clk_src", | |
863 | .parent_data = gcc_parent_data_0, | |
864 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
865 | .ops = &clk_rcg2_ops, | |
866 | }, | |
867 | }; | |
868 | ||
869 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { | |
870 | F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), | |
871 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), | |
872 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
873 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
874 | { } | |
875 | }; | |
876 | ||
877 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { | |
878 | .cmd_rcgr = 0xf01c, | |
879 | .mnd_width = 8, | |
880 | .hid_width = 5, | |
881 | .parent_map = gcc_parent_map_0, | |
882 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
883 | .clkr.hw.init = &(struct clk_init_data){ | |
884 | .name = "gcc_usb30_prim_master_clk_src", | |
885 | .parent_data = gcc_parent_data_0, | |
886 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
887 | .ops = &clk_rcg2_ops, | |
888 | }, | |
889 | }; | |
890 | ||
891 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { | |
892 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
893 | F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), | |
894 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), | |
895 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), | |
896 | { } | |
897 | }; | |
898 | ||
899 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { | |
900 | .cmd_rcgr = 0xf034, | |
901 | .mnd_width = 0, | |
902 | .hid_width = 5, | |
903 | .parent_map = gcc_parent_map_0, | |
904 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
905 | .clkr.hw.init = &(struct clk_init_data){ | |
906 | .name = "gcc_usb30_prim_mock_utmi_clk_src", | |
907 | .parent_data = gcc_parent_data_0, | |
908 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
909 | .ops = &clk_rcg2_ops, | |
910 | }, | |
911 | }; | |
912 | ||
913 | static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { | |
914 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
915 | { } | |
916 | }; | |
917 | ||
918 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { | |
919 | .cmd_rcgr = 0xf060, | |
920 | .mnd_width = 0, | |
921 | .hid_width = 5, | |
922 | .parent_map = gcc_parent_map_3, | |
923 | .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, | |
924 | .clkr.hw.init = &(struct clk_init_data){ | |
925 | .name = "gcc_usb3_prim_phy_aux_clk_src", | |
926 | .parent_data = gcc_parent_data_3, | |
927 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
928 | .ops = &clk_rcg2_ops, | |
929 | }, | |
930 | }; | |
931 | ||
932 | static struct clk_rcg2 gcc_vs_ctrl_clk_src = { | |
933 | .cmd_rcgr = 0x7a030, | |
934 | .mnd_width = 0, | |
935 | .hid_width = 5, | |
936 | .parent_map = gcc_parent_map_2, | |
937 | .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, | |
938 | .clkr.hw.init = &(struct clk_init_data){ | |
939 | .name = "gcc_vs_ctrl_clk_src", | |
940 | .parent_data = gcc_parent_data_2, | |
941 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
942 | .ops = &clk_rcg2_ops, | |
943 | }, | |
944 | }; | |
945 | ||
946 | static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { | |
947 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
948 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
949 | F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), | |
950 | { } | |
951 | }; | |
952 | ||
953 | static struct clk_rcg2 gcc_vsensor_clk_src = { | |
954 | .cmd_rcgr = 0x7a018, | |
955 | .mnd_width = 0, | |
956 | .hid_width = 5, | |
957 | .parent_map = gcc_parent_map_8, | |
958 | .freq_tbl = ftbl_gcc_vsensor_clk_src, | |
959 | .clkr.hw.init = &(struct clk_init_data){ | |
960 | .name = "gcc_vsensor_clk_src", | |
961 | .parent_data = gcc_parent_data_8, | |
962 | .num_parents = ARRAY_SIZE(gcc_parent_data_8), | |
963 | .ops = &clk_rcg2_ops, | |
964 | }, | |
965 | }; | |
966 | ||
967 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { | |
968 | .halt_reg = 0x2800c, | |
969 | .halt_check = BRANCH_HALT, | |
970 | .clkr = { | |
971 | .enable_reg = 0x2800c, | |
972 | .enable_mask = BIT(0), | |
973 | .hw.init = &(struct clk_init_data){ | |
974 | .name = "gcc_aggre_noc_pcie_tbu_clk", | |
975 | .ops = &clk_branch2_ops, | |
976 | }, | |
977 | }, | |
978 | }; | |
979 | ||
980 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { | |
981 | .halt_reg = 0x82024, | |
982 | .halt_check = BRANCH_HALT, | |
983 | .hwcg_reg = 0x82024, | |
984 | .hwcg_bit = 1, | |
985 | .clkr = { | |
986 | .enable_reg = 0x82024, | |
987 | .enable_mask = BIT(0), | |
988 | .hw.init = &(struct clk_init_data){ | |
989 | .name = "gcc_aggre_ufs_phy_axi_clk", | |
990 | .parent_hws = (const struct clk_hw*[]){ | |
991 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
992 | }, | |
993 | .num_parents = 1, | |
994 | .flags = CLK_SET_RATE_PARENT, | |
995 | .ops = &clk_branch2_ops, | |
996 | }, | |
997 | }, | |
998 | }; | |
999 | ||
1000 | static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { | |
1001 | .halt_reg = 0x82024, | |
1002 | .halt_check = BRANCH_HALT, | |
1003 | .hwcg_reg = 0x82024, | |
1004 | .hwcg_bit = 1, | |
1005 | .clkr = { | |
1006 | .enable_reg = 0x82024, | |
1007 | .enable_mask = BIT(1), | |
1008 | .hw.init = &(struct clk_init_data){ | |
1009 | .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", | |
1010 | .parent_hws = (const struct clk_hw*[]){ | |
1011 | &gcc_aggre_ufs_phy_axi_clk.clkr.hw, | |
1012 | }, | |
1013 | .num_parents = 1, | |
1014 | .flags = CLK_SET_RATE_PARENT, | |
1015 | .ops = &clk_branch_simple_ops, | |
1016 | }, | |
1017 | }, | |
1018 | }; | |
1019 | ||
1020 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { | |
1021 | .halt_reg = 0x8201c, | |
1022 | .halt_check = BRANCH_HALT, | |
1023 | .clkr = { | |
1024 | .enable_reg = 0x8201c, | |
1025 | .enable_mask = BIT(0), | |
1026 | .hw.init = &(struct clk_init_data){ | |
1027 | .name = "gcc_aggre_usb3_prim_axi_clk", | |
1028 | .parent_hws = (const struct clk_hw*[]){ | |
1029 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
1030 | }, | |
1031 | .num_parents = 1, | |
1032 | .flags = CLK_SET_RATE_PARENT, | |
1033 | .ops = &clk_branch2_ops, | |
1034 | }, | |
1035 | }, | |
1036 | }; | |
1037 | ||
1038 | static struct clk_branch gcc_apc_vs_clk = { | |
1039 | .halt_reg = 0x7a050, | |
1040 | .halt_check = BRANCH_HALT, | |
1041 | .clkr = { | |
1042 | .enable_reg = 0x7a050, | |
1043 | .enable_mask = BIT(0), | |
1044 | .hw.init = &(struct clk_init_data){ | |
1045 | .name = "gcc_apc_vs_clk", | |
1046 | .parent_hws = (const struct clk_hw*[]){ | |
1047 | &gcc_vsensor_clk_src.clkr.hw, | |
1048 | }, | |
1049 | .num_parents = 1, | |
1050 | .flags = CLK_SET_RATE_PARENT, | |
1051 | .ops = &clk_branch2_ops, | |
1052 | }, | |
1053 | }, | |
1054 | }; | |
1055 | ||
1056 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1057 | .halt_reg = 0x38004, | |
1058 | .halt_check = BRANCH_HALT_VOTED, | |
1059 | .hwcg_reg = 0x38004, | |
1060 | .hwcg_bit = 1, | |
1061 | .clkr = { | |
1062 | .enable_reg = 0x52004, | |
1063 | .enable_mask = BIT(10), | |
1064 | .hw.init = &(struct clk_init_data){ | |
1065 | .name = "gcc_boot_rom_ahb_clk", | |
1066 | .ops = &clk_branch2_ops, | |
1067 | }, | |
1068 | }, | |
1069 | }; | |
1070 | ||
1071 | static struct clk_branch gcc_camera_hf_axi_clk = { | |
1072 | .halt_reg = 0xb020, | |
1073 | .halt_check = BRANCH_HALT, | |
1074 | .clkr = { | |
1075 | .enable_reg = 0xb020, | |
1076 | .enable_mask = BIT(0), | |
1077 | .hw.init = &(struct clk_init_data){ | |
1078 | .name = "gcc_camera_hf_axi_clk", | |
1079 | .ops = &clk_branch2_ops, | |
1080 | }, | |
1081 | }, | |
1082 | }; | |
1083 | ||
1084 | static struct clk_branch gcc_camera_sf_axi_clk = { | |
1085 | .halt_reg = 0xb06c, | |
1086 | .halt_check = BRANCH_HALT, | |
1087 | .clkr = { | |
1088 | .enable_reg = 0xb06c, | |
1089 | .enable_mask = BIT(0), | |
1090 | .hw.init = &(struct clk_init_data){ | |
1091 | .name = "gcc_camera_sf_axi_clk", | |
1092 | .ops = &clk_branch2_ops, | |
1093 | }, | |
1094 | }, | |
1095 | }; | |
1096 | ||
1097 | static struct clk_branch gcc_ce1_ahb_clk = { | |
1098 | .halt_reg = 0x4100c, | |
1099 | .halt_check = BRANCH_HALT_VOTED, | |
1100 | .hwcg_reg = 0x4100c, | |
1101 | .hwcg_bit = 1, | |
1102 | .clkr = { | |
1103 | .enable_reg = 0x52004, | |
1104 | .enable_mask = BIT(3), | |
1105 | .hw.init = &(struct clk_init_data){ | |
1106 | .name = "gcc_ce1_ahb_clk", | |
1107 | .ops = &clk_branch2_ops, | |
1108 | }, | |
1109 | }, | |
1110 | }; | |
1111 | ||
1112 | static struct clk_branch gcc_ce1_axi_clk = { | |
1113 | .halt_reg = 0x41008, | |
1114 | .halt_check = BRANCH_HALT_VOTED, | |
1115 | .clkr = { | |
1116 | .enable_reg = 0x52004, | |
1117 | .enable_mask = BIT(4), | |
1118 | .hw.init = &(struct clk_init_data){ | |
1119 | .name = "gcc_ce1_axi_clk", | |
1120 | .ops = &clk_branch2_ops, | |
1121 | }, | |
1122 | }, | |
1123 | }; | |
1124 | ||
1125 | static struct clk_branch gcc_ce1_clk = { | |
1126 | .halt_reg = 0x41004, | |
1127 | .halt_check = BRANCH_HALT_VOTED, | |
1128 | .clkr = { | |
1129 | .enable_reg = 0x52004, | |
1130 | .enable_mask = BIT(5), | |
1131 | .hw.init = &(struct clk_init_data){ | |
1132 | .name = "gcc_ce1_clk", | |
1133 | .ops = &clk_branch2_ops, | |
1134 | }, | |
1135 | }, | |
1136 | }; | |
1137 | ||
1138 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { | |
1139 | .halt_reg = 0x502c, | |
1140 | .halt_check = BRANCH_HALT, | |
1141 | .clkr = { | |
1142 | .enable_reg = 0x502c, | |
1143 | .enable_mask = BIT(0), | |
1144 | .hw.init = &(struct clk_init_data){ | |
1145 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", | |
1146 | .parent_hws = (const struct clk_hw*[]){ | |
1147 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
1148 | }, | |
1149 | .num_parents = 1, | |
1150 | .flags = CLK_SET_RATE_PARENT, | |
1151 | .ops = &clk_branch2_ops, | |
1152 | }, | |
1153 | }, | |
1154 | }; | |
1155 | ||
1156 | static struct clk_branch gcc_cpuss_ahb_clk = { | |
1157 | .halt_reg = 0x48000, | |
1158 | .halt_check = BRANCH_HALT_VOTED, | |
1159 | .clkr = { | |
1160 | .enable_reg = 0x52004, | |
1161 | .enable_mask = BIT(21), | |
1162 | .hw.init = &(struct clk_init_data){ | |
1163 | .name = "gcc_cpuss_ahb_clk", | |
1164 | .parent_hws = (const struct clk_hw*[]){ | |
1165 | &gcc_cpuss_ahb_clk_src.clkr.hw, | |
1166 | }, | |
1167 | .num_parents = 1, | |
1168 | .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, | |
1169 | .ops = &clk_branch2_ops, | |
1170 | }, | |
1171 | }, | |
1172 | }; | |
1173 | ||
1174 | static struct clk_branch gcc_cpuss_rbcpr_clk = { | |
1175 | .halt_reg = 0x48008, | |
1176 | .halt_check = BRANCH_HALT, | |
1177 | .clkr = { | |
1178 | .enable_reg = 0x48008, | |
1179 | .enable_mask = BIT(0), | |
1180 | .hw.init = &(struct clk_init_data){ | |
1181 | .name = "gcc_cpuss_rbcpr_clk", | |
1182 | .parent_hws = (const struct clk_hw*[]){ | |
1183 | &gcc_cpuss_rbcpr_clk_src.clkr.hw, | |
1184 | }, | |
1185 | .num_parents = 1, | |
1186 | .flags = CLK_SET_RATE_PARENT, | |
1187 | .ops = &clk_branch2_ops, | |
1188 | }, | |
1189 | }, | |
1190 | }; | |
1191 | ||
1192 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { | |
1193 | .halt_reg = 0x4452c, | |
1194 | .halt_check = BRANCH_VOTED, | |
1195 | .clkr = { | |
1196 | .enable_reg = 0x4452c, | |
1197 | .enable_mask = BIT(0), | |
1198 | .hw.init = &(struct clk_init_data){ | |
1199 | .name = "gcc_ddrss_gpu_axi_clk", | |
1200 | .ops = &clk_branch2_ops, | |
1201 | }, | |
1202 | }, | |
1203 | }; | |
1204 | ||
1205 | ||
1206 | static struct clk_branch gcc_disp_gpll0_clk_src = { | |
1207 | .halt_check = BRANCH_HALT_DELAY, | |
1208 | .clkr = { | |
1209 | .enable_reg = 0x52004, | |
1210 | .enable_mask = BIT(18), | |
1211 | .hw.init = &(struct clk_init_data){ | |
1212 | .name = "gcc_disp_gpll0_clk_src", | |
1213 | .parent_hws = (const struct clk_hw*[]){ | |
1214 | &gpll0.clkr.hw, | |
1215 | }, | |
1216 | .num_parents = 1, | |
1217 | .ops = &clk_branch2_aon_ops, | |
1218 | }, | |
1219 | }, | |
1220 | }; | |
1221 | ||
1222 | static struct clk_branch gcc_disp_gpll0_div_clk_src = { | |
1223 | .halt_check = BRANCH_HALT_DELAY, | |
1224 | .clkr = { | |
1225 | .enable_reg = 0x52004, | |
1226 | .enable_mask = BIT(19), | |
1227 | .hw.init = &(struct clk_init_data){ | |
1228 | .name = "gcc_disp_gpll0_div_clk_src", | |
1229 | .parent_hws = (const struct clk_hw*[]){ | |
1230 | &gcc_pll0_main_div_cdiv.hw, | |
1231 | }, | |
1232 | .num_parents = 1, | |
1233 | .ops = &clk_branch2_ops, | |
1234 | }, | |
1235 | }, | |
1236 | }; | |
1237 | ||
1238 | static struct clk_branch gcc_disp_hf_axi_clk = { | |
1239 | .halt_reg = 0xb024, | |
1240 | .halt_check = BRANCH_HALT, | |
1241 | .clkr = { | |
1242 | .enable_reg = 0xb024, | |
1243 | .enable_mask = BIT(0), | |
1244 | .hw.init = &(struct clk_init_data){ | |
1245 | .name = "gcc_disp_hf_axi_clk", | |
1246 | .ops = &clk_branch2_ops, | |
1247 | }, | |
1248 | }, | |
1249 | }; | |
1250 | ||
1251 | static struct clk_branch gcc_disp_sf_axi_clk = { | |
1252 | .halt_reg = 0xb070, | |
1253 | .halt_check = BRANCH_HALT, | |
1254 | .clkr = { | |
1255 | .enable_reg = 0xb070, | |
1256 | .enable_mask = BIT(0), | |
1257 | .hw.init = &(struct clk_init_data){ | |
1258 | .name = "gcc_disp_sf_axi_clk", | |
1259 | .ops = &clk_branch2_ops, | |
1260 | }, | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | ||
1265 | static struct clk_branch gcc_gp1_clk = { | |
1266 | .halt_reg = 0x64000, | |
1267 | .halt_check = BRANCH_HALT, | |
1268 | .clkr = { | |
1269 | .enable_reg = 0x64000, | |
1270 | .enable_mask = BIT(0), | |
1271 | .hw.init = &(struct clk_init_data){ | |
1272 | .name = "gcc_gp1_clk", | |
1273 | .parent_hws = (const struct clk_hw*[]){ | |
1274 | &gcc_gp1_clk_src.clkr.hw, | |
1275 | }, | |
1276 | .num_parents = 1, | |
1277 | .flags = CLK_SET_RATE_PARENT, | |
1278 | .ops = &clk_branch2_ops, | |
1279 | }, | |
1280 | }, | |
1281 | }; | |
1282 | ||
1283 | static struct clk_branch gcc_gp2_clk = { | |
1284 | .halt_reg = 0x65000, | |
1285 | .halt_check = BRANCH_HALT, | |
1286 | .clkr = { | |
1287 | .enable_reg = 0x65000, | |
1288 | .enable_mask = BIT(0), | |
1289 | .hw.init = &(struct clk_init_data){ | |
1290 | .name = "gcc_gp2_clk", | |
1291 | .parent_hws = (const struct clk_hw*[]){ | |
1292 | &gcc_gp2_clk_src.clkr.hw, | |
1293 | }, | |
1294 | .num_parents = 1, | |
1295 | .flags = CLK_SET_RATE_PARENT, | |
1296 | .ops = &clk_branch2_ops, | |
1297 | }, | |
1298 | }, | |
1299 | }; | |
1300 | ||
1301 | static struct clk_branch gcc_gp3_clk = { | |
1302 | .halt_reg = 0x66000, | |
1303 | .halt_check = BRANCH_HALT, | |
1304 | .clkr = { | |
1305 | .enable_reg = 0x66000, | |
1306 | .enable_mask = BIT(0), | |
1307 | .hw.init = &(struct clk_init_data){ | |
1308 | .name = "gcc_gp3_clk", | |
1309 | .parent_hws = (const struct clk_hw*[]){ | |
1310 | &gcc_gp3_clk_src.clkr.hw, | |
1311 | }, | |
1312 | .num_parents = 1, | |
1313 | .flags = CLK_SET_RATE_PARENT, | |
1314 | .ops = &clk_branch2_ops, | |
1315 | }, | |
1316 | }, | |
1317 | }; | |
1318 | ||
1319 | static struct clk_branch gcc_gpu_gpll0_clk_src = { | |
1320 | .halt_check = BRANCH_HALT_DELAY, | |
1321 | .clkr = { | |
1322 | .enable_reg = 0x52004, | |
1323 | .enable_mask = BIT(15), | |
1324 | .hw.init = &(struct clk_init_data){ | |
1325 | .name = "gcc_gpu_gpll0_clk_src", | |
1326 | .parent_hws = (const struct clk_hw*[]){ | |
1327 | &gpll0.clkr.hw, | |
1328 | }, | |
1329 | .num_parents = 1, | |
1330 | .ops = &clk_branch2_ops, | |
1331 | }, | |
1332 | }, | |
1333 | }; | |
1334 | ||
1335 | static struct clk_branch gcc_gpu_gpll0_div_clk_src = { | |
1336 | .halt_check = BRANCH_HALT_DELAY, | |
1337 | .clkr = { | |
1338 | .enable_reg = 0x52004, | |
1339 | .enable_mask = BIT(16), | |
1340 | .hw.init = &(struct clk_init_data){ | |
1341 | .name = "gcc_gpu_gpll0_div_clk_src", | |
1342 | .parent_hws = (const struct clk_hw*[]){ | |
1343 | &gcc_pll0_main_div_cdiv.hw, | |
1344 | }, | |
1345 | .num_parents = 1, | |
1346 | .ops = &clk_branch2_ops, | |
1347 | }, | |
1348 | }, | |
1349 | }; | |
1350 | ||
1351 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { | |
1352 | .halt_reg = 0x7100c, | |
1353 | .halt_check = BRANCH_VOTED, | |
1354 | .clkr = { | |
1355 | .enable_reg = 0x7100c, | |
1356 | .enable_mask = BIT(0), | |
1357 | .hw.init = &(struct clk_init_data){ | |
1358 | .name = "gcc_gpu_memnoc_gfx_clk", | |
1359 | .ops = &clk_branch2_ops, | |
1360 | }, | |
1361 | }, | |
1362 | }; | |
1363 | ||
1364 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { | |
1365 | .halt_reg = 0x71018, | |
1366 | .halt_check = BRANCH_HALT, | |
1367 | .clkr = { | |
1368 | .enable_reg = 0x71018, | |
1369 | .enable_mask = BIT(0), | |
1370 | .hw.init = &(struct clk_init_data){ | |
1371 | .name = "gcc_gpu_snoc_dvm_gfx_clk", | |
1372 | .ops = &clk_branch2_ops, | |
1373 | }, | |
1374 | }, | |
1375 | }; | |
1376 | ||
1377 | static struct clk_branch gcc_gpu_vs_clk = { | |
1378 | .halt_reg = 0x7a04c, | |
1379 | .halt_check = BRANCH_HALT, | |
1380 | .clkr = { | |
1381 | .enable_reg = 0x7a04c, | |
1382 | .enable_mask = BIT(0), | |
1383 | .hw.init = &(struct clk_init_data){ | |
1384 | .name = "gcc_gpu_vs_clk", | |
1385 | .parent_hws = (const struct clk_hw*[]){ | |
1386 | &gcc_vsensor_clk_src.clkr.hw, | |
1387 | }, | |
1388 | .num_parents = 1, | |
1389 | .flags = CLK_SET_RATE_PARENT, | |
1390 | .ops = &clk_branch2_ops, | |
1391 | }, | |
1392 | }, | |
1393 | }; | |
1394 | ||
1395 | static struct clk_branch gcc_npu_axi_clk = { | |
1396 | .halt_reg = 0x4d008, | |
1397 | .halt_check = BRANCH_HALT, | |
1398 | .clkr = { | |
1399 | .enable_reg = 0x4d008, | |
1400 | .enable_mask = BIT(0), | |
1401 | .hw.init = &(struct clk_init_data){ | |
1402 | .name = "gcc_npu_axi_clk", | |
1403 | .ops = &clk_branch2_ops, | |
1404 | }, | |
1405 | }, | |
1406 | }; | |
1407 | ||
1408 | static struct clk_branch gcc_npu_cfg_ahb_clk = { | |
1409 | .halt_reg = 0x4d004, | |
1410 | .halt_check = BRANCH_HALT, | |
1411 | .hwcg_reg = 0x4d004, | |
1412 | .hwcg_bit = 1, | |
1413 | .clkr = { | |
1414 | .enable_reg = 0x4d004, | |
1415 | .enable_mask = BIT(0), | |
1416 | .hw.init = &(struct clk_init_data){ | |
1417 | .name = "gcc_npu_cfg_ahb_clk", | |
1418 | .flags = CLK_IS_CRITICAL, | |
1419 | .ops = &clk_branch2_ops, | |
1420 | }, | |
1421 | }, | |
1422 | }; | |
1423 | ||
1424 | static struct clk_branch gcc_npu_gpll0_clk_src = { | |
1425 | .halt_check = BRANCH_HALT_DELAY, | |
1426 | .clkr = { | |
1427 | .enable_reg = 0x52004, | |
1428 | .enable_mask = BIT(25), | |
1429 | .hw.init = &(struct clk_init_data){ | |
1430 | .name = "gcc_npu_gpll0_clk_src", | |
1431 | .parent_hws = (const struct clk_hw*[]){ | |
1432 | &gpll0.clkr.hw, | |
1433 | }, | |
1434 | .num_parents = 1, | |
1435 | .ops = &clk_branch2_ops, | |
1436 | }, | |
1437 | }, | |
1438 | }; | |
1439 | ||
1440 | static struct clk_branch gcc_npu_gpll0_div_clk_src = { | |
1441 | .halt_check = BRANCH_HALT_DELAY, | |
1442 | .clkr = { | |
1443 | .enable_reg = 0x52004, | |
1444 | .enable_mask = BIT(26), | |
1445 | .hw.init = &(struct clk_init_data){ | |
1446 | .name = "gcc_npu_gpll0_div_clk_src", | |
1447 | .parent_hws = (const struct clk_hw*[]){ | |
1448 | &gcc_pll0_main_div_cdiv.hw, | |
1449 | }, | |
1450 | .num_parents = 1, | |
1451 | .flags = CLK_SET_RATE_PARENT, | |
1452 | .ops = &clk_branch2_ops, | |
1453 | }, | |
1454 | }, | |
1455 | }; | |
1456 | ||
1457 | static struct clk_branch gcc_pcie_0_aux_clk = { | |
1458 | .halt_reg = 0x6b01c, | |
1459 | .halt_check = BRANCH_HALT_VOTED, | |
1460 | .clkr = { | |
1461 | .enable_reg = 0x5200c, | |
1462 | .enable_mask = BIT(3), | |
1463 | .hw.init = &(struct clk_init_data){ | |
1464 | .name = "gcc_pcie_0_aux_clk", | |
1465 | .parent_hws = (const struct clk_hw*[]){ | |
1466 | &gcc_pcie_0_aux_clk_src.clkr.hw, | |
1467 | }, | |
1468 | .num_parents = 1, | |
1469 | .flags = CLK_SET_RATE_PARENT, | |
1470 | .ops = &clk_branch2_ops, | |
1471 | }, | |
1472 | }, | |
1473 | }; | |
1474 | ||
1475 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
1476 | .halt_reg = 0x6b018, | |
1477 | .halt_check = BRANCH_HALT_VOTED, | |
1478 | .hwcg_reg = 0x6b018, | |
1479 | .hwcg_bit = 1, | |
1480 | .clkr = { | |
1481 | .enable_reg = 0x5200c, | |
1482 | .enable_mask = BIT(2), | |
1483 | .hw.init = &(struct clk_init_data){ | |
1484 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
1485 | .ops = &clk_branch2_ops, | |
1486 | }, | |
1487 | }, | |
1488 | }; | |
1489 | ||
1490 | static struct clk_branch gcc_pcie_0_clkref_clk = { | |
1491 | .halt_reg = 0x8c008, | |
1492 | .halt_check = BRANCH_HALT, | |
1493 | .clkr = { | |
1494 | .enable_reg = 0x8c008, | |
1495 | .enable_mask = BIT(0), | |
1496 | .hw.init = &(struct clk_init_data){ | |
1497 | .name = "gcc_pcie_0_clkref_clk", | |
1498 | .ops = &clk_branch2_ops, | |
1499 | }, | |
1500 | }, | |
1501 | }; | |
1502 | ||
1503 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
1504 | .halt_reg = 0x6b014, | |
1505 | .halt_check = BRANCH_HALT_VOTED, | |
1506 | .clkr = { | |
1507 | .enable_reg = 0x5200c, | |
1508 | .enable_mask = BIT(1), | |
1509 | .hw.init = &(struct clk_init_data){ | |
1510 | .name = "gcc_pcie_0_mstr_axi_clk", | |
1511 | .ops = &clk_branch2_ops, | |
1512 | }, | |
1513 | }, | |
1514 | }; | |
1515 | ||
1516 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
1517 | .halt_reg = 0x6b020, | |
1518 | .halt_check = BRANCH_HALT_SKIP, | |
1519 | .clkr = { | |
1520 | .enable_reg = 0x5200c, | |
1521 | .enable_mask = BIT(4), | |
1522 | .hw.init = &(struct clk_init_data){ | |
1523 | .name = "gcc_pcie_0_pipe_clk", | |
1524 | .ops = &clk_branch2_ops, | |
1525 | }, | |
1526 | }, | |
1527 | }; | |
1528 | ||
1529 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
1530 | .halt_reg = 0x6b010, | |
1531 | .halt_check = BRANCH_HALT_VOTED, | |
1532 | .hwcg_reg = 0x6b010, | |
1533 | .hwcg_bit = 1, | |
1534 | .clkr = { | |
1535 | .enable_reg = 0x5200c, | |
1536 | .enable_mask = BIT(0), | |
1537 | .hw.init = &(struct clk_init_data){ | |
1538 | .name = "gcc_pcie_0_slv_axi_clk", | |
1539 | .ops = &clk_branch2_ops, | |
1540 | }, | |
1541 | }, | |
1542 | }; | |
1543 | ||
1544 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { | |
1545 | .halt_reg = 0x6b00c, | |
1546 | .halt_check = BRANCH_HALT_VOTED, | |
1547 | .clkr = { | |
1548 | .enable_reg = 0x5200c, | |
1549 | .enable_mask = BIT(5), | |
1550 | .hw.init = &(struct clk_init_data){ | |
1551 | .name = "gcc_pcie_0_slv_q2a_axi_clk", | |
1552 | .ops = &clk_branch2_ops, | |
1553 | }, | |
1554 | }, | |
1555 | }; | |
1556 | ||
1557 | static struct clk_branch gcc_pcie_phy_aux_clk = { | |
1558 | .halt_reg = 0x6f004, | |
1559 | .halt_check = BRANCH_HALT, | |
1560 | .clkr = { | |
1561 | .enable_reg = 0x6f004, | |
1562 | .enable_mask = BIT(0), | |
1563 | .hw.init = &(struct clk_init_data){ | |
1564 | .name = "gcc_pcie_phy_aux_clk", | |
1565 | .parent_hws = (const struct clk_hw*[]){ | |
1566 | &gcc_pcie_0_aux_clk_src.clkr.hw, | |
1567 | }, | |
1568 | .num_parents = 1, | |
1569 | .flags = CLK_SET_RATE_PARENT, | |
1570 | .ops = &clk_branch2_ops, | |
1571 | }, | |
1572 | }, | |
1573 | }; | |
1574 | ||
1575 | static struct clk_branch gcc_pcie_phy_refgen_clk = { | |
1576 | .halt_reg = 0x6f02c, | |
1577 | .halt_check = BRANCH_HALT, | |
1578 | .clkr = { | |
1579 | .enable_reg = 0x6f02c, | |
1580 | .enable_mask = BIT(0), | |
1581 | .hw.init = &(struct clk_init_data){ | |
1582 | .name = "gcc_pcie_phy_refgen_clk", | |
1583 | .parent_hws = (const struct clk_hw*[]){ | |
1584 | &gcc_pcie_phy_refgen_clk_src.clkr.hw, | |
1585 | }, | |
1586 | .num_parents = 1, | |
1587 | .flags = CLK_SET_RATE_PARENT, | |
1588 | .ops = &clk_branch2_ops, | |
1589 | }, | |
1590 | }, | |
1591 | }; | |
1592 | ||
1593 | static struct clk_branch gcc_pdm2_clk = { | |
1594 | .halt_reg = 0x3300c, | |
1595 | .halt_check = BRANCH_HALT, | |
1596 | .clkr = { | |
1597 | .enable_reg = 0x3300c, | |
1598 | .enable_mask = BIT(0), | |
1599 | .hw.init = &(struct clk_init_data){ | |
1600 | .name = "gcc_pdm2_clk", | |
1601 | .parent_hws = (const struct clk_hw*[]){ | |
1602 | &gcc_pdm2_clk_src.clkr.hw, | |
1603 | }, | |
1604 | .num_parents = 1, | |
1605 | .flags = CLK_SET_RATE_PARENT, | |
1606 | .ops = &clk_branch2_ops, | |
1607 | }, | |
1608 | }, | |
1609 | }; | |
1610 | ||
1611 | static struct clk_branch gcc_pdm_ahb_clk = { | |
1612 | .halt_reg = 0x33004, | |
1613 | .halt_check = BRANCH_HALT, | |
1614 | .hwcg_reg = 0x33004, | |
1615 | .hwcg_bit = 1, | |
1616 | .clkr = { | |
1617 | .enable_reg = 0x33004, | |
1618 | .enable_mask = BIT(0), | |
1619 | .hw.init = &(struct clk_init_data){ | |
1620 | .name = "gcc_pdm_ahb_clk", | |
1621 | .ops = &clk_branch2_ops, | |
1622 | }, | |
1623 | }, | |
1624 | }; | |
1625 | ||
1626 | static struct clk_branch gcc_pdm_xo4_clk = { | |
1627 | .halt_reg = 0x33008, | |
1628 | .halt_check = BRANCH_HALT, | |
1629 | .clkr = { | |
1630 | .enable_reg = 0x33008, | |
1631 | .enable_mask = BIT(0), | |
1632 | .hw.init = &(struct clk_init_data){ | |
1633 | .name = "gcc_pdm_xo4_clk", | |
1634 | .ops = &clk_branch2_ops, | |
1635 | }, | |
1636 | }, | |
1637 | }; | |
1638 | ||
1639 | static struct clk_branch gcc_prng_ahb_clk = { | |
1640 | .halt_reg = 0x34004, | |
1641 | .halt_check = BRANCH_HALT_VOTED, | |
1642 | .hwcg_reg = 0x34004, | |
1643 | .hwcg_bit = 1, | |
1644 | .clkr = { | |
1645 | .enable_reg = 0x52004, | |
1646 | .enable_mask = BIT(13), | |
1647 | .hw.init = &(struct clk_init_data){ | |
1648 | .name = "gcc_prng_ahb_clk", | |
1649 | .ops = &clk_branch2_ops, | |
1650 | }, | |
1651 | }, | |
1652 | }; | |
1653 | ||
1654 | static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { | |
1655 | .halt_reg = 0x17014, | |
1656 | .halt_check = BRANCH_HALT_VOTED, | |
1657 | .clkr = { | |
1658 | .enable_reg = 0x5200c, | |
1659 | .enable_mask = BIT(9), | |
1660 | .hw.init = &(struct clk_init_data){ | |
1661 | .name = "gcc_qupv3_wrap0_core_2x_clk", | |
1662 | .ops = &clk_branch2_ops, | |
1663 | }, | |
1664 | }, | |
1665 | }; | |
1666 | ||
1667 | static struct clk_branch gcc_qupv3_wrap0_core_clk = { | |
1668 | .halt_reg = 0x1700c, | |
1669 | .halt_check = BRANCH_HALT_VOTED, | |
1670 | .clkr = { | |
1671 | .enable_reg = 0x5200c, | |
1672 | .enable_mask = BIT(8), | |
1673 | .hw.init = &(struct clk_init_data){ | |
1674 | .name = "gcc_qupv3_wrap0_core_clk", | |
1675 | .ops = &clk_branch2_ops, | |
1676 | }, | |
1677 | }, | |
1678 | }; | |
1679 | ||
1680 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { | |
1681 | .halt_reg = 0x17030, | |
1682 | .halt_check = BRANCH_HALT_VOTED, | |
1683 | .clkr = { | |
1684 | .enable_reg = 0x5200c, | |
1685 | .enable_mask = BIT(10), | |
1686 | .hw.init = &(struct clk_init_data){ | |
1687 | .name = "gcc_qupv3_wrap0_s0_clk", | |
1688 | .parent_hws = (const struct clk_hw*[]){ | |
1689 | &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, | |
1690 | }, | |
1691 | .num_parents = 1, | |
1692 | .flags = CLK_SET_RATE_PARENT, | |
1693 | .ops = &clk_branch2_ops, | |
1694 | }, | |
1695 | }, | |
1696 | }; | |
1697 | ||
1698 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { | |
1699 | .halt_reg = 0x17160, | |
1700 | .halt_check = BRANCH_HALT_VOTED, | |
1701 | .clkr = { | |
1702 | .enable_reg = 0x5200c, | |
1703 | .enable_mask = BIT(11), | |
1704 | .hw.init = &(struct clk_init_data){ | |
1705 | .name = "gcc_qupv3_wrap0_s1_clk", | |
1706 | .parent_hws = (const struct clk_hw*[]){ | |
1707 | &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, | |
1708 | }, | |
1709 | .num_parents = 1, | |
1710 | .flags = CLK_SET_RATE_PARENT, | |
1711 | .ops = &clk_branch2_ops, | |
1712 | }, | |
1713 | }, | |
1714 | }; | |
1715 | ||
1716 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { | |
1717 | .halt_reg = 0x17290, | |
1718 | .halt_check = BRANCH_HALT_VOTED, | |
1719 | .clkr = { | |
1720 | .enable_reg = 0x5200c, | |
1721 | .enable_mask = BIT(12), | |
1722 | .hw.init = &(struct clk_init_data){ | |
1723 | .name = "gcc_qupv3_wrap0_s2_clk", | |
1724 | .parent_hws = (const struct clk_hw*[]){ | |
1725 | &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, | |
1726 | }, | |
1727 | .num_parents = 1, | |
1728 | .flags = CLK_SET_RATE_PARENT, | |
1729 | .ops = &clk_branch2_ops, | |
1730 | }, | |
1731 | }, | |
1732 | }; | |
1733 | ||
1734 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { | |
1735 | .halt_reg = 0x173c0, | |
1736 | .halt_check = BRANCH_HALT_VOTED, | |
1737 | .clkr = { | |
1738 | .enable_reg = 0x5200c, | |
1739 | .enable_mask = BIT(13), | |
1740 | .hw.init = &(struct clk_init_data){ | |
1741 | .name = "gcc_qupv3_wrap0_s3_clk", | |
1742 | .parent_hws = (const struct clk_hw*[]){ | |
1743 | &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, | |
1744 | }, | |
1745 | .num_parents = 1, | |
1746 | .flags = CLK_SET_RATE_PARENT, | |
1747 | .ops = &clk_branch2_ops, | |
1748 | }, | |
1749 | }, | |
1750 | }; | |
1751 | ||
1752 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { | |
1753 | .halt_reg = 0x174f0, | |
1754 | .halt_check = BRANCH_HALT_VOTED, | |
1755 | .clkr = { | |
1756 | .enable_reg = 0x5200c, | |
1757 | .enable_mask = BIT(14), | |
1758 | .hw.init = &(struct clk_init_data){ | |
1759 | .name = "gcc_qupv3_wrap0_s4_clk", | |
1760 | .parent_hws = (const struct clk_hw*[]){ | |
1761 | &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, | |
1762 | }, | |
1763 | .num_parents = 1, | |
1764 | .flags = CLK_SET_RATE_PARENT, | |
1765 | .ops = &clk_branch2_ops, | |
1766 | }, | |
1767 | }, | |
1768 | }; | |
1769 | ||
1770 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { | |
1771 | .halt_reg = 0x17620, | |
1772 | .halt_check = BRANCH_HALT_VOTED, | |
1773 | .clkr = { | |
1774 | .enable_reg = 0x5200c, | |
1775 | .enable_mask = BIT(15), | |
1776 | .hw.init = &(struct clk_init_data){ | |
1777 | .name = "gcc_qupv3_wrap0_s5_clk", | |
1778 | .parent_hws = (const struct clk_hw*[]){ | |
1779 | &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, | |
1780 | }, | |
1781 | .num_parents = 1, | |
1782 | .flags = CLK_SET_RATE_PARENT, | |
1783 | .ops = &clk_branch2_ops, | |
1784 | }, | |
1785 | }, | |
1786 | }; | |
1787 | ||
1788 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { | |
1789 | .halt_reg = 0x17750, | |
1790 | .halt_check = BRANCH_HALT_VOTED, | |
1791 | .clkr = { | |
1792 | .enable_reg = 0x5200c, | |
1793 | .enable_mask = BIT(16), | |
1794 | .hw.init = &(struct clk_init_data){ | |
1795 | .name = "gcc_qupv3_wrap0_s6_clk", | |
1796 | .parent_hws = (const struct clk_hw*[]){ | |
1797 | &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, | |
1798 | }, | |
1799 | .num_parents = 1, | |
1800 | .flags = CLK_SET_RATE_PARENT, | |
1801 | .ops = &clk_branch2_ops, | |
1802 | }, | |
1803 | }, | |
1804 | }; | |
1805 | ||
1806 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { | |
1807 | .halt_reg = 0x17880, | |
1808 | .halt_check = BRANCH_HALT_VOTED, | |
1809 | .clkr = { | |
1810 | .enable_reg = 0x5200c, | |
1811 | .enable_mask = BIT(17), | |
1812 | .hw.init = &(struct clk_init_data){ | |
1813 | .name = "gcc_qupv3_wrap0_s7_clk", | |
1814 | .parent_hws = (const struct clk_hw*[]){ | |
1815 | &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, | |
1816 | }, | |
1817 | .num_parents = 1, | |
1818 | .flags = CLK_SET_RATE_PARENT, | |
1819 | .ops = &clk_branch2_ops, | |
1820 | }, | |
1821 | }, | |
1822 | }; | |
1823 | ||
1824 | static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { | |
1825 | .halt_reg = 0x18004, | |
1826 | .halt_check = BRANCH_HALT_VOTED, | |
1827 | .clkr = { | |
1828 | .enable_reg = 0x5200c, | |
1829 | .enable_mask = BIT(18), | |
1830 | .hw.init = &(struct clk_init_data){ | |
1831 | .name = "gcc_qupv3_wrap1_core_2x_clk", | |
1832 | .ops = &clk_branch2_ops, | |
1833 | }, | |
1834 | }, | |
1835 | }; | |
1836 | ||
1837 | static struct clk_branch gcc_qupv3_wrap1_core_clk = { | |
1838 | .halt_reg = 0x18008, | |
1839 | .halt_check = BRANCH_HALT_VOTED, | |
1840 | .clkr = { | |
1841 | .enable_reg = 0x5200c, | |
1842 | .enable_mask = BIT(19), | |
1843 | .hw.init = &(struct clk_init_data){ | |
1844 | .name = "gcc_qupv3_wrap1_core_clk", | |
1845 | .ops = &clk_branch2_ops, | |
1846 | }, | |
1847 | }, | |
1848 | }; | |
1849 | ||
1850 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { | |
1851 | .halt_reg = 0x18014, | |
1852 | .halt_check = BRANCH_HALT_VOTED, | |
1853 | .clkr = { | |
1854 | .enable_reg = 0x5200c, | |
1855 | .enable_mask = BIT(22), | |
1856 | .hw.init = &(struct clk_init_data){ | |
1857 | .name = "gcc_qupv3_wrap1_s0_clk", | |
1858 | .parent_hws = (const struct clk_hw*[]){ | |
1859 | &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, | |
1860 | }, | |
1861 | .num_parents = 1, | |
1862 | .flags = CLK_SET_RATE_PARENT, | |
1863 | .ops = &clk_branch2_ops, | |
1864 | }, | |
1865 | }, | |
1866 | }; | |
1867 | ||
1868 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { | |
1869 | .halt_reg = 0x18144, | |
1870 | .halt_check = BRANCH_HALT_VOTED, | |
1871 | .clkr = { | |
1872 | .enable_reg = 0x5200c, | |
1873 | .enable_mask = BIT(23), | |
1874 | .hw.init = &(struct clk_init_data){ | |
1875 | .name = "gcc_qupv3_wrap1_s1_clk", | |
1876 | .parent_hws = (const struct clk_hw*[]){ | |
1877 | &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, | |
1878 | }, | |
1879 | .num_parents = 1, | |
1880 | .flags = CLK_SET_RATE_PARENT, | |
1881 | .ops = &clk_branch2_ops, | |
1882 | }, | |
1883 | }, | |
1884 | }; | |
1885 | ||
1886 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { | |
1887 | .halt_reg = 0x18274, | |
1888 | .halt_check = BRANCH_HALT_VOTED, | |
1889 | .clkr = { | |
1890 | .enable_reg = 0x5200c, | |
1891 | .enable_mask = BIT(24), | |
1892 | .hw.init = &(struct clk_init_data){ | |
1893 | .name = "gcc_qupv3_wrap1_s2_clk", | |
1894 | .parent_hws = (const struct clk_hw*[]){ | |
1895 | &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, | |
1896 | }, | |
1897 | .num_parents = 1, | |
1898 | .flags = CLK_SET_RATE_PARENT, | |
1899 | .ops = &clk_branch2_ops, | |
1900 | }, | |
1901 | }, | |
1902 | }; | |
1903 | ||
1904 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { | |
1905 | .halt_reg = 0x183a4, | |
1906 | .halt_check = BRANCH_HALT_VOTED, | |
1907 | .clkr = { | |
1908 | .enable_reg = 0x5200c, | |
1909 | .enable_mask = BIT(25), | |
1910 | .hw.init = &(struct clk_init_data){ | |
1911 | .name = "gcc_qupv3_wrap1_s3_clk", | |
1912 | .parent_hws = (const struct clk_hw*[]){ | |
1913 | &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, | |
1914 | }, | |
1915 | .num_parents = 1, | |
1916 | .flags = CLK_SET_RATE_PARENT, | |
1917 | .ops = &clk_branch2_ops, | |
1918 | }, | |
1919 | }, | |
1920 | }; | |
1921 | ||
1922 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { | |
1923 | .halt_reg = 0x184d4, | |
1924 | .halt_check = BRANCH_HALT_VOTED, | |
1925 | .clkr = { | |
1926 | .enable_reg = 0x5200c, | |
1927 | .enable_mask = BIT(26), | |
1928 | .hw.init = &(struct clk_init_data){ | |
1929 | .name = "gcc_qupv3_wrap1_s4_clk", | |
1930 | .parent_hws = (const struct clk_hw*[]){ | |
1931 | &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, | |
1932 | }, | |
1933 | .num_parents = 1, | |
1934 | .flags = CLK_SET_RATE_PARENT, | |
1935 | .ops = &clk_branch2_ops, | |
1936 | }, | |
1937 | }, | |
1938 | }; | |
1939 | ||
1940 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { | |
1941 | .halt_reg = 0x18604, | |
1942 | .halt_check = BRANCH_HALT_VOTED, | |
1943 | .clkr = { | |
1944 | .enable_reg = 0x5200c, | |
1945 | .enable_mask = BIT(27), | |
1946 | .hw.init = &(struct clk_init_data){ | |
1947 | .name = "gcc_qupv3_wrap1_s5_clk", | |
1948 | .parent_hws = (const struct clk_hw*[]){ | |
1949 | &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, | |
1950 | }, | |
1951 | .num_parents = 1, | |
1952 | .flags = CLK_SET_RATE_PARENT, | |
1953 | .ops = &clk_branch2_ops, | |
1954 | }, | |
1955 | }, | |
1956 | }; | |
1957 | ||
1958 | static struct clk_branch gcc_qupv3_wrap1_s6_clk = { | |
1959 | .halt_reg = 0x18734, | |
1960 | .halt_check = BRANCH_HALT_VOTED, | |
1961 | .clkr = { | |
1962 | .enable_reg = 0x5200c, | |
1963 | .enable_mask = BIT(28), | |
1964 | .hw.init = &(struct clk_init_data){ | |
1965 | .name = "gcc_qupv3_wrap1_s6_clk", | |
1966 | .parent_hws = (const struct clk_hw*[]){ | |
1967 | &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, | |
1968 | }, | |
1969 | .num_parents = 1, | |
1970 | .flags = CLK_SET_RATE_PARENT, | |
1971 | .ops = &clk_branch2_ops, | |
1972 | }, | |
1973 | }, | |
1974 | }; | |
1975 | ||
1976 | static struct clk_branch gcc_qupv3_wrap1_s7_clk = { | |
1977 | .halt_reg = 0x18864, | |
1978 | .halt_check = BRANCH_HALT_VOTED, | |
1979 | .clkr = { | |
1980 | .enable_reg = 0x5200c, | |
1981 | .enable_mask = BIT(29), | |
1982 | .hw.init = &(struct clk_init_data){ | |
1983 | .name = "gcc_qupv3_wrap1_s7_clk", | |
1984 | .parent_hws = (const struct clk_hw*[]){ | |
1985 | &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, | |
1986 | }, | |
1987 | .num_parents = 1, | |
1988 | .flags = CLK_SET_RATE_PARENT, | |
1989 | .ops = &clk_branch2_ops, | |
1990 | }, | |
1991 | }, | |
1992 | }; | |
1993 | ||
1994 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { | |
1995 | .halt_reg = 0x17004, | |
1996 | .halt_check = BRANCH_HALT_VOTED, | |
1997 | .clkr = { | |
1998 | .enable_reg = 0x5200c, | |
1999 | .enable_mask = BIT(6), | |
2000 | .hw.init = &(struct clk_init_data){ | |
2001 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", | |
2002 | .ops = &clk_branch2_ops, | |
2003 | }, | |
2004 | }, | |
2005 | }; | |
2006 | ||
2007 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { | |
2008 | .halt_reg = 0x17008, | |
2009 | .halt_check = BRANCH_HALT_VOTED, | |
2010 | .hwcg_reg = 0x17008, | |
2011 | .hwcg_bit = 1, | |
2012 | .clkr = { | |
2013 | .enable_reg = 0x5200c, | |
2014 | .enable_mask = BIT(7), | |
2015 | .hw.init = &(struct clk_init_data){ | |
2016 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", | |
2017 | .ops = &clk_branch2_ops, | |
2018 | }, | |
2019 | }, | |
2020 | }; | |
2021 | ||
2022 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { | |
2023 | .halt_reg = 0x1800c, | |
2024 | .halt_check = BRANCH_HALT_VOTED, | |
2025 | .clkr = { | |
2026 | .enable_reg = 0x5200c, | |
2027 | .enable_mask = BIT(20), | |
2028 | .hw.init = &(struct clk_init_data){ | |
2029 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", | |
2030 | .ops = &clk_branch2_ops, | |
2031 | }, | |
2032 | }, | |
2033 | }; | |
2034 | ||
2035 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { | |
2036 | .halt_reg = 0x18010, | |
2037 | .halt_check = BRANCH_HALT_VOTED, | |
2038 | .hwcg_reg = 0x18010, | |
2039 | .hwcg_bit = 1, | |
2040 | .clkr = { | |
2041 | .enable_reg = 0x5200c, | |
2042 | .enable_mask = BIT(21), | |
2043 | .hw.init = &(struct clk_init_data){ | |
2044 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", | |
2045 | .ops = &clk_branch2_ops, | |
2046 | }, | |
2047 | }, | |
2048 | }; | |
2049 | ||
2050 | static struct clk_branch gcc_sdcc1_ahb_clk = { | |
2051 | .halt_reg = 0x12008, | |
2052 | .halt_check = BRANCH_HALT, | |
2053 | .clkr = { | |
2054 | .enable_reg = 0x12008, | |
2055 | .enable_mask = BIT(0), | |
2056 | .hw.init = &(struct clk_init_data){ | |
2057 | .name = "gcc_sdcc1_ahb_clk", | |
2058 | .ops = &clk_branch2_ops, | |
2059 | }, | |
2060 | }, | |
2061 | }; | |
2062 | ||
2063 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
2064 | .halt_reg = 0x1200c, | |
2065 | .halt_check = BRANCH_HALT, | |
2066 | .clkr = { | |
2067 | .enable_reg = 0x1200c, | |
2068 | .enable_mask = BIT(0), | |
2069 | .hw.init = &(struct clk_init_data){ | |
2070 | .name = "gcc_sdcc1_apps_clk", | |
2071 | .parent_hws = (const struct clk_hw*[]){ | |
2072 | &gcc_sdcc1_apps_clk_src.clkr.hw, | |
2073 | }, | |
2074 | .num_parents = 1, | |
2075 | .flags = CLK_SET_RATE_PARENT, | |
2076 | .ops = &clk_branch2_ops, | |
2077 | }, | |
2078 | }, | |
2079 | }; | |
2080 | ||
2081 | static struct clk_branch gcc_sdcc1_ice_core_clk = { | |
2082 | .halt_reg = 0x12040, | |
2083 | .halt_check = BRANCH_HALT, | |
2084 | .clkr = { | |
2085 | .enable_reg = 0x12040, | |
2086 | .enable_mask = BIT(0), | |
2087 | .hw.init = &(struct clk_init_data){ | |
2088 | .name = "gcc_sdcc1_ice_core_clk", | |
2089 | .parent_hws = (const struct clk_hw*[]){ | |
2090 | &gcc_sdcc1_ice_core_clk_src.clkr.hw, | |
2091 | }, | |
2092 | .num_parents = 1, | |
2093 | .flags = CLK_SET_RATE_PARENT, | |
2094 | .ops = &clk_branch2_ops, | |
2095 | }, | |
2096 | }, | |
2097 | }; | |
2098 | ||
2099 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
2100 | .halt_reg = 0x14008, | |
2101 | .halt_check = BRANCH_HALT, | |
2102 | .clkr = { | |
2103 | .enable_reg = 0x14008, | |
2104 | .enable_mask = BIT(0), | |
2105 | .hw.init = &(struct clk_init_data){ | |
2106 | .name = "gcc_sdcc2_ahb_clk", | |
2107 | .ops = &clk_branch2_ops, | |
2108 | }, | |
2109 | }, | |
2110 | }; | |
2111 | ||
2112 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2113 | .halt_reg = 0x14004, | |
2114 | .halt_check = BRANCH_HALT, | |
2115 | .clkr = { | |
2116 | .enable_reg = 0x14004, | |
2117 | .enable_mask = BIT(0), | |
2118 | .hw.init = &(struct clk_init_data){ | |
2119 | .name = "gcc_sdcc2_apps_clk", | |
2120 | .parent_hws = (const struct clk_hw*[]){ | |
2121 | &gcc_sdcc2_apps_clk_src.clkr.hw, | |
2122 | }, | |
2123 | .num_parents = 1, | |
2124 | .flags = CLK_SET_RATE_PARENT, | |
2125 | .ops = &clk_branch2_ops, | |
2126 | }, | |
2127 | }, | |
2128 | }; | |
2129 | ||
2130 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2131 | .halt_reg = 0x16008, | |
2132 | .halt_check = BRANCH_HALT, | |
2133 | .clkr = { | |
2134 | .enable_reg = 0x16008, | |
2135 | .enable_mask = BIT(0), | |
2136 | .hw.init = &(struct clk_init_data){ | |
2137 | .name = "gcc_sdcc4_ahb_clk", | |
2138 | .ops = &clk_branch2_ops, | |
2139 | }, | |
2140 | }, | |
2141 | }; | |
2142 | ||
2143 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2144 | .halt_reg = 0x16004, | |
2145 | .halt_check = BRANCH_HALT, | |
2146 | .clkr = { | |
2147 | .enable_reg = 0x16004, | |
2148 | .enable_mask = BIT(0), | |
2149 | .hw.init = &(struct clk_init_data){ | |
2150 | .name = "gcc_sdcc4_apps_clk", | |
2151 | .parent_hws = (const struct clk_hw*[]){ | |
2152 | &gcc_sdcc4_apps_clk_src.clkr.hw, | |
2153 | }, | |
2154 | .num_parents = 1, | |
2155 | .flags = CLK_SET_RATE_PARENT, | |
2156 | .ops = &clk_branch2_ops, | |
2157 | }, | |
2158 | }, | |
2159 | }; | |
2160 | ||
2161 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { | |
2162 | .halt_reg = 0x4144, | |
2163 | .halt_check = BRANCH_HALT_VOTED, | |
2164 | .clkr = { | |
2165 | .enable_reg = 0x52004, | |
2166 | .enable_mask = BIT(0), | |
2167 | .hw.init = &(struct clk_init_data){ | |
2168 | .name = "gcc_sys_noc_cpuss_ahb_clk", | |
2169 | .parent_hws = (const struct clk_hw*[]){ | |
2170 | &gcc_cpuss_ahb_clk_src.clkr.hw, | |
2171 | }, | |
2172 | .num_parents = 1, | |
2173 | .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, | |
2174 | .ops = &clk_branch2_ops, | |
2175 | }, | |
2176 | }, | |
2177 | }; | |
2178 | ||
2179 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2180 | .halt_reg = 0x36004, | |
2181 | .halt_check = BRANCH_HALT, | |
2182 | .clkr = { | |
2183 | .enable_reg = 0x36004, | |
2184 | .enable_mask = BIT(0), | |
2185 | .hw.init = &(struct clk_init_data){ | |
2186 | .name = "gcc_tsif_ahb_clk", | |
2187 | .ops = &clk_branch2_ops, | |
2188 | }, | |
2189 | }, | |
2190 | }; | |
2191 | ||
2192 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { | |
2193 | .halt_reg = 0x3600c, | |
2194 | .halt_check = BRANCH_HALT, | |
2195 | .clkr = { | |
2196 | .enable_reg = 0x3600c, | |
2197 | .enable_mask = BIT(0), | |
2198 | .hw.init = &(struct clk_init_data){ | |
2199 | .name = "gcc_tsif_inactivity_timers_clk", | |
2200 | .ops = &clk_branch2_ops, | |
2201 | }, | |
2202 | }, | |
2203 | }; | |
2204 | ||
2205 | static struct clk_branch gcc_tsif_ref_clk = { | |
2206 | .halt_reg = 0x36008, | |
2207 | .halt_check = BRANCH_HALT, | |
2208 | .clkr = { | |
2209 | .enable_reg = 0x36008, | |
2210 | .enable_mask = BIT(0), | |
2211 | .hw.init = &(struct clk_init_data){ | |
2212 | .name = "gcc_tsif_ref_clk", | |
2213 | .parent_hws = (const struct clk_hw*[]){ | |
2214 | &gcc_tsif_ref_clk_src.clkr.hw, | |
2215 | }, | |
2216 | .num_parents = 1, | |
2217 | .flags = CLK_SET_RATE_PARENT, | |
2218 | .ops = &clk_branch2_ops, | |
2219 | }, | |
2220 | }, | |
2221 | }; | |
2222 | ||
2223 | static struct clk_branch gcc_ufs_mem_clkref_clk = { | |
2224 | .halt_reg = 0x8c000, | |
2225 | .halt_check = BRANCH_HALT, | |
2226 | .clkr = { | |
2227 | .enable_reg = 0x8c000, | |
2228 | .enable_mask = BIT(0), | |
2229 | .hw.init = &(struct clk_init_data){ | |
2230 | .name = "gcc_ufs_mem_clkref_clk", | |
2231 | .ops = &clk_branch2_ops, | |
2232 | }, | |
2233 | }, | |
2234 | }; | |
2235 | ||
2236 | static struct clk_branch gcc_ufs_phy_ahb_clk = { | |
2237 | .halt_reg = 0x77014, | |
2238 | .halt_check = BRANCH_HALT, | |
2239 | .hwcg_reg = 0x77014, | |
2240 | .hwcg_bit = 1, | |
2241 | .clkr = { | |
2242 | .enable_reg = 0x77014, | |
2243 | .enable_mask = BIT(0), | |
2244 | .hw.init = &(struct clk_init_data){ | |
2245 | .name = "gcc_ufs_phy_ahb_clk", | |
2246 | .ops = &clk_branch2_ops, | |
2247 | }, | |
2248 | }, | |
2249 | }; | |
2250 | ||
2251 | static struct clk_branch gcc_ufs_phy_axi_clk = { | |
2252 | .halt_reg = 0x77038, | |
2253 | .halt_check = BRANCH_HALT, | |
2254 | .hwcg_reg = 0x77038, | |
2255 | .hwcg_bit = 1, | |
2256 | .clkr = { | |
2257 | .enable_reg = 0x77038, | |
2258 | .enable_mask = BIT(0), | |
2259 | .hw.init = &(struct clk_init_data){ | |
2260 | .name = "gcc_ufs_phy_axi_clk", | |
2261 | .parent_hws = (const struct clk_hw*[]){ | |
2262 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
2263 | }, | |
2264 | .num_parents = 1, | |
2265 | .flags = CLK_SET_RATE_PARENT, | |
2266 | .ops = &clk_branch2_ops, | |
2267 | }, | |
2268 | }, | |
2269 | }; | |
2270 | ||
2271 | static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { | |
2272 | .halt_reg = 0x77038, | |
2273 | .halt_check = BRANCH_HALT, | |
2274 | .hwcg_reg = 0x77038, | |
2275 | .hwcg_bit = 1, | |
2276 | .clkr = { | |
2277 | .enable_reg = 0x77038, | |
2278 | .enable_mask = BIT(1), | |
2279 | .hw.init = &(struct clk_init_data){ | |
2280 | .name = "gcc_ufs_phy_axi_hw_ctl_clk", | |
2281 | .parent_hws = (const struct clk_hw*[]){ | |
2282 | &gcc_ufs_phy_axi_clk.clkr.hw, | |
2283 | }, | |
2284 | .num_parents = 1, | |
2285 | .flags = CLK_SET_RATE_PARENT, | |
2286 | .ops = &clk_branch_simple_ops, | |
2287 | }, | |
2288 | }, | |
2289 | }; | |
2290 | ||
2291 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { | |
2292 | .halt_reg = 0x77090, | |
2293 | .halt_check = BRANCH_HALT, | |
2294 | .hwcg_reg = 0x77090, | |
2295 | .hwcg_bit = 1, | |
2296 | .clkr = { | |
2297 | .enable_reg = 0x77090, | |
2298 | .enable_mask = BIT(0), | |
2299 | .hw.init = &(struct clk_init_data){ | |
2300 | .name = "gcc_ufs_phy_ice_core_clk", | |
2301 | .parent_hws = (const struct clk_hw*[]){ | |
2302 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw, | |
2303 | }, | |
2304 | .num_parents = 1, | |
2305 | .flags = CLK_SET_RATE_PARENT, | |
2306 | .ops = &clk_branch2_ops, | |
2307 | }, | |
2308 | }, | |
2309 | }; | |
2310 | ||
2311 | static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { | |
2312 | .halt_reg = 0x77090, | |
2313 | .halt_check = BRANCH_HALT, | |
2314 | .hwcg_reg = 0x77090, | |
2315 | .hwcg_bit = 1, | |
2316 | .clkr = { | |
2317 | .enable_reg = 0x77090, | |
2318 | .enable_mask = BIT(1), | |
2319 | .hw.init = &(struct clk_init_data){ | |
2320 | .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", | |
2321 | .parent_hws = (const struct clk_hw*[]){ | |
2322 | &gcc_ufs_phy_ice_core_clk.clkr.hw, | |
2323 | }, | |
2324 | .num_parents = 1, | |
2325 | .flags = CLK_SET_RATE_PARENT, | |
2326 | .ops = &clk_branch_simple_ops, | |
2327 | }, | |
2328 | }, | |
2329 | }; | |
2330 | ||
2331 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { | |
2332 | .halt_reg = 0x77094, | |
2333 | .halt_check = BRANCH_HALT, | |
2334 | .hwcg_reg = 0x77094, | |
2335 | .hwcg_bit = 1, | |
2336 | .clkr = { | |
2337 | .enable_reg = 0x77094, | |
2338 | .enable_mask = BIT(0), | |
2339 | .hw.init = &(struct clk_init_data){ | |
2340 | .name = "gcc_ufs_phy_phy_aux_clk", | |
2341 | .parent_hws = (const struct clk_hw*[]){ | |
2342 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, | |
2343 | }, | |
2344 | .num_parents = 1, | |
2345 | .flags = CLK_SET_RATE_PARENT, | |
2346 | .ops = &clk_branch2_ops, | |
2347 | }, | |
2348 | }, | |
2349 | }; | |
2350 | ||
2351 | static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { | |
2352 | .halt_reg = 0x77094, | |
2353 | .halt_check = BRANCH_HALT, | |
2354 | .hwcg_reg = 0x77094, | |
2355 | .hwcg_bit = 1, | |
2356 | .clkr = { | |
2357 | .enable_reg = 0x77094, | |
2358 | .enable_mask = BIT(1), | |
2359 | .hw.init = &(struct clk_init_data){ | |
2360 | .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", | |
2361 | .parent_hws = (const struct clk_hw*[]){ | |
2362 | &gcc_ufs_phy_phy_aux_clk.clkr.hw, | |
2363 | }, | |
2364 | .num_parents = 1, | |
2365 | .flags = CLK_SET_RATE_PARENT, | |
2366 | .ops = &clk_branch_simple_ops, | |
2367 | }, | |
2368 | }, | |
2369 | }; | |
2370 | ||
2371 | static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { | |
2372 | .halt_reg = 0x7701c, | |
2373 | .halt_check = BRANCH_HALT_SKIP, | |
2374 | .clkr = { | |
2375 | .enable_reg = 0x7701c, | |
2376 | .enable_mask = BIT(0), | |
2377 | .hw.init = &(struct clk_init_data){ | |
2378 | .name = "gcc_ufs_phy_rx_symbol_0_clk", | |
2379 | .ops = &clk_branch2_ops, | |
2380 | }, | |
2381 | }, | |
2382 | }; | |
2383 | ||
2384 | static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { | |
2385 | .halt_reg = 0x77018, | |
2386 | .halt_check = BRANCH_HALT_SKIP, | |
2387 | .clkr = { | |
2388 | .enable_reg = 0x77018, | |
2389 | .enable_mask = BIT(0), | |
2390 | .hw.init = &(struct clk_init_data){ | |
2391 | .name = "gcc_ufs_phy_tx_symbol_0_clk", | |
2392 | .ops = &clk_branch2_ops, | |
2393 | }, | |
2394 | }, | |
2395 | }; | |
2396 | ||
2397 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { | |
2398 | .halt_reg = 0x7708c, | |
2399 | .halt_check = BRANCH_HALT, | |
2400 | .hwcg_reg = 0x7708c, | |
2401 | .hwcg_bit = 1, | |
2402 | .clkr = { | |
2403 | .enable_reg = 0x7708c, | |
2404 | .enable_mask = BIT(0), | |
2405 | .hw.init = &(struct clk_init_data){ | |
2406 | .name = "gcc_ufs_phy_unipro_core_clk", | |
2407 | .parent_hws = (const struct clk_hw*[]){ | |
2408 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, | |
2409 | }, | |
2410 | .num_parents = 1, | |
2411 | .flags = CLK_SET_RATE_PARENT, | |
2412 | .ops = &clk_branch2_ops, | |
2413 | }, | |
2414 | }, | |
2415 | }; | |
2416 | ||
2417 | static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { | |
2418 | .halt_reg = 0x7708c, | |
2419 | .halt_check = BRANCH_HALT, | |
2420 | .hwcg_reg = 0x7708c, | |
2421 | .hwcg_bit = 1, | |
2422 | .clkr = { | |
2423 | .enable_reg = 0x7708c, | |
2424 | .enable_mask = BIT(1), | |
2425 | .hw.init = &(struct clk_init_data){ | |
2426 | .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", | |
2427 | .parent_hws = (const struct clk_hw*[]){ | |
2428 | &gcc_ufs_phy_unipro_core_clk.clkr.hw, | |
2429 | }, | |
2430 | .num_parents = 1, | |
2431 | .flags = CLK_SET_RATE_PARENT, | |
2432 | .ops = &clk_branch_simple_ops, | |
2433 | }, | |
2434 | }, | |
2435 | }; | |
2436 | ||
2437 | static struct clk_branch gcc_usb30_prim_master_clk = { | |
2438 | .halt_reg = 0xf010, | |
2439 | .halt_check = BRANCH_HALT, | |
2440 | .clkr = { | |
2441 | .enable_reg = 0xf010, | |
2442 | .enable_mask = BIT(0), | |
2443 | .hw.init = &(struct clk_init_data){ | |
2444 | .name = "gcc_usb30_prim_master_clk", | |
2445 | .parent_hws = (const struct clk_hw*[]){ | |
2446 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
2447 | }, | |
2448 | .num_parents = 1, | |
2449 | .flags = CLK_SET_RATE_PARENT, | |
2450 | .ops = &clk_branch2_ops, | |
2451 | }, | |
2452 | }, | |
2453 | }; | |
2454 | ||
2455 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { | |
2456 | .halt_reg = 0xf018, | |
2457 | .halt_check = BRANCH_HALT, | |
2458 | .clkr = { | |
2459 | .enable_reg = 0xf018, | |
2460 | .enable_mask = BIT(0), | |
2461 | .hw.init = &(struct clk_init_data){ | |
2462 | .name = "gcc_usb30_prim_mock_utmi_clk", | |
2463 | .parent_hws = (const struct clk_hw*[]){ | |
2464 | &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, | |
2465 | }, | |
2466 | .num_parents = 1, | |
2467 | .flags = CLK_SET_RATE_PARENT, | |
2468 | .ops = &clk_branch2_ops, | |
2469 | }, | |
2470 | }, | |
2471 | }; | |
2472 | ||
2473 | static struct clk_branch gcc_usb30_prim_sleep_clk = { | |
2474 | .halt_reg = 0xf014, | |
2475 | .halt_check = BRANCH_HALT, | |
2476 | .clkr = { | |
2477 | .enable_reg = 0xf014, | |
2478 | .enable_mask = BIT(0), | |
2479 | .hw.init = &(struct clk_init_data){ | |
2480 | .name = "gcc_usb30_prim_sleep_clk", | |
2481 | .ops = &clk_branch2_ops, | |
2482 | }, | |
2483 | }, | |
2484 | }; | |
2485 | ||
2486 | static struct clk_branch gcc_usb3_prim_clkref_clk = { | |
2487 | .halt_reg = 0x8c010, | |
2488 | .halt_check = BRANCH_HALT, | |
2489 | .clkr = { | |
2490 | .enable_reg = 0x8c010, | |
2491 | .enable_mask = BIT(0), | |
2492 | .hw.init = &(struct clk_init_data){ | |
2493 | .name = "gcc_usb3_prim_clkref_clk", | |
2494 | .ops = &clk_branch2_ops, | |
2495 | }, | |
2496 | }, | |
2497 | }; | |
2498 | ||
2499 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { | |
2500 | .halt_reg = 0xf050, | |
2501 | .halt_check = BRANCH_HALT, | |
2502 | .clkr = { | |
2503 | .enable_reg = 0xf050, | |
2504 | .enable_mask = BIT(0), | |
2505 | .hw.init = &(struct clk_init_data){ | |
2506 | .name = "gcc_usb3_prim_phy_aux_clk", | |
2507 | .parent_hws = (const struct clk_hw*[]){ | |
2508 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
2509 | }, | |
2510 | .num_parents = 1, | |
2511 | .flags = CLK_SET_RATE_PARENT, | |
2512 | .ops = &clk_branch2_ops, | |
2513 | }, | |
2514 | }, | |
2515 | }; | |
2516 | ||
2517 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { | |
2518 | .halt_reg = 0xf054, | |
2519 | .halt_check = BRANCH_HALT, | |
2520 | .clkr = { | |
2521 | .enable_reg = 0xf054, | |
2522 | .enable_mask = BIT(0), | |
2523 | .hw.init = &(struct clk_init_data){ | |
2524 | .name = "gcc_usb3_prim_phy_com_aux_clk", | |
2525 | .parent_hws = (const struct clk_hw*[]){ | |
2526 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
2527 | }, | |
2528 | .num_parents = 1, | |
2529 | .flags = CLK_SET_RATE_PARENT, | |
2530 | .ops = &clk_branch2_ops, | |
2531 | }, | |
2532 | }, | |
2533 | }; | |
2534 | ||
2535 | static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { | |
2536 | .halt_check = BRANCH_HALT_SKIP, | |
2537 | .clkr = { | |
2538 | .enable_reg = 0xf058, | |
2539 | .enable_mask = BIT(0), | |
2540 | .hw.init = &(struct clk_init_data){ | |
2541 | .name = "gcc_usb3_prim_phy_pipe_clk", | |
2542 | .ops = &clk_branch2_ops, | |
2543 | }, | |
2544 | }, | |
2545 | }; | |
2546 | ||
2547 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { | |
2548 | .halt_reg = 0x6a004, | |
2549 | .halt_check = BRANCH_HALT, | |
2550 | .hwcg_reg = 0x6a004, | |
2551 | .hwcg_bit = 1, | |
2552 | .clkr = { | |
2553 | .enable_reg = 0x6a004, | |
2554 | .enable_mask = BIT(0), | |
2555 | .hw.init = &(struct clk_init_data){ | |
2556 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", | |
2557 | .ops = &clk_branch2_ops, | |
2558 | }, | |
2559 | }, | |
2560 | }; | |
2561 | ||
2562 | static struct clk_branch gcc_vdda_vs_clk = { | |
2563 | .halt_reg = 0x7a00c, | |
2564 | .halt_check = BRANCH_HALT, | |
2565 | .clkr = { | |
2566 | .enable_reg = 0x7a00c, | |
2567 | .enable_mask = BIT(0), | |
2568 | .hw.init = &(struct clk_init_data){ | |
2569 | .name = "gcc_vdda_vs_clk", | |
2570 | .parent_hws = (const struct clk_hw*[]){ | |
2571 | &gcc_vsensor_clk_src.clkr.hw, | |
2572 | }, | |
2573 | .num_parents = 1, | |
2574 | .flags = CLK_SET_RATE_PARENT, | |
2575 | .ops = &clk_branch2_ops, | |
2576 | }, | |
2577 | }, | |
2578 | }; | |
2579 | ||
2580 | static struct clk_branch gcc_vddcx_vs_clk = { | |
2581 | .halt_reg = 0x7a004, | |
2582 | .halt_check = BRANCH_HALT, | |
2583 | .clkr = { | |
2584 | .enable_reg = 0x7a004, | |
2585 | .enable_mask = BIT(0), | |
2586 | .hw.init = &(struct clk_init_data){ | |
2587 | .name = "gcc_vddcx_vs_clk", | |
2588 | .parent_hws = (const struct clk_hw*[]){ | |
2589 | &gcc_vsensor_clk_src.clkr.hw, | |
2590 | }, | |
2591 | .num_parents = 1, | |
2592 | .flags = CLK_SET_RATE_PARENT, | |
2593 | .ops = &clk_branch2_ops, | |
2594 | }, | |
2595 | }, | |
2596 | }; | |
2597 | ||
2598 | static struct clk_branch gcc_vddmx_vs_clk = { | |
2599 | .halt_reg = 0x7a008, | |
2600 | .halt_check = BRANCH_HALT, | |
2601 | .clkr = { | |
2602 | .enable_reg = 0x7a008, | |
2603 | .enable_mask = BIT(0), | |
2604 | .hw.init = &(struct clk_init_data){ | |
2605 | .name = "gcc_vddmx_vs_clk", | |
2606 | .parent_hws = (const struct clk_hw*[]){ | |
2607 | &gcc_vsensor_clk_src.clkr.hw, | |
2608 | }, | |
2609 | .num_parents = 1, | |
2610 | .flags = CLK_SET_RATE_PARENT, | |
2611 | .ops = &clk_branch2_ops, | |
2612 | }, | |
2613 | }, | |
2614 | }; | |
2615 | ||
2616 | ||
2617 | static struct clk_branch gcc_video_axi_clk = { | |
2618 | .halt_reg = 0xb01c, | |
2619 | .halt_check = BRANCH_HALT, | |
2620 | .clkr = { | |
2621 | .enable_reg = 0xb01c, | |
2622 | .enable_mask = BIT(0), | |
2623 | .hw.init = &(struct clk_init_data){ | |
2624 | .name = "gcc_video_axi_clk", | |
2625 | .ops = &clk_branch2_ops, | |
2626 | }, | |
2627 | }, | |
2628 | }; | |
2629 | ||
2630 | static struct clk_branch gcc_vs_ctrl_ahb_clk = { | |
2631 | .halt_reg = 0x7a014, | |
2632 | .halt_check = BRANCH_HALT, | |
2633 | .hwcg_reg = 0x7a014, | |
2634 | .hwcg_bit = 1, | |
2635 | .clkr = { | |
2636 | .enable_reg = 0x7a014, | |
2637 | .enable_mask = BIT(0), | |
2638 | .hw.init = &(struct clk_init_data){ | |
2639 | .name = "gcc_vs_ctrl_ahb_clk", | |
2640 | .ops = &clk_branch2_ops, | |
2641 | }, | |
2642 | }, | |
2643 | }; | |
2644 | ||
2645 | static struct clk_branch gcc_vs_ctrl_clk = { | |
2646 | .halt_reg = 0x7a010, | |
2647 | .halt_check = BRANCH_HALT, | |
2648 | .clkr = { | |
2649 | .enable_reg = 0x7a010, | |
2650 | .enable_mask = BIT(0), | |
2651 | .hw.init = &(struct clk_init_data){ | |
2652 | .name = "gcc_vs_ctrl_clk", | |
2653 | .parent_hws = (const struct clk_hw*[]){ | |
2654 | &gcc_vs_ctrl_clk_src.clkr.hw, | |
2655 | }, | |
2656 | .num_parents = 1, | |
2657 | .flags = CLK_SET_RATE_PARENT, | |
2658 | .ops = &clk_branch2_ops, | |
2659 | }, | |
2660 | }, | |
2661 | }; | |
2662 | ||
2663 | static struct gdsc pcie_0_gdsc = { | |
2664 | .gdscr = 0x6b004, | |
2665 | .pd = { | |
2666 | .name = "pcie_0_gdsc", | |
2667 | }, | |
2668 | .pwrsts = PWRSTS_OFF_ON, | |
2669 | }; | |
2670 | ||
2671 | static struct gdsc ufs_phy_gdsc = { | |
2672 | .gdscr = 0x77004, | |
2673 | .pd = { | |
2674 | .name = "ufs_phy_gdsc", | |
2675 | }, | |
2676 | .pwrsts = PWRSTS_OFF_ON, | |
2677 | }; | |
2678 | ||
2679 | static struct gdsc usb30_prim_gdsc = { | |
2680 | .gdscr = 0xf004, | |
2681 | .pd = { | |
2682 | .name = "usb30_prim_gdsc", | |
2683 | }, | |
2684 | .pwrsts = PWRSTS_OFF_ON, | |
2685 | }; | |
2686 | ||
2687 | static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { | |
2688 | .gdscr = 0x7d030, | |
2689 | .pd = { | |
2690 | .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", | |
2691 | }, | |
2692 | .pwrsts = PWRSTS_OFF_ON, | |
2693 | .flags = VOTABLE, | |
2694 | }; | |
2695 | ||
2696 | static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { | |
2697 | .gdscr = 0x7d03c, | |
2698 | .pd = { | |
2699 | .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", | |
2700 | }, | |
2701 | .pwrsts = PWRSTS_OFF_ON, | |
2702 | .flags = VOTABLE, | |
2703 | }; | |
2704 | ||
2705 | static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { | |
2706 | .gdscr = 0x7d034, | |
2707 | .pd = { | |
2708 | .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", | |
2709 | }, | |
2710 | .pwrsts = PWRSTS_OFF_ON, | |
2711 | .flags = VOTABLE, | |
2712 | }; | |
2713 | ||
2714 | static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { | |
2715 | .gdscr = 0x7d038, | |
2716 | .pd = { | |
2717 | .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", | |
2718 | }, | |
2719 | .pwrsts = PWRSTS_OFF_ON, | |
2720 | .flags = VOTABLE, | |
2721 | }; | |
2722 | ||
2723 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { | |
2724 | .gdscr = 0x7d040, | |
2725 | .pd = { | |
2726 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", | |
2727 | }, | |
2728 | .pwrsts = PWRSTS_OFF_ON, | |
2729 | .flags = VOTABLE, | |
2730 | }; | |
2731 | ||
2732 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { | |
2733 | .gdscr = 0x7d048, | |
2734 | .pd = { | |
2735 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", | |
2736 | }, | |
2737 | .pwrsts = PWRSTS_OFF_ON, | |
2738 | .flags = VOTABLE, | |
2739 | }; | |
2740 | ||
2741 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { | |
2742 | .gdscr = 0x7d044, | |
2743 | .pd = { | |
2744 | .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", | |
2745 | }, | |
2746 | .pwrsts = PWRSTS_OFF_ON, | |
2747 | .flags = VOTABLE, | |
2748 | }; | |
2749 | ||
2750 | static struct clk_hw *gcc_sm7150_hws[] = { | |
2751 | [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, | |
2752 | }; | |
2753 | ||
2754 | static struct clk_regmap *gcc_sm7150_clocks[] = { | |
2755 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, | |
2756 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, | |
2757 | [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = | |
2758 | &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, | |
2759 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, | |
2760 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, | |
2761 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
2762 | [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, | |
2763 | [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, | |
2764 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
2765 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
2766 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
2767 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
2768 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, | |
2769 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, | |
2770 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, | |
2771 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, | |
2772 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, | |
2773 | [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, | |
2774 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, | |
2775 | [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, | |
2776 | [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, | |
2777 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
2778 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
2779 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
2780 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
2781 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
2782 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
2783 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, | |
2784 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, | |
2785 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
2786 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
2787 | [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, | |
2788 | [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, | |
2789 | [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, | |
2790 | [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, | |
2791 | [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, | |
2792 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, | |
2793 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, | |
2794 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
2795 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, | |
2796 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
2797 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
2798 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
2799 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, | |
2800 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, | |
2801 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, | |
2802 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, | |
2803 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
2804 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
2805 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
2806 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
2807 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
2808 | [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, | |
2809 | [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, | |
2810 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
2811 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
2812 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
2813 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
2814 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
2815 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
2816 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
2817 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
2818 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
2819 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
2820 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
2821 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
2822 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, | |
2823 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, | |
2824 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, | |
2825 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, | |
2826 | [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, | |
2827 | [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, | |
2828 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
2829 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
2830 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
2831 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
2832 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
2833 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
2834 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
2835 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
2836 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
2837 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
2838 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
2839 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
2840 | [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, | |
2841 | [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, | |
2842 | [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, | |
2843 | [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, | |
2844 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
2845 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
2846 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
2847 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
2848 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, | |
2849 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
2850 | [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, | |
2851 | [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, | |
2852 | [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, | |
2853 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
2854 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
2855 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
2856 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
2857 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
2858 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, | |
2859 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, | |
2860 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
2861 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, | |
2862 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
2863 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, | |
2864 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, | |
2865 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
2866 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
2867 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
2868 | [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, | |
2869 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
2870 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
2871 | [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = | |
2872 | &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, | |
2873 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
2874 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
2875 | [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, | |
2876 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, | |
2877 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, | |
2878 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
2879 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = | |
2880 | &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
2881 | [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = | |
2882 | &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, | |
2883 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
2884 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
2885 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
2886 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = | |
2887 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
2888 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
2889 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, | |
2890 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, | |
2891 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
2892 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
2893 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, | |
2894 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, | |
2895 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, | |
2896 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, | |
2897 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, | |
2898 | [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, | |
2899 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, | |
2900 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, | |
2901 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, | |
2902 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, | |
2903 | [GPLL0] = &gpll0.clkr, | |
2904 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, | |
2905 | [GPLL6] = &gpll6.clkr, | |
2906 | [GPLL7] = &gpll7.clkr, | |
2907 | }; | |
2908 | ||
2909 | static const struct qcom_reset_map gcc_sm7150_resets[] = { | |
2910 | [GCC_PCIE_0_BCR] = { 0x6b000 }, | |
2911 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, | |
2912 | [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, | |
2913 | [GCC_UFS_PHY_BCR] = { 0x77000 }, | |
2914 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, | |
2915 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, | |
2916 | [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, | |
2917 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, | |
2918 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, | |
2919 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, | |
2920 | [GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 }, | |
2921 | }; | |
2922 | ||
2923 | static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = { | |
2924 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), | |
2925 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), | |
2926 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), | |
2927 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), | |
2928 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), | |
2929 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), | |
2930 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), | |
2931 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), | |
2932 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), | |
2933 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), | |
2934 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), | |
2935 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), | |
2936 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), | |
2937 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), | |
2938 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), | |
2939 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), | |
2940 | }; | |
2941 | ||
2942 | static struct gdsc *gcc_sm7150_gdscs[] = { | |
2943 | [PCIE_0_GDSC] = &pcie_0_gdsc, | |
2944 | [UFS_PHY_GDSC] = &ufs_phy_gdsc, | |
2945 | [USB30_PRIM_GDSC] = &usb30_prim_gdsc, | |
2946 | [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = | |
2947 | &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, | |
2948 | [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = | |
2949 | &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, | |
2950 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = | |
2951 | &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, | |
2952 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = | |
2953 | &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, | |
2954 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = | |
2955 | &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, | |
2956 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = | |
2957 | &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, | |
2958 | [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, | |
2959 | }; | |
2960 | ||
2961 | static const struct regmap_config gcc_sm7150_regmap_config = { | |
2962 | .reg_bits = 32, | |
2963 | .reg_stride = 4, | |
2964 | .val_bits = 32, | |
2965 | .max_register = 0x1820b0, | |
2966 | .fast_io = true, | |
2967 | }; | |
2968 | ||
2969 | static const struct qcom_cc_desc gcc_sm7150_desc = { | |
2970 | .config = &gcc_sm7150_regmap_config, | |
2971 | .clk_hws = gcc_sm7150_hws, | |
2972 | .num_clk_hws = ARRAY_SIZE(gcc_sm7150_hws), | |
2973 | .clks = gcc_sm7150_clocks, | |
2974 | .num_clks = ARRAY_SIZE(gcc_sm7150_clocks), | |
2975 | .resets = gcc_sm7150_resets, | |
2976 | .num_resets = ARRAY_SIZE(gcc_sm7150_resets), | |
2977 | .gdscs = gcc_sm7150_gdscs, | |
2978 | .num_gdscs = ARRAY_SIZE(gcc_sm7150_gdscs), | |
2979 | }; | |
2980 | ||
2981 | static const struct of_device_id gcc_sm7150_match_table[] = { | |
2982 | { .compatible = "qcom,sm7150-gcc" }, | |
2983 | { } | |
2984 | }; | |
2985 | MODULE_DEVICE_TABLE(of, gcc_sm7150_match_table); | |
2986 | ||
2987 | static int gcc_sm7150_probe(struct platform_device *pdev) | |
2988 | { | |
2989 | struct regmap *regmap; | |
2990 | int ret; | |
2991 | ||
2992 | regmap = qcom_cc_map(pdev, &gcc_sm7150_desc); | |
2993 | if (IS_ERR(regmap)) | |
2994 | return PTR_ERR(regmap); | |
2995 | ||
2996 | /* | |
2997 | * Disable the GPLL0 active input to MM blocks, NPU | |
2998 | * and GPU via MISC registers. | |
2999 | */ | |
3000 | regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); | |
3001 | regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); | |
3002 | regmap_update_bits(regmap, 0x71028, 0x3, 0x3); | |
3003 | ||
3004 | /* | |
3005 | * Keep the critical clocks always-ON | |
3006 | * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, | |
3007 | * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, | |
3008 | * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK | |
3009 | */ | |
3010 | regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); | |
3011 | regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); | |
3012 | regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); | |
3013 | regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); | |
3014 | regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); | |
3015 | regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); | |
3016 | regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); | |
3017 | regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); | |
3018 | ||
3019 | ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, | |
3020 | ARRAY_SIZE(gcc_sm7150_dfs_desc)); | |
3021 | if (ret) | |
3022 | return ret; | |
3023 | ||
3024 | return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap); | |
3025 | } | |
3026 | ||
3027 | static struct platform_driver gcc_sm7150_driver = { | |
3028 | .probe = gcc_sm7150_probe, | |
3029 | .driver = { | |
3030 | .name = "gcc-sm7150", | |
3031 | .of_match_table = gcc_sm7150_match_table, | |
3032 | }, | |
3033 | }; | |
3034 | ||
3035 | static int __init gcc_sm7150_init(void) | |
3036 | { | |
3037 | return platform_driver_register(&gcc_sm7150_driver); | |
3038 | } | |
3039 | subsys_initcall(gcc_sm7150_init); | |
3040 | ||
3041 | static void __exit gcc_sm7150_exit(void) | |
3042 | { | |
3043 | platform_driver_unregister(&gcc_sm7150_driver); | |
3044 | } | |
3045 | module_exit(gcc_sm7150_exit); | |
3046 | ||
3047 | MODULE_DESCRIPTION("Qualcomm SM7150 Global Clock Controller"); | |
3048 | MODULE_LICENSE("GPL"); |