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4b8d6ae5 KD |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/of_device.h> | |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/regmap.h> | |
14 | #include <linux/reset-controller.h> | |
15 | ||
16 | #include <dt-bindings/clock/qcom,gcc-sm6125.h> | |
17 | ||
18 | #include "clk-alpha-pll.h" | |
19 | #include "clk-branch.h" | |
20 | #include "clk-rcg.h" | |
21 | #include "clk-regmap.h" | |
22 | #include "common.h" | |
23 | #include "gdsc.h" | |
24 | #include "reset.h" | |
25 | ||
26 | enum { | |
27 | P_BI_TCXO, | |
28 | P_GPLL0_OUT_AUX2, | |
29 | P_GPLL0_OUT_EARLY, | |
30 | P_GPLL3_OUT_EARLY, | |
31 | P_GPLL4_OUT_MAIN, | |
32 | P_GPLL5_OUT_MAIN, | |
33 | P_GPLL6_OUT_EARLY, | |
34 | P_GPLL6_OUT_MAIN, | |
35 | P_GPLL7_OUT_MAIN, | |
36 | P_GPLL8_OUT_EARLY, | |
37 | P_GPLL8_OUT_MAIN, | |
38 | P_GPLL9_OUT_MAIN, | |
39 | P_SLEEP_CLK, | |
40 | }; | |
41 | ||
42 | static struct clk_alpha_pll gpll0_out_early = { | |
43 | .offset = 0x0, | |
44 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
45 | .clkr = { | |
46 | .enable_reg = 0x79000, | |
47 | .enable_mask = BIT(0), | |
48 | .hw.init = &(struct clk_init_data){ | |
49 | .name = "gpll0_out_early", | |
50 | .parent_data = &(const struct clk_parent_data){ | |
51 | .fw_name = "bi_tcxo", | |
52 | }, | |
53 | .num_parents = 1, | |
54 | .ops = &clk_alpha_pll_ops, | |
55 | }, | |
56 | }, | |
57 | }; | |
58 | ||
59 | static struct clk_fixed_factor gpll0_out_aux2 = { | |
60 | .mult = 1, | |
61 | .div = 2, | |
62 | .hw.init = &(struct clk_init_data){ | |
63 | .name = "gpll0_out_aux2", | |
64 | .parent_hws = (const struct clk_hw*[]){ | |
65 | &gpll0_out_early.clkr.hw, | |
66 | }, | |
67 | .num_parents = 1, | |
68 | .ops = &clk_fixed_factor_ops, | |
69 | }, | |
70 | }; | |
71 | ||
72 | static struct clk_fixed_factor gpll0_out_main = { | |
73 | .mult = 1, | |
74 | .div = 2, | |
75 | .hw.init = &(struct clk_init_data){ | |
76 | .name = "gpll0_out_main", | |
77 | .parent_hws = (const struct clk_hw*[]){ | |
78 | &gpll0_out_early.clkr.hw, | |
79 | }, | |
80 | .num_parents = 1, | |
81 | .ops = &clk_fixed_factor_ops, | |
82 | }, | |
83 | }; | |
84 | ||
85 | static struct clk_alpha_pll gpll3_out_early = { | |
86 | .offset = 0x3000, | |
87 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
88 | .clkr = { | |
89 | .enable_reg = 0x79000, | |
90 | .enable_mask = BIT(3), | |
91 | .hw.init = &(struct clk_init_data){ | |
92 | .name = "gpll3_out_early", | |
93 | .parent_data = &(const struct clk_parent_data){ | |
94 | .fw_name = "bi_tcxo", | |
95 | }, | |
96 | .num_parents = 1, | |
97 | .ops = &clk_alpha_pll_ops, | |
98 | }, | |
99 | }, | |
100 | }; | |
101 | ||
102 | static struct clk_alpha_pll gpll4_out_main = { | |
103 | .offset = 0x4000, | |
104 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
105 | .clkr = { | |
106 | .enable_reg = 0x79000, | |
107 | .enable_mask = BIT(4), | |
108 | .hw.init = &(struct clk_init_data){ | |
109 | .name = "gpll4_out_main", | |
110 | .parent_data = &(const struct clk_parent_data){ | |
111 | .fw_name = "bi_tcxo", | |
112 | }, | |
113 | .num_parents = 1, | |
114 | .ops = &clk_alpha_pll_ops, | |
115 | }, | |
116 | }, | |
117 | }; | |
118 | ||
119 | static struct clk_alpha_pll gpll5_out_main = { | |
120 | .offset = 0x5000, | |
121 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
122 | .clkr = { | |
123 | .enable_reg = 0x79000, | |
124 | .enable_mask = BIT(5), | |
125 | .hw.init = &(struct clk_init_data){ | |
126 | .name = "gpll5_out_main", | |
127 | .parent_data = &(const struct clk_parent_data){ | |
128 | .fw_name = "bi_tcxo", | |
129 | }, | |
130 | .num_parents = 1, | |
131 | .ops = &clk_alpha_pll_ops, | |
132 | }, | |
133 | }, | |
134 | }; | |
135 | ||
136 | static struct clk_alpha_pll gpll6_out_early = { | |
137 | .offset = 0x6000, | |
138 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
139 | .clkr = { | |
140 | .enable_reg = 0x79000, | |
141 | .enable_mask = BIT(6), | |
142 | .hw.init = &(struct clk_init_data){ | |
143 | .name = "gpll6_out_early", | |
144 | .parent_data = &(const struct clk_parent_data){ | |
145 | .fw_name = "bi_tcxo", | |
146 | }, | |
147 | .num_parents = 1, | |
148 | .ops = &clk_alpha_pll_ops, | |
149 | }, | |
150 | }, | |
151 | }; | |
152 | ||
153 | static struct clk_fixed_factor gpll6_out_main = { | |
154 | .mult = 1, | |
155 | .div = 2, | |
156 | .hw.init = &(struct clk_init_data){ | |
157 | .name = "gpll6_out_main", | |
158 | .parent_hws = (const struct clk_hw*[]){ | |
159 | &gpll6_out_early.clkr.hw, | |
160 | }, | |
161 | .num_parents = 1, | |
162 | .ops = &clk_fixed_factor_ops, | |
163 | }, | |
164 | }; | |
165 | ||
166 | static struct clk_alpha_pll gpll7_out_early = { | |
167 | .offset = 0x7000, | |
168 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
169 | .clkr = { | |
170 | .enable_reg = 0x79000, | |
171 | .enable_mask = BIT(7), | |
172 | .hw.init = &(struct clk_init_data){ | |
173 | .name = "gpll7_out_early", | |
174 | .parent_data = &(const struct clk_parent_data){ | |
175 | .fw_name = "bi_tcxo", | |
176 | }, | |
177 | .num_parents = 1, | |
178 | .ops = &clk_alpha_pll_ops, | |
179 | }, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct clk_fixed_factor gpll7_out_main = { | |
184 | .mult = 1, | |
185 | .div = 2, | |
186 | .hw.init = &(struct clk_init_data){ | |
187 | .name = "gpll7_out_main", | |
188 | .parent_hws = (const struct clk_hw*[]){ | |
189 | &gpll7_out_early.clkr.hw, | |
190 | }, | |
191 | .num_parents = 1, | |
192 | .ops = &clk_fixed_factor_ops, | |
193 | }, | |
194 | }; | |
195 | ||
196 | static struct clk_alpha_pll gpll8_out_early = { | |
197 | .offset = 0x8000, | |
198 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
199 | .clkr = { | |
200 | .enable_reg = 0x79000, | |
201 | .enable_mask = BIT(8), | |
202 | .hw.init = &(struct clk_init_data){ | |
203 | .name = "gpll8_out_early", | |
204 | .parent_data = &(const struct clk_parent_data){ | |
205 | .fw_name = "bi_tcxo", | |
206 | }, | |
207 | .num_parents = 1, | |
208 | .ops = &clk_alpha_pll_ops, | |
209 | }, | |
210 | }, | |
211 | }; | |
212 | ||
213 | static struct clk_fixed_factor gpll8_out_main = { | |
214 | .mult = 1, | |
215 | .div = 2, | |
216 | .hw.init = &(struct clk_init_data){ | |
217 | .name = "gpll8_out_main", | |
218 | .parent_hws = (const struct clk_hw*[]){ | |
219 | &gpll8_out_early.clkr.hw, | |
220 | }, | |
221 | .num_parents = 1, | |
222 | .ops = &clk_fixed_factor_ops, | |
223 | }, | |
224 | }; | |
225 | ||
226 | static struct clk_alpha_pll gpll9_out_early = { | |
227 | .offset = 0x9000, | |
228 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], | |
229 | .clkr = { | |
230 | .enable_reg = 0x79000, | |
231 | .enable_mask = BIT(9), | |
232 | .hw.init = &(struct clk_init_data){ | |
233 | .name = "gpll9_out_early", | |
234 | .parent_data = &(const struct clk_parent_data){ | |
235 | .fw_name = "bi_tcxo", | |
236 | }, | |
237 | .num_parents = 1, | |
238 | .ops = &clk_alpha_pll_ops, | |
239 | }, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct clk_fixed_factor gpll9_out_main = { | |
244 | .mult = 1, | |
245 | .div = 2, | |
246 | .hw.init = &(struct clk_init_data){ | |
247 | .name = "gpll9_out_main", | |
248 | .parent_hws = (const struct clk_hw*[]){ | |
249 | &gpll9_out_early.clkr.hw, | |
250 | }, | |
251 | .num_parents = 1, | |
252 | .ops = &clk_fixed_factor_ops, | |
253 | }, | |
254 | }; | |
255 | ||
256 | static const struct parent_map gcc_parent_map_0[] = { | |
257 | { P_BI_TCXO, 0 }, | |
258 | { P_GPLL0_OUT_EARLY, 1 }, | |
259 | { P_GPLL0_OUT_AUX2, 2 }, | |
260 | }; | |
261 | ||
262 | static const struct clk_parent_data gcc_parent_data_0[] = { | |
263 | { .fw_name = "bi_tcxo" }, | |
264 | { .hw = &gpll0_out_early.clkr.hw }, | |
265 | { .hw = &gpll0_out_aux2.hw }, | |
266 | }; | |
267 | ||
268 | static const struct parent_map gcc_parent_map_1[] = { | |
269 | { P_BI_TCXO, 0 }, | |
270 | { P_GPLL0_OUT_EARLY, 1 }, | |
271 | { P_GPLL0_OUT_AUX2, 2 }, | |
272 | { P_GPLL6_OUT_MAIN, 4 }, | |
273 | }; | |
274 | ||
275 | static const struct clk_parent_data gcc_parent_data_1[] = { | |
276 | { .fw_name = "bi_tcxo" }, | |
277 | { .hw = &gpll0_out_early.clkr.hw }, | |
278 | { .hw = &gpll0_out_aux2.hw }, | |
279 | { .hw = &gpll6_out_main.hw }, | |
280 | }; | |
281 | ||
282 | static const struct parent_map gcc_parent_map_2[] = { | |
283 | { P_BI_TCXO, 0 }, | |
284 | { P_GPLL0_OUT_EARLY, 1 }, | |
285 | { P_GPLL0_OUT_AUX2, 2 }, | |
286 | { P_SLEEP_CLK, 5 }, | |
287 | }; | |
288 | ||
289 | static const struct clk_parent_data gcc_parent_data_2[] = { | |
290 | { .fw_name = "bi_tcxo" }, | |
291 | { .hw = &gpll0_out_early.clkr.hw }, | |
292 | { .hw = &gpll0_out_aux2.hw }, | |
293 | { .fw_name = "sleep_clk" }, | |
294 | }; | |
295 | ||
296 | static const struct parent_map gcc_parent_map_3[] = { | |
297 | { P_BI_TCXO, 0 }, | |
298 | { P_GPLL0_OUT_EARLY, 1 }, | |
299 | { P_GPLL5_OUT_MAIN, 3 }, | |
300 | { P_GPLL4_OUT_MAIN, 5 }, | |
301 | }; | |
302 | ||
303 | static const struct clk_parent_data gcc_parent_data_3[] = { | |
304 | { .fw_name = "bi_tcxo" }, | |
305 | { .hw = &gpll0_out_early.clkr.hw }, | |
306 | { .hw = &gpll5_out_main.clkr.hw }, | |
307 | { .hw = &gpll4_out_main.clkr.hw }, | |
308 | }; | |
309 | ||
310 | static const struct parent_map gcc_parent_map_4[] = { | |
311 | { P_BI_TCXO, 0 }, | |
312 | { P_GPLL0_OUT_EARLY, 1 }, | |
313 | { P_GPLL9_OUT_MAIN, 2 }, | |
314 | }; | |
315 | ||
316 | static const struct clk_parent_data gcc_parent_data_4[] = { | |
317 | { .fw_name = "bi_tcxo" }, | |
318 | { .hw = &gpll0_out_early.clkr.hw }, | |
319 | { .hw = &gpll9_out_main.hw }, | |
320 | }; | |
321 | ||
322 | static const struct parent_map gcc_parent_map_5[] = { | |
323 | { P_BI_TCXO, 0 }, | |
324 | { P_GPLL0_OUT_EARLY, 1 }, | |
325 | }; | |
326 | ||
327 | static const struct clk_parent_data gcc_parent_data_5[] = { | |
328 | { .fw_name = "bi_tcxo" }, | |
329 | { .hw = &gpll0_out_early.clkr.hw }, | |
330 | }; | |
331 | ||
332 | static const struct parent_map gcc_parent_map_6[] = { | |
333 | { P_BI_TCXO, 0 }, | |
334 | { P_GPLL0_OUT_EARLY, 1 }, | |
335 | { P_GPLL4_OUT_MAIN, 5 }, | |
336 | }; | |
337 | ||
338 | static const struct clk_parent_data gcc_parent_data_6[] = { | |
339 | { .fw_name = "bi_tcxo" }, | |
340 | { .hw = &gpll0_out_early.clkr.hw }, | |
341 | { .hw = &gpll4_out_main.clkr.hw }, | |
342 | }; | |
343 | ||
344 | static const struct parent_map gcc_parent_map_7[] = { | |
345 | { P_BI_TCXO, 0 }, | |
346 | { P_GPLL0_OUT_EARLY, 1 }, | |
347 | { P_SLEEP_CLK, 5 }, | |
348 | }; | |
349 | ||
350 | static const struct clk_parent_data gcc_parent_data_7[] = { | |
351 | { .fw_name = "bi_tcxo" }, | |
352 | { .hw = &gpll0_out_early.clkr.hw }, | |
353 | { .fw_name = "sleep_clk" }, | |
354 | }; | |
355 | ||
356 | static const struct parent_map gcc_parent_map_8[] = { | |
357 | { P_BI_TCXO, 0 }, | |
358 | { P_GPLL0_OUT_EARLY, 1 }, | |
359 | { P_GPLL9_OUT_MAIN, 2 }, | |
360 | { P_GPLL6_OUT_EARLY, 3 }, | |
361 | { P_GPLL8_OUT_MAIN, 4 }, | |
362 | { P_GPLL4_OUT_MAIN, 5 }, | |
363 | { P_GPLL3_OUT_EARLY, 6 }, | |
364 | }; | |
365 | ||
366 | static const struct clk_parent_data gcc_parent_data_8[] = { | |
367 | { .fw_name = "bi_tcxo" }, | |
368 | { .hw = &gpll0_out_early.clkr.hw }, | |
369 | { .hw = &gpll9_out_main.hw }, | |
370 | { .hw = &gpll6_out_early.clkr.hw }, | |
371 | { .hw = &gpll8_out_main.hw }, | |
372 | { .hw = &gpll4_out_main.clkr.hw }, | |
373 | { .hw = &gpll3_out_early.clkr.hw }, | |
374 | }; | |
375 | ||
376 | static const struct parent_map gcc_parent_map_9[] = { | |
377 | { P_BI_TCXO, 0 }, | |
378 | { P_GPLL0_OUT_EARLY, 1 }, | |
379 | { P_GPLL8_OUT_MAIN, 4 }, | |
380 | }; | |
381 | ||
382 | static const struct clk_parent_data gcc_parent_data_9[] = { | |
383 | { .fw_name = "bi_tcxo" }, | |
384 | { .hw = &gpll0_out_early.clkr.hw }, | |
385 | { .hw = &gpll8_out_main.hw }, | |
386 | }; | |
387 | ||
388 | static const struct parent_map gcc_parent_map_10[] = { | |
389 | { P_BI_TCXO, 0 }, | |
390 | { P_GPLL0_OUT_EARLY, 1 }, | |
391 | { P_GPLL9_OUT_MAIN, 2 }, | |
392 | { P_GPLL6_OUT_EARLY, 3 }, | |
393 | { P_GPLL8_OUT_MAIN, 4 }, | |
394 | { P_GPLL3_OUT_EARLY, 6 }, | |
395 | }; | |
396 | ||
397 | static const struct clk_parent_data gcc_parent_data_10[] = { | |
398 | { .fw_name = "bi_tcxo" }, | |
399 | { .hw = &gpll0_out_early.clkr.hw }, | |
400 | { .hw = &gpll9_out_main.hw }, | |
401 | { .hw = &gpll6_out_early.clkr.hw }, | |
402 | { .hw = &gpll8_out_main.hw }, | |
403 | { .hw = &gpll3_out_early.clkr.hw }, | |
404 | }; | |
405 | ||
406 | static const struct parent_map gcc_parent_map_11[] = { | |
407 | { P_BI_TCXO, 0 }, | |
408 | { P_GPLL0_OUT_EARLY, 1 }, | |
409 | { P_GPLL8_OUT_EARLY, 4 }, | |
410 | { P_GPLL4_OUT_MAIN, 5 }, | |
411 | }; | |
412 | ||
413 | static const struct clk_parent_data gcc_parent_data_11[] = { | |
414 | { .fw_name = "bi_tcxo" }, | |
415 | { .hw = &gpll0_out_early.clkr.hw }, | |
416 | { .hw = &gpll8_out_early.clkr.hw }, | |
417 | { .hw = &gpll4_out_main.clkr.hw }, | |
418 | }; | |
419 | ||
420 | static const struct parent_map gcc_parent_map_12[] = { | |
421 | { P_BI_TCXO, 0 }, | |
422 | { P_GPLL0_OUT_EARLY, 1 }, | |
423 | { P_GPLL6_OUT_EARLY, 3 }, | |
424 | { P_GPLL8_OUT_EARLY, 4 }, | |
425 | }; | |
426 | ||
427 | static const struct clk_parent_data gcc_parent_data_12[] = { | |
428 | { .fw_name = "bi_tcxo" }, | |
429 | { .hw = &gpll0_out_early.clkr.hw }, | |
430 | { .hw = &gpll6_out_early.clkr.hw }, | |
431 | { .hw = &gpll8_out_early.clkr.hw }, | |
432 | }; | |
433 | ||
434 | static const struct parent_map gcc_parent_map_13[] = { | |
435 | { P_BI_TCXO, 0 }, | |
436 | { P_GPLL0_OUT_EARLY, 1 }, | |
437 | { P_GPLL0_OUT_AUX2, 2 }, | |
438 | { P_GPLL7_OUT_MAIN, 3 }, | |
439 | { P_GPLL4_OUT_MAIN, 5 }, | |
440 | }; | |
441 | ||
442 | static const struct clk_parent_data gcc_parent_data_13[] = { | |
443 | { .fw_name = "bi_tcxo" }, | |
444 | { .hw = &gpll0_out_early.clkr.hw }, | |
445 | { .hw = &gpll0_out_aux2.hw }, | |
446 | { .hw = &gpll7_out_main.hw }, | |
447 | { .hw = &gpll4_out_main.clkr.hw }, | |
448 | }; | |
449 | ||
450 | static const struct parent_map gcc_parent_map_14[] = { | |
451 | { P_BI_TCXO, 0 }, | |
452 | { P_SLEEP_CLK, 5 }, | |
453 | }; | |
454 | ||
455 | static const struct clk_parent_data gcc_parent_data_14[] = { | |
456 | { .fw_name = "bi_tcxo" }, | |
457 | { .fw_name = "sleep_clk" }, | |
458 | }; | |
459 | ||
460 | static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = { | |
461 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
462 | F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0), | |
463 | F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0), | |
464 | { } | |
465 | }; | |
466 | ||
467 | static struct clk_rcg2 gcc_camss_ahb_clk_src = { | |
468 | .cmd_rcgr = 0x56088, | |
469 | .mnd_width = 0, | |
470 | .hid_width = 5, | |
471 | .parent_map = gcc_parent_map_9, | |
472 | .freq_tbl = ftbl_gcc_camss_ahb_clk_src, | |
473 | .clkr.hw.init = &(struct clk_init_data){ | |
474 | .name = "gcc_camss_ahb_clk_src", | |
475 | .parent_data = gcc_parent_data_9, | |
476 | .num_parents = ARRAY_SIZE(gcc_parent_data_9), | |
477 | .ops = &clk_rcg2_ops, | |
478 | }, | |
479 | }; | |
480 | ||
481 | static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { | |
482 | F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0), | |
483 | F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), | |
484 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
485 | { } | |
486 | }; | |
487 | ||
488 | static struct clk_rcg2 gcc_camss_cci_clk_src = { | |
489 | .cmd_rcgr = 0x52004, | |
490 | .mnd_width = 8, | |
491 | .hid_width = 5, | |
492 | .parent_map = gcc_parent_map_5, | |
493 | .freq_tbl = ftbl_gcc_camss_cci_clk_src, | |
494 | .clkr.hw.init = &(struct clk_init_data){ | |
495 | .name = "gcc_camss_cci_clk_src", | |
496 | .parent_data = gcc_parent_data_5, | |
497 | .num_parents = ARRAY_SIZE(gcc_parent_data_5), | |
498 | .ops = &clk_rcg2_ops, | |
499 | }, | |
500 | }; | |
501 | ||
502 | static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = { | |
503 | F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), | |
504 | F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0), | |
505 | F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0), | |
506 | F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), | |
507 | F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), | |
508 | { } | |
509 | }; | |
510 | ||
511 | static struct clk_rcg2 gcc_camss_cpp_clk_src = { | |
512 | .cmd_rcgr = 0x560c8, | |
513 | .mnd_width = 0, | |
514 | .hid_width = 5, | |
515 | .parent_map = gcc_parent_map_10, | |
516 | .freq_tbl = ftbl_gcc_camss_cpp_clk_src, | |
517 | .clkr.hw.init = &(struct clk_init_data){ | |
518 | .name = "gcc_camss_cpp_clk_src", | |
519 | .parent_data = gcc_parent_data_10, | |
520 | .num_parents = ARRAY_SIZE(gcc_parent_data_10), | |
521 | .ops = &clk_rcg2_ops, | |
522 | }, | |
523 | }; | |
524 | ||
525 | static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = { | |
526 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
527 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
528 | F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0), | |
529 | F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), | |
530 | F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0), | |
531 | { } | |
532 | }; | |
533 | ||
534 | static struct clk_rcg2 gcc_camss_csi0_clk_src = { | |
535 | .cmd_rcgr = 0x55030, | |
536 | .mnd_width = 0, | |
537 | .hid_width = 5, | |
538 | .parent_map = gcc_parent_map_3, | |
539 | .freq_tbl = ftbl_gcc_camss_csi0_clk_src, | |
540 | .clkr.hw.init = &(struct clk_init_data){ | |
541 | .name = "gcc_camss_csi0_clk_src", | |
542 | .parent_data = gcc_parent_data_3, | |
543 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
544 | .ops = &clk_rcg2_ops, | |
545 | }, | |
546 | }; | |
547 | ||
548 | static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { | |
549 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
550 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
551 | F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), | |
552 | { } | |
553 | }; | |
554 | ||
555 | static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { | |
556 | .cmd_rcgr = 0x53004, | |
557 | .mnd_width = 0, | |
558 | .hid_width = 5, | |
559 | .parent_map = gcc_parent_map_6, | |
560 | .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, | |
561 | .clkr.hw.init = &(struct clk_init_data){ | |
562 | .name = "gcc_camss_csi0phytimer_clk_src", | |
563 | .parent_data = gcc_parent_data_6, | |
564 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), | |
565 | .ops = &clk_rcg2_ops, | |
566 | }, | |
567 | }; | |
568 | ||
569 | static struct clk_rcg2 gcc_camss_csi1_clk_src = { | |
570 | .cmd_rcgr = 0x5506c, | |
571 | .mnd_width = 0, | |
572 | .hid_width = 5, | |
573 | .parent_map = gcc_parent_map_3, | |
574 | .freq_tbl = ftbl_gcc_camss_csi0_clk_src, | |
575 | .clkr.hw.init = &(struct clk_init_data){ | |
576 | .name = "gcc_camss_csi1_clk_src", | |
577 | .parent_data = gcc_parent_data_3, | |
578 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
579 | .ops = &clk_rcg2_ops, | |
580 | }, | |
581 | }; | |
582 | ||
583 | static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { | |
584 | .cmd_rcgr = 0x53024, | |
585 | .mnd_width = 0, | |
586 | .hid_width = 5, | |
587 | .parent_map = gcc_parent_map_6, | |
588 | .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, | |
589 | .clkr.hw.init = &(struct clk_init_data){ | |
590 | .name = "gcc_camss_csi1phytimer_clk_src", | |
591 | .parent_data = gcc_parent_data_6, | |
592 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), | |
593 | .ops = &clk_rcg2_ops, | |
594 | }, | |
595 | }; | |
596 | ||
597 | static struct clk_rcg2 gcc_camss_csi2_clk_src = { | |
598 | .cmd_rcgr = 0x550a4, | |
599 | .mnd_width = 0, | |
600 | .hid_width = 5, | |
601 | .parent_map = gcc_parent_map_3, | |
602 | .freq_tbl = ftbl_gcc_camss_csi0_clk_src, | |
603 | .clkr.hw.init = &(struct clk_init_data){ | |
604 | .name = "gcc_camss_csi2_clk_src", | |
605 | .parent_data = gcc_parent_data_3, | |
606 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
607 | .ops = &clk_rcg2_ops, | |
608 | }, | |
609 | }; | |
610 | ||
611 | static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { | |
612 | .cmd_rcgr = 0x53044, | |
613 | .mnd_width = 0, | |
614 | .hid_width = 5, | |
615 | .parent_map = gcc_parent_map_6, | |
616 | .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, | |
617 | .clkr.hw.init = &(struct clk_init_data){ | |
618 | .name = "gcc_camss_csi2phytimer_clk_src", | |
619 | .parent_data = gcc_parent_data_6, | |
620 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), | |
621 | .ops = &clk_rcg2_ops, | |
622 | }, | |
623 | }; | |
624 | ||
625 | static struct clk_rcg2 gcc_camss_csi3_clk_src = { | |
626 | .cmd_rcgr = 0x550e0, | |
627 | .mnd_width = 0, | |
628 | .hid_width = 5, | |
629 | .parent_map = gcc_parent_map_3, | |
630 | .freq_tbl = ftbl_gcc_camss_csi0_clk_src, | |
631 | .clkr.hw.init = &(struct clk_init_data){ | |
632 | .name = "gcc_camss_csi3_clk_src", | |
633 | .parent_data = gcc_parent_data_3, | |
634 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
635 | .ops = &clk_rcg2_ops, | |
636 | }, | |
637 | }; | |
638 | ||
639 | static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = { | |
640 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
641 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
642 | F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), | |
643 | F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), | |
644 | { } | |
645 | }; | |
646 | ||
647 | static struct clk_rcg2 gcc_camss_csiphy_clk_src = { | |
648 | .cmd_rcgr = 0x55000, | |
649 | .mnd_width = 0, | |
650 | .hid_width = 5, | |
651 | .parent_map = gcc_parent_map_11, | |
652 | .freq_tbl = ftbl_gcc_camss_csiphy_clk_src, | |
653 | .clkr.hw.init = &(struct clk_init_data){ | |
654 | .name = "gcc_camss_csiphy_clk_src", | |
655 | .parent_data = gcc_parent_data_11, | |
656 | .num_parents = ARRAY_SIZE(gcc_parent_data_11), | |
657 | .ops = &clk_rcg2_ops, | |
658 | }, | |
659 | }; | |
660 | ||
661 | static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = { | |
662 | F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), | |
663 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
664 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
665 | { } | |
666 | }; | |
667 | ||
668 | static struct clk_rcg2 gcc_camss_gp0_clk_src = { | |
669 | .cmd_rcgr = 0x50000, | |
670 | .mnd_width = 8, | |
671 | .hid_width = 5, | |
672 | .parent_map = gcc_parent_map_7, | |
673 | .freq_tbl = ftbl_gcc_camss_gp0_clk_src, | |
674 | .clkr.hw.init = &(struct clk_init_data){ | |
675 | .name = "gcc_camss_gp0_clk_src", | |
676 | .parent_data = gcc_parent_data_7, | |
677 | .num_parents = ARRAY_SIZE(gcc_parent_data_7), | |
678 | .ops = &clk_rcg2_ops, | |
679 | }, | |
680 | }; | |
681 | ||
682 | static struct clk_rcg2 gcc_camss_gp1_clk_src = { | |
683 | .cmd_rcgr = 0x5001c, | |
684 | .mnd_width = 8, | |
685 | .hid_width = 5, | |
686 | .parent_map = gcc_parent_map_7, | |
687 | .freq_tbl = ftbl_gcc_camss_gp0_clk_src, | |
688 | .clkr.hw.init = &(struct clk_init_data){ | |
689 | .name = "gcc_camss_gp1_clk_src", | |
690 | .parent_data = gcc_parent_data_7, | |
691 | .num_parents = ARRAY_SIZE(gcc_parent_data_7), | |
692 | .ops = &clk_rcg2_ops, | |
693 | }, | |
694 | }; | |
695 | ||
696 | static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = { | |
697 | F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0), | |
698 | F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), | |
699 | F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0), | |
700 | F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), | |
701 | F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0), | |
702 | { } | |
703 | }; | |
704 | ||
705 | static struct clk_rcg2 gcc_camss_jpeg_clk_src = { | |
706 | .cmd_rcgr = 0x52028, | |
707 | .mnd_width = 0, | |
708 | .hid_width = 5, | |
709 | .parent_map = gcc_parent_map_12, | |
710 | .freq_tbl = ftbl_gcc_camss_jpeg_clk_src, | |
711 | .clkr.hw.init = &(struct clk_init_data){ | |
712 | .name = "gcc_camss_jpeg_clk_src", | |
713 | .parent_data = gcc_parent_data_12, | |
714 | .num_parents = ARRAY_SIZE(gcc_parent_data_12), | |
715 | .ops = &clk_rcg2_ops, | |
716 | }, | |
717 | }; | |
718 | ||
719 | static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { | |
720 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
721 | F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), | |
722 | F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), | |
723 | { } | |
724 | }; | |
725 | ||
726 | static struct clk_rcg2 gcc_camss_mclk0_clk_src = { | |
727 | .cmd_rcgr = 0x51000, | |
728 | .mnd_width = 8, | |
729 | .hid_width = 5, | |
730 | .parent_map = gcc_parent_map_4, | |
731 | .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, | |
732 | .clkr.hw.init = &(struct clk_init_data){ | |
733 | .name = "gcc_camss_mclk0_clk_src", | |
734 | .parent_data = gcc_parent_data_4, | |
735 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
736 | .ops = &clk_rcg2_ops, | |
737 | }, | |
738 | }; | |
739 | ||
740 | static struct clk_rcg2 gcc_camss_mclk1_clk_src = { | |
741 | .cmd_rcgr = 0x5101c, | |
742 | .mnd_width = 8, | |
743 | .hid_width = 5, | |
744 | .parent_map = gcc_parent_map_4, | |
745 | .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, | |
746 | .clkr.hw.init = &(struct clk_init_data){ | |
747 | .name = "gcc_camss_mclk1_clk_src", | |
748 | .parent_data = gcc_parent_data_4, | |
749 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
750 | .ops = &clk_rcg2_ops, | |
751 | }, | |
752 | }; | |
753 | ||
754 | static struct clk_rcg2 gcc_camss_mclk2_clk_src = { | |
755 | .cmd_rcgr = 0x51038, | |
756 | .mnd_width = 8, | |
757 | .hid_width = 5, | |
758 | .parent_map = gcc_parent_map_4, | |
759 | .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, | |
760 | .clkr.hw.init = &(struct clk_init_data){ | |
761 | .name = "gcc_camss_mclk2_clk_src", | |
762 | .parent_data = gcc_parent_data_4, | |
763 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
764 | .ops = &clk_rcg2_ops, | |
765 | }, | |
766 | }; | |
767 | ||
768 | static struct clk_rcg2 gcc_camss_mclk3_clk_src = { | |
769 | .cmd_rcgr = 0x51054, | |
770 | .mnd_width = 8, | |
771 | .hid_width = 5, | |
772 | .parent_map = gcc_parent_map_4, | |
773 | .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, | |
774 | .clkr.hw.init = &(struct clk_init_data){ | |
775 | .name = "gcc_camss_mclk3_clk_src", | |
776 | .parent_data = gcc_parent_data_4, | |
777 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
778 | .ops = &clk_rcg2_ops, | |
779 | }, | |
780 | }; | |
781 | ||
782 | static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = { | |
783 | F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), | |
784 | F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0), | |
785 | F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), | |
786 | F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), | |
787 | F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0), | |
788 | F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), | |
789 | { } | |
790 | }; | |
791 | ||
792 | static struct clk_rcg2 gcc_camss_vfe0_clk_src = { | |
793 | .cmd_rcgr = 0x54010, | |
794 | .mnd_width = 0, | |
795 | .hid_width = 5, | |
796 | .parent_map = gcc_parent_map_8, | |
797 | .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, | |
798 | .clkr.hw.init = &(struct clk_init_data){ | |
799 | .name = "gcc_camss_vfe0_clk_src", | |
800 | .parent_data = gcc_parent_data_8, | |
801 | .num_parents = ARRAY_SIZE(gcc_parent_data_8), | |
802 | .ops = &clk_rcg2_ops, | |
803 | }, | |
804 | }; | |
805 | ||
806 | static struct clk_rcg2 gcc_camss_vfe1_clk_src = { | |
807 | .cmd_rcgr = 0x54048, | |
808 | .mnd_width = 0, | |
809 | .hid_width = 5, | |
810 | .parent_map = gcc_parent_map_8, | |
811 | .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, | |
812 | .clkr.hw.init = &(struct clk_init_data){ | |
813 | .name = "gcc_camss_vfe1_clk_src", | |
814 | .parent_data = gcc_parent_data_8, | |
815 | .num_parents = ARRAY_SIZE(gcc_parent_data_8), | |
816 | .ops = &clk_rcg2_ops, | |
817 | }, | |
818 | }; | |
819 | ||
820 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { | |
821 | F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), | |
822 | F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), | |
823 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
824 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
825 | { } | |
826 | }; | |
827 | ||
828 | static struct clk_rcg2 gcc_gp1_clk_src = { | |
829 | .cmd_rcgr = 0x4d004, | |
830 | .mnd_width = 8, | |
831 | .hid_width = 5, | |
832 | .parent_map = gcc_parent_map_2, | |
833 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
834 | .clkr.hw.init = &(struct clk_init_data){ | |
835 | .name = "gcc_gp1_clk_src", | |
836 | .parent_data = gcc_parent_data_2, | |
837 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
838 | .ops = &clk_rcg2_ops, | |
839 | }, | |
840 | }; | |
841 | ||
842 | static struct clk_rcg2 gcc_gp2_clk_src = { | |
843 | .cmd_rcgr = 0x4e004, | |
844 | .mnd_width = 8, | |
845 | .hid_width = 5, | |
846 | .parent_map = gcc_parent_map_2, | |
847 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
848 | .clkr.hw.init = &(struct clk_init_data){ | |
849 | .name = "gcc_gp2_clk_src", | |
850 | .parent_data = gcc_parent_data_2, | |
851 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
852 | .ops = &clk_rcg2_ops, | |
853 | }, | |
854 | }; | |
855 | ||
856 | static struct clk_rcg2 gcc_gp3_clk_src = { | |
857 | .cmd_rcgr = 0x4f004, | |
858 | .mnd_width = 8, | |
859 | .hid_width = 5, | |
860 | .parent_map = gcc_parent_map_2, | |
861 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
862 | .clkr.hw.init = &(struct clk_init_data){ | |
863 | .name = "gcc_gp3_clk_src", | |
864 | .parent_data = gcc_parent_data_2, | |
865 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
866 | .ops = &clk_rcg2_ops, | |
867 | }, | |
868 | }; | |
869 | ||
870 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { | |
871 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
872 | F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), | |
873 | { } | |
874 | }; | |
875 | ||
876 | static struct clk_rcg2 gcc_pdm2_clk_src = { | |
877 | .cmd_rcgr = 0x20010, | |
878 | .mnd_width = 0, | |
879 | .hid_width = 5, | |
880 | .parent_map = gcc_parent_map_0, | |
881 | .freq_tbl = ftbl_gcc_pdm2_clk_src, | |
882 | .clkr.hw.init = &(struct clk_init_data){ | |
883 | .name = "gcc_pdm2_clk_src", | |
884 | .parent_data = gcc_parent_data_0, | |
885 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
886 | .ops = &clk_rcg2_ops, | |
887 | }, | |
888 | }; | |
889 | ||
890 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { | |
891 | F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), | |
892 | F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), | |
893 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
894 | F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), | |
895 | F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), | |
896 | F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), | |
897 | F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), | |
898 | F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), | |
899 | F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), | |
900 | F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), | |
901 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
902 | F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), | |
903 | F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), | |
904 | F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), | |
905 | F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), | |
906 | F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), | |
907 | { } | |
908 | }; | |
909 | ||
910 | static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { | |
911 | .name = "gcc_qupv3_wrap0_s0_clk_src", | |
912 | .parent_data = gcc_parent_data_1, | |
913 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
914 | .ops = &clk_rcg2_ops, | |
915 | }; | |
916 | ||
917 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { | |
918 | .cmd_rcgr = 0x1f148, | |
919 | .mnd_width = 16, | |
920 | .hid_width = 5, | |
921 | .parent_map = gcc_parent_map_1, | |
922 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
923 | .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, | |
924 | }; | |
925 | ||
926 | static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { | |
927 | .name = "gcc_qupv3_wrap0_s1_clk_src", | |
928 | .parent_data = gcc_parent_data_1, | |
929 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
930 | .ops = &clk_rcg2_ops, | |
931 | }; | |
932 | ||
933 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { | |
934 | .cmd_rcgr = 0x1f278, | |
935 | .mnd_width = 16, | |
936 | .hid_width = 5, | |
937 | .parent_map = gcc_parent_map_1, | |
938 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
939 | .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, | |
940 | }; | |
941 | ||
942 | static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { | |
943 | .name = "gcc_qupv3_wrap0_s2_clk_src", | |
944 | .parent_data = gcc_parent_data_1, | |
945 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
946 | .ops = &clk_rcg2_ops, | |
947 | }; | |
948 | ||
949 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { | |
950 | .cmd_rcgr = 0x1f3a8, | |
951 | .mnd_width = 16, | |
952 | .hid_width = 5, | |
953 | .parent_map = gcc_parent_map_1, | |
954 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
955 | .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, | |
956 | }; | |
957 | ||
958 | static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { | |
959 | .name = "gcc_qupv3_wrap0_s3_clk_src", | |
960 | .parent_data = gcc_parent_data_1, | |
961 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
962 | .ops = &clk_rcg2_ops, | |
963 | }; | |
964 | ||
965 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { | |
966 | .cmd_rcgr = 0x1f4d8, | |
967 | .mnd_width = 16, | |
968 | .hid_width = 5, | |
969 | .parent_map = gcc_parent_map_1, | |
970 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
971 | .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, | |
972 | }; | |
973 | ||
974 | static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { | |
975 | .name = "gcc_qupv3_wrap0_s4_clk_src", | |
976 | .parent_data = gcc_parent_data_1, | |
977 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
978 | .ops = &clk_rcg2_ops, | |
979 | }; | |
980 | ||
981 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { | |
982 | .cmd_rcgr = 0x1f608, | |
983 | .mnd_width = 16, | |
984 | .hid_width = 5, | |
985 | .parent_map = gcc_parent_map_1, | |
986 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
987 | .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, | |
988 | }; | |
989 | ||
990 | static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { | |
991 | .name = "gcc_qupv3_wrap0_s5_clk_src", | |
992 | .parent_data = gcc_parent_data_1, | |
993 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
994 | .ops = &clk_rcg2_ops, | |
995 | }; | |
996 | ||
997 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { | |
998 | .cmd_rcgr = 0x1f738, | |
999 | .mnd_width = 16, | |
1000 | .hid_width = 5, | |
1001 | .parent_map = gcc_parent_map_1, | |
1002 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1003 | .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, | |
1004 | }; | |
1005 | ||
1006 | static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { | |
1007 | .name = "gcc_qupv3_wrap1_s0_clk_src", | |
1008 | .parent_data = gcc_parent_data_1, | |
1009 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1010 | .ops = &clk_rcg2_ops, | |
1011 | }; | |
1012 | ||
1013 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { | |
1014 | .cmd_rcgr = 0x39148, | |
1015 | .mnd_width = 16, | |
1016 | .hid_width = 5, | |
1017 | .parent_map = gcc_parent_map_1, | |
1018 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1019 | .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, | |
1020 | }; | |
1021 | ||
1022 | static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { | |
1023 | .name = "gcc_qupv3_wrap1_s1_clk_src", | |
1024 | .parent_data = gcc_parent_data_1, | |
1025 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1026 | .ops = &clk_rcg2_ops, | |
1027 | }; | |
1028 | ||
1029 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { | |
1030 | .cmd_rcgr = 0x39278, | |
1031 | .mnd_width = 16, | |
1032 | .hid_width = 5, | |
1033 | .parent_map = gcc_parent_map_1, | |
1034 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1035 | .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, | |
1036 | }; | |
1037 | ||
1038 | static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { | |
1039 | .name = "gcc_qupv3_wrap1_s2_clk_src", | |
1040 | .parent_data = gcc_parent_data_1, | |
1041 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1042 | .ops = &clk_rcg2_ops, | |
1043 | }; | |
1044 | ||
1045 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { | |
1046 | .cmd_rcgr = 0x393a8, | |
1047 | .mnd_width = 16, | |
1048 | .hid_width = 5, | |
1049 | .parent_map = gcc_parent_map_1, | |
1050 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1051 | .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, | |
1052 | }; | |
1053 | ||
1054 | static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { | |
1055 | .name = "gcc_qupv3_wrap1_s3_clk_src", | |
1056 | .parent_data = gcc_parent_data_1, | |
1057 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1058 | .ops = &clk_rcg2_ops, | |
1059 | }; | |
1060 | ||
1061 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { | |
1062 | .cmd_rcgr = 0x394d8, | |
1063 | .mnd_width = 16, | |
1064 | .hid_width = 5, | |
1065 | .parent_map = gcc_parent_map_1, | |
1066 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1067 | .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, | |
1068 | }; | |
1069 | ||
1070 | static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { | |
1071 | .name = "gcc_qupv3_wrap1_s4_clk_src", | |
1072 | .parent_data = gcc_parent_data_1, | |
1073 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1074 | .ops = &clk_rcg2_ops, | |
1075 | }; | |
1076 | ||
1077 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { | |
1078 | .cmd_rcgr = 0x39608, | |
1079 | .mnd_width = 16, | |
1080 | .hid_width = 5, | |
1081 | .parent_map = gcc_parent_map_1, | |
1082 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1083 | .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, | |
1084 | }; | |
1085 | ||
1086 | static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { | |
1087 | .name = "gcc_qupv3_wrap1_s5_clk_src", | |
1088 | .parent_data = gcc_parent_data_1, | |
1089 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
1090 | .ops = &clk_rcg2_ops, | |
1091 | }; | |
1092 | ||
1093 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { | |
1094 | .cmd_rcgr = 0x39738, | |
1095 | .mnd_width = 16, | |
1096 | .hid_width = 5, | |
1097 | .parent_map = gcc_parent_map_1, | |
1098 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1099 | .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, | |
1100 | }; | |
1101 | ||
1102 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { | |
1103 | F(144000, P_BI_TCXO, 16, 3, 25), | |
1104 | F(400000, P_BI_TCXO, 12, 1, 4), | |
1105 | F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), | |
1106 | F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), | |
1107 | F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), | |
1108 | F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), | |
1109 | F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), | |
1110 | F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), | |
1111 | { } | |
1112 | }; | |
1113 | ||
1114 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { | |
1115 | .cmd_rcgr = 0x38028, | |
1116 | .mnd_width = 8, | |
1117 | .hid_width = 5, | |
1118 | .parent_map = gcc_parent_map_1, | |
1119 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, | |
1120 | .clkr.hw.init = &(struct clk_init_data){ | |
1121 | .name = "gcc_sdcc1_apps_clk_src", | |
1122 | .parent_data = gcc_parent_data_1, | |
1123 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
e53f2086 | 1124 | .ops = &clk_rcg2_floor_ops, |
4b8d6ae5 KD |
1125 | }, |
1126 | }; | |
1127 | ||
1128 | static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { | |
1129 | F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), | |
1130 | F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), | |
1131 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
1132 | F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), | |
1133 | { } | |
1134 | }; | |
1135 | ||
1136 | static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { | |
1137 | .cmd_rcgr = 0x38010, | |
1138 | .mnd_width = 0, | |
1139 | .hid_width = 5, | |
1140 | .parent_map = gcc_parent_map_0, | |
1141 | .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, | |
1142 | .clkr.hw.init = &(struct clk_init_data){ | |
1143 | .name = "gcc_sdcc1_ice_core_clk_src", | |
1144 | .parent_data = gcc_parent_data_0, | |
1145 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
e53f2086 | 1146 | .ops = &clk_rcg2_ops, |
4b8d6ae5 KD |
1147 | }, |
1148 | }; | |
1149 | ||
1150 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { | |
1151 | F(400000, P_BI_TCXO, 12, 1, 4), | |
1152 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1153 | F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), | |
1154 | F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), | |
1155 | F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), | |
4b8d6ae5 KD |
1156 | { } |
1157 | }; | |
1158 | ||
1159 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | |
1160 | .cmd_rcgr = 0x1e00c, | |
1161 | .mnd_width = 8, | |
1162 | .hid_width = 5, | |
1163 | .parent_map = gcc_parent_map_13, | |
1164 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, | |
1165 | .clkr.hw.init = &(struct clk_init_data){ | |
1166 | .name = "gcc_sdcc2_apps_clk_src", | |
1167 | .parent_data = gcc_parent_data_13, | |
1168 | .num_parents = ARRAY_SIZE(gcc_parent_data_13), | |
1169 | .ops = &clk_rcg2_floor_ops, | |
1170 | }, | |
1171 | }; | |
1172 | ||
1173 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { | |
1174 | F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), | |
1175 | F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), | |
1176 | F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), | |
1177 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
1178 | F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), | |
1179 | { } | |
1180 | }; | |
1181 | ||
1182 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { | |
1183 | .cmd_rcgr = 0x45020, | |
1184 | .mnd_width = 8, | |
1185 | .hid_width = 5, | |
1186 | .parent_map = gcc_parent_map_0, | |
1187 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, | |
1188 | .clkr.hw.init = &(struct clk_init_data){ | |
1189 | .name = "gcc_ufs_phy_axi_clk_src", | |
1190 | .parent_data = gcc_parent_data_0, | |
1191 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1192 | .ops = &clk_rcg2_ops, | |
1193 | }, | |
1194 | }; | |
1195 | ||
1196 | static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { | |
1197 | F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), | |
1198 | F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), | |
1199 | F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), | |
1200 | F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), | |
1201 | { } | |
1202 | }; | |
1203 | ||
1204 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { | |
1205 | .cmd_rcgr = 0x45048, | |
1206 | .mnd_width = 0, | |
1207 | .hid_width = 5, | |
1208 | .parent_map = gcc_parent_map_0, | |
1209 | .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, | |
1210 | .clkr.hw.init = &(struct clk_init_data){ | |
1211 | .name = "gcc_ufs_phy_ice_core_clk_src", | |
1212 | .parent_data = gcc_parent_data_0, | |
1213 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1214 | .ops = &clk_rcg2_ops, | |
1215 | }, | |
1216 | }; | |
1217 | ||
1218 | static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { | |
1219 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
1220 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1221 | { } | |
1222 | }; | |
1223 | ||
1224 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { | |
1225 | .cmd_rcgr = 0x4507c, | |
1226 | .mnd_width = 0, | |
1227 | .hid_width = 5, | |
1228 | .parent_map = gcc_parent_map_0, | |
1229 | .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, | |
1230 | .clkr.hw.init = &(struct clk_init_data){ | |
1231 | .name = "gcc_ufs_phy_phy_aux_clk_src", | |
1232 | .parent_data = gcc_parent_data_0, | |
1233 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1234 | .ops = &clk_rcg2_ops, | |
1235 | }, | |
1236 | }; | |
1237 | ||
1238 | static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { | |
1239 | F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), | |
1240 | F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0), | |
1241 | F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), | |
1242 | { } | |
1243 | }; | |
1244 | ||
1245 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { | |
1246 | .cmd_rcgr = 0x45060, | |
1247 | .mnd_width = 0, | |
1248 | .hid_width = 5, | |
1249 | .parent_map = gcc_parent_map_0, | |
1250 | .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, | |
1251 | .clkr.hw.init = &(struct clk_init_data){ | |
1252 | .name = "gcc_ufs_phy_unipro_core_clk_src", | |
1253 | .parent_data = gcc_parent_data_0, | |
1254 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1255 | .ops = &clk_rcg2_ops, | |
1256 | }, | |
1257 | }; | |
1258 | ||
1259 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { | |
1260 | F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), | |
1261 | F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), | |
1262 | F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), | |
1263 | F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), | |
1264 | { } | |
1265 | }; | |
1266 | ||
1267 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { | |
1268 | .cmd_rcgr = 0x1a01c, | |
1269 | .mnd_width = 8, | |
1270 | .hid_width = 5, | |
1271 | .parent_map = gcc_parent_map_0, | |
1272 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1273 | .clkr.hw.init = &(struct clk_init_data){ | |
1274 | .name = "gcc_usb30_prim_master_clk_src", | |
1275 | .parent_data = gcc_parent_data_0, | |
1276 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1277 | .ops = &clk_rcg2_ops, | |
1278 | }, | |
1279 | }; | |
1280 | ||
1281 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { | |
1282 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1283 | F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0), | |
1284 | F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), | |
1285 | F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), | |
1286 | { } | |
1287 | }; | |
1288 | ||
1289 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { | |
1290 | .cmd_rcgr = 0x1a034, | |
1291 | .mnd_width = 0, | |
1292 | .hid_width = 5, | |
1293 | .parent_map = gcc_parent_map_0, | |
1294 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
1295 | .clkr.hw.init = &(struct clk_init_data){ | |
1296 | .name = "gcc_usb30_prim_mock_utmi_clk_src", | |
1297 | .parent_data = gcc_parent_data_0, | |
1298 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
1299 | .ops = &clk_rcg2_ops, | |
1300 | }, | |
1301 | }; | |
1302 | ||
1303 | static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { | |
1304 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1305 | { } | |
1306 | }; | |
1307 | ||
1308 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { | |
1309 | .cmd_rcgr = 0x1a060, | |
1310 | .mnd_width = 0, | |
1311 | .hid_width = 5, | |
1312 | .parent_map = gcc_parent_map_14, | |
1313 | .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, | |
1314 | .clkr.hw.init = &(struct clk_init_data){ | |
1315 | .name = "gcc_usb3_prim_phy_aux_clk_src", | |
1316 | .parent_data = gcc_parent_data_14, | |
1317 | .num_parents = ARRAY_SIZE(gcc_parent_data_14), | |
1318 | .ops = &clk_rcg2_ops, | |
1319 | }, | |
1320 | }; | |
1321 | ||
1322 | static struct clk_rcg2 gcc_vs_ctrl_clk_src = { | |
1323 | .cmd_rcgr = 0x42030, | |
1324 | .mnd_width = 0, | |
1325 | .hid_width = 5, | |
1326 | .parent_map = gcc_parent_map_5, | |
1327 | .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, | |
1328 | .clkr.hw.init = &(struct clk_init_data){ | |
1329 | .name = "gcc_vs_ctrl_clk_src", | |
1330 | .parent_data = gcc_parent_data_5, | |
1331 | .num_parents = ARRAY_SIZE(gcc_parent_data_5), | |
1332 | .ops = &clk_rcg2_ops, | |
1333 | }, | |
1334 | }; | |
1335 | ||
1336 | static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { | |
1337 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1338 | F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0), | |
1339 | F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0), | |
1340 | { } | |
1341 | }; | |
1342 | ||
1343 | static struct clk_rcg2 gcc_vsensor_clk_src = { | |
1344 | .cmd_rcgr = 0x42018, | |
1345 | .mnd_width = 0, | |
1346 | .hid_width = 5, | |
1347 | .parent_map = gcc_parent_map_5, | |
1348 | .freq_tbl = ftbl_gcc_vsensor_clk_src, | |
1349 | .clkr.hw.init = &(struct clk_init_data){ | |
1350 | .name = "gcc_vsensor_clk_src", | |
1351 | .parent_data = gcc_parent_data_5, | |
1352 | .num_parents = ARRAY_SIZE(gcc_parent_data_5), | |
1353 | .ops = &clk_rcg2_ops, | |
1354 | }, | |
1355 | }; | |
1356 | ||
1357 | static struct clk_branch gcc_ahb2phy_csi_clk = { | |
1358 | .halt_reg = 0x1d004, | |
1359 | .halt_check = BRANCH_HALT, | |
1360 | .hwcg_reg = 0x1d004, | |
1361 | .hwcg_bit = 1, | |
1362 | .clkr = { | |
1363 | .enable_reg = 0x1d004, | |
1364 | .enable_mask = BIT(0), | |
1365 | .hw.init = &(struct clk_init_data){ | |
1366 | .name = "gcc_ahb2phy_csi_clk", | |
1367 | .ops = &clk_branch2_ops, | |
1368 | }, | |
1369 | }, | |
1370 | }; | |
1371 | ||
1372 | static struct clk_branch gcc_ahb2phy_usb_clk = { | |
1373 | .halt_reg = 0x1d008, | |
1374 | .halt_check = BRANCH_HALT, | |
1375 | .hwcg_reg = 0x1d008, | |
1376 | .hwcg_bit = 1, | |
1377 | .clkr = { | |
1378 | .enable_reg = 0x1d008, | |
1379 | .enable_mask = BIT(0), | |
1380 | .hw.init = &(struct clk_init_data){ | |
1381 | .name = "gcc_ahb2phy_usb_clk", | |
1382 | .ops = &clk_branch2_ops, | |
1383 | }, | |
1384 | }, | |
1385 | }; | |
1386 | ||
1387 | static struct clk_branch gcc_apc_vs_clk = { | |
1388 | .halt_reg = 0x4204c, | |
1389 | .halt_check = BRANCH_HALT, | |
1390 | .clkr = { | |
1391 | .enable_reg = 0x4204c, | |
1392 | .enable_mask = BIT(0), | |
1393 | .hw.init = &(struct clk_init_data){ | |
1394 | .name = "gcc_apc_vs_clk", | |
1395 | .parent_hws = (const struct clk_hw*[]){ | |
1396 | &gcc_vsensor_clk_src.clkr.hw, | |
1397 | }, | |
1398 | .num_parents = 1, | |
1399 | .flags = CLK_SET_RATE_PARENT, | |
1400 | .ops = &clk_branch2_ops, | |
1401 | }, | |
1402 | }, | |
1403 | }; | |
1404 | ||
1405 | static struct clk_branch gcc_bimc_gpu_axi_clk = { | |
1406 | .halt_reg = 0x71154, | |
1407 | .halt_check = BRANCH_HALT_DELAY, | |
1408 | .clkr = { | |
1409 | .enable_reg = 0x71154, | |
1410 | .enable_mask = BIT(0), | |
1411 | .hw.init = &(struct clk_init_data){ | |
1412 | .name = "gcc_bimc_gpu_axi_clk", | |
1413 | .ops = &clk_branch2_ops, | |
1414 | }, | |
1415 | }, | |
1416 | }; | |
1417 | ||
1418 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1419 | .halt_reg = 0x23004, | |
1420 | .halt_check = BRANCH_HALT_VOTED, | |
1421 | .hwcg_reg = 0x23004, | |
1422 | .hwcg_bit = 1, | |
1423 | .clkr = { | |
1424 | .enable_reg = 0x79004, | |
1425 | .enable_mask = BIT(10), | |
1426 | .hw.init = &(struct clk_init_data){ | |
1427 | .name = "gcc_boot_rom_ahb_clk", | |
1428 | .ops = &clk_branch2_ops, | |
1429 | }, | |
1430 | }, | |
1431 | }; | |
1432 | ||
1433 | static struct clk_branch gcc_camera_ahb_clk = { | |
1434 | .halt_reg = 0x17008, | |
1435 | .halt_check = BRANCH_HALT_DELAY, | |
1436 | .hwcg_reg = 0x17008, | |
1437 | .hwcg_bit = 1, | |
1438 | .clkr = { | |
1439 | .enable_reg = 0x17008, | |
1440 | .enable_mask = BIT(0), | |
1441 | .hw.init = &(struct clk_init_data){ | |
1442 | .name = "gcc_camera_ahb_clk", | |
1443 | .flags = CLK_IS_CRITICAL, | |
1444 | .ops = &clk_branch2_ops, | |
1445 | }, | |
1446 | }, | |
1447 | }; | |
1448 | ||
1449 | static struct clk_branch gcc_camera_xo_clk = { | |
1450 | .halt_reg = 0x17028, | |
1451 | .halt_check = BRANCH_HALT, | |
1452 | .clkr = { | |
1453 | .enable_reg = 0x17028, | |
1454 | .enable_mask = BIT(0), | |
1455 | .hw.init = &(struct clk_init_data){ | |
1456 | .name = "gcc_camera_xo_clk", | |
1457 | .flags = CLK_IS_CRITICAL, | |
1458 | .ops = &clk_branch2_ops, | |
1459 | }, | |
1460 | }, | |
1461 | }; | |
1462 | ||
1463 | static struct clk_branch gcc_camss_cci_ahb_clk = { | |
1464 | .halt_reg = 0x52020, | |
1465 | .halt_check = BRANCH_HALT, | |
1466 | .clkr = { | |
1467 | .enable_reg = 0x52020, | |
1468 | .enable_mask = BIT(0), | |
1469 | .hw.init = &(struct clk_init_data){ | |
1470 | .name = "gcc_camss_cci_ahb_clk", | |
1471 | .parent_hws = (const struct clk_hw*[]){ | |
1472 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1473 | }, | |
1474 | .num_parents = 1, | |
1475 | .flags = CLK_SET_RATE_PARENT, | |
1476 | .ops = &clk_branch2_ops, | |
1477 | }, | |
1478 | }, | |
1479 | }; | |
1480 | ||
1481 | static struct clk_branch gcc_camss_cci_clk = { | |
1482 | .halt_reg = 0x5201c, | |
1483 | .halt_check = BRANCH_HALT, | |
1484 | .clkr = { | |
1485 | .enable_reg = 0x5201c, | |
1486 | .enable_mask = BIT(0), | |
1487 | .hw.init = &(struct clk_init_data){ | |
1488 | .name = "gcc_camss_cci_clk", | |
1489 | .parent_hws = (const struct clk_hw*[]){ | |
1490 | &gcc_camss_cci_clk_src.clkr.hw, | |
1491 | }, | |
1492 | .num_parents = 1, | |
1493 | .flags = CLK_SET_RATE_PARENT, | |
1494 | .ops = &clk_branch2_ops, | |
1495 | }, | |
1496 | }, | |
1497 | }; | |
1498 | ||
1499 | static struct clk_branch gcc_camss_cphy_csid0_clk = { | |
1500 | .halt_reg = 0x5504c, | |
1501 | .halt_check = BRANCH_HALT, | |
1502 | .clkr = { | |
1503 | .enable_reg = 0x5504c, | |
1504 | .enable_mask = BIT(0), | |
1505 | .hw.init = &(struct clk_init_data){ | |
1506 | .name = "gcc_camss_cphy_csid0_clk", | |
1507 | .parent_hws = (const struct clk_hw*[]){ | |
1508 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
1509 | }, | |
1510 | .num_parents = 1, | |
1511 | .flags = CLK_SET_RATE_PARENT, | |
1512 | .ops = &clk_branch2_ops, | |
1513 | }, | |
1514 | }, | |
1515 | }; | |
1516 | ||
1517 | static struct clk_branch gcc_camss_cphy_csid1_clk = { | |
1518 | .halt_reg = 0x55088, | |
1519 | .halt_check = BRANCH_HALT, | |
1520 | .clkr = { | |
1521 | .enable_reg = 0x55088, | |
1522 | .enable_mask = BIT(0), | |
1523 | .hw.init = &(struct clk_init_data){ | |
1524 | .name = "gcc_camss_cphy_csid1_clk", | |
1525 | .parent_hws = (const struct clk_hw*[]){ | |
1526 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
1527 | }, | |
1528 | .num_parents = 1, | |
1529 | .flags = CLK_SET_RATE_PARENT, | |
1530 | .ops = &clk_branch2_ops, | |
1531 | }, | |
1532 | }, | |
1533 | }; | |
1534 | ||
1535 | static struct clk_branch gcc_camss_cphy_csid2_clk = { | |
1536 | .halt_reg = 0x550c0, | |
1537 | .halt_check = BRANCH_HALT, | |
1538 | .clkr = { | |
1539 | .enable_reg = 0x550c0, | |
1540 | .enable_mask = BIT(0), | |
1541 | .hw.init = &(struct clk_init_data){ | |
1542 | .name = "gcc_camss_cphy_csid2_clk", | |
1543 | .parent_hws = (const struct clk_hw*[]){ | |
1544 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
1545 | }, | |
1546 | .num_parents = 1, | |
1547 | .flags = CLK_SET_RATE_PARENT, | |
1548 | .ops = &clk_branch2_ops, | |
1549 | }, | |
1550 | }, | |
1551 | }; | |
1552 | ||
1553 | static struct clk_branch gcc_camss_cphy_csid3_clk = { | |
1554 | .halt_reg = 0x550fc, | |
1555 | .halt_check = BRANCH_HALT, | |
1556 | .clkr = { | |
1557 | .enable_reg = 0x550fc, | |
1558 | .enable_mask = BIT(0), | |
1559 | .hw.init = &(struct clk_init_data){ | |
1560 | .name = "gcc_camss_cphy_csid3_clk", | |
1561 | .parent_hws = (const struct clk_hw*[]){ | |
1562 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
1563 | }, | |
1564 | .num_parents = 1, | |
1565 | .flags = CLK_SET_RATE_PARENT, | |
1566 | .ops = &clk_branch2_ops, | |
1567 | }, | |
1568 | }, | |
1569 | }; | |
1570 | ||
1571 | static struct clk_branch gcc_camss_cpp_ahb_clk = { | |
1572 | .halt_reg = 0x560e8, | |
1573 | .halt_check = BRANCH_HALT, | |
1574 | .clkr = { | |
1575 | .enable_reg = 0x560e8, | |
1576 | .enable_mask = BIT(0), | |
1577 | .hw.init = &(struct clk_init_data){ | |
1578 | .name = "gcc_camss_cpp_ahb_clk", | |
1579 | .parent_hws = (const struct clk_hw*[]){ | |
1580 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1581 | }, | |
1582 | .num_parents = 1, | |
1583 | .flags = CLK_SET_RATE_PARENT, | |
1584 | .ops = &clk_branch2_ops, | |
1585 | }, | |
1586 | }, | |
1587 | }; | |
1588 | ||
1589 | static struct clk_branch gcc_camss_cpp_axi_clk = { | |
1590 | .halt_reg = 0x560f4, | |
1591 | .halt_check = BRANCH_HALT, | |
1592 | .clkr = { | |
1593 | .enable_reg = 0x560f4, | |
1594 | .enable_mask = BIT(0), | |
1595 | .hw.init = &(struct clk_init_data){ | |
1596 | .name = "gcc_camss_cpp_axi_clk", | |
1597 | .ops = &clk_branch2_ops, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
1602 | static struct clk_branch gcc_camss_cpp_clk = { | |
1603 | .halt_reg = 0x560e0, | |
1604 | .halt_check = BRANCH_HALT, | |
1605 | .clkr = { | |
1606 | .enable_reg = 0x560e0, | |
1607 | .enable_mask = BIT(0), | |
1608 | .hw.init = &(struct clk_init_data){ | |
1609 | .name = "gcc_camss_cpp_clk", | |
1610 | .parent_hws = (const struct clk_hw*[]){ | |
1611 | &gcc_camss_cpp_clk_src.clkr.hw, | |
1612 | }, | |
1613 | .num_parents = 1, | |
1614 | .flags = CLK_SET_RATE_PARENT, | |
1615 | .ops = &clk_branch2_ops, | |
1616 | }, | |
1617 | }, | |
1618 | }; | |
1619 | ||
1620 | static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = { | |
1621 | .halt_reg = 0x560f0, | |
1622 | .halt_check = BRANCH_HALT, | |
1623 | .clkr = { | |
1624 | .enable_reg = 0x560f0, | |
1625 | .enable_mask = BIT(0), | |
1626 | .hw.init = &(struct clk_init_data){ | |
1627 | .name = "gcc_camss_cpp_vbif_ahb_clk", | |
1628 | .parent_hws = (const struct clk_hw*[]){ | |
1629 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1630 | }, | |
1631 | .num_parents = 1, | |
1632 | .flags = CLK_SET_RATE_PARENT, | |
1633 | .ops = &clk_branch2_ops, | |
1634 | }, | |
1635 | }, | |
1636 | }; | |
1637 | ||
1638 | static struct clk_branch gcc_camss_csi0_ahb_clk = { | |
1639 | .halt_reg = 0x55050, | |
1640 | .halt_check = BRANCH_HALT, | |
1641 | .clkr = { | |
1642 | .enable_reg = 0x55050, | |
1643 | .enable_mask = BIT(0), | |
1644 | .hw.init = &(struct clk_init_data){ | |
1645 | .name = "gcc_camss_csi0_ahb_clk", | |
1646 | .parent_hws = (const struct clk_hw*[]){ | |
1647 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1648 | }, | |
1649 | .num_parents = 1, | |
1650 | .flags = CLK_SET_RATE_PARENT, | |
1651 | .ops = &clk_branch2_ops, | |
1652 | }, | |
1653 | }, | |
1654 | }; | |
1655 | ||
1656 | static struct clk_branch gcc_camss_csi0_clk = { | |
1657 | .halt_reg = 0x55048, | |
1658 | .halt_check = BRANCH_HALT, | |
1659 | .clkr = { | |
1660 | .enable_reg = 0x55048, | |
1661 | .enable_mask = BIT(0), | |
1662 | .hw.init = &(struct clk_init_data){ | |
1663 | .name = "gcc_camss_csi0_clk", | |
1664 | .parent_hws = (const struct clk_hw*[]){ | |
1665 | &gcc_camss_csi0_clk_src.clkr.hw, | |
1666 | }, | |
1667 | .num_parents = 1, | |
1668 | .flags = CLK_SET_RATE_PARENT, | |
1669 | .ops = &clk_branch2_ops, | |
1670 | }, | |
1671 | }, | |
1672 | }; | |
1673 | ||
1674 | static struct clk_branch gcc_camss_csi0phytimer_clk = { | |
1675 | .halt_reg = 0x5301c, | |
1676 | .halt_check = BRANCH_HALT, | |
1677 | .clkr = { | |
1678 | .enable_reg = 0x5301c, | |
1679 | .enable_mask = BIT(0), | |
1680 | .hw.init = &(struct clk_init_data){ | |
1681 | .name = "gcc_camss_csi0phytimer_clk", | |
1682 | .parent_hws = (const struct clk_hw*[]){ | |
1683 | &gcc_camss_csi0phytimer_clk_src.clkr.hw, | |
1684 | }, | |
1685 | .num_parents = 1, | |
1686 | .flags = CLK_SET_RATE_PARENT, | |
1687 | .ops = &clk_branch2_ops, | |
1688 | }, | |
1689 | }, | |
1690 | }; | |
1691 | ||
1692 | static struct clk_branch gcc_camss_csi0pix_clk = { | |
1693 | .halt_reg = 0x55060, | |
1694 | .halt_check = BRANCH_HALT, | |
1695 | .clkr = { | |
1696 | .enable_reg = 0x55060, | |
1697 | .enable_mask = BIT(0), | |
1698 | .hw.init = &(struct clk_init_data){ | |
1699 | .name = "gcc_camss_csi0pix_clk", | |
1700 | .parent_hws = (const struct clk_hw*[]){ | |
1701 | &gcc_camss_csi0_clk_src.clkr.hw, | |
1702 | }, | |
1703 | .num_parents = 1, | |
1704 | .flags = CLK_SET_RATE_PARENT, | |
1705 | .ops = &clk_branch2_ops, | |
1706 | }, | |
1707 | }, | |
1708 | }; | |
1709 | ||
1710 | static struct clk_branch gcc_camss_csi0rdi_clk = { | |
1711 | .halt_reg = 0x55058, | |
1712 | .halt_check = BRANCH_HALT, | |
1713 | .clkr = { | |
1714 | .enable_reg = 0x55058, | |
1715 | .enable_mask = BIT(0), | |
1716 | .hw.init = &(struct clk_init_data){ | |
1717 | .name = "gcc_camss_csi0rdi_clk", | |
1718 | .parent_hws = (const struct clk_hw*[]){ | |
1719 | &gcc_camss_csi0_clk_src.clkr.hw, | |
1720 | }, | |
1721 | .num_parents = 1, | |
1722 | .flags = CLK_SET_RATE_PARENT, | |
1723 | .ops = &clk_branch2_ops, | |
1724 | }, | |
1725 | }, | |
1726 | }; | |
1727 | ||
1728 | static struct clk_branch gcc_camss_csi1_ahb_clk = { | |
1729 | .halt_reg = 0x5508c, | |
1730 | .halt_check = BRANCH_HALT, | |
1731 | .clkr = { | |
1732 | .enable_reg = 0x5508c, | |
1733 | .enable_mask = BIT(0), | |
1734 | .hw.init = &(struct clk_init_data){ | |
1735 | .name = "gcc_camss_csi1_ahb_clk", | |
1736 | .parent_hws = (const struct clk_hw*[]){ | |
1737 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1738 | }, | |
1739 | .num_parents = 1, | |
1740 | .flags = CLK_SET_RATE_PARENT, | |
1741 | .ops = &clk_branch2_ops, | |
1742 | }, | |
1743 | }, | |
1744 | }; | |
1745 | ||
1746 | static struct clk_branch gcc_camss_csi1_clk = { | |
1747 | .halt_reg = 0x55084, | |
1748 | .halt_check = BRANCH_HALT, | |
1749 | .clkr = { | |
1750 | .enable_reg = 0x55084, | |
1751 | .enable_mask = BIT(0), | |
1752 | .hw.init = &(struct clk_init_data){ | |
1753 | .name = "gcc_camss_csi1_clk", | |
1754 | .parent_hws = (const struct clk_hw*[]){ | |
1755 | &gcc_camss_csi1_clk_src.clkr.hw, | |
1756 | }, | |
1757 | .num_parents = 1, | |
1758 | .flags = CLK_SET_RATE_PARENT, | |
1759 | .ops = &clk_branch2_ops, | |
1760 | }, | |
1761 | }, | |
1762 | }; | |
1763 | ||
1764 | static struct clk_branch gcc_camss_csi1phytimer_clk = { | |
1765 | .halt_reg = 0x5303c, | |
1766 | .halt_check = BRANCH_HALT, | |
1767 | .clkr = { | |
1768 | .enable_reg = 0x5303c, | |
1769 | .enable_mask = BIT(0), | |
1770 | .hw.init = &(struct clk_init_data){ | |
1771 | .name = "gcc_camss_csi1phytimer_clk", | |
1772 | .parent_hws = (const struct clk_hw*[]){ | |
1773 | &gcc_camss_csi1phytimer_clk_src.clkr.hw, | |
1774 | }, | |
1775 | .num_parents = 1, | |
1776 | .flags = CLK_SET_RATE_PARENT, | |
1777 | .ops = &clk_branch2_ops, | |
1778 | }, | |
1779 | }, | |
1780 | }; | |
1781 | ||
1782 | static struct clk_branch gcc_camss_csi1pix_clk = { | |
1783 | .halt_reg = 0x5509c, | |
1784 | .halt_check = BRANCH_HALT, | |
1785 | .clkr = { | |
1786 | .enable_reg = 0x5509c, | |
1787 | .enable_mask = BIT(0), | |
1788 | .hw.init = &(struct clk_init_data){ | |
1789 | .name = "gcc_camss_csi1pix_clk", | |
1790 | .parent_hws = (const struct clk_hw*[]){ | |
1791 | &gcc_camss_csi1_clk_src.clkr.hw, | |
1792 | }, | |
1793 | .num_parents = 1, | |
1794 | .flags = CLK_SET_RATE_PARENT, | |
1795 | .ops = &clk_branch2_ops, | |
1796 | }, | |
1797 | }, | |
1798 | }; | |
1799 | ||
1800 | static struct clk_branch gcc_camss_csi1rdi_clk = { | |
1801 | .halt_reg = 0x55094, | |
1802 | .halt_check = BRANCH_HALT, | |
1803 | .clkr = { | |
1804 | .enable_reg = 0x55094, | |
1805 | .enable_mask = BIT(0), | |
1806 | .hw.init = &(struct clk_init_data){ | |
1807 | .name = "gcc_camss_csi1rdi_clk", | |
1808 | .parent_hws = (const struct clk_hw*[]){ | |
1809 | &gcc_camss_csi1_clk_src.clkr.hw, | |
1810 | }, | |
1811 | .num_parents = 1, | |
1812 | .flags = CLK_SET_RATE_PARENT, | |
1813 | .ops = &clk_branch2_ops, | |
1814 | }, | |
1815 | }, | |
1816 | }; | |
1817 | ||
1818 | static struct clk_branch gcc_camss_csi2_ahb_clk = { | |
1819 | .halt_reg = 0x550c4, | |
1820 | .halt_check = BRANCH_HALT, | |
1821 | .clkr = { | |
1822 | .enable_reg = 0x550c4, | |
1823 | .enable_mask = BIT(0), | |
1824 | .hw.init = &(struct clk_init_data){ | |
1825 | .name = "gcc_camss_csi2_ahb_clk", | |
1826 | .parent_hws = (const struct clk_hw*[]){ | |
1827 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1828 | }, | |
1829 | .num_parents = 1, | |
1830 | .flags = CLK_SET_RATE_PARENT, | |
1831 | .ops = &clk_branch2_ops, | |
1832 | }, | |
1833 | }, | |
1834 | }; | |
1835 | ||
1836 | static struct clk_branch gcc_camss_csi2_clk = { | |
1837 | .halt_reg = 0x550bc, | |
1838 | .halt_check = BRANCH_HALT, | |
1839 | .clkr = { | |
1840 | .enable_reg = 0x550bc, | |
1841 | .enable_mask = BIT(0), | |
1842 | .hw.init = &(struct clk_init_data){ | |
1843 | .name = "gcc_camss_csi2_clk", | |
1844 | .parent_hws = (const struct clk_hw*[]){ | |
1845 | &gcc_camss_csi2_clk_src.clkr.hw, | |
1846 | }, | |
1847 | .num_parents = 1, | |
1848 | .flags = CLK_SET_RATE_PARENT, | |
1849 | .ops = &clk_branch2_ops, | |
1850 | }, | |
1851 | }, | |
1852 | }; | |
1853 | ||
1854 | static struct clk_branch gcc_camss_csi2phytimer_clk = { | |
1855 | .halt_reg = 0x5305c, | |
1856 | .halt_check = BRANCH_HALT, | |
1857 | .clkr = { | |
1858 | .enable_reg = 0x5305c, | |
1859 | .enable_mask = BIT(0), | |
1860 | .hw.init = &(struct clk_init_data){ | |
1861 | .name = "gcc_camss_csi2phytimer_clk", | |
1862 | .parent_hws = (const struct clk_hw*[]){ | |
1863 | &gcc_camss_csi2phytimer_clk_src.clkr.hw, | |
1864 | }, | |
1865 | .num_parents = 1, | |
1866 | .flags = CLK_SET_RATE_PARENT, | |
1867 | .ops = &clk_branch2_ops, | |
1868 | }, | |
1869 | }, | |
1870 | }; | |
1871 | ||
1872 | static struct clk_branch gcc_camss_csi2pix_clk = { | |
1873 | .halt_reg = 0x550d4, | |
1874 | .halt_check = BRANCH_HALT, | |
1875 | .clkr = { | |
1876 | .enable_reg = 0x550d4, | |
1877 | .enable_mask = BIT(0), | |
1878 | .hw.init = &(struct clk_init_data){ | |
1879 | .name = "gcc_camss_csi2pix_clk", | |
1880 | .parent_hws = (const struct clk_hw*[]){ | |
1881 | &gcc_camss_csi2_clk_src.clkr.hw, | |
1882 | }, | |
1883 | .num_parents = 1, | |
1884 | .flags = CLK_SET_RATE_PARENT, | |
1885 | .ops = &clk_branch2_ops, | |
1886 | }, | |
1887 | }, | |
1888 | }; | |
1889 | ||
1890 | static struct clk_branch gcc_camss_csi2rdi_clk = { | |
1891 | .halt_reg = 0x550cc, | |
1892 | .halt_check = BRANCH_HALT, | |
1893 | .clkr = { | |
1894 | .enable_reg = 0x550cc, | |
1895 | .enable_mask = BIT(0), | |
1896 | .hw.init = &(struct clk_init_data){ | |
1897 | .name = "gcc_camss_csi2rdi_clk", | |
1898 | .parent_hws = (const struct clk_hw*[]){ | |
1899 | &gcc_camss_csi2_clk_src.clkr.hw, | |
1900 | }, | |
1901 | .num_parents = 1, | |
1902 | .flags = CLK_SET_RATE_PARENT, | |
1903 | .ops = &clk_branch2_ops, | |
1904 | }, | |
1905 | }, | |
1906 | }; | |
1907 | ||
1908 | static struct clk_branch gcc_camss_csi3_ahb_clk = { | |
1909 | .halt_reg = 0x55100, | |
1910 | .halt_check = BRANCH_HALT, | |
1911 | .clkr = { | |
1912 | .enable_reg = 0x55100, | |
1913 | .enable_mask = BIT(0), | |
1914 | .hw.init = &(struct clk_init_data){ | |
1915 | .name = "gcc_camss_csi3_ahb_clk", | |
1916 | .parent_hws = (const struct clk_hw*[]){ | |
1917 | &gcc_camss_ahb_clk_src.clkr.hw, | |
1918 | }, | |
1919 | .num_parents = 1, | |
1920 | .flags = CLK_SET_RATE_PARENT, | |
1921 | .ops = &clk_branch2_ops, | |
1922 | }, | |
1923 | }, | |
1924 | }; | |
1925 | ||
1926 | static struct clk_branch gcc_camss_csi3_clk = { | |
1927 | .halt_reg = 0x550f8, | |
1928 | .halt_check = BRANCH_HALT, | |
1929 | .clkr = { | |
1930 | .enable_reg = 0x550f8, | |
1931 | .enable_mask = BIT(0), | |
1932 | .hw.init = &(struct clk_init_data){ | |
1933 | .name = "gcc_camss_csi3_clk", | |
1934 | .parent_hws = (const struct clk_hw*[]){ | |
1935 | &gcc_camss_csi3_clk_src.clkr.hw, | |
1936 | }, | |
1937 | .num_parents = 1, | |
1938 | .flags = CLK_SET_RATE_PARENT, | |
1939 | .ops = &clk_branch2_ops, | |
1940 | }, | |
1941 | }, | |
1942 | }; | |
1943 | ||
1944 | static struct clk_branch gcc_camss_csi3pix_clk = { | |
1945 | .halt_reg = 0x55110, | |
1946 | .halt_check = BRANCH_HALT, | |
1947 | .clkr = { | |
1948 | .enable_reg = 0x55110, | |
1949 | .enable_mask = BIT(0), | |
1950 | .hw.init = &(struct clk_init_data){ | |
1951 | .name = "gcc_camss_csi3pix_clk", | |
1952 | .parent_hws = (const struct clk_hw*[]){ | |
1953 | &gcc_camss_csi3_clk_src.clkr.hw, | |
1954 | }, | |
1955 | .num_parents = 1, | |
1956 | .flags = CLK_SET_RATE_PARENT, | |
1957 | .ops = &clk_branch2_ops, | |
1958 | }, | |
1959 | }, | |
1960 | }; | |
1961 | ||
1962 | static struct clk_branch gcc_camss_csi3rdi_clk = { | |
1963 | .halt_reg = 0x55108, | |
1964 | .halt_check = BRANCH_HALT, | |
1965 | .clkr = { | |
1966 | .enable_reg = 0x55108, | |
1967 | .enable_mask = BIT(0), | |
1968 | .hw.init = &(struct clk_init_data){ | |
1969 | .name = "gcc_camss_csi3rdi_clk", | |
1970 | .parent_hws = (const struct clk_hw*[]){ | |
1971 | &gcc_camss_csi3_clk_src.clkr.hw, | |
1972 | }, | |
1973 | .num_parents = 1, | |
1974 | .flags = CLK_SET_RATE_PARENT, | |
1975 | .ops = &clk_branch2_ops, | |
1976 | }, | |
1977 | }, | |
1978 | }; | |
1979 | ||
1980 | static struct clk_branch gcc_camss_csi_vfe0_clk = { | |
1981 | .halt_reg = 0x54074, | |
1982 | .halt_check = BRANCH_HALT, | |
1983 | .clkr = { | |
1984 | .enable_reg = 0x54074, | |
1985 | .enable_mask = BIT(0), | |
1986 | .hw.init = &(struct clk_init_data){ | |
1987 | .name = "gcc_camss_csi_vfe0_clk", | |
1988 | .parent_hws = (const struct clk_hw*[]){ | |
1989 | &gcc_camss_vfe0_clk_src.clkr.hw, | |
1990 | }, | |
1991 | .num_parents = 1, | |
1992 | .flags = CLK_SET_RATE_PARENT, | |
1993 | .ops = &clk_branch2_ops, | |
1994 | }, | |
1995 | }, | |
1996 | }; | |
1997 | ||
1998 | static struct clk_branch gcc_camss_csi_vfe1_clk = { | |
1999 | .halt_reg = 0x54080, | |
2000 | .halt_check = BRANCH_HALT, | |
2001 | .clkr = { | |
2002 | .enable_reg = 0x54080, | |
2003 | .enable_mask = BIT(0), | |
2004 | .hw.init = &(struct clk_init_data){ | |
2005 | .name = "gcc_camss_csi_vfe1_clk", | |
2006 | .parent_hws = (const struct clk_hw*[]){ | |
2007 | &gcc_camss_vfe1_clk_src.clkr.hw, | |
2008 | }, | |
2009 | .num_parents = 1, | |
2010 | .flags = CLK_SET_RATE_PARENT, | |
2011 | .ops = &clk_branch2_ops, | |
2012 | }, | |
2013 | }, | |
2014 | }; | |
2015 | ||
2016 | static struct clk_branch gcc_camss_csiphy0_clk = { | |
2017 | .halt_reg = 0x55018, | |
2018 | .halt_check = BRANCH_HALT, | |
2019 | .clkr = { | |
2020 | .enable_reg = 0x55018, | |
2021 | .enable_mask = BIT(0), | |
2022 | .hw.init = &(struct clk_init_data){ | |
2023 | .name = "gcc_camss_csiphy0_clk", | |
2024 | .parent_hws = (const struct clk_hw*[]){ | |
2025 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
2026 | }, | |
2027 | .num_parents = 1, | |
2028 | .flags = CLK_SET_RATE_PARENT, | |
2029 | .ops = &clk_branch2_ops, | |
2030 | }, | |
2031 | }, | |
2032 | }; | |
2033 | ||
2034 | static struct clk_branch gcc_camss_csiphy1_clk = { | |
2035 | .halt_reg = 0x5501c, | |
2036 | .halt_check = BRANCH_HALT, | |
2037 | .clkr = { | |
2038 | .enable_reg = 0x5501c, | |
2039 | .enable_mask = BIT(0), | |
2040 | .hw.init = &(struct clk_init_data){ | |
2041 | .name = "gcc_camss_csiphy1_clk", | |
2042 | .parent_hws = (const struct clk_hw*[]){ | |
2043 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
2044 | }, | |
2045 | .num_parents = 1, | |
2046 | .flags = CLK_SET_RATE_PARENT, | |
2047 | .ops = &clk_branch2_ops, | |
2048 | }, | |
2049 | }, | |
2050 | }; | |
2051 | ||
2052 | static struct clk_branch gcc_camss_csiphy2_clk = { | |
2053 | .halt_reg = 0x55020, | |
2054 | .halt_check = BRANCH_HALT, | |
2055 | .clkr = { | |
2056 | .enable_reg = 0x55020, | |
2057 | .enable_mask = BIT(0), | |
2058 | .hw.init = &(struct clk_init_data){ | |
2059 | .name = "gcc_camss_csiphy2_clk", | |
2060 | .parent_hws = (const struct clk_hw*[]){ | |
2061 | &gcc_camss_csiphy_clk_src.clkr.hw, | |
2062 | }, | |
2063 | .num_parents = 1, | |
2064 | .flags = CLK_SET_RATE_PARENT, | |
2065 | .ops = &clk_branch2_ops, | |
2066 | }, | |
2067 | }, | |
2068 | }; | |
2069 | ||
2070 | static struct clk_branch gcc_camss_gp0_clk = { | |
2071 | .halt_reg = 0x50018, | |
2072 | .halt_check = BRANCH_HALT, | |
2073 | .clkr = { | |
2074 | .enable_reg = 0x50018, | |
2075 | .enable_mask = BIT(0), | |
2076 | .hw.init = &(struct clk_init_data){ | |
2077 | .name = "gcc_camss_gp0_clk", | |
2078 | .parent_hws = (const struct clk_hw*[]){ | |
2079 | &gcc_camss_gp0_clk_src.clkr.hw, | |
2080 | }, | |
2081 | .num_parents = 1, | |
2082 | .flags = CLK_SET_RATE_PARENT, | |
2083 | .ops = &clk_branch2_ops, | |
2084 | }, | |
2085 | }, | |
2086 | }; | |
2087 | ||
2088 | static struct clk_branch gcc_camss_gp1_clk = { | |
2089 | .halt_reg = 0x50034, | |
2090 | .halt_check = BRANCH_HALT, | |
2091 | .clkr = { | |
2092 | .enable_reg = 0x50034, | |
2093 | .enable_mask = BIT(0), | |
2094 | .hw.init = &(struct clk_init_data){ | |
2095 | .name = "gcc_camss_gp1_clk", | |
2096 | .parent_hws = (const struct clk_hw*[]){ | |
2097 | &gcc_camss_gp1_clk_src.clkr.hw, | |
2098 | }, | |
2099 | .num_parents = 1, | |
2100 | .flags = CLK_SET_RATE_PARENT, | |
2101 | .ops = &clk_branch2_ops, | |
2102 | }, | |
2103 | }, | |
2104 | }; | |
2105 | ||
2106 | static struct clk_branch gcc_camss_ispif_ahb_clk = { | |
2107 | .halt_reg = 0x540a4, | |
2108 | .halt_check = BRANCH_HALT, | |
2109 | .clkr = { | |
2110 | .enable_reg = 0x540a4, | |
2111 | .enable_mask = BIT(0), | |
2112 | .hw.init = &(struct clk_init_data){ | |
2113 | .name = "gcc_camss_ispif_ahb_clk", | |
2114 | .parent_hws = (const struct clk_hw*[]){ | |
2115 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2116 | }, | |
2117 | .num_parents = 1, | |
2118 | .flags = CLK_SET_RATE_PARENT, | |
2119 | .ops = &clk_branch2_ops, | |
2120 | }, | |
2121 | }, | |
2122 | }; | |
2123 | ||
2124 | static struct clk_branch gcc_camss_jpeg_ahb_clk = { | |
2125 | .halt_reg = 0x52048, | |
2126 | .halt_check = BRANCH_HALT, | |
2127 | .clkr = { | |
2128 | .enable_reg = 0x52048, | |
2129 | .enable_mask = BIT(0), | |
2130 | .hw.init = &(struct clk_init_data){ | |
2131 | .name = "gcc_camss_jpeg_ahb_clk", | |
2132 | .parent_hws = (const struct clk_hw*[]){ | |
2133 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2134 | }, | |
2135 | .num_parents = 1, | |
2136 | .flags = CLK_SET_RATE_PARENT, | |
2137 | .ops = &clk_branch2_ops, | |
2138 | }, | |
2139 | }, | |
2140 | }; | |
2141 | ||
2142 | static struct clk_branch gcc_camss_jpeg_axi_clk = { | |
2143 | .halt_reg = 0x5204c, | |
2144 | .halt_check = BRANCH_HALT, | |
2145 | .clkr = { | |
2146 | .enable_reg = 0x5204c, | |
2147 | .enable_mask = BIT(0), | |
2148 | .hw.init = &(struct clk_init_data){ | |
2149 | .name = "gcc_camss_jpeg_axi_clk", | |
2150 | .ops = &clk_branch2_ops, | |
2151 | }, | |
2152 | }, | |
2153 | }; | |
2154 | ||
2155 | static struct clk_branch gcc_camss_jpeg_clk = { | |
2156 | .halt_reg = 0x52040, | |
2157 | .halt_check = BRANCH_HALT, | |
2158 | .clkr = { | |
2159 | .enable_reg = 0x52040, | |
2160 | .enable_mask = BIT(0), | |
2161 | .hw.init = &(struct clk_init_data){ | |
2162 | .name = "gcc_camss_jpeg_clk", | |
2163 | .parent_hws = (const struct clk_hw*[]){ | |
2164 | &gcc_camss_jpeg_clk_src.clkr.hw, | |
2165 | }, | |
2166 | .num_parents = 1, | |
2167 | .flags = CLK_SET_RATE_PARENT, | |
2168 | .ops = &clk_branch2_ops, | |
2169 | }, | |
2170 | }, | |
2171 | }; | |
2172 | ||
2173 | static struct clk_branch gcc_camss_mclk0_clk = { | |
2174 | .halt_reg = 0x51018, | |
2175 | .halt_check = BRANCH_HALT, | |
2176 | .clkr = { | |
2177 | .enable_reg = 0x51018, | |
2178 | .enable_mask = BIT(0), | |
2179 | .hw.init = &(struct clk_init_data){ | |
2180 | .name = "gcc_camss_mclk0_clk", | |
2181 | .parent_hws = (const struct clk_hw*[]){ | |
2182 | &gcc_camss_mclk0_clk_src.clkr.hw, | |
2183 | }, | |
2184 | .num_parents = 1, | |
2185 | .flags = CLK_SET_RATE_PARENT, | |
2186 | .ops = &clk_branch2_ops, | |
2187 | }, | |
2188 | }, | |
2189 | }; | |
2190 | ||
2191 | static struct clk_branch gcc_camss_mclk1_clk = { | |
2192 | .halt_reg = 0x51034, | |
2193 | .halt_check = BRANCH_HALT, | |
2194 | .clkr = { | |
2195 | .enable_reg = 0x51034, | |
2196 | .enable_mask = BIT(0), | |
2197 | .hw.init = &(struct clk_init_data){ | |
2198 | .name = "gcc_camss_mclk1_clk", | |
2199 | .parent_hws = (const struct clk_hw*[]){ | |
2200 | &gcc_camss_mclk1_clk_src.clkr.hw, | |
2201 | }, | |
2202 | .num_parents = 1, | |
2203 | .flags = CLK_SET_RATE_PARENT, | |
2204 | .ops = &clk_branch2_ops, | |
2205 | }, | |
2206 | }, | |
2207 | }; | |
2208 | ||
2209 | static struct clk_branch gcc_camss_mclk2_clk = { | |
2210 | .halt_reg = 0x51050, | |
2211 | .halt_check = BRANCH_HALT, | |
2212 | .clkr = { | |
2213 | .enable_reg = 0x51050, | |
2214 | .enable_mask = BIT(0), | |
2215 | .hw.init = &(struct clk_init_data){ | |
2216 | .name = "gcc_camss_mclk2_clk", | |
2217 | .parent_hws = (const struct clk_hw*[]){ | |
2218 | &gcc_camss_mclk2_clk_src.clkr.hw, | |
2219 | }, | |
2220 | .num_parents = 1, | |
2221 | .flags = CLK_SET_RATE_PARENT, | |
2222 | .ops = &clk_branch2_ops, | |
2223 | }, | |
2224 | }, | |
2225 | }; | |
2226 | ||
2227 | static struct clk_branch gcc_camss_mclk3_clk = { | |
2228 | .halt_reg = 0x5106c, | |
2229 | .halt_check = BRANCH_HALT, | |
2230 | .clkr = { | |
2231 | .enable_reg = 0x5106c, | |
2232 | .enable_mask = BIT(0), | |
2233 | .hw.init = &(struct clk_init_data){ | |
2234 | .name = "gcc_camss_mclk3_clk", | |
2235 | .parent_hws = (const struct clk_hw*[]){ | |
2236 | &gcc_camss_mclk3_clk_src.clkr.hw, | |
2237 | }, | |
2238 | .num_parents = 1, | |
2239 | .flags = CLK_SET_RATE_PARENT, | |
2240 | .ops = &clk_branch2_ops, | |
2241 | }, | |
2242 | }, | |
2243 | }; | |
2244 | ||
2245 | static struct clk_branch gcc_camss_micro_ahb_clk = { | |
2246 | .halt_reg = 0x560b0, | |
2247 | .halt_check = BRANCH_HALT, | |
2248 | .clkr = { | |
2249 | .enable_reg = 0x560b0, | |
2250 | .enable_mask = BIT(0), | |
2251 | .hw.init = &(struct clk_init_data){ | |
2252 | .name = "gcc_camss_micro_ahb_clk", | |
2253 | .parent_hws = (const struct clk_hw*[]){ | |
2254 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2255 | }, | |
2256 | .num_parents = 1, | |
2257 | .flags = CLK_SET_RATE_PARENT, | |
2258 | .ops = &clk_branch2_ops, | |
2259 | }, | |
2260 | }, | |
2261 | }; | |
2262 | ||
2263 | static struct clk_branch gcc_camss_throttle_nrt_axi_clk = { | |
2264 | .halt_reg = 0x560a4, | |
2265 | .halt_check = BRANCH_HALT_VOTED, | |
2266 | .clkr = { | |
2267 | .enable_reg = 0x79004, | |
2268 | .enable_mask = BIT(27), | |
2269 | .hw.init = &(struct clk_init_data){ | |
2270 | .name = "gcc_camss_throttle_nrt_axi_clk", | |
2271 | .ops = &clk_branch2_ops, | |
2272 | }, | |
2273 | }, | |
2274 | }; | |
2275 | ||
2276 | static struct clk_branch gcc_camss_throttle_rt_axi_clk = { | |
2277 | .halt_reg = 0x560a8, | |
2278 | .halt_check = BRANCH_HALT_VOTED, | |
2279 | .clkr = { | |
2280 | .enable_reg = 0x79004, | |
2281 | .enable_mask = BIT(26), | |
2282 | .hw.init = &(struct clk_init_data){ | |
2283 | .name = "gcc_camss_throttle_rt_axi_clk", | |
2284 | .ops = &clk_branch2_ops, | |
2285 | }, | |
2286 | }, | |
2287 | }; | |
2288 | ||
2289 | static struct clk_branch gcc_camss_top_ahb_clk = { | |
2290 | .halt_reg = 0x560a0, | |
2291 | .halt_check = BRANCH_HALT, | |
2292 | .clkr = { | |
2293 | .enable_reg = 0x560a0, | |
2294 | .enable_mask = BIT(0), | |
2295 | .hw.init = &(struct clk_init_data){ | |
2296 | .name = "gcc_camss_top_ahb_clk", | |
2297 | .parent_hws = (const struct clk_hw*[]){ | |
2298 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2299 | }, | |
2300 | .num_parents = 1, | |
2301 | .flags = CLK_SET_RATE_PARENT, | |
2302 | .ops = &clk_branch2_ops, | |
2303 | }, | |
2304 | }, | |
2305 | }; | |
2306 | ||
2307 | static struct clk_branch gcc_camss_vfe0_ahb_clk = { | |
2308 | .halt_reg = 0x54034, | |
2309 | .halt_check = BRANCH_HALT, | |
2310 | .clkr = { | |
2311 | .enable_reg = 0x54034, | |
2312 | .enable_mask = BIT(0), | |
2313 | .hw.init = &(struct clk_init_data){ | |
2314 | .name = "gcc_camss_vfe0_ahb_clk", | |
2315 | .parent_hws = (const struct clk_hw*[]){ | |
2316 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2317 | }, | |
2318 | .num_parents = 1, | |
2319 | .flags = CLK_SET_RATE_PARENT, | |
2320 | .ops = &clk_branch2_ops, | |
2321 | }, | |
2322 | }, | |
2323 | }; | |
2324 | ||
2325 | static struct clk_branch gcc_camss_vfe0_clk = { | |
2326 | .halt_reg = 0x54028, | |
2327 | .halt_check = BRANCH_HALT, | |
2328 | .clkr = { | |
2329 | .enable_reg = 0x54028, | |
2330 | .enable_mask = BIT(0), | |
2331 | .hw.init = &(struct clk_init_data){ | |
2332 | .name = "gcc_camss_vfe0_clk", | |
2333 | .parent_hws = (const struct clk_hw*[]){ | |
2334 | &gcc_camss_vfe0_clk_src.clkr.hw, | |
2335 | }, | |
2336 | .num_parents = 1, | |
2337 | .flags = CLK_SET_RATE_PARENT, | |
2338 | .ops = &clk_branch2_ops, | |
2339 | }, | |
2340 | }, | |
2341 | }; | |
2342 | ||
2343 | static struct clk_branch gcc_camss_vfe0_stream_clk = { | |
2344 | .halt_reg = 0x54030, | |
2345 | .halt_check = BRANCH_HALT, | |
2346 | .clkr = { | |
2347 | .enable_reg = 0x54030, | |
2348 | .enable_mask = BIT(0), | |
2349 | .hw.init = &(struct clk_init_data){ | |
2350 | .name = "gcc_camss_vfe0_stream_clk", | |
2351 | .parent_hws = (const struct clk_hw*[]){ | |
2352 | &gcc_camss_vfe0_clk_src.clkr.hw, | |
2353 | }, | |
2354 | .num_parents = 1, | |
2355 | .flags = CLK_SET_RATE_PARENT, | |
2356 | .ops = &clk_branch2_ops, | |
2357 | }, | |
2358 | }, | |
2359 | }; | |
2360 | ||
2361 | static struct clk_branch gcc_camss_vfe1_ahb_clk = { | |
2362 | .halt_reg = 0x5406c, | |
2363 | .halt_check = BRANCH_HALT, | |
2364 | .clkr = { | |
2365 | .enable_reg = 0x5406c, | |
2366 | .enable_mask = BIT(0), | |
2367 | .hw.init = &(struct clk_init_data){ | |
2368 | .name = "gcc_camss_vfe1_ahb_clk", | |
2369 | .parent_hws = (const struct clk_hw*[]){ | |
2370 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2371 | }, | |
2372 | .num_parents = 1, | |
2373 | .flags = CLK_SET_RATE_PARENT, | |
2374 | .ops = &clk_branch2_ops, | |
2375 | }, | |
2376 | }, | |
2377 | }; | |
2378 | ||
2379 | static struct clk_branch gcc_camss_vfe1_clk = { | |
2380 | .halt_reg = 0x54060, | |
2381 | .halt_check = BRANCH_HALT, | |
2382 | .clkr = { | |
2383 | .enable_reg = 0x54060, | |
2384 | .enable_mask = BIT(0), | |
2385 | .hw.init = &(struct clk_init_data){ | |
2386 | .name = "gcc_camss_vfe1_clk", | |
2387 | .parent_hws = (const struct clk_hw*[]){ | |
2388 | &gcc_camss_vfe1_clk_src.clkr.hw, | |
2389 | }, | |
2390 | .num_parents = 1, | |
2391 | .flags = CLK_SET_RATE_PARENT, | |
2392 | .ops = &clk_branch2_ops, | |
2393 | }, | |
2394 | }, | |
2395 | }; | |
2396 | ||
2397 | static struct clk_branch gcc_camss_vfe1_stream_clk = { | |
2398 | .halt_reg = 0x54068, | |
2399 | .halt_check = BRANCH_HALT, | |
2400 | .clkr = { | |
2401 | .enable_reg = 0x54068, | |
2402 | .enable_mask = BIT(0), | |
2403 | .hw.init = &(struct clk_init_data){ | |
2404 | .name = "gcc_camss_vfe1_stream_clk", | |
2405 | .parent_hws = (const struct clk_hw*[]){ | |
2406 | &gcc_camss_vfe1_clk_src.clkr.hw, | |
2407 | }, | |
2408 | .num_parents = 1, | |
2409 | .flags = CLK_SET_RATE_PARENT, | |
2410 | .ops = &clk_branch2_ops, | |
2411 | }, | |
2412 | }, | |
2413 | }; | |
2414 | ||
2415 | static struct clk_branch gcc_camss_vfe_tsctr_clk = { | |
2416 | .halt_reg = 0x5409c, | |
2417 | .halt_check = BRANCH_HALT, | |
2418 | .clkr = { | |
2419 | .enable_reg = 0x5409c, | |
2420 | .enable_mask = BIT(0), | |
2421 | .hw.init = &(struct clk_init_data){ | |
2422 | .name = "gcc_camss_vfe_tsctr_clk", | |
2423 | .ops = &clk_branch2_ops, | |
2424 | }, | |
2425 | }, | |
2426 | }; | |
2427 | ||
2428 | static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = { | |
2429 | .halt_reg = 0x5408c, | |
2430 | .halt_check = BRANCH_HALT, | |
2431 | .clkr = { | |
2432 | .enable_reg = 0x5408c, | |
2433 | .enable_mask = BIT(0), | |
2434 | .hw.init = &(struct clk_init_data){ | |
2435 | .name = "gcc_camss_vfe_vbif_ahb_clk", | |
2436 | .parent_hws = (const struct clk_hw*[]){ | |
2437 | &gcc_camss_ahb_clk_src.clkr.hw, | |
2438 | }, | |
2439 | .num_parents = 1, | |
2440 | .flags = CLK_SET_RATE_PARENT, | |
2441 | .ops = &clk_branch2_ops, | |
2442 | }, | |
2443 | }, | |
2444 | }; | |
2445 | ||
2446 | static struct clk_branch gcc_camss_vfe_vbif_axi_clk = { | |
2447 | .halt_reg = 0x54090, | |
2448 | .halt_check = BRANCH_HALT, | |
2449 | .clkr = { | |
2450 | .enable_reg = 0x54090, | |
2451 | .enable_mask = BIT(0), | |
2452 | .hw.init = &(struct clk_init_data){ | |
2453 | .name = "gcc_camss_vfe_vbif_axi_clk", | |
2454 | .ops = &clk_branch2_ops, | |
2455 | }, | |
2456 | }, | |
2457 | }; | |
2458 | ||
2459 | static struct clk_branch gcc_ce1_ahb_clk = { | |
2460 | .halt_reg = 0x2700c, | |
2461 | .halt_check = BRANCH_HALT_VOTED, | |
2462 | .hwcg_reg = 0x2700c, | |
2463 | .hwcg_bit = 1, | |
2464 | .clkr = { | |
2465 | .enable_reg = 0x79004, | |
2466 | .enable_mask = BIT(3), | |
2467 | .hw.init = &(struct clk_init_data){ | |
2468 | .name = "gcc_ce1_ahb_clk", | |
2469 | .ops = &clk_branch2_ops, | |
2470 | }, | |
2471 | }, | |
2472 | }; | |
2473 | ||
2474 | static struct clk_branch gcc_ce1_axi_clk = { | |
2475 | .halt_reg = 0x27008, | |
2476 | .halt_check = BRANCH_HALT_VOTED, | |
2477 | .clkr = { | |
2478 | .enable_reg = 0x79004, | |
2479 | .enable_mask = BIT(4), | |
2480 | .hw.init = &(struct clk_init_data){ | |
2481 | .name = "gcc_ce1_axi_clk", | |
2482 | .ops = &clk_branch2_ops, | |
2483 | }, | |
2484 | }, | |
2485 | }; | |
2486 | ||
2487 | static struct clk_branch gcc_ce1_clk = { | |
2488 | .halt_reg = 0x27004, | |
2489 | .halt_check = BRANCH_HALT_VOTED, | |
2490 | .clkr = { | |
2491 | .enable_reg = 0x79004, | |
2492 | .enable_mask = BIT(5), | |
2493 | .hw.init = &(struct clk_init_data){ | |
2494 | .name = "gcc_ce1_clk", | |
2495 | .ops = &clk_branch2_ops, | |
2496 | }, | |
2497 | }, | |
2498 | }; | |
2499 | ||
2500 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { | |
2501 | .halt_reg = 0x1a084, | |
2502 | .halt_check = BRANCH_HALT, | |
2503 | .clkr = { | |
2504 | .enable_reg = 0x1a084, | |
2505 | .enable_mask = BIT(0), | |
2506 | .hw.init = &(struct clk_init_data){ | |
2507 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", | |
2508 | .parent_hws = (const struct clk_hw*[]){ | |
2509 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
2510 | }, | |
2511 | .num_parents = 1, | |
2512 | .flags = CLK_SET_RATE_PARENT, | |
2513 | .ops = &clk_branch2_ops, | |
2514 | }, | |
2515 | }, | |
2516 | }; | |
2517 | ||
2518 | static struct clk_branch gcc_cpuss_gnoc_clk = { | |
2519 | .halt_reg = 0x2b004, | |
2520 | .halt_check = BRANCH_HALT_VOTED, | |
2521 | .hwcg_reg = 0x2b004, | |
2522 | .hwcg_bit = 1, | |
2523 | .clkr = { | |
2524 | .enable_reg = 0x79004, | |
2525 | .enable_mask = BIT(22), | |
2526 | .hw.init = &(struct clk_init_data){ | |
2527 | .name = "gcc_cpuss_gnoc_clk", | |
2528 | .flags = CLK_IS_CRITICAL, | |
2529 | .ops = &clk_branch2_ops, | |
2530 | }, | |
2531 | }, | |
2532 | }; | |
2533 | ||
2534 | static struct clk_branch gcc_disp_ahb_clk = { | |
2535 | .halt_reg = 0x1700c, | |
2536 | .halt_check = BRANCH_HALT, | |
2537 | .hwcg_reg = 0x1700c, | |
2538 | .hwcg_bit = 1, | |
2539 | .clkr = { | |
2540 | .enable_reg = 0x1700c, | |
2541 | .enable_mask = BIT(0), | |
2542 | .hw.init = &(struct clk_init_data){ | |
2543 | .name = "gcc_disp_ahb_clk", | |
2544 | .flags = CLK_IS_CRITICAL, | |
2545 | .ops = &clk_branch2_ops, | |
2546 | }, | |
2547 | }, | |
2548 | }; | |
2549 | ||
2550 | static struct clk_branch gcc_disp_gpll0_div_clk_src = { | |
2551 | .halt_check = BRANCH_HALT_DELAY, | |
2552 | .clkr = { | |
2553 | .enable_reg = 0x79004, | |
2554 | .enable_mask = BIT(20), | |
2555 | .hw.init = &(struct clk_init_data){ | |
2556 | .name = "gcc_disp_gpll0_div_clk_src", | |
2557 | .parent_hws = (const struct clk_hw*[]){ | |
2558 | &gpll0_out_early.clkr.hw, | |
2559 | }, | |
2560 | .num_parents = 1, | |
2561 | .ops = &clk_branch2_ops, | |
2562 | }, | |
2563 | }, | |
2564 | }; | |
2565 | ||
2566 | static struct clk_branch gcc_disp_hf_axi_clk = { | |
2567 | .halt_reg = 0x17020, | |
2568 | .halt_check = BRANCH_HALT, | |
2569 | .clkr = { | |
2570 | .enable_reg = 0x17020, | |
2571 | .enable_mask = BIT(0), | |
2572 | .hw.init = &(struct clk_init_data){ | |
2573 | .name = "gcc_disp_hf_axi_clk", | |
2574 | .ops = &clk_branch2_ops, | |
2575 | }, | |
2576 | }, | |
2577 | }; | |
2578 | ||
2579 | static struct clk_branch gcc_disp_throttle_core_clk = { | |
2580 | .halt_reg = 0x17064, | |
2581 | .halt_check = BRANCH_HALT_VOTED, | |
2582 | .clkr = { | |
2583 | .enable_reg = 0x7900c, | |
2584 | .enable_mask = BIT(5), | |
2585 | .hw.init = &(struct clk_init_data){ | |
2586 | .name = "gcc_disp_throttle_core_clk", | |
2587 | .ops = &clk_branch2_ops, | |
2588 | }, | |
2589 | }, | |
2590 | }; | |
2591 | ||
2592 | static struct clk_branch gcc_disp_xo_clk = { | |
2593 | .halt_reg = 0x1702c, | |
2594 | .halt_check = BRANCH_HALT, | |
2595 | .clkr = { | |
2596 | .enable_reg = 0x1702c, | |
2597 | .enable_mask = BIT(0), | |
2598 | .hw.init = &(struct clk_init_data){ | |
2599 | .name = "gcc_disp_xo_clk", | |
2600 | .flags = CLK_IS_CRITICAL, | |
2601 | .ops = &clk_branch2_ops, | |
2602 | }, | |
2603 | }, | |
2604 | }; | |
2605 | ||
2606 | static struct clk_branch gcc_gp1_clk = { | |
2607 | .halt_reg = 0x4d000, | |
2608 | .halt_check = BRANCH_HALT, | |
2609 | .clkr = { | |
2610 | .enable_reg = 0x4d000, | |
2611 | .enable_mask = BIT(0), | |
2612 | .hw.init = &(struct clk_init_data){ | |
2613 | .name = "gcc_gp1_clk", | |
2614 | .parent_hws = (const struct clk_hw*[]){ | |
2615 | &gcc_gp1_clk_src.clkr.hw, | |
2616 | }, | |
2617 | .num_parents = 1, | |
2618 | .flags = CLK_SET_RATE_PARENT, | |
2619 | .ops = &clk_branch2_ops, | |
2620 | }, | |
2621 | }, | |
2622 | }; | |
2623 | ||
2624 | static struct clk_branch gcc_gp2_clk = { | |
2625 | .halt_reg = 0x4e000, | |
2626 | .halt_check = BRANCH_HALT, | |
2627 | .clkr = { | |
2628 | .enable_reg = 0x4e000, | |
2629 | .enable_mask = BIT(0), | |
2630 | .hw.init = &(struct clk_init_data){ | |
2631 | .name = "gcc_gp2_clk", | |
2632 | .parent_hws = (const struct clk_hw*[]){ | |
2633 | &gcc_gp2_clk_src.clkr.hw, | |
2634 | }, | |
2635 | .num_parents = 1, | |
2636 | .flags = CLK_SET_RATE_PARENT, | |
2637 | .ops = &clk_branch2_ops, | |
2638 | }, | |
2639 | }, | |
2640 | }; | |
2641 | ||
2642 | static struct clk_branch gcc_gp3_clk = { | |
2643 | .halt_reg = 0x4f000, | |
2644 | .halt_check = BRANCH_HALT, | |
2645 | .clkr = { | |
2646 | .enable_reg = 0x4f000, | |
2647 | .enable_mask = BIT(0), | |
2648 | .hw.init = &(struct clk_init_data){ | |
2649 | .name = "gcc_gp3_clk", | |
2650 | .parent_hws = (const struct clk_hw*[]){ | |
2651 | &gcc_gp3_clk_src.clkr.hw, | |
2652 | }, | |
2653 | .num_parents = 1, | |
2654 | .flags = CLK_SET_RATE_PARENT, | |
2655 | .ops = &clk_branch2_ops, | |
2656 | }, | |
2657 | }, | |
2658 | }; | |
2659 | ||
2660 | static struct clk_branch gcc_gpu_cfg_ahb_clk = { | |
2661 | .halt_reg = 0x36004, | |
2662 | .halt_check = BRANCH_HALT, | |
2663 | .hwcg_reg = 0x36004, | |
2664 | .hwcg_bit = 1, | |
2665 | .clkr = { | |
2666 | .enable_reg = 0x36004, | |
2667 | .enable_mask = BIT(0), | |
2668 | .hw.init = &(struct clk_init_data){ | |
2669 | .name = "gcc_gpu_cfg_ahb_clk", | |
2670 | .flags = CLK_IS_CRITICAL, | |
2671 | .ops = &clk_branch2_ops, | |
2672 | }, | |
2673 | }, | |
2674 | }; | |
2675 | ||
2676 | static struct clk_branch gcc_gpu_gpll0_clk_src = { | |
2677 | .halt_check = BRANCH_HALT_DELAY, | |
2678 | .clkr = { | |
2679 | .enable_reg = 0x79004, | |
2680 | .enable_mask = BIT(15), | |
2681 | .hw.init = &(struct clk_init_data){ | |
2682 | .name = "gcc_gpu_gpll0_clk_src", | |
2683 | .parent_hws = (const struct clk_hw*[]){ | |
2684 | &gpll0_out_early.clkr.hw, | |
2685 | }, | |
2686 | .num_parents = 1, | |
2687 | .ops = &clk_branch2_ops, | |
2688 | }, | |
2689 | }, | |
2690 | }; | |
2691 | ||
2692 | static struct clk_branch gcc_gpu_gpll0_div_clk_src = { | |
2693 | .halt_check = BRANCH_HALT_DELAY, | |
2694 | .clkr = { | |
2695 | .enable_reg = 0x79004, | |
2696 | .enable_mask = BIT(16), | |
2697 | .hw.init = &(struct clk_init_data){ | |
2698 | .name = "gcc_gpu_gpll0_div_clk_src", | |
2699 | .parent_hws = (const struct clk_hw*[]){ | |
2700 | &gpll0_out_aux2.hw, | |
2701 | }, | |
2702 | .num_parents = 1, | |
2703 | .ops = &clk_branch2_ops, | |
2704 | }, | |
2705 | }, | |
2706 | }; | |
2707 | ||
2708 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { | |
2709 | .halt_reg = 0x3600c, | |
2710 | .halt_check = BRANCH_VOTED, | |
2711 | .clkr = { | |
2712 | .enable_reg = 0x3600c, | |
2713 | .enable_mask = BIT(0), | |
2714 | .hw.init = &(struct clk_init_data){ | |
2715 | .name = "gcc_gpu_memnoc_gfx_clk", | |
2716 | .ops = &clk_branch2_ops, | |
2717 | }, | |
2718 | }, | |
2719 | }; | |
2720 | ||
2721 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { | |
2722 | .halt_reg = 0x36018, | |
2723 | .halt_check = BRANCH_HALT, | |
2724 | .clkr = { | |
2725 | .enable_reg = 0x36018, | |
2726 | .enable_mask = BIT(0), | |
2727 | .hw.init = &(struct clk_init_data){ | |
2728 | .name = "gcc_gpu_snoc_dvm_gfx_clk", | |
2729 | .ops = &clk_branch2_ops, | |
2730 | }, | |
2731 | }, | |
2732 | }; | |
2733 | ||
2734 | static struct clk_branch gcc_gpu_throttle_core_clk = { | |
2735 | .halt_reg = 0x36048, | |
2736 | .halt_check = BRANCH_HALT_VOTED, | |
2737 | .clkr = { | |
2738 | .enable_reg = 0x79004, | |
2739 | .enable_mask = BIT(31), | |
2740 | .hw.init = &(struct clk_init_data){ | |
2741 | .name = "gcc_gpu_throttle_core_clk", | |
2742 | .ops = &clk_branch2_ops, | |
2743 | }, | |
2744 | }, | |
2745 | }; | |
2746 | ||
2747 | static struct clk_branch gcc_gpu_throttle_xo_clk = { | |
2748 | .halt_reg = 0x36044, | |
2749 | .halt_check = BRANCH_HALT, | |
2750 | .clkr = { | |
2751 | .enable_reg = 0x36044, | |
2752 | .enable_mask = BIT(0), | |
2753 | .hw.init = &(struct clk_init_data){ | |
2754 | .name = "gcc_gpu_throttle_xo_clk", | |
2755 | .ops = &clk_branch2_ops, | |
2756 | }, | |
2757 | }, | |
2758 | }; | |
2759 | ||
2760 | static struct clk_branch gcc_mss_vs_clk = { | |
2761 | .halt_reg = 0x42048, | |
2762 | .halt_check = BRANCH_HALT, | |
2763 | .clkr = { | |
2764 | .enable_reg = 0x42048, | |
2765 | .enable_mask = BIT(0), | |
2766 | .hw.init = &(struct clk_init_data){ | |
2767 | .name = "gcc_mss_vs_clk", | |
2768 | .parent_hws = (const struct clk_hw*[]){ | |
2769 | &gcc_vsensor_clk_src.clkr.hw, | |
2770 | }, | |
2771 | .num_parents = 1, | |
2772 | .flags = CLK_SET_RATE_PARENT, | |
2773 | .ops = &clk_branch2_ops, | |
2774 | }, | |
2775 | }, | |
2776 | }; | |
2777 | ||
2778 | static struct clk_branch gcc_pdm2_clk = { | |
2779 | .halt_reg = 0x2000c, | |
2780 | .halt_check = BRANCH_HALT, | |
2781 | .clkr = { | |
2782 | .enable_reg = 0x2000c, | |
2783 | .enable_mask = BIT(0), | |
2784 | .hw.init = &(struct clk_init_data){ | |
2785 | .name = "gcc_pdm2_clk", | |
2786 | .parent_hws = (const struct clk_hw*[]){ | |
2787 | &gcc_pdm2_clk_src.clkr.hw, | |
2788 | }, | |
2789 | .num_parents = 1, | |
2790 | .flags = CLK_SET_RATE_PARENT, | |
2791 | .ops = &clk_branch2_ops, | |
2792 | }, | |
2793 | }, | |
2794 | }; | |
2795 | ||
2796 | static struct clk_branch gcc_pdm_ahb_clk = { | |
2797 | .halt_reg = 0x20004, | |
2798 | .halt_check = BRANCH_HALT, | |
2799 | .hwcg_reg = 0x20004, | |
2800 | .hwcg_bit = 1, | |
2801 | .clkr = { | |
2802 | .enable_reg = 0x20004, | |
2803 | .enable_mask = BIT(0), | |
2804 | .hw.init = &(struct clk_init_data){ | |
2805 | .name = "gcc_pdm_ahb_clk", | |
2806 | .ops = &clk_branch2_ops, | |
2807 | }, | |
2808 | }, | |
2809 | }; | |
2810 | ||
2811 | static struct clk_branch gcc_pdm_xo4_clk = { | |
2812 | .halt_reg = 0x20008, | |
2813 | .halt_check = BRANCH_HALT, | |
2814 | .clkr = { | |
2815 | .enable_reg = 0x20008, | |
2816 | .enable_mask = BIT(0), | |
2817 | .hw.init = &(struct clk_init_data){ | |
2818 | .name = "gcc_pdm_xo4_clk", | |
2819 | .ops = &clk_branch2_ops, | |
2820 | }, | |
2821 | }, | |
2822 | }; | |
2823 | ||
2824 | static struct clk_branch gcc_prng_ahb_clk = { | |
2825 | .halt_reg = 0x21004, | |
2826 | .halt_check = BRANCH_HALT_VOTED, | |
2827 | .hwcg_reg = 0x21004, | |
2828 | .hwcg_bit = 1, | |
2829 | .clkr = { | |
2830 | .enable_reg = 0x79004, | |
2831 | .enable_mask = BIT(13), | |
2832 | .hw.init = &(struct clk_init_data){ | |
2833 | .name = "gcc_prng_ahb_clk", | |
2834 | .ops = &clk_branch2_ops, | |
2835 | }, | |
2836 | }, | |
2837 | }; | |
2838 | ||
2839 | static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { | |
2840 | .halt_reg = 0x17014, | |
2841 | .halt_check = BRANCH_HALT, | |
2842 | .hwcg_reg = 0x17014, | |
2843 | .hwcg_bit = 1, | |
2844 | .clkr = { | |
2845 | .enable_reg = 0x7900c, | |
2846 | .enable_mask = BIT(0), | |
2847 | .hw.init = &(struct clk_init_data){ | |
2848 | .name = "gcc_qmip_camera_nrt_ahb_clk", | |
2849 | .ops = &clk_branch2_ops, | |
2850 | }, | |
2851 | }, | |
2852 | }; | |
2853 | ||
2854 | static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { | |
2855 | .halt_reg = 0x17060, | |
2856 | .halt_check = BRANCH_HALT_VOTED, | |
2857 | .hwcg_reg = 0x17060, | |
2858 | .hwcg_bit = 1, | |
2859 | .clkr = { | |
2860 | .enable_reg = 0x7900c, | |
2861 | .enable_mask = BIT(2), | |
2862 | .hw.init = &(struct clk_init_data){ | |
2863 | .name = "gcc_qmip_camera_rt_ahb_clk", | |
2864 | .ops = &clk_branch2_ops, | |
2865 | }, | |
2866 | }, | |
2867 | }; | |
2868 | ||
2869 | static struct clk_branch gcc_qmip_disp_ahb_clk = { | |
2870 | .halt_reg = 0x17018, | |
2871 | .halt_check = BRANCH_HALT, | |
2872 | .hwcg_reg = 0x17018, | |
2873 | .hwcg_bit = 1, | |
2874 | .clkr = { | |
2875 | .enable_reg = 0x7900c, | |
2876 | .enable_mask = BIT(1), | |
2877 | .hw.init = &(struct clk_init_data){ | |
2878 | .name = "gcc_qmip_disp_ahb_clk", | |
2879 | .ops = &clk_branch2_ops, | |
2880 | }, | |
2881 | }, | |
2882 | }; | |
2883 | ||
2884 | static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { | |
2885 | .halt_reg = 0x36040, | |
2886 | .halt_check = BRANCH_HALT_VOTED, | |
2887 | .hwcg_reg = 0x36040, | |
2888 | .hwcg_bit = 1, | |
2889 | .clkr = { | |
2890 | .enable_reg = 0x7900c, | |
2891 | .enable_mask = BIT(4), | |
2892 | .hw.init = &(struct clk_init_data){ | |
2893 | .name = "gcc_qmip_gpu_cfg_ahb_clk", | |
2894 | .ops = &clk_branch2_ops, | |
2895 | }, | |
2896 | }, | |
2897 | }; | |
2898 | ||
2899 | static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { | |
2900 | .halt_reg = 0x17010, | |
2901 | .halt_check = BRANCH_HALT, | |
2902 | .hwcg_reg = 0x17010, | |
2903 | .hwcg_bit = 1, | |
2904 | .clkr = { | |
2905 | .enable_reg = 0x79004, | |
2906 | .enable_mask = BIT(25), | |
2907 | .hw.init = &(struct clk_init_data){ | |
2908 | .name = "gcc_qmip_video_vcodec_ahb_clk", | |
2909 | .ops = &clk_branch2_ops, | |
2910 | }, | |
2911 | }, | |
2912 | }; | |
2913 | ||
2914 | static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { | |
2915 | .halt_reg = 0x1f014, | |
2916 | .halt_check = BRANCH_HALT_VOTED, | |
2917 | .clkr = { | |
2918 | .enable_reg = 0x7900c, | |
2919 | .enable_mask = BIT(9), | |
2920 | .hw.init = &(struct clk_init_data){ | |
2921 | .name = "gcc_qupv3_wrap0_core_2x_clk", | |
2922 | .ops = &clk_branch2_ops, | |
2923 | }, | |
2924 | }, | |
2925 | }; | |
2926 | ||
2927 | static struct clk_branch gcc_qupv3_wrap0_core_clk = { | |
2928 | .halt_reg = 0x1f00c, | |
2929 | .halt_check = BRANCH_HALT_VOTED, | |
2930 | .clkr = { | |
2931 | .enable_reg = 0x7900c, | |
2932 | .enable_mask = BIT(8), | |
2933 | .hw.init = &(struct clk_init_data){ | |
2934 | .name = "gcc_qupv3_wrap0_core_clk", | |
2935 | .ops = &clk_branch2_ops, | |
2936 | }, | |
2937 | }, | |
2938 | }; | |
2939 | ||
2940 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { | |
2941 | .halt_reg = 0x1f144, | |
2942 | .halt_check = BRANCH_HALT_VOTED, | |
2943 | .clkr = { | |
2944 | .enable_reg = 0x7900c, | |
2945 | .enable_mask = BIT(10), | |
2946 | .hw.init = &(struct clk_init_data){ | |
2947 | .name = "gcc_qupv3_wrap0_s0_clk", | |
2948 | .parent_hws = (const struct clk_hw*[]){ | |
2949 | &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, | |
2950 | }, | |
2951 | .num_parents = 1, | |
2952 | .flags = CLK_SET_RATE_PARENT, | |
2953 | .ops = &clk_branch2_ops, | |
2954 | }, | |
2955 | }, | |
2956 | }; | |
2957 | ||
2958 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { | |
2959 | .halt_reg = 0x1f274, | |
2960 | .halt_check = BRANCH_HALT_VOTED, | |
2961 | .clkr = { | |
2962 | .enable_reg = 0x7900c, | |
2963 | .enable_mask = BIT(11), | |
2964 | .hw.init = &(struct clk_init_data){ | |
2965 | .name = "gcc_qupv3_wrap0_s1_clk", | |
2966 | .parent_hws = (const struct clk_hw*[]){ | |
2967 | &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, | |
2968 | }, | |
2969 | .num_parents = 1, | |
2970 | .flags = CLK_SET_RATE_PARENT, | |
2971 | .ops = &clk_branch2_ops, | |
2972 | }, | |
2973 | }, | |
2974 | }; | |
2975 | ||
2976 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { | |
2977 | .halt_reg = 0x1f3a4, | |
2978 | .halt_check = BRANCH_HALT_VOTED, | |
2979 | .clkr = { | |
2980 | .enable_reg = 0x7900c, | |
2981 | .enable_mask = BIT(12), | |
2982 | .hw.init = &(struct clk_init_data){ | |
2983 | .name = "gcc_qupv3_wrap0_s2_clk", | |
2984 | .parent_hws = (const struct clk_hw*[]){ | |
2985 | &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, | |
2986 | }, | |
2987 | .num_parents = 1, | |
2988 | .flags = CLK_SET_RATE_PARENT, | |
2989 | .ops = &clk_branch2_ops, | |
2990 | }, | |
2991 | }, | |
2992 | }; | |
2993 | ||
2994 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { | |
2995 | .halt_reg = 0x1f4d4, | |
2996 | .halt_check = BRANCH_HALT_VOTED, | |
2997 | .clkr = { | |
2998 | .enable_reg = 0x7900c, | |
2999 | .enable_mask = BIT(13), | |
3000 | .hw.init = &(struct clk_init_data){ | |
3001 | .name = "gcc_qupv3_wrap0_s3_clk", | |
3002 | .parent_hws = (const struct clk_hw*[]){ | |
3003 | &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, | |
3004 | }, | |
3005 | .num_parents = 1, | |
3006 | .flags = CLK_SET_RATE_PARENT, | |
3007 | .ops = &clk_branch2_ops, | |
3008 | }, | |
3009 | }, | |
3010 | }; | |
3011 | ||
3012 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { | |
3013 | .halt_reg = 0x1f604, | |
3014 | .halt_check = BRANCH_HALT_VOTED, | |
3015 | .clkr = { | |
3016 | .enable_reg = 0x7900c, | |
3017 | .enable_mask = BIT(14), | |
3018 | .hw.init = &(struct clk_init_data){ | |
3019 | .name = "gcc_qupv3_wrap0_s4_clk", | |
3020 | .parent_hws = (const struct clk_hw*[]){ | |
3021 | &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, | |
3022 | }, | |
3023 | .num_parents = 1, | |
3024 | .flags = CLK_SET_RATE_PARENT, | |
3025 | .ops = &clk_branch2_ops, | |
3026 | }, | |
3027 | }, | |
3028 | }; | |
3029 | ||
3030 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { | |
3031 | .halt_reg = 0x1f734, | |
3032 | .halt_check = BRANCH_HALT_VOTED, | |
3033 | .clkr = { | |
3034 | .enable_reg = 0x7900c, | |
3035 | .enable_mask = BIT(15), | |
3036 | .hw.init = &(struct clk_init_data){ | |
3037 | .name = "gcc_qupv3_wrap0_s5_clk", | |
3038 | .parent_hws = (const struct clk_hw*[]){ | |
3039 | &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, | |
3040 | }, | |
3041 | .num_parents = 1, | |
3042 | .flags = CLK_SET_RATE_PARENT, | |
3043 | .ops = &clk_branch2_ops, | |
3044 | }, | |
3045 | }, | |
3046 | }; | |
3047 | ||
3048 | static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { | |
3049 | .halt_reg = 0x39014, | |
3050 | .halt_check = BRANCH_HALT_VOTED, | |
3051 | .clkr = { | |
3052 | .enable_reg = 0x7900c, | |
3053 | .enable_mask = BIT(18), | |
3054 | .hw.init = &(struct clk_init_data){ | |
3055 | .name = "gcc_qupv3_wrap1_core_2x_clk", | |
3056 | .ops = &clk_branch2_ops, | |
3057 | }, | |
3058 | }, | |
3059 | }; | |
3060 | ||
3061 | static struct clk_branch gcc_qupv3_wrap1_core_clk = { | |
3062 | .halt_reg = 0x3900c, | |
3063 | .halt_check = BRANCH_HALT_VOTED, | |
3064 | .clkr = { | |
3065 | .enable_reg = 0x7900c, | |
3066 | .enable_mask = BIT(19), | |
3067 | .hw.init = &(struct clk_init_data){ | |
3068 | .name = "gcc_qupv3_wrap1_core_clk", | |
3069 | .ops = &clk_branch2_ops, | |
3070 | }, | |
3071 | }, | |
3072 | }; | |
3073 | ||
3074 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { | |
3075 | .halt_reg = 0x39144, | |
3076 | .halt_check = BRANCH_HALT_VOTED, | |
3077 | .clkr = { | |
3078 | .enable_reg = 0x7900c, | |
3079 | .enable_mask = BIT(22), | |
3080 | .hw.init = &(struct clk_init_data){ | |
3081 | .name = "gcc_qupv3_wrap1_s0_clk", | |
3082 | .parent_hws = (const struct clk_hw*[]){ | |
3083 | &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, | |
3084 | }, | |
3085 | .num_parents = 1, | |
3086 | .flags = CLK_SET_RATE_PARENT, | |
3087 | .ops = &clk_branch2_ops, | |
3088 | }, | |
3089 | }, | |
3090 | }; | |
3091 | ||
3092 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { | |
3093 | .halt_reg = 0x39274, | |
3094 | .halt_check = BRANCH_HALT_VOTED, | |
3095 | .clkr = { | |
3096 | .enable_reg = 0x7900c, | |
3097 | .enable_mask = BIT(23), | |
3098 | .hw.init = &(struct clk_init_data){ | |
3099 | .name = "gcc_qupv3_wrap1_s1_clk", | |
3100 | .parent_hws = (const struct clk_hw*[]){ | |
3101 | &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, | |
3102 | }, | |
3103 | .num_parents = 1, | |
3104 | .flags = CLK_SET_RATE_PARENT, | |
3105 | .ops = &clk_branch2_ops, | |
3106 | }, | |
3107 | }, | |
3108 | }; | |
3109 | ||
3110 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { | |
3111 | .halt_reg = 0x393a4, | |
3112 | .halt_check = BRANCH_HALT_VOTED, | |
3113 | .clkr = { | |
3114 | .enable_reg = 0x7900c, | |
3115 | .enable_mask = BIT(24), | |
3116 | .hw.init = &(struct clk_init_data){ | |
3117 | .name = "gcc_qupv3_wrap1_s2_clk", | |
3118 | .parent_hws = (const struct clk_hw*[]){ | |
3119 | &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, | |
3120 | }, | |
3121 | .num_parents = 1, | |
3122 | .flags = CLK_SET_RATE_PARENT, | |
3123 | .ops = &clk_branch2_ops, | |
3124 | }, | |
3125 | }, | |
3126 | }; | |
3127 | ||
3128 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { | |
3129 | .halt_reg = 0x394d4, | |
3130 | .halt_check = BRANCH_HALT_VOTED, | |
3131 | .clkr = { | |
3132 | .enable_reg = 0x7900c, | |
3133 | .enable_mask = BIT(25), | |
3134 | .hw.init = &(struct clk_init_data){ | |
3135 | .name = "gcc_qupv3_wrap1_s3_clk", | |
3136 | .parent_hws = (const struct clk_hw*[]){ | |
3137 | &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, | |
3138 | }, | |
3139 | .num_parents = 1, | |
3140 | .flags = CLK_SET_RATE_PARENT, | |
3141 | .ops = &clk_branch2_ops, | |
3142 | }, | |
3143 | }, | |
3144 | }; | |
3145 | ||
3146 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { | |
3147 | .halt_reg = 0x39604, | |
3148 | .halt_check = BRANCH_HALT_VOTED, | |
3149 | .clkr = { | |
3150 | .enable_reg = 0x7900c, | |
3151 | .enable_mask = BIT(26), | |
3152 | .hw.init = &(struct clk_init_data){ | |
3153 | .name = "gcc_qupv3_wrap1_s4_clk", | |
3154 | .parent_hws = (const struct clk_hw*[]){ | |
3155 | &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, | |
3156 | }, | |
3157 | .num_parents = 1, | |
3158 | .flags = CLK_SET_RATE_PARENT, | |
3159 | .ops = &clk_branch2_ops, | |
3160 | }, | |
3161 | }, | |
3162 | }; | |
3163 | ||
3164 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { | |
3165 | .halt_reg = 0x39734, | |
3166 | .halt_check = BRANCH_HALT_VOTED, | |
3167 | .clkr = { | |
3168 | .enable_reg = 0x7900c, | |
3169 | .enable_mask = BIT(27), | |
3170 | .hw.init = &(struct clk_init_data){ | |
3171 | .name = "gcc_qupv3_wrap1_s5_clk", | |
3172 | .parent_hws = (const struct clk_hw*[]){ | |
3173 | &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, | |
3174 | }, | |
3175 | .num_parents = 1, | |
3176 | .flags = CLK_SET_RATE_PARENT, | |
3177 | .ops = &clk_branch2_ops, | |
3178 | }, | |
3179 | }, | |
3180 | }; | |
3181 | ||
3182 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { | |
3183 | .halt_reg = 0x1f004, | |
3184 | .halt_check = BRANCH_HALT_VOTED, | |
3185 | .clkr = { | |
3186 | .enable_reg = 0x7900c, | |
3187 | .enable_mask = BIT(6), | |
3188 | .hw.init = &(struct clk_init_data){ | |
3189 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", | |
3190 | .ops = &clk_branch2_ops, | |
3191 | }, | |
3192 | }, | |
3193 | }; | |
3194 | ||
3195 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { | |
3196 | .halt_reg = 0x1f008, | |
3197 | .halt_check = BRANCH_HALT_VOTED, | |
3198 | .hwcg_reg = 0x1f008, | |
3199 | .hwcg_bit = 1, | |
3200 | .clkr = { | |
3201 | .enable_reg = 0x7900c, | |
3202 | .enable_mask = BIT(7), | |
3203 | .hw.init = &(struct clk_init_data){ | |
3204 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", | |
3205 | .ops = &clk_branch2_ops, | |
3206 | }, | |
3207 | }, | |
3208 | }; | |
3209 | ||
3210 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { | |
3211 | .halt_reg = 0x39004, | |
3212 | .halt_check = BRANCH_HALT_VOTED, | |
3213 | .clkr = { | |
3214 | .enable_reg = 0x7900c, | |
3215 | .enable_mask = BIT(20), | |
3216 | .hw.init = &(struct clk_init_data){ | |
3217 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", | |
3218 | .ops = &clk_branch2_ops, | |
3219 | }, | |
3220 | }, | |
3221 | }; | |
3222 | ||
3223 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { | |
3224 | .halt_reg = 0x39008, | |
3225 | .halt_check = BRANCH_HALT_VOTED, | |
3226 | .hwcg_reg = 0x39008, | |
3227 | .hwcg_bit = 1, | |
3228 | .clkr = { | |
3229 | .enable_reg = 0x7900c, | |
3230 | .enable_mask = BIT(21), | |
3231 | .hw.init = &(struct clk_init_data){ | |
3232 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", | |
3233 | .ops = &clk_branch2_ops, | |
3234 | }, | |
3235 | }, | |
3236 | }; | |
3237 | ||
3238 | static struct clk_branch gcc_sdcc1_ahb_clk = { | |
3239 | .halt_reg = 0x38008, | |
3240 | .halt_check = BRANCH_HALT, | |
3241 | .clkr = { | |
3242 | .enable_reg = 0x38008, | |
3243 | .enable_mask = BIT(0), | |
3244 | .hw.init = &(struct clk_init_data){ | |
3245 | .name = "gcc_sdcc1_ahb_clk", | |
3246 | .ops = &clk_branch2_ops, | |
3247 | }, | |
3248 | }, | |
3249 | }; | |
3250 | ||
3251 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
3252 | .halt_reg = 0x38004, | |
3253 | .halt_check = BRANCH_HALT, | |
3254 | .clkr = { | |
3255 | .enable_reg = 0x38004, | |
3256 | .enable_mask = BIT(0), | |
3257 | .hw.init = &(struct clk_init_data){ | |
3258 | .name = "gcc_sdcc1_apps_clk", | |
3259 | .parent_hws = (const struct clk_hw*[]){ | |
3260 | &gcc_sdcc1_apps_clk_src.clkr.hw, | |
3261 | }, | |
3262 | .num_parents = 1, | |
3263 | .flags = CLK_SET_RATE_PARENT, | |
3264 | .ops = &clk_branch2_ops, | |
3265 | }, | |
3266 | }, | |
3267 | }; | |
3268 | ||
3269 | static struct clk_branch gcc_sdcc1_ice_core_clk = { | |
3270 | .halt_reg = 0x3800c, | |
3271 | .halt_check = BRANCH_HALT, | |
3272 | .clkr = { | |
3273 | .enable_reg = 0x3800c, | |
3274 | .enable_mask = BIT(0), | |
3275 | .hw.init = &(struct clk_init_data){ | |
3276 | .name = "gcc_sdcc1_ice_core_clk", | |
3277 | .parent_hws = (const struct clk_hw*[]){ | |
3278 | &gcc_sdcc1_ice_core_clk_src.clkr.hw, | |
3279 | }, | |
3280 | .num_parents = 1, | |
3281 | .flags = CLK_SET_RATE_PARENT, | |
3282 | .ops = &clk_branch2_ops, | |
3283 | }, | |
3284 | }, | |
3285 | }; | |
3286 | ||
3287 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
3288 | .halt_reg = 0x1e008, | |
3289 | .halt_check = BRANCH_HALT, | |
3290 | .clkr = { | |
3291 | .enable_reg = 0x1e008, | |
3292 | .enable_mask = BIT(0), | |
3293 | .hw.init = &(struct clk_init_data){ | |
3294 | .name = "gcc_sdcc2_ahb_clk", | |
3295 | .ops = &clk_branch2_ops, | |
3296 | }, | |
3297 | }, | |
3298 | }; | |
3299 | ||
3300 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
3301 | .halt_reg = 0x1e004, | |
3302 | .halt_check = BRANCH_HALT, | |
3303 | .clkr = { | |
3304 | .enable_reg = 0x1e004, | |
3305 | .enable_mask = BIT(0), | |
3306 | .hw.init = &(struct clk_init_data){ | |
3307 | .name = "gcc_sdcc2_apps_clk", | |
3308 | .parent_hws = (const struct clk_hw*[]){ | |
3309 | &gcc_sdcc2_apps_clk_src.clkr.hw, | |
3310 | }, | |
3311 | .num_parents = 1, | |
3312 | .flags = CLK_SET_RATE_PARENT, | |
3313 | .ops = &clk_branch2_ops, | |
3314 | }, | |
3315 | }, | |
3316 | }; | |
3317 | ||
3318 | static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = { | |
3319 | .halt_reg = 0x1050c, | |
3320 | .halt_check = BRANCH_HALT, | |
3321 | .clkr = { | |
3322 | .enable_reg = 0x1050c, | |
3323 | .enable_mask = BIT(0), | |
3324 | .hw.init = &(struct clk_init_data){ | |
3325 | .name = "gcc_sys_noc_compute_sf_axi_clk", | |
3326 | .flags = CLK_IS_CRITICAL, | |
3327 | .ops = &clk_branch2_ops, | |
3328 | }, | |
3329 | }, | |
3330 | }; | |
3331 | ||
3332 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { | |
3333 | .halt_reg = 0x2b06c, | |
3334 | .halt_check = BRANCH_HALT_VOTED, | |
3335 | .clkr = { | |
3336 | .enable_reg = 0x79004, | |
3337 | .enable_mask = BIT(0), | |
3338 | .hw.init = &(struct clk_init_data){ | |
3339 | .name = "gcc_sys_noc_cpuss_ahb_clk", | |
3340 | .flags = CLK_IS_CRITICAL, | |
3341 | .ops = &clk_branch2_ops, | |
3342 | }, | |
3343 | }, | |
3344 | }; | |
3345 | ||
3346 | static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { | |
3347 | .halt_reg = 0x45098, | |
3348 | .halt_check = BRANCH_HALT, | |
3349 | .clkr = { | |
3350 | .enable_reg = 0x45098, | |
3351 | .enable_mask = BIT(0), | |
3352 | .hw.init = &(struct clk_init_data){ | |
3353 | .name = "gcc_sys_noc_ufs_phy_axi_clk", | |
3354 | .parent_hws = (const struct clk_hw*[]){ | |
3355 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
3356 | }, | |
3357 | .num_parents = 1, | |
3358 | .flags = CLK_SET_RATE_PARENT, | |
3359 | .ops = &clk_branch2_ops, | |
3360 | }, | |
3361 | }, | |
3362 | }; | |
3363 | ||
3364 | static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { | |
3365 | .halt_reg = 0x1a080, | |
3366 | .halt_check = BRANCH_HALT, | |
3367 | .clkr = { | |
3368 | .enable_reg = 0x1a080, | |
3369 | .enable_mask = BIT(0), | |
3370 | .hw.init = &(struct clk_init_data){ | |
3371 | .name = "gcc_sys_noc_usb3_prim_axi_clk", | |
3372 | .parent_hws = (const struct clk_hw*[]){ | |
3373 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
3374 | }, | |
3375 | .num_parents = 1, | |
3376 | .flags = CLK_SET_RATE_PARENT, | |
3377 | .ops = &clk_branch2_ops, | |
3378 | }, | |
3379 | }, | |
3380 | }; | |
3381 | ||
3382 | static struct clk_branch gcc_ufs_mem_clkref_clk = { | |
3383 | .halt_reg = 0x8c000, | |
3384 | .halt_check = BRANCH_HALT, | |
3385 | .clkr = { | |
3386 | .enable_reg = 0x8c000, | |
3387 | .enable_mask = BIT(0), | |
3388 | .hw.init = &(struct clk_init_data){ | |
3389 | .name = "gcc_ufs_mem_clkref_clk", | |
3390 | .ops = &clk_branch2_ops, | |
3391 | }, | |
3392 | }, | |
3393 | }; | |
3394 | ||
3395 | static struct clk_branch gcc_ufs_phy_ahb_clk = { | |
3396 | .halt_reg = 0x45014, | |
3397 | .halt_check = BRANCH_HALT, | |
3398 | .hwcg_reg = 0x45014, | |
3399 | .hwcg_bit = 1, | |
3400 | .clkr = { | |
3401 | .enable_reg = 0x45014, | |
3402 | .enable_mask = BIT(0), | |
3403 | .hw.init = &(struct clk_init_data){ | |
3404 | .name = "gcc_ufs_phy_ahb_clk", | |
3405 | .ops = &clk_branch2_ops, | |
3406 | }, | |
3407 | }, | |
3408 | }; | |
3409 | ||
3410 | static struct clk_branch gcc_ufs_phy_axi_clk = { | |
3411 | .halt_reg = 0x45010, | |
3412 | .halt_check = BRANCH_HALT, | |
3413 | .hwcg_reg = 0x45010, | |
3414 | .hwcg_bit = 1, | |
3415 | .clkr = { | |
3416 | .enable_reg = 0x45010, | |
3417 | .enable_mask = BIT(0), | |
3418 | .hw.init = &(struct clk_init_data){ | |
3419 | .name = "gcc_ufs_phy_axi_clk", | |
3420 | .parent_hws = (const struct clk_hw*[]){ | |
3421 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
3422 | }, | |
3423 | .num_parents = 1, | |
3424 | .flags = CLK_SET_RATE_PARENT, | |
3425 | .ops = &clk_branch2_ops, | |
3426 | }, | |
3427 | }, | |
3428 | }; | |
3429 | ||
3430 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { | |
3431 | .halt_reg = 0x45044, | |
3432 | .halt_check = BRANCH_HALT, | |
3433 | .hwcg_reg = 0x45044, | |
3434 | .hwcg_bit = 1, | |
3435 | .clkr = { | |
3436 | .enable_reg = 0x45044, | |
3437 | .enable_mask = BIT(0), | |
3438 | .hw.init = &(struct clk_init_data){ | |
3439 | .name = "gcc_ufs_phy_ice_core_clk", | |
3440 | .parent_hws = (const struct clk_hw*[]){ | |
3441 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw, | |
3442 | }, | |
3443 | .num_parents = 1, | |
3444 | .flags = CLK_SET_RATE_PARENT, | |
3445 | .ops = &clk_branch2_ops, | |
3446 | }, | |
3447 | }, | |
3448 | }; | |
3449 | ||
3450 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { | |
3451 | .halt_reg = 0x45078, | |
3452 | .halt_check = BRANCH_HALT, | |
3453 | .hwcg_reg = 0x45078, | |
3454 | .hwcg_bit = 1, | |
3455 | .clkr = { | |
3456 | .enable_reg = 0x45078, | |
3457 | .enable_mask = BIT(0), | |
3458 | .hw.init = &(struct clk_init_data){ | |
3459 | .name = "gcc_ufs_phy_phy_aux_clk", | |
3460 | .parent_hws = (const struct clk_hw*[]){ | |
3461 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, | |
3462 | }, | |
3463 | .num_parents = 1, | |
3464 | .flags = CLK_SET_RATE_PARENT, | |
3465 | .ops = &clk_branch2_ops, | |
3466 | }, | |
3467 | }, | |
3468 | }; | |
3469 | ||
3470 | static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { | |
3471 | .halt_reg = 0x4501c, | |
3472 | .halt_check = BRANCH_HALT_SKIP, | |
3473 | .clkr = { | |
3474 | .enable_reg = 0x4501c, | |
3475 | .enable_mask = BIT(0), | |
3476 | .hw.init = &(struct clk_init_data){ | |
3477 | .name = "gcc_ufs_phy_rx_symbol_0_clk", | |
3478 | .ops = &clk_branch2_ops, | |
3479 | }, | |
3480 | }, | |
3481 | }; | |
3482 | ||
3483 | static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { | |
3484 | .halt_reg = 0x45018, | |
3485 | .halt_check = BRANCH_HALT_SKIP, | |
3486 | .clkr = { | |
3487 | .enable_reg = 0x45018, | |
3488 | .enable_mask = BIT(0), | |
3489 | .hw.init = &(struct clk_init_data){ | |
3490 | .name = "gcc_ufs_phy_tx_symbol_0_clk", | |
3491 | .ops = &clk_branch2_ops, | |
3492 | }, | |
3493 | }, | |
3494 | }; | |
3495 | ||
3496 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { | |
3497 | .halt_reg = 0x45040, | |
3498 | .halt_check = BRANCH_HALT, | |
3499 | .hwcg_reg = 0x45040, | |
3500 | .hwcg_bit = 1, | |
3501 | .clkr = { | |
3502 | .enable_reg = 0x45040, | |
3503 | .enable_mask = BIT(0), | |
3504 | .hw.init = &(struct clk_init_data){ | |
3505 | .name = "gcc_ufs_phy_unipro_core_clk", | |
3506 | .parent_hws = (const struct clk_hw*[]){ | |
3507 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, | |
3508 | }, | |
3509 | .num_parents = 1, | |
3510 | .flags = CLK_SET_RATE_PARENT, | |
3511 | .ops = &clk_branch2_ops, | |
3512 | }, | |
3513 | }, | |
3514 | }; | |
3515 | ||
3516 | static struct clk_branch gcc_usb30_prim_master_clk = { | |
3517 | .halt_reg = 0x1a010, | |
3518 | .halt_check = BRANCH_HALT, | |
3519 | .clkr = { | |
3520 | .enable_reg = 0x1a010, | |
3521 | .enable_mask = BIT(0), | |
3522 | .hw.init = &(struct clk_init_data){ | |
3523 | .name = "gcc_usb30_prim_master_clk", | |
3524 | .parent_hws = (const struct clk_hw*[]){ | |
3525 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
3526 | }, | |
3527 | .num_parents = 1, | |
3528 | .flags = CLK_SET_RATE_PARENT, | |
3529 | .ops = &clk_branch2_ops, | |
3530 | }, | |
3531 | }, | |
3532 | }; | |
3533 | ||
3534 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { | |
3535 | .halt_reg = 0x1a018, | |
3536 | .halt_check = BRANCH_HALT, | |
3537 | .clkr = { | |
3538 | .enable_reg = 0x1a018, | |
3539 | .enable_mask = BIT(0), | |
3540 | .hw.init = &(struct clk_init_data){ | |
3541 | .name = "gcc_usb30_prim_mock_utmi_clk", | |
3542 | .parent_hws = (const struct clk_hw*[]){ | |
3543 | &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, | |
3544 | }, | |
3545 | .num_parents = 1, | |
3546 | .flags = CLK_SET_RATE_PARENT, | |
3547 | .ops = &clk_branch2_ops, | |
3548 | }, | |
3549 | }, | |
3550 | }; | |
3551 | ||
3552 | static struct clk_branch gcc_usb30_prim_sleep_clk = { | |
3553 | .halt_reg = 0x1a014, | |
3554 | .halt_check = BRANCH_HALT, | |
3555 | .clkr = { | |
3556 | .enable_reg = 0x1a014, | |
3557 | .enable_mask = BIT(0), | |
3558 | .hw.init = &(struct clk_init_data){ | |
3559 | .name = "gcc_usb30_prim_sleep_clk", | |
3560 | .ops = &clk_branch2_ops, | |
3561 | }, | |
3562 | }, | |
3563 | }; | |
3564 | ||
3565 | static struct clk_branch gcc_usb3_prim_clkref_clk = { | |
3566 | .halt_reg = 0x80278, | |
3567 | .halt_check = BRANCH_HALT, | |
3568 | .clkr = { | |
3569 | .enable_reg = 0x80278, | |
3570 | .enable_mask = BIT(0), | |
3571 | .hw.init = &(struct clk_init_data){ | |
3572 | .name = "gcc_usb3_prim_clkref_clk", | |
3573 | .ops = &clk_branch2_ops, | |
3574 | }, | |
3575 | }, | |
3576 | }; | |
3577 | ||
3578 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { | |
3579 | .halt_reg = 0x1a054, | |
3580 | .halt_check = BRANCH_HALT, | |
3581 | .clkr = { | |
3582 | .enable_reg = 0x1a054, | |
3583 | .enable_mask = BIT(0), | |
3584 | .hw.init = &(struct clk_init_data){ | |
3585 | .name = "gcc_usb3_prim_phy_com_aux_clk", | |
3586 | .parent_hws = (const struct clk_hw*[]){ | |
3587 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
3588 | }, | |
3589 | .num_parents = 1, | |
3590 | .flags = CLK_SET_RATE_PARENT, | |
3591 | .ops = &clk_branch2_ops, | |
3592 | }, | |
3593 | }, | |
3594 | }; | |
3595 | ||
3596 | static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { | |
3597 | .halt_check = BRANCH_HALT_SKIP, | |
3598 | .clkr = { | |
3599 | .enable_reg = 0x1a058, | |
3600 | .enable_mask = BIT(0), | |
3601 | .hw.init = &(struct clk_init_data){ | |
3602 | .name = "gcc_usb3_prim_phy_pipe_clk", | |
3603 | .ops = &clk_branch2_ops, | |
3604 | }, | |
3605 | }, | |
3606 | }; | |
3607 | ||
3608 | static struct clk_branch gcc_vdda_vs_clk = { | |
3609 | .halt_reg = 0x4200c, | |
3610 | .halt_check = BRANCH_HALT, | |
3611 | .clkr = { | |
3612 | .enable_reg = 0x4200c, | |
3613 | .enable_mask = BIT(0), | |
3614 | .hw.init = &(struct clk_init_data){ | |
3615 | .name = "gcc_vdda_vs_clk", | |
3616 | .parent_hws = (const struct clk_hw*[]){ | |
3617 | &gcc_vsensor_clk_src.clkr.hw, | |
3618 | }, | |
3619 | .num_parents = 1, | |
3620 | .flags = CLK_SET_RATE_PARENT, | |
3621 | .ops = &clk_branch2_ops, | |
3622 | }, | |
3623 | }, | |
3624 | }; | |
3625 | ||
3626 | static struct clk_branch gcc_vddcx_vs_clk = { | |
3627 | .halt_reg = 0x42004, | |
3628 | .halt_check = BRANCH_HALT, | |
3629 | .clkr = { | |
3630 | .enable_reg = 0x42004, | |
3631 | .enable_mask = BIT(0), | |
3632 | .hw.init = &(struct clk_init_data){ | |
3633 | .name = "gcc_vddcx_vs_clk", | |
3634 | .parent_hws = (const struct clk_hw*[]){ | |
3635 | &gcc_vsensor_clk_src.clkr.hw, | |
3636 | }, | |
3637 | .num_parents = 1, | |
3638 | .flags = CLK_SET_RATE_PARENT, | |
3639 | .ops = &clk_branch2_ops, | |
3640 | }, | |
3641 | }, | |
3642 | }; | |
3643 | ||
3644 | static struct clk_branch gcc_vddmx_vs_clk = { | |
3645 | .halt_reg = 0x42008, | |
3646 | .halt_check = BRANCH_HALT, | |
3647 | .clkr = { | |
3648 | .enable_reg = 0x42008, | |
3649 | .enable_mask = BIT(0), | |
3650 | .hw.init = &(struct clk_init_data){ | |
3651 | .name = "gcc_vddmx_vs_clk", | |
3652 | .parent_hws = (const struct clk_hw*[]){ | |
3653 | &gcc_vsensor_clk_src.clkr.hw, | |
3654 | }, | |
3655 | .num_parents = 1, | |
3656 | .flags = CLK_SET_RATE_PARENT, | |
3657 | .ops = &clk_branch2_ops, | |
3658 | }, | |
3659 | }, | |
3660 | }; | |
3661 | ||
3662 | static struct clk_branch gcc_video_ahb_clk = { | |
3663 | .halt_reg = 0x17004, | |
3664 | .halt_check = BRANCH_HALT, | |
3665 | .hwcg_reg = 0x17004, | |
3666 | .hwcg_bit = 1, | |
3667 | .clkr = { | |
3668 | .enable_reg = 0x17004, | |
3669 | .enable_mask = BIT(0), | |
3670 | .hw.init = &(struct clk_init_data){ | |
3671 | .name = "gcc_video_ahb_clk", | |
3672 | .flags = CLK_IS_CRITICAL, | |
3673 | .ops = &clk_branch2_ops, | |
3674 | }, | |
3675 | }, | |
3676 | }; | |
3677 | ||
3678 | static struct clk_branch gcc_video_axi0_clk = { | |
3679 | .halt_reg = 0x1701c, | |
3680 | .halt_check = BRANCH_HALT, | |
3681 | .clkr = { | |
3682 | .enable_reg = 0x1701c, | |
3683 | .enable_mask = BIT(0), | |
3684 | .hw.init = &(struct clk_init_data){ | |
3685 | .name = "gcc_video_axi0_clk", | |
3686 | .ops = &clk_branch2_ops, | |
3687 | }, | |
3688 | }, | |
3689 | }; | |
3690 | ||
3691 | static struct clk_branch gcc_video_throttle_core_clk = { | |
3692 | .halt_reg = 0x17068, | |
3693 | .halt_check = BRANCH_HALT_VOTED, | |
3694 | .clkr = { | |
3695 | .enable_reg = 0x79004, | |
3696 | .enable_mask = BIT(28), | |
3697 | .hw.init = &(struct clk_init_data){ | |
3698 | .name = "gcc_video_throttle_core_clk", | |
3699 | .ops = &clk_branch2_ops, | |
3700 | }, | |
3701 | }, | |
3702 | }; | |
3703 | ||
3704 | static struct clk_branch gcc_video_xo_clk = { | |
3705 | .halt_reg = 0x17024, | |
3706 | .halt_check = BRANCH_HALT, | |
3707 | .clkr = { | |
3708 | .enable_reg = 0x17024, | |
3709 | .enable_mask = BIT(0), | |
3710 | .hw.init = &(struct clk_init_data){ | |
3711 | .name = "gcc_video_xo_clk", | |
3712 | .flags = CLK_IS_CRITICAL, | |
3713 | .ops = &clk_branch2_ops, | |
3714 | }, | |
3715 | }, | |
3716 | }; | |
3717 | ||
3718 | static struct clk_branch gcc_vs_ctrl_ahb_clk = { | |
3719 | .halt_reg = 0x42014, | |
3720 | .halt_check = BRANCH_HALT, | |
3721 | .hwcg_reg = 0x42014, | |
3722 | .hwcg_bit = 1, | |
3723 | .clkr = { | |
3724 | .enable_reg = 0x42014, | |
3725 | .enable_mask = BIT(0), | |
3726 | .hw.init = &(struct clk_init_data){ | |
3727 | .name = "gcc_vs_ctrl_ahb_clk", | |
3728 | .ops = &clk_branch2_ops, | |
3729 | }, | |
3730 | }, | |
3731 | }; | |
3732 | ||
3733 | static struct clk_branch gcc_vs_ctrl_clk = { | |
3734 | .halt_reg = 0x42010, | |
3735 | .halt_check = BRANCH_HALT, | |
3736 | .clkr = { | |
3737 | .enable_reg = 0x42010, | |
3738 | .enable_mask = BIT(0), | |
3739 | .hw.init = &(struct clk_init_data){ | |
3740 | .name = "gcc_vs_ctrl_clk", | |
3741 | .parent_hws = (const struct clk_hw*[]){ | |
3742 | &gcc_vs_ctrl_clk_src.clkr.hw, | |
3743 | }, | |
3744 | .num_parents = 1, | |
3745 | .flags = CLK_SET_RATE_PARENT, | |
3746 | .ops = &clk_branch2_ops, | |
3747 | }, | |
3748 | }, | |
3749 | }; | |
3750 | ||
3751 | static struct clk_branch gcc_wcss_vs_clk = { | |
3752 | .halt_reg = 0x42050, | |
3753 | .halt_check = BRANCH_HALT, | |
3754 | .clkr = { | |
3755 | .enable_reg = 0x42050, | |
3756 | .enable_mask = BIT(0), | |
3757 | .hw.init = &(struct clk_init_data){ | |
3758 | .name = "gcc_wcss_vs_clk", | |
3759 | .parent_hws = (const struct clk_hw*[]){ | |
3760 | &gcc_vsensor_clk_src.clkr.hw, | |
3761 | }, | |
3762 | .num_parents = 1, | |
3763 | .flags = CLK_SET_RATE_PARENT, | |
3764 | .ops = &clk_branch2_ops, | |
3765 | }, | |
3766 | }, | |
3767 | }; | |
3768 | ||
3769 | static struct gdsc usb30_prim_gdsc = { | |
3770 | .gdscr = 0x1a004, | |
3771 | .pd = { | |
3772 | .name = "usb30_prim_gdsc", | |
3773 | }, | |
3774 | .pwrsts = PWRSTS_OFF_ON, | |
3775 | }; | |
3776 | ||
3777 | static struct gdsc ufs_phy_gdsc = { | |
3778 | .gdscr = 0x45004, | |
3779 | .pd = { | |
3780 | .name = "ufs_phy_gdsc", | |
3781 | }, | |
3782 | .pwrsts = PWRSTS_OFF_ON, | |
3783 | }; | |
3784 | ||
3785 | static struct gdsc camss_vfe0_gdsc = { | |
3786 | .gdscr = 0x54004, | |
3787 | .pd = { | |
3788 | .name = "camss_vfe0_gdsc", | |
3789 | }, | |
3790 | .pwrsts = PWRSTS_OFF_ON, | |
3791 | }; | |
3792 | ||
3793 | static struct gdsc camss_vfe1_gdsc = { | |
3794 | .gdscr = 0x5403c, | |
3795 | .pd = { | |
3796 | .name = "camss_vfe1_gdsc", | |
3797 | }, | |
3798 | .pwrsts = PWRSTS_OFF_ON, | |
3799 | }; | |
3800 | ||
3801 | static struct gdsc camss_top_gdsc = { | |
3802 | .gdscr = 0x5607c, | |
3803 | .pd = { | |
3804 | .name = "camss_top_gdsc", | |
3805 | }, | |
3806 | .pwrsts = PWRSTS_OFF_ON, | |
3807 | }; | |
3808 | ||
3809 | static struct gdsc cam_cpp_gdsc = { | |
3810 | .gdscr = 0x560bc, | |
3811 | .pd = { | |
3812 | .name = "cam_cpp_gdsc", | |
3813 | }, | |
3814 | .pwrsts = PWRSTS_OFF_ON, | |
3815 | }; | |
3816 | ||
3817 | static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { | |
3818 | .gdscr = 0x7d060, | |
3819 | .pd = { | |
3820 | .name = "hlos1_vote_turing_mmu_tbu1_gdsc", | |
3821 | }, | |
3822 | .pwrsts = PWRSTS_OFF_ON, | |
3823 | .flags = VOTABLE, | |
3824 | }; | |
3825 | ||
3826 | static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { | |
3827 | .gdscr = 0x80074, | |
3828 | .pd = { | |
3829 | .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", | |
3830 | }, | |
3831 | .pwrsts = PWRSTS_OFF_ON, | |
3832 | .flags = VOTABLE, | |
3833 | }; | |
3834 | ||
3835 | static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { | |
3836 | .gdscr = 0x80084, | |
3837 | .pd = { | |
3838 | .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", | |
3839 | }, | |
3840 | .pwrsts = PWRSTS_OFF_ON, | |
3841 | .flags = VOTABLE, | |
3842 | }; | |
3843 | ||
3844 | ||
3845 | static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { | |
3846 | .gdscr = 0x80094, | |
3847 | .pd = { | |
3848 | .name = "hlos1_vote_turing_mmu_tbu0_gdsc", | |
3849 | }, | |
3850 | .pwrsts = PWRSTS_OFF_ON, | |
3851 | .flags = VOTABLE, | |
3852 | }; | |
3853 | ||
3854 | static struct gdsc *gcc_sm6125_gdscs[] = { | |
3855 | [USB30_PRIM_GDSC] = &usb30_prim_gdsc, | |
3856 | [UFS_PHY_GDSC] = &ufs_phy_gdsc, | |
3857 | [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc, | |
3858 | [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc, | |
3859 | [CAMSS_TOP_GDSC] = &camss_top_gdsc, | |
3860 | [CAM_CPP_GDSC] = &cam_cpp_gdsc, | |
3861 | [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, | |
3862 | [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, | |
3863 | [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, | |
3864 | [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, | |
3865 | }; | |
3866 | ||
3867 | static struct clk_hw *gcc_sm6125_hws[] = { | |
3868 | [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw, | |
3869 | [GPLL0_OUT_MAIN] = &gpll0_out_main.hw, | |
3870 | [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, | |
3871 | [GPLL7_OUT_MAIN] = &gpll7_out_main.hw, | |
3872 | [GPLL8_OUT_MAIN] = &gpll8_out_main.hw, | |
3873 | [GPLL9_OUT_MAIN] = &gpll9_out_main.hw, | |
3874 | }; | |
3875 | ||
3876 | static struct clk_regmap *gcc_sm6125_clocks[] = { | |
3877 | [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, | |
3878 | [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, | |
3879 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, | |
3880 | [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, | |
3881 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3882 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, | |
3883 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, | |
3884 | [GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr, | |
3885 | [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, | |
3886 | [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, | |
3887 | [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, | |
3888 | [GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr, | |
3889 | [GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr, | |
3890 | [GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr, | |
3891 | [GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr, | |
3892 | [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, | |
3893 | [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr, | |
3894 | [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, | |
3895 | [GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr, | |
3896 | [GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr, | |
3897 | [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, | |
3898 | [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, | |
3899 | [GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr, | |
3900 | [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, | |
3901 | [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, | |
3902 | [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, | |
3903 | [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, | |
3904 | [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, | |
3905 | [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, | |
3906 | [GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr, | |
3907 | [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, | |
3908 | [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, | |
3909 | [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, | |
3910 | [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, | |
3911 | [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, | |
3912 | [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, | |
3913 | [GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr, | |
3914 | [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, | |
3915 | [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, | |
3916 | [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, | |
3917 | [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, | |
3918 | [GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr, | |
3919 | [GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr, | |
3920 | [GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr, | |
3921 | [GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr, | |
3922 | [GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr, | |
3923 | [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, | |
3924 | [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr, | |
3925 | [GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr, | |
3926 | [GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr, | |
3927 | [GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr, | |
3928 | [GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr, | |
3929 | [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, | |
3930 | [GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr, | |
3931 | [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, | |
3932 | [GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr, | |
3933 | [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, | |
3934 | [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, | |
3935 | [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, | |
3936 | [GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr, | |
3937 | [GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr, | |
3938 | [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, | |
3939 | [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, | |
3940 | [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, | |
3941 | [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, | |
3942 | [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, | |
3943 | [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, | |
3944 | [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, | |
3945 | [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, | |
3946 | [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, | |
3947 | [GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr, | |
3948 | [GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr, | |
3949 | [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, | |
3950 | [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr, | |
3951 | [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, | |
3952 | [GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr, | |
3953 | [GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr, | |
3954 | [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr, | |
3955 | [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr, | |
3956 | [GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr, | |
3957 | [GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr, | |
3958 | [GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr, | |
3959 | [GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr, | |
3960 | [GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr, | |
3961 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
3962 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
3963 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
3964 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
3965 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, | |
3966 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, | |
3967 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, | |
3968 | [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, | |
3969 | [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, | |
3970 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, | |
3971 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3972 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
3973 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3974 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
3975 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3976 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
3977 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, | |
3978 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, | |
3979 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, | |
3980 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
3981 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
3982 | [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, | |
3983 | [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, | |
3984 | [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, | |
3985 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3986 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
3987 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3988 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
3989 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
3990 | [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, | |
3991 | [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, | |
3992 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, | |
3993 | [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, | |
3994 | [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, | |
3995 | [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, | |
3996 | [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, | |
3997 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
3998 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
3999 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
4000 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
4001 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
4002 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
4003 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
4004 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
4005 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
4006 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
4007 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
4008 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
4009 | [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, | |
4010 | [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, | |
4011 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
4012 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
4013 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
4014 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
4015 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
4016 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
4017 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
4018 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
4019 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
4020 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
4021 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
4022 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
4023 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
4024 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
4025 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
4026 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
4027 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, | |
4028 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
4029 | [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, | |
4030 | [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, | |
4031 | [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, | |
4032 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
4033 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
4034 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
4035 | [GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr, | |
4036 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, | |
4037 | [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, | |
4038 | [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, | |
4039 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, | |
4040 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
4041 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
4042 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
4043 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
4044 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
4045 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
4046 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
4047 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, | |
4048 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, | |
4049 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
4050 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = | |
4051 | &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
4052 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
4053 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
4054 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
4055 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = | |
4056 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
4057 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
4058 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
4059 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
4060 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, | |
4061 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, | |
4062 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, | |
4063 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, | |
4064 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, | |
4065 | [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, | |
4066 | [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, | |
4067 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, | |
4068 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, | |
4069 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, | |
4070 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, | |
4071 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, | |
4072 | [GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr, | |
4073 | [GPLL0_OUT_EARLY] = &gpll0_out_early.clkr, | |
4074 | [GPLL3_OUT_EARLY] = &gpll3_out_early.clkr, | |
4075 | [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, | |
4076 | [GPLL5_OUT_MAIN] = &gpll5_out_main.clkr, | |
4077 | [GPLL6_OUT_EARLY] = &gpll6_out_early.clkr, | |
4078 | [GPLL7_OUT_EARLY] = &gpll7_out_early.clkr, | |
4079 | [GPLL8_OUT_EARLY] = &gpll8_out_early.clkr, | |
4080 | [GPLL9_OUT_EARLY] = &gpll9_out_early.clkr, | |
4081 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, | |
4082 | }; | |
4083 | ||
4084 | static const struct qcom_reset_map gcc_sm6125_resets[] = { | |
4085 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, | |
4086 | [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, | |
4087 | [GCC_UFS_PHY_BCR] = { 0x45000 }, | |
4088 | [GCC_USB30_PRIM_BCR] = { 0x1a000 }, | |
4089 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, | |
4090 | [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, | |
4091 | [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, | |
4092 | [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, | |
4093 | }; | |
4094 | ||
4095 | static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { | |
4096 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), | |
4097 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), | |
4098 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), | |
4099 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), | |
4100 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), | |
4101 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), | |
4102 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), | |
4103 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), | |
4104 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), | |
4105 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), | |
4106 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), | |
4107 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), | |
4108 | }; | |
4109 | ||
4110 | static const struct regmap_config gcc_sm6125_regmap_config = { | |
4111 | .reg_bits = 32, | |
4112 | .reg_stride = 4, | |
4113 | .val_bits = 32, | |
4114 | .max_register = 0xc7000, | |
4115 | .fast_io = true, | |
4116 | }; | |
4117 | ||
4118 | static const struct qcom_cc_desc gcc_sm6125_desc = { | |
4119 | .config = &gcc_sm6125_regmap_config, | |
4120 | .clks = gcc_sm6125_clocks, | |
4121 | .num_clks = ARRAY_SIZE(gcc_sm6125_clocks), | |
4122 | .clk_hws = gcc_sm6125_hws, | |
4123 | .num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws), | |
4124 | .resets = gcc_sm6125_resets, | |
4125 | .num_resets = ARRAY_SIZE(gcc_sm6125_resets), | |
4126 | .gdscs = gcc_sm6125_gdscs, | |
4127 | .num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs), | |
4128 | }; | |
4129 | ||
4130 | static const struct of_device_id gcc_sm6125_match_table[] = { | |
4131 | { .compatible = "qcom,gcc-sm6125" }, | |
4132 | { } | |
4133 | }; | |
4134 | MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table); | |
4135 | ||
4136 | static int gcc_sm6125_probe(struct platform_device *pdev) | |
4137 | { | |
4138 | struct regmap *regmap; | |
4139 | int ret; | |
4140 | ||
4141 | regmap = qcom_cc_map(pdev, &gcc_sm6125_desc); | |
4142 | if (IS_ERR(regmap)) | |
4143 | return PTR_ERR(regmap); | |
4144 | ||
4145 | /* | |
4146 | * Disable the GPLL0 active input to video block via | |
4147 | * MISC registers. | |
4148 | */ | |
4149 | regmap_update_bits(regmap, 0x80258, 0x1, 0x1); | |
4150 | ||
4151 | /* | |
4152 | * Enable DUAL_EDGE mode for MCLK RCGs | |
bb7f4b8c | 4153 | * This is required to enable MND divider mode |
4b8d6ae5 KD |
4154 | */ |
4155 | regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); | |
4156 | regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); | |
4157 | regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000); | |
4158 | regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000); | |
4159 | ||
4160 | ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, | |
4161 | ARRAY_SIZE(gcc_dfs_clocks)); | |
4162 | if (ret) | |
4163 | return ret; | |
4164 | ||
4165 | return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap); | |
4166 | } | |
4167 | ||
4168 | static struct platform_driver gcc_sm6125_driver = { | |
4169 | .probe = gcc_sm6125_probe, | |
4170 | .driver = { | |
4171 | .name = "gcc-sm6125", | |
4172 | .of_match_table = gcc_sm6125_match_table, | |
4173 | }, | |
4174 | }; | |
4175 | ||
4176 | static int __init gcc_sm6125_init(void) | |
4177 | { | |
4178 | return platform_driver_register(&gcc_sm6125_driver); | |
4179 | } | |
4180 | subsys_initcall(gcc_sm6125_init); | |
4181 | ||
4182 | static void __exit gcc_sm6125_exit(void) | |
4183 | { | |
4184 | platform_driver_unregister(&gcc_sm6125_driver); | |
4185 | } | |
4186 | module_exit(gcc_sm6125_exit); | |
4187 | ||
4188 | MODULE_DESCRIPTION("QTI GCC SM6125 Driver"); | |
4189 | MODULE_LICENSE("GPL v2"); |