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06391edd TD |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
9c3df2b1 | 3 | * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. |
06391edd TD |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/bitops.h> | |
8 | #include <linux/err.h> | |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
06391edd TD |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/regmap.h> | |
14 | #include <linux/reset-controller.h> | |
15 | ||
16 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> | |
17 | ||
18 | #include "common.h" | |
19 | #include "clk-regmap.h" | |
20 | #include "clk-pll.h" | |
21 | #include "clk-rcg.h" | |
22 | #include "clk-branch.h" | |
23 | #include "clk-alpha-pll.h" | |
24 | #include "gdsc.h" | |
25 | #include "reset.h" | |
26 | ||
06391edd TD |
27 | enum { |
28 | P_BI_TCXO, | |
29 | P_AUD_REF_CLK, | |
06391edd TD |
30 | P_GPLL0_OUT_EVEN, |
31 | P_GPLL0_OUT_MAIN, | |
32 | P_GPLL4_OUT_MAIN, | |
ae66b1fe | 33 | P_GPLL6_OUT_MAIN, |
06391edd TD |
34 | P_SLEEP_CLK, |
35 | }; | |
36 | ||
ea434d7a DB |
37 | static struct clk_alpha_pll gpll0 = { |
38 | .offset = 0x0, | |
39 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
40 | .clkr = { | |
41 | .enable_reg = 0x52000, | |
42 | .enable_mask = BIT(0), | |
43 | .hw.init = &(struct clk_init_data){ | |
44 | .name = "gpll0", | |
45 | .parent_data = &(const struct clk_parent_data){ | |
46 | .fw_name = "bi_tcxo", .name = "bi_tcxo", | |
47 | }, | |
48 | .num_parents = 1, | |
49 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
50 | }, | |
51 | }, | |
52 | }; | |
53 | ||
54 | static struct clk_alpha_pll gpll4 = { | |
55 | .offset = 0x76000, | |
56 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
57 | .clkr = { | |
58 | .enable_reg = 0x52000, | |
59 | .enable_mask = BIT(4), | |
60 | .hw.init = &(struct clk_init_data){ | |
61 | .name = "gpll4", | |
62 | .parent_data = &(const struct clk_parent_data){ | |
63 | .fw_name = "bi_tcxo", .name = "bi_tcxo", | |
64 | }, | |
65 | .num_parents = 1, | |
66 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
67 | }, | |
68 | }, | |
69 | }; | |
70 | ||
ae66b1fe RA |
71 | static struct clk_alpha_pll gpll6 = { |
72 | .offset = 0x13000, | |
73 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
74 | .clkr = { | |
75 | .enable_reg = 0x52000, | |
76 | .enable_mask = BIT(6), | |
77 | .hw.init = &(struct clk_init_data){ | |
78 | .name = "gpll6", | |
79 | .parent_data = &(const struct clk_parent_data){ | |
80 | .fw_name = "bi_tcxo", .name = "bi_tcxo", | |
81 | }, | |
82 | .num_parents = 1, | |
83 | .ops = &clk_alpha_pll_fixed_fabia_ops, | |
84 | }, | |
85 | }, | |
86 | }; | |
87 | ||
ea434d7a DB |
88 | static const struct clk_div_table post_div_table_fabia_even[] = { |
89 | { 0x0, 1 }, | |
90 | { 0x1, 2 }, | |
91 | { 0x3, 4 }, | |
92 | { 0x7, 8 }, | |
93 | { } | |
94 | }; | |
95 | ||
96 | static struct clk_alpha_pll_postdiv gpll0_out_even = { | |
97 | .offset = 0x0, | |
98 | .post_div_shift = 8, | |
99 | .post_div_table = post_div_table_fabia_even, | |
100 | .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), | |
101 | .width = 4, | |
102 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], | |
103 | .clkr.hw.init = &(struct clk_init_data){ | |
104 | .name = "gpll0_out_even", | |
105 | .parent_hws = (const struct clk_hw*[]){ | |
106 | &gpll0.clkr.hw, | |
107 | }, | |
108 | .num_parents = 1, | |
109 | .ops = &clk_alpha_pll_postdiv_fabia_ops, | |
110 | }, | |
111 | }; | |
112 | ||
06391edd TD |
113 | static const struct parent_map gcc_parent_map_0[] = { |
114 | { P_BI_TCXO, 0 }, | |
115 | { P_GPLL0_OUT_MAIN, 1 }, | |
116 | { P_GPLL0_OUT_EVEN, 6 }, | |
06391edd TD |
117 | }; |
118 | ||
ea434d7a DB |
119 | static const struct clk_parent_data gcc_parent_data_0[] = { |
120 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
121 | { .hw = &gpll0.clkr.hw }, | |
122 | { .hw = &gpll0_out_even.clkr.hw }, | |
06391edd TD |
123 | }; |
124 | ||
125 | static const struct parent_map gcc_parent_map_1[] = { | |
126 | { P_BI_TCXO, 0 }, | |
127 | { P_GPLL0_OUT_MAIN, 1 }, | |
128 | { P_SLEEP_CLK, 5 }, | |
129 | { P_GPLL0_OUT_EVEN, 6 }, | |
06391edd TD |
130 | }; |
131 | ||
ea434d7a DB |
132 | static const struct clk_parent_data gcc_parent_data_1[] = { |
133 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
134 | { .hw = &gpll0.clkr.hw }, | |
135 | { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" }, | |
136 | { .hw = &gpll0_out_even.clkr.hw }, | |
06391edd TD |
137 | }; |
138 | ||
139 | static const struct parent_map gcc_parent_map_2[] = { | |
140 | { P_BI_TCXO, 0 }, | |
141 | { P_SLEEP_CLK, 5 }, | |
06391edd TD |
142 | }; |
143 | ||
ea434d7a DB |
144 | static const struct clk_parent_data gcc_parent_data_2[] = { |
145 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
146 | { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" }, | |
06391edd TD |
147 | }; |
148 | ||
149 | static const struct parent_map gcc_parent_map_3[] = { | |
150 | { P_BI_TCXO, 0 }, | |
151 | { P_GPLL0_OUT_MAIN, 1 }, | |
06391edd TD |
152 | }; |
153 | ||
ea434d7a DB |
154 | static const struct clk_parent_data gcc_parent_data_3[] = { |
155 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
156 | { .hw = &gpll0.clkr.hw }, | |
06391edd TD |
157 | }; |
158 | ||
159 | static const struct parent_map gcc_parent_map_4[] = { | |
160 | { P_BI_TCXO, 0 }, | |
06391edd TD |
161 | }; |
162 | ||
ea434d7a DB |
163 | static const struct clk_parent_data gcc_parent_data_4[] = { |
164 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
06391edd TD |
165 | }; |
166 | ||
06391edd TD |
167 | static const struct parent_map gcc_parent_map_6[] = { |
168 | { P_BI_TCXO, 0 }, | |
169 | { P_GPLL0_OUT_MAIN, 1 }, | |
170 | { P_AUD_REF_CLK, 2 }, | |
171 | { P_GPLL0_OUT_EVEN, 6 }, | |
06391edd TD |
172 | }; |
173 | ||
ea434d7a DB |
174 | static const struct clk_parent_data gcc_parent_data_6[] = { |
175 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
176 | { .hw = &gpll0.clkr.hw }, | |
177 | { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, | |
178 | { .hw = &gpll0_out_even.clkr.hw }, | |
06391edd TD |
179 | }; |
180 | ||
ea434d7a DB |
181 | static const struct clk_parent_data gcc_parent_data_7_ao[] = { |
182 | { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, | |
183 | { .hw = &gpll0.clkr.hw }, | |
184 | { .hw = &gpll0_out_even.clkr.hw }, | |
185 | { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, | |
06391edd TD |
186 | }; |
187 | ||
ea434d7a DB |
188 | static const struct clk_parent_data gcc_parent_data_8[] = { |
189 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
190 | { .hw = &gpll0.clkr.hw }, | |
191 | { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, | |
06391edd TD |
192 | }; |
193 | ||
ea434d7a DB |
194 | static const struct clk_parent_data gcc_parent_data_8_ao[] = { |
195 | { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, | |
196 | { .hw = &gpll0.clkr.hw }, | |
197 | { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, | |
9ff1a3b4 TD |
198 | }; |
199 | ||
06391edd TD |
200 | static const struct parent_map gcc_parent_map_10[] = { |
201 | { P_BI_TCXO, 0 }, | |
202 | { P_GPLL0_OUT_MAIN, 1 }, | |
203 | { P_GPLL4_OUT_MAIN, 5 }, | |
204 | { P_GPLL0_OUT_EVEN, 6 }, | |
06391edd TD |
205 | }; |
206 | ||
ea434d7a DB |
207 | static const struct clk_parent_data gcc_parent_data_10[] = { |
208 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
209 | { .hw = &gpll0.clkr.hw }, | |
210 | { .hw = &gpll4.clkr.hw }, | |
211 | { .hw = &gpll0_out_even.clkr.hw }, | |
06391edd TD |
212 | }; |
213 | ||
ae66b1fe RA |
214 | static const struct parent_map gcc_parent_map_11[] = { |
215 | { P_BI_TCXO, 0 }, | |
216 | { P_GPLL0_OUT_MAIN, 1 }, | |
217 | { P_GPLL6_OUT_MAIN, 2 }, | |
218 | { P_GPLL0_OUT_EVEN, 6 }, | |
219 | }; | |
220 | ||
221 | static const struct clk_parent_data gcc_parent_data_11[] = { | |
222 | { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, | |
223 | { .hw = &gpll0.clkr.hw }, | |
224 | { .hw = &gpll6.clkr.hw }, | |
225 | { .hw = &gpll0_out_even.clkr.hw }, | |
226 | }; | |
06391edd TD |
227 | |
228 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { | |
229 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
230 | { } | |
231 | }; | |
232 | ||
233 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { | |
234 | .cmd_rcgr = 0x48014, | |
235 | .mnd_width = 0, | |
236 | .hid_width = 5, | |
237 | .parent_map = gcc_parent_map_0, | |
238 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, | |
239 | .clkr.hw.init = &(struct clk_init_data){ | |
240 | .name = "gcc_cpuss_ahb_clk_src", | |
ea434d7a DB |
241 | .parent_data = gcc_parent_data_7_ao, |
242 | .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao), | |
06391edd TD |
243 | .ops = &clk_rcg2_ops, |
244 | }, | |
245 | }; | |
246 | ||
247 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { | |
248 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
249 | { } | |
250 | }; | |
251 | ||
252 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { | |
253 | .cmd_rcgr = 0x4815c, | |
254 | .mnd_width = 0, | |
255 | .hid_width = 5, | |
256 | .parent_map = gcc_parent_map_3, | |
257 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
258 | .clkr.hw.init = &(struct clk_init_data){ | |
259 | .name = "gcc_cpuss_rbcpr_clk_src", | |
ea434d7a DB |
260 | .parent_data = gcc_parent_data_8_ao, |
261 | .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao), | |
06391edd TD |
262 | .ops = &clk_rcg2_ops, |
263 | }, | |
264 | }; | |
265 | ||
ae66b1fe RA |
266 | static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = { |
267 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
268 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
269 | { } | |
270 | }; | |
271 | ||
272 | static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = { | |
273 | .cmd_rcgr = 0x4815c, | |
274 | .mnd_width = 0, | |
275 | .hid_width = 5, | |
276 | .parent_map = gcc_parent_map_3, | |
277 | .freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src, | |
278 | .clkr.hw.init = &(struct clk_init_data){ | |
279 | .name = "gcc_cpuss_rbcpr_clk_src", | |
280 | .parent_data = gcc_parent_data_8_ao, | |
281 | .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao), | |
282 | .ops = &clk_rcg2_ops, | |
283 | }, | |
284 | }; | |
285 | ||
06391edd TD |
286 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { |
287 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
288 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
289 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
290 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
291 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
292 | { } | |
293 | }; | |
294 | ||
295 | static struct clk_rcg2 gcc_gp1_clk_src = { | |
296 | .cmd_rcgr = 0x64004, | |
297 | .mnd_width = 8, | |
298 | .hid_width = 5, | |
299 | .parent_map = gcc_parent_map_1, | |
300 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
301 | .clkr.hw.init = &(struct clk_init_data){ | |
302 | .name = "gcc_gp1_clk_src", | |
ea434d7a DB |
303 | .parent_data = gcc_parent_data_1, |
304 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
06391edd TD |
305 | .ops = &clk_rcg2_ops, |
306 | }, | |
307 | }; | |
308 | ||
309 | static struct clk_rcg2 gcc_gp2_clk_src = { | |
310 | .cmd_rcgr = 0x65004, | |
311 | .mnd_width = 8, | |
312 | .hid_width = 5, | |
313 | .parent_map = gcc_parent_map_1, | |
314 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
315 | .clkr.hw.init = &(struct clk_init_data){ | |
316 | .name = "gcc_gp2_clk_src", | |
ea434d7a DB |
317 | .parent_data = gcc_parent_data_1, |
318 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
06391edd TD |
319 | .ops = &clk_rcg2_ops, |
320 | }, | |
321 | }; | |
322 | ||
323 | static struct clk_rcg2 gcc_gp3_clk_src = { | |
324 | .cmd_rcgr = 0x66004, | |
325 | .mnd_width = 8, | |
326 | .hid_width = 5, | |
327 | .parent_map = gcc_parent_map_1, | |
328 | .freq_tbl = ftbl_gcc_gp1_clk_src, | |
329 | .clkr.hw.init = &(struct clk_init_data){ | |
330 | .name = "gcc_gp3_clk_src", | |
ea434d7a DB |
331 | .parent_data = gcc_parent_data_1, |
332 | .num_parents = ARRAY_SIZE(gcc_parent_data_1), | |
06391edd TD |
333 | .ops = &clk_rcg2_ops, |
334 | }, | |
335 | }; | |
336 | ||
337 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { | |
338 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
339 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
340 | { } | |
341 | }; | |
342 | ||
343 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { | |
344 | .cmd_rcgr = 0x6b028, | |
345 | .mnd_width = 16, | |
346 | .hid_width = 5, | |
347 | .parent_map = gcc_parent_map_2, | |
348 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
349 | .clkr.hw.init = &(struct clk_init_data){ | |
350 | .name = "gcc_pcie_0_aux_clk_src", | |
ea434d7a DB |
351 | .parent_data = gcc_parent_data_2, |
352 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
06391edd TD |
353 | .ops = &clk_rcg2_ops, |
354 | }, | |
355 | }; | |
356 | ||
357 | static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { | |
358 | .cmd_rcgr = 0x8d028, | |
359 | .mnd_width = 16, | |
360 | .hid_width = 5, | |
361 | .parent_map = gcc_parent_map_2, | |
362 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
363 | .clkr.hw.init = &(struct clk_init_data){ | |
364 | .name = "gcc_pcie_1_aux_clk_src", | |
ea434d7a DB |
365 | .parent_data = gcc_parent_data_2, |
366 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
06391edd TD |
367 | .ops = &clk_rcg2_ops, |
368 | }, | |
369 | }; | |
370 | ||
371 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { | |
372 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
373 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
374 | { } | |
375 | }; | |
376 | ||
377 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { | |
378 | .cmd_rcgr = 0x6f014, | |
379 | .mnd_width = 0, | |
380 | .hid_width = 5, | |
381 | .parent_map = gcc_parent_map_0, | |
382 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, | |
383 | .clkr.hw.init = &(struct clk_init_data){ | |
384 | .name = "gcc_pcie_phy_refgen_clk_src", | |
ea434d7a DB |
385 | .parent_data = gcc_parent_data_0, |
386 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
387 | .ops = &clk_rcg2_ops, |
388 | }, | |
389 | }; | |
390 | ||
4f83d9b8 DA |
391 | static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { |
392 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
393 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
394 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
395 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
396 | { } | |
397 | }; | |
398 | ||
399 | static struct clk_rcg2 gcc_qspi_core_clk_src = { | |
400 | .cmd_rcgr = 0x4b008, | |
401 | .mnd_width = 0, | |
402 | .hid_width = 5, | |
403 | .parent_map = gcc_parent_map_0, | |
404 | .freq_tbl = ftbl_gcc_qspi_core_clk_src, | |
405 | .clkr.hw.init = &(struct clk_init_data){ | |
406 | .name = "gcc_qspi_core_clk_src", | |
ea434d7a DB |
407 | .parent_data = gcc_parent_data_0, |
408 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
4f83d9b8 DA |
409 | .ops = &clk_rcg2_floor_ops, |
410 | }, | |
411 | }; | |
412 | ||
06391edd TD |
413 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { |
414 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
415 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
416 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), | |
417 | { } | |
418 | }; | |
419 | ||
420 | static struct clk_rcg2 gcc_pdm2_clk_src = { | |
421 | .cmd_rcgr = 0x33010, | |
422 | .mnd_width = 0, | |
423 | .hid_width = 5, | |
424 | .parent_map = gcc_parent_map_0, | |
425 | .freq_tbl = ftbl_gcc_pdm2_clk_src, | |
426 | .clkr.hw.init = &(struct clk_init_data){ | |
427 | .name = "gcc_pdm2_clk_src", | |
ea434d7a DB |
428 | .parent_data = gcc_parent_data_0, |
429 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
430 | .ops = &clk_rcg2_ops, |
431 | }, | |
432 | }; | |
433 | ||
434 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { | |
435 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), | |
436 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), | |
437 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
438 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), | |
439 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), | |
440 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), | |
441 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), | |
442 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), | |
443 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), | |
444 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), | |
445 | F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), | |
446 | F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), | |
447 | F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), | |
448 | F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), | |
449 | F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), | |
450 | { } | |
451 | }; | |
452 | ||
1a1c7821 | 453 | static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { |
8b69c6db | 454 | .name = "gcc_qupv3_wrap0_s0_clk_src", |
ea434d7a DB |
455 | .parent_data = gcc_parent_data_0, |
456 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db TD |
457 | .ops = &clk_rcg2_shared_ops, |
458 | }; | |
459 | ||
06391edd TD |
460 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { |
461 | .cmd_rcgr = 0x17034, | |
462 | .mnd_width = 16, | |
463 | .hid_width = 5, | |
464 | .parent_map = gcc_parent_map_0, | |
465 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 466 | .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, |
8b69c6db TD |
467 | }; |
468 | ||
1a1c7821 | 469 | static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { |
8b69c6db | 470 | .name = "gcc_qupv3_wrap0_s1_clk_src", |
ea434d7a DB |
471 | .parent_data = gcc_parent_data_0, |
472 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 473 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
474 | }; |
475 | ||
476 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { | |
477 | .cmd_rcgr = 0x17164, | |
478 | .mnd_width = 16, | |
479 | .hid_width = 5, | |
480 | .parent_map = gcc_parent_map_0, | |
481 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 482 | .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, |
8b69c6db TD |
483 | }; |
484 | ||
1a1c7821 | 485 | static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { |
8b69c6db | 486 | .name = "gcc_qupv3_wrap0_s2_clk_src", |
ea434d7a DB |
487 | .parent_data = gcc_parent_data_0, |
488 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 489 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
490 | }; |
491 | ||
492 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { | |
493 | .cmd_rcgr = 0x17294, | |
494 | .mnd_width = 16, | |
495 | .hid_width = 5, | |
496 | .parent_map = gcc_parent_map_0, | |
497 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 498 | .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, |
8b69c6db TD |
499 | }; |
500 | ||
1a1c7821 | 501 | static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { |
8b69c6db | 502 | .name = "gcc_qupv3_wrap0_s3_clk_src", |
ea434d7a DB |
503 | .parent_data = gcc_parent_data_0, |
504 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 505 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
506 | }; |
507 | ||
508 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { | |
509 | .cmd_rcgr = 0x173c4, | |
510 | .mnd_width = 16, | |
511 | .hid_width = 5, | |
512 | .parent_map = gcc_parent_map_0, | |
513 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 514 | .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, |
8b69c6db TD |
515 | }; |
516 | ||
1a1c7821 | 517 | static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { |
8b69c6db | 518 | .name = "gcc_qupv3_wrap0_s4_clk_src", |
ea434d7a DB |
519 | .parent_data = gcc_parent_data_0, |
520 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 521 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
522 | }; |
523 | ||
524 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { | |
525 | .cmd_rcgr = 0x174f4, | |
526 | .mnd_width = 16, | |
527 | .hid_width = 5, | |
528 | .parent_map = gcc_parent_map_0, | |
529 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 530 | .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, |
8b69c6db TD |
531 | }; |
532 | ||
1a1c7821 | 533 | static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { |
8b69c6db | 534 | .name = "gcc_qupv3_wrap0_s5_clk_src", |
ea434d7a DB |
535 | .parent_data = gcc_parent_data_0, |
536 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 537 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
538 | }; |
539 | ||
540 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { | |
541 | .cmd_rcgr = 0x17624, | |
542 | .mnd_width = 16, | |
543 | .hid_width = 5, | |
544 | .parent_map = gcc_parent_map_0, | |
545 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 546 | .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, |
8b69c6db TD |
547 | }; |
548 | ||
1a1c7821 | 549 | static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { |
8b69c6db | 550 | .name = "gcc_qupv3_wrap0_s6_clk_src", |
ea434d7a DB |
551 | .parent_data = gcc_parent_data_0, |
552 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 553 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
554 | }; |
555 | ||
556 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { | |
557 | .cmd_rcgr = 0x17754, | |
558 | .mnd_width = 16, | |
559 | .hid_width = 5, | |
560 | .parent_map = gcc_parent_map_0, | |
561 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 562 | .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, |
8b69c6db TD |
563 | }; |
564 | ||
1a1c7821 | 565 | static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { |
8b69c6db | 566 | .name = "gcc_qupv3_wrap0_s7_clk_src", |
ea434d7a DB |
567 | .parent_data = gcc_parent_data_0, |
568 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 569 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
570 | }; |
571 | ||
572 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { | |
573 | .cmd_rcgr = 0x17884, | |
574 | .mnd_width = 16, | |
575 | .hid_width = 5, | |
576 | .parent_map = gcc_parent_map_0, | |
577 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 578 | .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, |
8b69c6db TD |
579 | }; |
580 | ||
1a1c7821 | 581 | static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { |
8b69c6db | 582 | .name = "gcc_qupv3_wrap1_s0_clk_src", |
ea434d7a DB |
583 | .parent_data = gcc_parent_data_0, |
584 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 585 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
586 | }; |
587 | ||
588 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { | |
589 | .cmd_rcgr = 0x18018, | |
590 | .mnd_width = 16, | |
591 | .hid_width = 5, | |
592 | .parent_map = gcc_parent_map_0, | |
593 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 594 | .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, |
8b69c6db TD |
595 | }; |
596 | ||
1a1c7821 | 597 | static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { |
8b69c6db | 598 | .name = "gcc_qupv3_wrap1_s1_clk_src", |
ea434d7a DB |
599 | .parent_data = gcc_parent_data_0, |
600 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 601 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
602 | }; |
603 | ||
604 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { | |
605 | .cmd_rcgr = 0x18148, | |
606 | .mnd_width = 16, | |
607 | .hid_width = 5, | |
608 | .parent_map = gcc_parent_map_0, | |
609 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 610 | .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, |
8b69c6db TD |
611 | }; |
612 | ||
1a1c7821 | 613 | static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { |
8b69c6db | 614 | .name = "gcc_qupv3_wrap1_s2_clk_src", |
ea434d7a DB |
615 | .parent_data = gcc_parent_data_0, |
616 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 617 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
618 | }; |
619 | ||
620 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { | |
621 | .cmd_rcgr = 0x18278, | |
622 | .mnd_width = 16, | |
623 | .hid_width = 5, | |
624 | .parent_map = gcc_parent_map_0, | |
625 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 626 | .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, |
8b69c6db TD |
627 | }; |
628 | ||
1a1c7821 | 629 | static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { |
8b69c6db | 630 | .name = "gcc_qupv3_wrap1_s3_clk_src", |
ea434d7a DB |
631 | .parent_data = gcc_parent_data_0, |
632 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 633 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
634 | }; |
635 | ||
636 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { | |
637 | .cmd_rcgr = 0x183a8, | |
638 | .mnd_width = 16, | |
639 | .hid_width = 5, | |
640 | .parent_map = gcc_parent_map_0, | |
641 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 642 | .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, |
8b69c6db TD |
643 | }; |
644 | ||
1a1c7821 | 645 | static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { |
8b69c6db | 646 | .name = "gcc_qupv3_wrap1_s4_clk_src", |
ea434d7a DB |
647 | .parent_data = gcc_parent_data_0, |
648 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 649 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
650 | }; |
651 | ||
652 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { | |
653 | .cmd_rcgr = 0x184d8, | |
654 | .mnd_width = 16, | |
655 | .hid_width = 5, | |
656 | .parent_map = gcc_parent_map_0, | |
657 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 658 | .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, |
8b69c6db TD |
659 | }; |
660 | ||
1a1c7821 | 661 | static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { |
8b69c6db | 662 | .name = "gcc_qupv3_wrap1_s5_clk_src", |
ea434d7a DB |
663 | .parent_data = gcc_parent_data_0, |
664 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 665 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
666 | }; |
667 | ||
668 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { | |
669 | .cmd_rcgr = 0x18608, | |
670 | .mnd_width = 16, | |
671 | .hid_width = 5, | |
672 | .parent_map = gcc_parent_map_0, | |
673 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 674 | .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, |
8b69c6db TD |
675 | }; |
676 | ||
1a1c7821 | 677 | static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { |
8b69c6db | 678 | .name = "gcc_qupv3_wrap1_s6_clk_src", |
ea434d7a DB |
679 | .parent_data = gcc_parent_data_0, |
680 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 681 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
682 | }; |
683 | ||
684 | static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { | |
685 | .cmd_rcgr = 0x18738, | |
686 | .mnd_width = 16, | |
687 | .hid_width = 5, | |
688 | .parent_map = gcc_parent_map_0, | |
689 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 690 | .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, |
8b69c6db TD |
691 | }; |
692 | ||
1a1c7821 | 693 | static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { |
8b69c6db | 694 | .name = "gcc_qupv3_wrap1_s7_clk_src", |
ea434d7a DB |
695 | .parent_data = gcc_parent_data_0, |
696 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
8b69c6db | 697 | .ops = &clk_rcg2_shared_ops, |
06391edd TD |
698 | }; |
699 | ||
700 | static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { | |
701 | .cmd_rcgr = 0x18868, | |
702 | .mnd_width = 16, | |
703 | .hid_width = 5, | |
704 | .parent_map = gcc_parent_map_0, | |
705 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, | |
1a1c7821 | 706 | .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, |
06391edd TD |
707 | }; |
708 | ||
ae66b1fe RA |
709 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { |
710 | F(144000, P_BI_TCXO, 16, 3, 25), | |
711 | F(400000, P_BI_TCXO, 12, 1, 4), | |
712 | F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), | |
713 | F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), | |
714 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
715 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
716 | F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), | |
717 | F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), | |
718 | { } | |
719 | }; | |
720 | ||
721 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { | |
722 | .cmd_rcgr = 0x26028, | |
723 | .mnd_width = 8, | |
724 | .hid_width = 5, | |
725 | .parent_map = gcc_parent_map_11, | |
726 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, | |
727 | .clkr.hw.init = &(struct clk_init_data){ | |
728 | .name = "gcc_sdcc1_apps_clk_src", | |
729 | .parent_data = gcc_parent_data_11, | |
730 | .num_parents = ARRAY_SIZE(gcc_parent_data_11), | |
731 | .ops = &clk_rcg2_floor_ops, | |
732 | }, | |
733 | }; | |
734 | ||
735 | static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { | |
736 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
737 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
738 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
739 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
740 | { } | |
741 | }; | |
742 | ||
743 | static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { | |
744 | .cmd_rcgr = 0x26010, | |
745 | .mnd_width = 8, | |
746 | .hid_width = 5, | |
747 | .parent_map = gcc_parent_map_0, | |
748 | .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, | |
749 | .clkr.hw.init = &(struct clk_init_data){ | |
750 | .name = "gcc_sdcc1_ice_core_clk_src", | |
751 | .parent_data = gcc_parent_data_0, | |
752 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
753 | .ops = &clk_rcg2_ops, | |
754 | }, | |
755 | }; | |
756 | ||
06391edd TD |
757 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { |
758 | F(400000, P_BI_TCXO, 12, 1, 4), | |
759 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
760 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
761 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
762 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
763 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
764 | F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), | |
765 | { } | |
766 | }; | |
767 | ||
768 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | |
769 | .cmd_rcgr = 0x1400c, | |
770 | .mnd_width = 8, | |
771 | .hid_width = 5, | |
772 | .parent_map = gcc_parent_map_10, | |
773 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, | |
774 | .clkr.hw.init = &(struct clk_init_data){ | |
775 | .name = "gcc_sdcc2_apps_clk_src", | |
ea434d7a DB |
776 | .parent_data = gcc_parent_data_10, |
777 | .num_parents = ARRAY_SIZE(gcc_parent_data_10), | |
5e4b7e82 | 778 | .ops = &clk_rcg2_floor_ops, |
06391edd TD |
779 | }, |
780 | }; | |
781 | ||
782 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { | |
783 | F(400000, P_BI_TCXO, 12, 1, 4), | |
784 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
785 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
786 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), | |
787 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
788 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
789 | { } | |
790 | }; | |
791 | ||
792 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { | |
793 | .cmd_rcgr = 0x1600c, | |
794 | .mnd_width = 8, | |
795 | .hid_width = 5, | |
796 | .parent_map = gcc_parent_map_0, | |
797 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, | |
798 | .clkr.hw.init = &(struct clk_init_data){ | |
799 | .name = "gcc_sdcc4_apps_clk_src", | |
ea434d7a DB |
800 | .parent_data = gcc_parent_data_0, |
801 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
5e4b7e82 | 802 | .ops = &clk_rcg2_floor_ops, |
06391edd TD |
803 | }, |
804 | }; | |
805 | ||
ae66b1fe RA |
806 | static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = { |
807 | F(400000, P_BI_TCXO, 12, 1, 4), | |
808 | F(9600000, P_BI_TCXO, 2, 0, 0), | |
809 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
810 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
811 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), | |
812 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), | |
813 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
814 | { } | |
815 | }; | |
816 | ||
817 | static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = { | |
818 | .cmd_rcgr = 0x1600c, | |
819 | .mnd_width = 8, | |
820 | .hid_width = 5, | |
821 | .parent_map = gcc_parent_map_0, | |
822 | .freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src, | |
823 | .clkr.hw.init = &(struct clk_init_data){ | |
824 | .name = "gcc_sdcc4_apps_clk_src", | |
825 | .parent_data = gcc_parent_data_0, | |
826 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
827 | .ops = &clk_rcg2_floor_ops, | |
828 | }, | |
829 | }; | |
830 | ||
06391edd TD |
831 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { |
832 | F(105495, P_BI_TCXO, 2, 1, 91), | |
833 | { } | |
834 | }; | |
835 | ||
836 | static struct clk_rcg2 gcc_tsif_ref_clk_src = { | |
837 | .cmd_rcgr = 0x36010, | |
838 | .mnd_width = 8, | |
839 | .hid_width = 5, | |
840 | .parent_map = gcc_parent_map_6, | |
841 | .freq_tbl = ftbl_gcc_tsif_ref_clk_src, | |
842 | .clkr.hw.init = &(struct clk_init_data){ | |
843 | .name = "gcc_tsif_ref_clk_src", | |
ea434d7a DB |
844 | .parent_data = gcc_parent_data_6, |
845 | .num_parents = ARRAY_SIZE(gcc_parent_data_6), | |
06391edd TD |
846 | .ops = &clk_rcg2_ops, |
847 | }, | |
848 | }; | |
849 | ||
850 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { | |
851 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
852 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
853 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
854 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
855 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
856 | { } | |
857 | }; | |
858 | ||
859 | static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { | |
860 | .cmd_rcgr = 0x7501c, | |
861 | .mnd_width = 8, | |
862 | .hid_width = 5, | |
863 | .parent_map = gcc_parent_map_0, | |
864 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, | |
865 | .clkr.hw.init = &(struct clk_init_data){ | |
866 | .name = "gcc_ufs_card_axi_clk_src", | |
ea434d7a DB |
867 | .parent_data = gcc_parent_data_0, |
868 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
869 | .ops = &clk_rcg2_shared_ops, |
870 | }, | |
871 | }; | |
872 | ||
873 | static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { | |
874 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
875 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), | |
876 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
877 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
878 | { } | |
879 | }; | |
880 | ||
881 | static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { | |
882 | .cmd_rcgr = 0x7505c, | |
883 | .mnd_width = 0, | |
884 | .hid_width = 5, | |
885 | .parent_map = gcc_parent_map_0, | |
886 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
887 | .clkr.hw.init = &(struct clk_init_data){ | |
888 | .name = "gcc_ufs_card_ice_core_clk_src", | |
ea434d7a DB |
889 | .parent_data = gcc_parent_data_0, |
890 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
891 | .ops = &clk_rcg2_shared_ops, |
892 | }, | |
893 | }; | |
894 | ||
895 | static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { | |
896 | .cmd_rcgr = 0x75090, | |
897 | .mnd_width = 0, | |
898 | .hid_width = 5, | |
899 | .parent_map = gcc_parent_map_4, | |
900 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
901 | .clkr.hw.init = &(struct clk_init_data){ | |
902 | .name = "gcc_ufs_card_phy_aux_clk_src", | |
ea434d7a DB |
903 | .parent_data = gcc_parent_data_4, |
904 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
06391edd TD |
905 | .ops = &clk_rcg2_ops, |
906 | }, | |
907 | }; | |
908 | ||
909 | static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { | |
910 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), | |
911 | F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), | |
912 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), | |
913 | { } | |
914 | }; | |
915 | ||
916 | static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { | |
917 | .cmd_rcgr = 0x75074, | |
918 | .mnd_width = 0, | |
919 | .hid_width = 5, | |
920 | .parent_map = gcc_parent_map_0, | |
921 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, | |
922 | .clkr.hw.init = &(struct clk_init_data){ | |
923 | .name = "gcc_ufs_card_unipro_core_clk_src", | |
ea434d7a DB |
924 | .parent_data = gcc_parent_data_0, |
925 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
926 | .ops = &clk_rcg2_shared_ops, |
927 | }, | |
928 | }; | |
929 | ||
930 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { | |
931 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), | |
932 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), | |
933 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), | |
934 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
935 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
936 | { } | |
937 | }; | |
938 | ||
939 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { | |
940 | .cmd_rcgr = 0x7701c, | |
941 | .mnd_width = 8, | |
942 | .hid_width = 5, | |
943 | .parent_map = gcc_parent_map_0, | |
944 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, | |
945 | .clkr.hw.init = &(struct clk_init_data){ | |
946 | .name = "gcc_ufs_phy_axi_clk_src", | |
ea434d7a DB |
947 | .parent_data = gcc_parent_data_0, |
948 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
949 | .ops = &clk_rcg2_shared_ops, |
950 | }, | |
951 | }; | |
952 | ||
953 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { | |
954 | .cmd_rcgr = 0x7705c, | |
955 | .mnd_width = 0, | |
956 | .hid_width = 5, | |
957 | .parent_map = gcc_parent_map_0, | |
958 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, | |
959 | .clkr.hw.init = &(struct clk_init_data){ | |
960 | .name = "gcc_ufs_phy_ice_core_clk_src", | |
ea434d7a DB |
961 | .parent_data = gcc_parent_data_0, |
962 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
963 | .ops = &clk_rcg2_shared_ops, |
964 | }, | |
965 | }; | |
966 | ||
967 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { | |
968 | .cmd_rcgr = 0x77090, | |
969 | .mnd_width = 0, | |
970 | .hid_width = 5, | |
971 | .parent_map = gcc_parent_map_4, | |
972 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, | |
973 | .clkr.hw.init = &(struct clk_init_data){ | |
974 | .name = "gcc_ufs_phy_phy_aux_clk_src", | |
ea434d7a DB |
975 | .parent_data = gcc_parent_data_4, |
976 | .num_parents = ARRAY_SIZE(gcc_parent_data_4), | |
06391edd TD |
977 | .ops = &clk_rcg2_shared_ops, |
978 | }, | |
979 | }; | |
980 | ||
981 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { | |
982 | .cmd_rcgr = 0x77074, | |
983 | .mnd_width = 0, | |
984 | .hid_width = 5, | |
985 | .parent_map = gcc_parent_map_0, | |
986 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, | |
987 | .clkr.hw.init = &(struct clk_init_data){ | |
988 | .name = "gcc_ufs_phy_unipro_core_clk_src", | |
ea434d7a DB |
989 | .parent_data = gcc_parent_data_0, |
990 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
991 | .ops = &clk_rcg2_shared_ops, |
992 | }, | |
993 | }; | |
994 | ||
995 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { | |
996 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), | |
997 | F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), | |
998 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), | |
999 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), | |
1000 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), | |
1001 | { } | |
1002 | }; | |
1003 | ||
1004 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { | |
1005 | .cmd_rcgr = 0xf018, | |
1006 | .mnd_width = 8, | |
1007 | .hid_width = 5, | |
1008 | .parent_map = gcc_parent_map_0, | |
1009 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1010 | .clkr.hw.init = &(struct clk_init_data){ | |
1011 | .name = "gcc_usb30_prim_master_clk_src", | |
ea434d7a DB |
1012 | .parent_data = gcc_parent_data_0, |
1013 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
1014 | .ops = &clk_rcg2_shared_ops, |
1015 | }, | |
1016 | }; | |
1017 | ||
1018 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { | |
1019 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1020 | F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), | |
1021 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), | |
1022 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), | |
1023 | { } | |
1024 | }; | |
1025 | ||
1026 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { | |
1027 | .cmd_rcgr = 0xf030, | |
1028 | .mnd_width = 0, | |
1029 | .hid_width = 5, | |
1030 | .parent_map = gcc_parent_map_0, | |
1031 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
1032 | .clkr.hw.init = &(struct clk_init_data){ | |
1033 | .name = "gcc_usb30_prim_mock_utmi_clk_src", | |
ea434d7a DB |
1034 | .parent_data = gcc_parent_data_0, |
1035 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
1036 | .ops = &clk_rcg2_shared_ops, |
1037 | }, | |
1038 | }; | |
1039 | ||
1040 | static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { | |
1041 | .cmd_rcgr = 0x10018, | |
1042 | .mnd_width = 8, | |
1043 | .hid_width = 5, | |
1044 | .parent_map = gcc_parent_map_0, | |
1045 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, | |
1046 | .clkr.hw.init = &(struct clk_init_data){ | |
1047 | .name = "gcc_usb30_sec_master_clk_src", | |
ea434d7a DB |
1048 | .parent_data = gcc_parent_data_0, |
1049 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
1050 | .ops = &clk_rcg2_ops, |
1051 | }, | |
1052 | }; | |
1053 | ||
1054 | static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { | |
1055 | .cmd_rcgr = 0x10030, | |
1056 | .mnd_width = 0, | |
1057 | .hid_width = 5, | |
1058 | .parent_map = gcc_parent_map_0, | |
1059 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, | |
1060 | .clkr.hw.init = &(struct clk_init_data){ | |
1061 | .name = "gcc_usb30_sec_mock_utmi_clk_src", | |
ea434d7a DB |
1062 | .parent_data = gcc_parent_data_0, |
1063 | .num_parents = ARRAY_SIZE(gcc_parent_data_0), | |
06391edd TD |
1064 | .ops = &clk_rcg2_ops, |
1065 | }, | |
1066 | }; | |
1067 | ||
1068 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { | |
1069 | .cmd_rcgr = 0xf05c, | |
1070 | .mnd_width = 0, | |
1071 | .hid_width = 5, | |
1072 | .parent_map = gcc_parent_map_2, | |
1073 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
1074 | .clkr.hw.init = &(struct clk_init_data){ | |
1075 | .name = "gcc_usb3_prim_phy_aux_clk_src", | |
ea434d7a DB |
1076 | .parent_data = gcc_parent_data_2, |
1077 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
06391edd TD |
1078 | .ops = &clk_rcg2_ops, |
1079 | }, | |
1080 | }; | |
1081 | ||
1082 | static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { | |
1083 | .cmd_rcgr = 0x1005c, | |
1084 | .mnd_width = 0, | |
1085 | .hid_width = 5, | |
1086 | .parent_map = gcc_parent_map_2, | |
1087 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
1088 | .clkr.hw.init = &(struct clk_init_data){ | |
1089 | .name = "gcc_usb3_sec_phy_aux_clk_src", | |
ea434d7a DB |
1090 | .parent_data = gcc_parent_data_2, |
1091 | .num_parents = ARRAY_SIZE(gcc_parent_data_2), | |
06391edd TD |
1092 | .ops = &clk_rcg2_shared_ops, |
1093 | }, | |
1094 | }; | |
1095 | ||
1096 | static struct clk_rcg2 gcc_vs_ctrl_clk_src = { | |
1097 | .cmd_rcgr = 0x7a030, | |
1098 | .mnd_width = 0, | |
1099 | .hid_width = 5, | |
1100 | .parent_map = gcc_parent_map_3, | |
1101 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, | |
1102 | .clkr.hw.init = &(struct clk_init_data){ | |
1103 | .name = "gcc_vs_ctrl_clk_src", | |
ea434d7a DB |
1104 | .parent_data = gcc_parent_data_3, |
1105 | .num_parents = ARRAY_SIZE(gcc_parent_data_3), | |
06391edd TD |
1106 | .ops = &clk_rcg2_ops, |
1107 | }, | |
1108 | }; | |
1109 | ||
1110 | static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { | |
1111 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
1112 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), | |
1113 | F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), | |
1114 | { } | |
1115 | }; | |
1116 | ||
1117 | static struct clk_rcg2 gcc_vsensor_clk_src = { | |
1118 | .cmd_rcgr = 0x7a018, | |
1119 | .mnd_width = 0, | |
1120 | .hid_width = 5, | |
1121 | .parent_map = gcc_parent_map_3, | |
1122 | .freq_tbl = ftbl_gcc_vsensor_clk_src, | |
1123 | .clkr.hw.init = &(struct clk_init_data){ | |
1124 | .name = "gcc_vsensor_clk_src", | |
ea434d7a DB |
1125 | .parent_data = gcc_parent_data_8, |
1126 | .num_parents = ARRAY_SIZE(gcc_parent_data_8), | |
06391edd TD |
1127 | .ops = &clk_rcg2_ops, |
1128 | }, | |
1129 | }; | |
1130 | ||
1131 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { | |
1132 | .halt_reg = 0x90014, | |
1133 | .halt_check = BRANCH_HALT, | |
1134 | .clkr = { | |
1135 | .enable_reg = 0x90014, | |
1136 | .enable_mask = BIT(0), | |
1137 | .hw.init = &(struct clk_init_data){ | |
1138 | .name = "gcc_aggre_noc_pcie_tbu_clk", | |
1139 | .ops = &clk_branch2_ops, | |
1140 | }, | |
1141 | }, | |
1142 | }; | |
1143 | ||
1144 | static struct clk_branch gcc_aggre_ufs_card_axi_clk = { | |
1145 | .halt_reg = 0x82028, | |
1146 | .halt_check = BRANCH_HALT, | |
1147 | .hwcg_reg = 0x82028, | |
1148 | .hwcg_bit = 1, | |
1149 | .clkr = { | |
1150 | .enable_reg = 0x82028, | |
1151 | .enable_mask = BIT(0), | |
1152 | .hw.init = &(struct clk_init_data){ | |
1153 | .name = "gcc_aggre_ufs_card_axi_clk", | |
ea434d7a DB |
1154 | .parent_hws = (const struct clk_hw*[]){ |
1155 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
06391edd TD |
1156 | }, |
1157 | .num_parents = 1, | |
1158 | .flags = CLK_SET_RATE_PARENT, | |
1159 | .ops = &clk_branch2_ops, | |
1160 | }, | |
1161 | }, | |
1162 | }; | |
1163 | ||
1164 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { | |
1165 | .halt_reg = 0x82024, | |
1166 | .halt_check = BRANCH_HALT, | |
1167 | .hwcg_reg = 0x82024, | |
1168 | .hwcg_bit = 1, | |
1169 | .clkr = { | |
1170 | .enable_reg = 0x82024, | |
1171 | .enable_mask = BIT(0), | |
1172 | .hw.init = &(struct clk_init_data){ | |
1173 | .name = "gcc_aggre_ufs_phy_axi_clk", | |
ea434d7a DB |
1174 | .parent_hws = (const struct clk_hw*[]){ |
1175 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
06391edd TD |
1176 | }, |
1177 | .num_parents = 1, | |
1178 | .flags = CLK_SET_RATE_PARENT, | |
1179 | .ops = &clk_branch2_ops, | |
1180 | }, | |
1181 | }, | |
1182 | }; | |
1183 | ||
1184 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { | |
1185 | .halt_reg = 0x8201c, | |
1186 | .halt_check = BRANCH_HALT, | |
1187 | .clkr = { | |
1188 | .enable_reg = 0x8201c, | |
1189 | .enable_mask = BIT(0), | |
1190 | .hw.init = &(struct clk_init_data){ | |
1191 | .name = "gcc_aggre_usb3_prim_axi_clk", | |
ea434d7a DB |
1192 | .parent_hws = (const struct clk_hw*[]){ |
1193 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
06391edd TD |
1194 | }, |
1195 | .num_parents = 1, | |
1196 | .flags = CLK_SET_RATE_PARENT, | |
1197 | .ops = &clk_branch2_ops, | |
1198 | }, | |
1199 | }, | |
1200 | }; | |
1201 | ||
1202 | static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { | |
1203 | .halt_reg = 0x82020, | |
1204 | .halt_check = BRANCH_HALT, | |
1205 | .clkr = { | |
1206 | .enable_reg = 0x82020, | |
1207 | .enable_mask = BIT(0), | |
1208 | .hw.init = &(struct clk_init_data){ | |
1209 | .name = "gcc_aggre_usb3_sec_axi_clk", | |
ea434d7a DB |
1210 | .parent_hws = (const struct clk_hw*[]){ |
1211 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
06391edd TD |
1212 | }, |
1213 | .num_parents = 1, | |
1214 | .flags = CLK_SET_RATE_PARENT, | |
1215 | .ops = &clk_branch2_ops, | |
1216 | }, | |
1217 | }, | |
1218 | }; | |
1219 | ||
1220 | static struct clk_branch gcc_apc_vs_clk = { | |
1221 | .halt_reg = 0x7a050, | |
1222 | .halt_check = BRANCH_HALT, | |
1223 | .clkr = { | |
1224 | .enable_reg = 0x7a050, | |
1225 | .enable_mask = BIT(0), | |
1226 | .hw.init = &(struct clk_init_data){ | |
1227 | .name = "gcc_apc_vs_clk", | |
ea434d7a DB |
1228 | .parent_hws = (const struct clk_hw*[]){ |
1229 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
1230 | }, |
1231 | .num_parents = 1, | |
1232 | .flags = CLK_SET_RATE_PARENT, | |
1233 | .ops = &clk_branch2_ops, | |
1234 | }, | |
1235 | }, | |
1236 | }; | |
1237 | ||
1238 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1239 | .halt_reg = 0x38004, | |
1240 | .halt_check = BRANCH_HALT_VOTED, | |
1241 | .hwcg_reg = 0x38004, | |
1242 | .hwcg_bit = 1, | |
1243 | .clkr = { | |
1244 | .enable_reg = 0x52004, | |
1245 | .enable_mask = BIT(10), | |
1246 | .hw.init = &(struct clk_init_data){ | |
1247 | .name = "gcc_boot_rom_ahb_clk", | |
1248 | .ops = &clk_branch2_ops, | |
1249 | }, | |
1250 | }, | |
1251 | }; | |
1252 | ||
1253 | static struct clk_branch gcc_camera_ahb_clk = { | |
1254 | .halt_reg = 0xb008, | |
1255 | .halt_check = BRANCH_HALT, | |
1256 | .hwcg_reg = 0xb008, | |
1257 | .hwcg_bit = 1, | |
1258 | .clkr = { | |
1259 | .enable_reg = 0xb008, | |
1260 | .enable_mask = BIT(0), | |
1261 | .hw.init = &(struct clk_init_data){ | |
1262 | .name = "gcc_camera_ahb_clk", | |
cfb8282e | 1263 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
1264 | .ops = &clk_branch2_ops, |
1265 | }, | |
1266 | }, | |
1267 | }; | |
1268 | ||
1269 | static struct clk_branch gcc_camera_axi_clk = { | |
1270 | .halt_reg = 0xb020, | |
1271 | .halt_check = BRANCH_VOTED, | |
1272 | .clkr = { | |
1273 | .enable_reg = 0xb020, | |
1274 | .enable_mask = BIT(0), | |
1275 | .hw.init = &(struct clk_init_data){ | |
1276 | .name = "gcc_camera_axi_clk", | |
1277 | .ops = &clk_branch2_ops, | |
1278 | }, | |
1279 | }, | |
1280 | }; | |
1281 | ||
1282 | static struct clk_branch gcc_camera_xo_clk = { | |
1283 | .halt_reg = 0xb02c, | |
1284 | .halt_check = BRANCH_HALT, | |
1285 | .clkr = { | |
1286 | .enable_reg = 0xb02c, | |
1287 | .enable_mask = BIT(0), | |
1288 | .hw.init = &(struct clk_init_data){ | |
1289 | .name = "gcc_camera_xo_clk", | |
cfb8282e | 1290 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
1291 | .ops = &clk_branch2_ops, |
1292 | }, | |
1293 | }, | |
1294 | }; | |
1295 | ||
1296 | static struct clk_branch gcc_ce1_ahb_clk = { | |
1297 | .halt_reg = 0x4100c, | |
1298 | .halt_check = BRANCH_HALT_VOTED, | |
1299 | .hwcg_reg = 0x4100c, | |
1300 | .hwcg_bit = 1, | |
1301 | .clkr = { | |
1302 | .enable_reg = 0x52004, | |
1303 | .enable_mask = BIT(3), | |
1304 | .hw.init = &(struct clk_init_data){ | |
1305 | .name = "gcc_ce1_ahb_clk", | |
1306 | .ops = &clk_branch2_ops, | |
1307 | }, | |
1308 | }, | |
1309 | }; | |
1310 | ||
1311 | static struct clk_branch gcc_ce1_axi_clk = { | |
1312 | .halt_reg = 0x41008, | |
1313 | .halt_check = BRANCH_HALT_VOTED, | |
1314 | .clkr = { | |
1315 | .enable_reg = 0x52004, | |
1316 | .enable_mask = BIT(4), | |
1317 | .hw.init = &(struct clk_init_data){ | |
1318 | .name = "gcc_ce1_axi_clk", | |
1319 | .ops = &clk_branch2_ops, | |
1320 | }, | |
1321 | }, | |
1322 | }; | |
1323 | ||
1324 | static struct clk_branch gcc_ce1_clk = { | |
1325 | .halt_reg = 0x41004, | |
1326 | .halt_check = BRANCH_HALT_VOTED, | |
1327 | .clkr = { | |
1328 | .enable_reg = 0x52004, | |
1329 | .enable_mask = BIT(5), | |
1330 | .hw.init = &(struct clk_init_data){ | |
1331 | .name = "gcc_ce1_clk", | |
1332 | .ops = &clk_branch2_ops, | |
1333 | }, | |
1334 | }, | |
1335 | }; | |
1336 | ||
1337 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { | |
1338 | .halt_reg = 0x502c, | |
1339 | .halt_check = BRANCH_HALT, | |
1340 | .clkr = { | |
1341 | .enable_reg = 0x502c, | |
1342 | .enable_mask = BIT(0), | |
1343 | .hw.init = &(struct clk_init_data){ | |
1344 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", | |
ea434d7a DB |
1345 | .parent_hws = (const struct clk_hw*[]){ |
1346 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
06391edd TD |
1347 | }, |
1348 | .num_parents = 1, | |
1349 | .flags = CLK_SET_RATE_PARENT, | |
1350 | .ops = &clk_branch2_ops, | |
1351 | }, | |
1352 | }, | |
1353 | }; | |
1354 | ||
1355 | static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { | |
1356 | .halt_reg = 0x5030, | |
1357 | .halt_check = BRANCH_HALT, | |
1358 | .clkr = { | |
1359 | .enable_reg = 0x5030, | |
1360 | .enable_mask = BIT(0), | |
1361 | .hw.init = &(struct clk_init_data){ | |
1362 | .name = "gcc_cfg_noc_usb3_sec_axi_clk", | |
ea434d7a DB |
1363 | .parent_hws = (const struct clk_hw*[]){ |
1364 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
06391edd TD |
1365 | }, |
1366 | .num_parents = 1, | |
1367 | .flags = CLK_SET_RATE_PARENT, | |
1368 | .ops = &clk_branch2_ops, | |
1369 | }, | |
1370 | }, | |
1371 | }; | |
1372 | ||
1373 | static struct clk_branch gcc_cpuss_ahb_clk = { | |
1374 | .halt_reg = 0x48000, | |
1375 | .halt_check = BRANCH_HALT_VOTED, | |
1376 | .clkr = { | |
1377 | .enable_reg = 0x52004, | |
1378 | .enable_mask = BIT(21), | |
1379 | .hw.init = &(struct clk_init_data){ | |
1380 | .name = "gcc_cpuss_ahb_clk", | |
ea434d7a DB |
1381 | .parent_hws = (const struct clk_hw*[]){ |
1382 | &gcc_cpuss_ahb_clk_src.clkr.hw, | |
06391edd TD |
1383 | }, |
1384 | .num_parents = 1, | |
1385 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, | |
1386 | .ops = &clk_branch2_ops, | |
1387 | }, | |
1388 | }, | |
1389 | }; | |
1390 | ||
1391 | static struct clk_branch gcc_cpuss_rbcpr_clk = { | |
1392 | .halt_reg = 0x48008, | |
1393 | .halt_check = BRANCH_HALT, | |
1394 | .clkr = { | |
1395 | .enable_reg = 0x48008, | |
1396 | .enable_mask = BIT(0), | |
1397 | .hw.init = &(struct clk_init_data){ | |
1398 | .name = "gcc_cpuss_rbcpr_clk", | |
ea434d7a DB |
1399 | .parent_hws = (const struct clk_hw*[]){ |
1400 | &gcc_cpuss_rbcpr_clk_src.clkr.hw, | |
06391edd TD |
1401 | }, |
1402 | .num_parents = 1, | |
1403 | .flags = CLK_SET_RATE_PARENT, | |
1404 | .ops = &clk_branch2_ops, | |
1405 | }, | |
1406 | }, | |
1407 | }; | |
1408 | ||
ae66b1fe RA |
1409 | /* |
1410 | * The source clock frequencies are different for SDM670; define a child clock | |
1411 | * pointing to the source clock that uses SDM670 frequencies. | |
1412 | */ | |
1413 | static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = { | |
1414 | .halt_reg = 0x48008, | |
1415 | .halt_check = BRANCH_HALT, | |
1416 | .clkr = { | |
1417 | .enable_reg = 0x48008, | |
1418 | .enable_mask = BIT(0), | |
1419 | .hw.init = &(struct clk_init_data){ | |
1420 | .name = "gcc_cpuss_rbcpr_clk", | |
1421 | .parent_hws = (const struct clk_hw*[]){ | |
1422 | &gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw, | |
1423 | }, | |
1424 | .num_parents = 1, | |
1425 | .flags = CLK_SET_RATE_PARENT, | |
1426 | .ops = &clk_branch2_ops, | |
1427 | }, | |
1428 | }, | |
1429 | }; | |
1430 | ||
06391edd TD |
1431 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { |
1432 | .halt_reg = 0x44038, | |
1433 | .halt_check = BRANCH_VOTED, | |
1434 | .clkr = { | |
1435 | .enable_reg = 0x44038, | |
1436 | .enable_mask = BIT(0), | |
1437 | .hw.init = &(struct clk_init_data){ | |
1438 | .name = "gcc_ddrss_gpu_axi_clk", | |
1439 | .ops = &clk_branch2_ops, | |
1440 | }, | |
1441 | }, | |
1442 | }; | |
1443 | ||
1444 | static struct clk_branch gcc_disp_ahb_clk = { | |
1445 | .halt_reg = 0xb00c, | |
1446 | .halt_check = BRANCH_HALT, | |
1447 | .hwcg_reg = 0xb00c, | |
1448 | .hwcg_bit = 1, | |
1449 | .clkr = { | |
1450 | .enable_reg = 0xb00c, | |
1451 | .enable_mask = BIT(0), | |
1452 | .hw.init = &(struct clk_init_data){ | |
1453 | .name = "gcc_disp_ahb_clk", | |
cfb8282e | 1454 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
1455 | .ops = &clk_branch2_ops, |
1456 | }, | |
1457 | }, | |
1458 | }; | |
1459 | ||
1460 | static struct clk_branch gcc_disp_axi_clk = { | |
1461 | .halt_reg = 0xb024, | |
1462 | .halt_check = BRANCH_VOTED, | |
1463 | .clkr = { | |
1464 | .enable_reg = 0xb024, | |
1465 | .enable_mask = BIT(0), | |
1466 | .hw.init = &(struct clk_init_data){ | |
1467 | .name = "gcc_disp_axi_clk", | |
1468 | .ops = &clk_branch2_ops, | |
1469 | }, | |
1470 | }, | |
1471 | }; | |
1472 | ||
1473 | static struct clk_branch gcc_disp_gpll0_clk_src = { | |
1474 | .halt_check = BRANCH_HALT_DELAY, | |
1475 | .clkr = { | |
1476 | .enable_reg = 0x52004, | |
1477 | .enable_mask = BIT(18), | |
1478 | .hw.init = &(struct clk_init_data){ | |
1479 | .name = "gcc_disp_gpll0_clk_src", | |
ea434d7a DB |
1480 | .parent_hws = (const struct clk_hw*[]){ |
1481 | &gpll0.clkr.hw, | |
06391edd TD |
1482 | }, |
1483 | .num_parents = 1, | |
9c3df2b1 | 1484 | .ops = &clk_branch2_aon_ops, |
06391edd TD |
1485 | }, |
1486 | }, | |
1487 | }; | |
1488 | ||
1489 | static struct clk_branch gcc_disp_gpll0_div_clk_src = { | |
1490 | .halt_check = BRANCH_HALT_DELAY, | |
1491 | .clkr = { | |
1492 | .enable_reg = 0x52004, | |
1493 | .enable_mask = BIT(19), | |
1494 | .hw.init = &(struct clk_init_data){ | |
1495 | .name = "gcc_disp_gpll0_div_clk_src", | |
ea434d7a DB |
1496 | .parent_hws = (const struct clk_hw*[]){ |
1497 | &gpll0_out_even.clkr.hw, | |
06391edd TD |
1498 | }, |
1499 | .num_parents = 1, | |
1500 | .ops = &clk_branch2_ops, | |
1501 | }, | |
1502 | }, | |
1503 | }; | |
1504 | ||
1505 | static struct clk_branch gcc_disp_xo_clk = { | |
1506 | .halt_reg = 0xb030, | |
1507 | .halt_check = BRANCH_HALT, | |
1508 | .clkr = { | |
1509 | .enable_reg = 0xb030, | |
1510 | .enable_mask = BIT(0), | |
1511 | .hw.init = &(struct clk_init_data){ | |
1512 | .name = "gcc_disp_xo_clk", | |
cfb8282e | 1513 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
1514 | .ops = &clk_branch2_ops, |
1515 | }, | |
1516 | }, | |
1517 | }; | |
1518 | ||
1519 | static struct clk_branch gcc_gp1_clk = { | |
1520 | .halt_reg = 0x64000, | |
1521 | .halt_check = BRANCH_HALT, | |
1522 | .clkr = { | |
1523 | .enable_reg = 0x64000, | |
1524 | .enable_mask = BIT(0), | |
1525 | .hw.init = &(struct clk_init_data){ | |
1526 | .name = "gcc_gp1_clk", | |
ea434d7a DB |
1527 | .parent_hws = (const struct clk_hw*[]){ |
1528 | &gcc_gp1_clk_src.clkr.hw, | |
06391edd TD |
1529 | }, |
1530 | .num_parents = 1, | |
1531 | .flags = CLK_SET_RATE_PARENT, | |
1532 | .ops = &clk_branch2_ops, | |
1533 | }, | |
1534 | }, | |
1535 | }; | |
1536 | ||
1537 | static struct clk_branch gcc_gp2_clk = { | |
1538 | .halt_reg = 0x65000, | |
1539 | .halt_check = BRANCH_HALT, | |
1540 | .clkr = { | |
1541 | .enable_reg = 0x65000, | |
1542 | .enable_mask = BIT(0), | |
1543 | .hw.init = &(struct clk_init_data){ | |
1544 | .name = "gcc_gp2_clk", | |
ea434d7a DB |
1545 | .parent_hws = (const struct clk_hw*[]){ |
1546 | &gcc_gp2_clk_src.clkr.hw, | |
06391edd TD |
1547 | }, |
1548 | .num_parents = 1, | |
1549 | .flags = CLK_SET_RATE_PARENT, | |
1550 | .ops = &clk_branch2_ops, | |
1551 | }, | |
1552 | }, | |
1553 | }; | |
1554 | ||
1555 | static struct clk_branch gcc_gp3_clk = { | |
1556 | .halt_reg = 0x66000, | |
1557 | .halt_check = BRANCH_HALT, | |
1558 | .clkr = { | |
1559 | .enable_reg = 0x66000, | |
1560 | .enable_mask = BIT(0), | |
1561 | .hw.init = &(struct clk_init_data){ | |
1562 | .name = "gcc_gp3_clk", | |
ea434d7a DB |
1563 | .parent_hws = (const struct clk_hw*[]){ |
1564 | &gcc_gp3_clk_src.clkr.hw, | |
06391edd TD |
1565 | }, |
1566 | .num_parents = 1, | |
1567 | .flags = CLK_SET_RATE_PARENT, | |
1568 | .ops = &clk_branch2_ops, | |
1569 | }, | |
1570 | }, | |
1571 | }; | |
1572 | ||
1573 | static struct clk_branch gcc_gpu_cfg_ahb_clk = { | |
1574 | .halt_reg = 0x71004, | |
1575 | .halt_check = BRANCH_HALT, | |
1576 | .hwcg_reg = 0x71004, | |
1577 | .hwcg_bit = 1, | |
1578 | .clkr = { | |
1579 | .enable_reg = 0x71004, | |
1580 | .enable_mask = BIT(0), | |
1581 | .hw.init = &(struct clk_init_data){ | |
1582 | .name = "gcc_gpu_cfg_ahb_clk", | |
cfb8282e | 1583 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
1584 | .ops = &clk_branch2_ops, |
1585 | }, | |
1586 | }, | |
1587 | }; | |
1588 | ||
1589 | static struct clk_branch gcc_gpu_gpll0_clk_src = { | |
1590 | .halt_check = BRANCH_HALT_DELAY, | |
1591 | .clkr = { | |
1592 | .enable_reg = 0x52004, | |
1593 | .enable_mask = BIT(15), | |
1594 | .hw.init = &(struct clk_init_data){ | |
1595 | .name = "gcc_gpu_gpll0_clk_src", | |
ea434d7a DB |
1596 | .parent_hws = (const struct clk_hw*[]){ |
1597 | &gpll0.clkr.hw, | |
06391edd TD |
1598 | }, |
1599 | .num_parents = 1, | |
1600 | .ops = &clk_branch2_ops, | |
1601 | }, | |
1602 | }, | |
1603 | }; | |
1604 | ||
1605 | static struct clk_branch gcc_gpu_gpll0_div_clk_src = { | |
1606 | .halt_check = BRANCH_HALT_DELAY, | |
1607 | .clkr = { | |
1608 | .enable_reg = 0x52004, | |
1609 | .enable_mask = BIT(16), | |
1610 | .hw.init = &(struct clk_init_data){ | |
1611 | .name = "gcc_gpu_gpll0_div_clk_src", | |
ea434d7a DB |
1612 | .parent_hws = (const struct clk_hw*[]){ |
1613 | &gpll0_out_even.clkr.hw, | |
06391edd TD |
1614 | }, |
1615 | .num_parents = 1, | |
1616 | .ops = &clk_branch2_ops, | |
1617 | }, | |
1618 | }, | |
1619 | }; | |
1620 | ||
1621 | static struct clk_branch gcc_gpu_iref_clk = { | |
1622 | .halt_reg = 0x8c010, | |
1623 | .halt_check = BRANCH_HALT, | |
1624 | .clkr = { | |
1625 | .enable_reg = 0x8c010, | |
1626 | .enable_mask = BIT(0), | |
1627 | .hw.init = &(struct clk_init_data){ | |
1628 | .name = "gcc_gpu_iref_clk", | |
1629 | .ops = &clk_branch2_ops, | |
1630 | }, | |
1631 | }, | |
1632 | }; | |
1633 | ||
1634 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { | |
1635 | .halt_reg = 0x7100c, | |
1636 | .halt_check = BRANCH_VOTED, | |
1637 | .clkr = { | |
1638 | .enable_reg = 0x7100c, | |
1639 | .enable_mask = BIT(0), | |
1640 | .hw.init = &(struct clk_init_data){ | |
1641 | .name = "gcc_gpu_memnoc_gfx_clk", | |
1642 | .ops = &clk_branch2_ops, | |
1643 | }, | |
1644 | }, | |
1645 | }; | |
1646 | ||
1647 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { | |
1648 | .halt_reg = 0x71018, | |
1649 | .halt_check = BRANCH_HALT, | |
1650 | .clkr = { | |
1651 | .enable_reg = 0x71018, | |
1652 | .enable_mask = BIT(0), | |
1653 | .hw.init = &(struct clk_init_data){ | |
1654 | .name = "gcc_gpu_snoc_dvm_gfx_clk", | |
1655 | .ops = &clk_branch2_ops, | |
1656 | }, | |
1657 | }, | |
1658 | }; | |
1659 | ||
1660 | static struct clk_branch gcc_gpu_vs_clk = { | |
1661 | .halt_reg = 0x7a04c, | |
1662 | .halt_check = BRANCH_HALT, | |
1663 | .clkr = { | |
1664 | .enable_reg = 0x7a04c, | |
1665 | .enable_mask = BIT(0), | |
1666 | .hw.init = &(struct clk_init_data){ | |
1667 | .name = "gcc_gpu_vs_clk", | |
ea434d7a DB |
1668 | .parent_hws = (const struct clk_hw*[]){ |
1669 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
1670 | }, |
1671 | .num_parents = 1, | |
1672 | .flags = CLK_SET_RATE_PARENT, | |
1673 | .ops = &clk_branch2_ops, | |
1674 | }, | |
1675 | }, | |
1676 | }; | |
1677 | ||
1678 | static struct clk_branch gcc_mss_axis2_clk = { | |
1679 | .halt_reg = 0x8a008, | |
1680 | .halt_check = BRANCH_HALT, | |
1681 | .clkr = { | |
1682 | .enable_reg = 0x8a008, | |
1683 | .enable_mask = BIT(0), | |
1684 | .hw.init = &(struct clk_init_data){ | |
1685 | .name = "gcc_mss_axis2_clk", | |
1686 | .ops = &clk_branch2_ops, | |
1687 | }, | |
1688 | }, | |
1689 | }; | |
1690 | ||
1691 | static struct clk_branch gcc_mss_cfg_ahb_clk = { | |
1692 | .halt_reg = 0x8a000, | |
1693 | .halt_check = BRANCH_HALT, | |
1694 | .hwcg_reg = 0x8a000, | |
1695 | .hwcg_bit = 1, | |
1696 | .clkr = { | |
1697 | .enable_reg = 0x8a000, | |
1698 | .enable_mask = BIT(0), | |
1699 | .hw.init = &(struct clk_init_data){ | |
1700 | .name = "gcc_mss_cfg_ahb_clk", | |
1701 | .ops = &clk_branch2_ops, | |
1702 | }, | |
1703 | }, | |
1704 | }; | |
1705 | ||
1706 | static struct clk_branch gcc_mss_gpll0_div_clk_src = { | |
1707 | .halt_check = BRANCH_HALT_DELAY, | |
1708 | .clkr = { | |
1709 | .enable_reg = 0x52004, | |
1710 | .enable_mask = BIT(17), | |
1711 | .hw.init = &(struct clk_init_data){ | |
1712 | .name = "gcc_mss_gpll0_div_clk_src", | |
1713 | .ops = &clk_branch2_ops, | |
1714 | }, | |
1715 | }, | |
1716 | }; | |
1717 | ||
1718 | static struct clk_branch gcc_mss_mfab_axis_clk = { | |
1719 | .halt_reg = 0x8a004, | |
1720 | .halt_check = BRANCH_VOTED, | |
1721 | .hwcg_reg = 0x8a004, | |
1722 | .hwcg_bit = 1, | |
1723 | .clkr = { | |
1724 | .enable_reg = 0x8a004, | |
1725 | .enable_mask = BIT(0), | |
1726 | .hw.init = &(struct clk_init_data){ | |
1727 | .name = "gcc_mss_mfab_axis_clk", | |
1728 | .ops = &clk_branch2_ops, | |
1729 | }, | |
1730 | }, | |
1731 | }; | |
1732 | ||
1733 | static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { | |
1734 | .halt_reg = 0x8a154, | |
1735 | .halt_check = BRANCH_VOTED, | |
1736 | .clkr = { | |
1737 | .enable_reg = 0x8a154, | |
1738 | .enable_mask = BIT(0), | |
1739 | .hw.init = &(struct clk_init_data){ | |
1740 | .name = "gcc_mss_q6_memnoc_axi_clk", | |
1741 | .ops = &clk_branch2_ops, | |
1742 | }, | |
1743 | }, | |
1744 | }; | |
1745 | ||
1746 | static struct clk_branch gcc_mss_snoc_axi_clk = { | |
1747 | .halt_reg = 0x8a150, | |
1748 | .halt_check = BRANCH_HALT, | |
1749 | .clkr = { | |
1750 | .enable_reg = 0x8a150, | |
1751 | .enable_mask = BIT(0), | |
1752 | .hw.init = &(struct clk_init_data){ | |
1753 | .name = "gcc_mss_snoc_axi_clk", | |
1754 | .ops = &clk_branch2_ops, | |
1755 | }, | |
1756 | }, | |
1757 | }; | |
1758 | ||
1759 | static struct clk_branch gcc_mss_vs_clk = { | |
1760 | .halt_reg = 0x7a048, | |
1761 | .halt_check = BRANCH_HALT, | |
1762 | .clkr = { | |
1763 | .enable_reg = 0x7a048, | |
1764 | .enable_mask = BIT(0), | |
1765 | .hw.init = &(struct clk_init_data){ | |
1766 | .name = "gcc_mss_vs_clk", | |
ea434d7a DB |
1767 | .parent_hws = (const struct clk_hw*[]){ |
1768 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
1769 | }, |
1770 | .num_parents = 1, | |
1771 | .flags = CLK_SET_RATE_PARENT, | |
1772 | .ops = &clk_branch2_ops, | |
1773 | }, | |
1774 | }, | |
1775 | }; | |
1776 | ||
1777 | static struct clk_branch gcc_pcie_0_aux_clk = { | |
1778 | .halt_reg = 0x6b01c, | |
1779 | .halt_check = BRANCH_HALT_VOTED, | |
1780 | .clkr = { | |
1781 | .enable_reg = 0x5200c, | |
1782 | .enable_mask = BIT(3), | |
1783 | .hw.init = &(struct clk_init_data){ | |
1784 | .name = "gcc_pcie_0_aux_clk", | |
ea434d7a DB |
1785 | .parent_hws = (const struct clk_hw*[]){ |
1786 | &gcc_pcie_0_aux_clk_src.clkr.hw, | |
06391edd TD |
1787 | }, |
1788 | .num_parents = 1, | |
1789 | .flags = CLK_SET_RATE_PARENT, | |
1790 | .ops = &clk_branch2_ops, | |
1791 | }, | |
1792 | }, | |
1793 | }; | |
1794 | ||
1795 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
1796 | .halt_reg = 0x6b018, | |
1797 | .halt_check = BRANCH_HALT_VOTED, | |
1798 | .hwcg_reg = 0x6b018, | |
1799 | .hwcg_bit = 1, | |
1800 | .clkr = { | |
1801 | .enable_reg = 0x5200c, | |
1802 | .enable_mask = BIT(2), | |
1803 | .hw.init = &(struct clk_init_data){ | |
1804 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
1805 | .ops = &clk_branch2_ops, | |
1806 | }, | |
1807 | }, | |
1808 | }; | |
1809 | ||
1810 | static struct clk_branch gcc_pcie_0_clkref_clk = { | |
1811 | .halt_reg = 0x8c00c, | |
1812 | .halt_check = BRANCH_HALT, | |
1813 | .clkr = { | |
1814 | .enable_reg = 0x8c00c, | |
1815 | .enable_mask = BIT(0), | |
1816 | .hw.init = &(struct clk_init_data){ | |
1817 | .name = "gcc_pcie_0_clkref_clk", | |
1818 | .ops = &clk_branch2_ops, | |
1819 | }, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
1824 | .halt_reg = 0x6b014, | |
1825 | .halt_check = BRANCH_HALT_VOTED, | |
1826 | .clkr = { | |
1827 | .enable_reg = 0x5200c, | |
1828 | .enable_mask = BIT(1), | |
1829 | .hw.init = &(struct clk_init_data){ | |
1830 | .name = "gcc_pcie_0_mstr_axi_clk", | |
1831 | .ops = &clk_branch2_ops, | |
1832 | }, | |
1833 | }, | |
1834 | }; | |
1835 | ||
1836 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
1837 | .halt_check = BRANCH_HALT_SKIP, | |
1838 | .clkr = { | |
1839 | .enable_reg = 0x5200c, | |
1840 | .enable_mask = BIT(4), | |
1841 | .hw.init = &(struct clk_init_data){ | |
1842 | .name = "gcc_pcie_0_pipe_clk", | |
ea434d7a DB |
1843 | .parent_data = &(const struct clk_parent_data){ |
1844 | .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk", | |
1845 | }, | |
4b5a59a2 BA |
1846 | .num_parents = 1, |
1847 | .flags = CLK_SET_RATE_PARENT, | |
06391edd TD |
1848 | .ops = &clk_branch2_ops, |
1849 | }, | |
1850 | }, | |
1851 | }; | |
1852 | ||
1853 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
1854 | .halt_reg = 0x6b010, | |
1855 | .halt_check = BRANCH_HALT_VOTED, | |
1856 | .hwcg_reg = 0x6b010, | |
1857 | .hwcg_bit = 1, | |
1858 | .clkr = { | |
1859 | .enable_reg = 0x5200c, | |
1860 | .enable_mask = BIT(0), | |
1861 | .hw.init = &(struct clk_init_data){ | |
1862 | .name = "gcc_pcie_0_slv_axi_clk", | |
1863 | .ops = &clk_branch2_ops, | |
1864 | }, | |
1865 | }, | |
1866 | }; | |
1867 | ||
1868 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { | |
1869 | .halt_reg = 0x6b00c, | |
1870 | .halt_check = BRANCH_HALT_VOTED, | |
1871 | .clkr = { | |
1872 | .enable_reg = 0x5200c, | |
1873 | .enable_mask = BIT(5), | |
1874 | .hw.init = &(struct clk_init_data){ | |
1875 | .name = "gcc_pcie_0_slv_q2a_axi_clk", | |
1876 | .ops = &clk_branch2_ops, | |
1877 | }, | |
1878 | }, | |
1879 | }; | |
1880 | ||
1881 | static struct clk_branch gcc_pcie_1_aux_clk = { | |
1882 | .halt_reg = 0x8d01c, | |
1883 | .halt_check = BRANCH_HALT_VOTED, | |
1884 | .clkr = { | |
1885 | .enable_reg = 0x52004, | |
1886 | .enable_mask = BIT(29), | |
1887 | .hw.init = &(struct clk_init_data){ | |
1888 | .name = "gcc_pcie_1_aux_clk", | |
ea434d7a DB |
1889 | .parent_hws = (const struct clk_hw*[]){ |
1890 | &gcc_pcie_1_aux_clk_src.clkr.hw, | |
06391edd TD |
1891 | }, |
1892 | .num_parents = 1, | |
1893 | .flags = CLK_SET_RATE_PARENT, | |
1894 | .ops = &clk_branch2_ops, | |
1895 | }, | |
1896 | }, | |
1897 | }; | |
1898 | ||
1899 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { | |
1900 | .halt_reg = 0x8d018, | |
1901 | .halt_check = BRANCH_HALT_VOTED, | |
1902 | .hwcg_reg = 0x8d018, | |
1903 | .hwcg_bit = 1, | |
1904 | .clkr = { | |
1905 | .enable_reg = 0x52004, | |
1906 | .enable_mask = BIT(28), | |
1907 | .hw.init = &(struct clk_init_data){ | |
1908 | .name = "gcc_pcie_1_cfg_ahb_clk", | |
1909 | .ops = &clk_branch2_ops, | |
1910 | }, | |
1911 | }, | |
1912 | }; | |
1913 | ||
1914 | static struct clk_branch gcc_pcie_1_clkref_clk = { | |
1915 | .halt_reg = 0x8c02c, | |
1916 | .halt_check = BRANCH_HALT, | |
1917 | .clkr = { | |
1918 | .enable_reg = 0x8c02c, | |
1919 | .enable_mask = BIT(0), | |
1920 | .hw.init = &(struct clk_init_data){ | |
1921 | .name = "gcc_pcie_1_clkref_clk", | |
1922 | .ops = &clk_branch2_ops, | |
1923 | }, | |
1924 | }, | |
1925 | }; | |
1926 | ||
1927 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { | |
1928 | .halt_reg = 0x8d014, | |
1929 | .halt_check = BRANCH_HALT_VOTED, | |
1930 | .clkr = { | |
1931 | .enable_reg = 0x52004, | |
1932 | .enable_mask = BIT(27), | |
1933 | .hw.init = &(struct clk_init_data){ | |
1934 | .name = "gcc_pcie_1_mstr_axi_clk", | |
1935 | .ops = &clk_branch2_ops, | |
1936 | }, | |
1937 | }, | |
1938 | }; | |
1939 | ||
1940 | static struct clk_branch gcc_pcie_1_pipe_clk = { | |
1941 | .halt_check = BRANCH_HALT_SKIP, | |
1942 | .clkr = { | |
1943 | .enable_reg = 0x52004, | |
1944 | .enable_mask = BIT(30), | |
1945 | .hw.init = &(struct clk_init_data){ | |
1946 | .name = "gcc_pcie_1_pipe_clk", | |
ea434d7a DB |
1947 | .parent_data = &(const struct clk_parent_data){ |
1948 | .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk", | |
1949 | }, | |
4b5a59a2 | 1950 | .num_parents = 1, |
06391edd TD |
1951 | .ops = &clk_branch2_ops, |
1952 | }, | |
1953 | }, | |
1954 | }; | |
1955 | ||
1956 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { | |
1957 | .halt_reg = 0x8d010, | |
1958 | .halt_check = BRANCH_HALT_VOTED, | |
1959 | .hwcg_reg = 0x8d010, | |
1960 | .hwcg_bit = 1, | |
1961 | .clkr = { | |
1962 | .enable_reg = 0x52004, | |
1963 | .enable_mask = BIT(26), | |
1964 | .hw.init = &(struct clk_init_data){ | |
1965 | .name = "gcc_pcie_1_slv_axi_clk", | |
1966 | .ops = &clk_branch2_ops, | |
1967 | }, | |
1968 | }, | |
1969 | }; | |
1970 | ||
1971 | static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { | |
1972 | .halt_reg = 0x8d00c, | |
1973 | .halt_check = BRANCH_HALT_VOTED, | |
1974 | .clkr = { | |
1975 | .enable_reg = 0x52004, | |
1976 | .enable_mask = BIT(25), | |
1977 | .hw.init = &(struct clk_init_data){ | |
1978 | .name = "gcc_pcie_1_slv_q2a_axi_clk", | |
1979 | .ops = &clk_branch2_ops, | |
1980 | }, | |
1981 | }, | |
1982 | }; | |
1983 | ||
1984 | static struct clk_branch gcc_pcie_phy_aux_clk = { | |
1985 | .halt_reg = 0x6f004, | |
1986 | .halt_check = BRANCH_HALT, | |
1987 | .clkr = { | |
1988 | .enable_reg = 0x6f004, | |
1989 | .enable_mask = BIT(0), | |
1990 | .hw.init = &(struct clk_init_data){ | |
1991 | .name = "gcc_pcie_phy_aux_clk", | |
ea434d7a DB |
1992 | .parent_hws = (const struct clk_hw*[]){ |
1993 | &gcc_pcie_0_aux_clk_src.clkr.hw, | |
06391edd TD |
1994 | }, |
1995 | .num_parents = 1, | |
1996 | .flags = CLK_SET_RATE_PARENT, | |
1997 | .ops = &clk_branch2_ops, | |
1998 | }, | |
1999 | }, | |
2000 | }; | |
2001 | ||
2002 | static struct clk_branch gcc_pcie_phy_refgen_clk = { | |
2003 | .halt_reg = 0x6f02c, | |
2004 | .halt_check = BRANCH_HALT, | |
2005 | .clkr = { | |
2006 | .enable_reg = 0x6f02c, | |
2007 | .enable_mask = BIT(0), | |
2008 | .hw.init = &(struct clk_init_data){ | |
2009 | .name = "gcc_pcie_phy_refgen_clk", | |
ea434d7a DB |
2010 | .parent_hws = (const struct clk_hw*[]){ |
2011 | &gcc_pcie_phy_refgen_clk_src.clkr.hw, | |
06391edd TD |
2012 | }, |
2013 | .num_parents = 1, | |
2014 | .flags = CLK_SET_RATE_PARENT, | |
2015 | .ops = &clk_branch2_ops, | |
2016 | }, | |
2017 | }, | |
2018 | }; | |
2019 | ||
2020 | static struct clk_branch gcc_pdm2_clk = { | |
2021 | .halt_reg = 0x3300c, | |
2022 | .halt_check = BRANCH_HALT, | |
2023 | .clkr = { | |
2024 | .enable_reg = 0x3300c, | |
2025 | .enable_mask = BIT(0), | |
2026 | .hw.init = &(struct clk_init_data){ | |
2027 | .name = "gcc_pdm2_clk", | |
ea434d7a DB |
2028 | .parent_hws = (const struct clk_hw*[]){ |
2029 | &gcc_pdm2_clk_src.clkr.hw, | |
06391edd TD |
2030 | }, |
2031 | .num_parents = 1, | |
2032 | .flags = CLK_SET_RATE_PARENT, | |
2033 | .ops = &clk_branch2_ops, | |
2034 | }, | |
2035 | }, | |
2036 | }; | |
2037 | ||
2038 | static struct clk_branch gcc_pdm_ahb_clk = { | |
2039 | .halt_reg = 0x33004, | |
2040 | .halt_check = BRANCH_HALT, | |
2041 | .hwcg_reg = 0x33004, | |
2042 | .hwcg_bit = 1, | |
2043 | .clkr = { | |
2044 | .enable_reg = 0x33004, | |
2045 | .enable_mask = BIT(0), | |
2046 | .hw.init = &(struct clk_init_data){ | |
2047 | .name = "gcc_pdm_ahb_clk", | |
2048 | .ops = &clk_branch2_ops, | |
2049 | }, | |
2050 | }, | |
2051 | }; | |
2052 | ||
2053 | static struct clk_branch gcc_pdm_xo4_clk = { | |
2054 | .halt_reg = 0x33008, | |
2055 | .halt_check = BRANCH_HALT, | |
2056 | .clkr = { | |
2057 | .enable_reg = 0x33008, | |
2058 | .enable_mask = BIT(0), | |
2059 | .hw.init = &(struct clk_init_data){ | |
2060 | .name = "gcc_pdm_xo4_clk", | |
2061 | .ops = &clk_branch2_ops, | |
2062 | }, | |
2063 | }, | |
2064 | }; | |
2065 | ||
2066 | static struct clk_branch gcc_prng_ahb_clk = { | |
2067 | .halt_reg = 0x34004, | |
2068 | .halt_check = BRANCH_HALT_VOTED, | |
2069 | .hwcg_reg = 0x34004, | |
2070 | .hwcg_bit = 1, | |
2071 | .clkr = { | |
2072 | .enable_reg = 0x52004, | |
2073 | .enable_mask = BIT(13), | |
2074 | .hw.init = &(struct clk_init_data){ | |
2075 | .name = "gcc_prng_ahb_clk", | |
2076 | .ops = &clk_branch2_ops, | |
2077 | }, | |
2078 | }, | |
2079 | }; | |
2080 | ||
2081 | static struct clk_branch gcc_qmip_camera_ahb_clk = { | |
2082 | .halt_reg = 0xb014, | |
2083 | .halt_check = BRANCH_HALT, | |
2084 | .hwcg_reg = 0xb014, | |
2085 | .hwcg_bit = 1, | |
2086 | .clkr = { | |
2087 | .enable_reg = 0xb014, | |
2088 | .enable_mask = BIT(0), | |
2089 | .hw.init = &(struct clk_init_data){ | |
2090 | .name = "gcc_qmip_camera_ahb_clk", | |
2091 | .ops = &clk_branch2_ops, | |
2092 | }, | |
2093 | }, | |
2094 | }; | |
2095 | ||
2096 | static struct clk_branch gcc_qmip_disp_ahb_clk = { | |
2097 | .halt_reg = 0xb018, | |
2098 | .halt_check = BRANCH_HALT, | |
2099 | .hwcg_reg = 0xb018, | |
2100 | .hwcg_bit = 1, | |
2101 | .clkr = { | |
2102 | .enable_reg = 0xb018, | |
2103 | .enable_mask = BIT(0), | |
2104 | .hw.init = &(struct clk_init_data){ | |
2105 | .name = "gcc_qmip_disp_ahb_clk", | |
2106 | .ops = &clk_branch2_ops, | |
2107 | }, | |
2108 | }, | |
2109 | }; | |
2110 | ||
2111 | static struct clk_branch gcc_qmip_video_ahb_clk = { | |
2112 | .halt_reg = 0xb010, | |
2113 | .halt_check = BRANCH_HALT, | |
2114 | .hwcg_reg = 0xb010, | |
2115 | .hwcg_bit = 1, | |
2116 | .clkr = { | |
2117 | .enable_reg = 0xb010, | |
2118 | .enable_mask = BIT(0), | |
2119 | .hw.init = &(struct clk_init_data){ | |
2120 | .name = "gcc_qmip_video_ahb_clk", | |
2121 | .ops = &clk_branch2_ops, | |
2122 | }, | |
2123 | }, | |
2124 | }; | |
2125 | ||
4f83d9b8 DA |
2126 | static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { |
2127 | .halt_reg = 0x4b000, | |
2128 | .halt_check = BRANCH_HALT, | |
2129 | .clkr = { | |
2130 | .enable_reg = 0x4b000, | |
2131 | .enable_mask = BIT(0), | |
2132 | .hw.init = &(struct clk_init_data){ | |
2133 | .name = "gcc_qspi_cnoc_periph_ahb_clk", | |
2134 | .ops = &clk_branch2_ops, | |
2135 | }, | |
2136 | }, | |
2137 | }; | |
2138 | ||
2139 | static struct clk_branch gcc_qspi_core_clk = { | |
2140 | .halt_reg = 0x4b004, | |
2141 | .halt_check = BRANCH_HALT, | |
2142 | .clkr = { | |
2143 | .enable_reg = 0x4b004, | |
2144 | .enable_mask = BIT(0), | |
2145 | .hw.init = &(struct clk_init_data){ | |
2146 | .name = "gcc_qspi_core_clk", | |
ea434d7a DB |
2147 | .parent_hws = (const struct clk_hw*[]){ |
2148 | &gcc_qspi_core_clk_src.clkr.hw, | |
4f83d9b8 DA |
2149 | }, |
2150 | .num_parents = 1, | |
2151 | .flags = CLK_SET_RATE_PARENT, | |
2152 | .ops = &clk_branch2_ops, | |
2153 | }, | |
2154 | }, | |
2155 | }; | |
2156 | ||
06391edd TD |
2157 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { |
2158 | .halt_reg = 0x17030, | |
2159 | .halt_check = BRANCH_HALT_VOTED, | |
2160 | .clkr = { | |
2161 | .enable_reg = 0x5200c, | |
2162 | .enable_mask = BIT(10), | |
2163 | .hw.init = &(struct clk_init_data){ | |
2164 | .name = "gcc_qupv3_wrap0_s0_clk", | |
ea434d7a DB |
2165 | .parent_hws = (const struct clk_hw*[]){ |
2166 | &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, | |
06391edd TD |
2167 | }, |
2168 | .num_parents = 1, | |
2169 | .flags = CLK_SET_RATE_PARENT, | |
2170 | .ops = &clk_branch2_ops, | |
2171 | }, | |
2172 | }, | |
2173 | }; | |
2174 | ||
2175 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { | |
2176 | .halt_reg = 0x17160, | |
2177 | .halt_check = BRANCH_HALT_VOTED, | |
2178 | .clkr = { | |
2179 | .enable_reg = 0x5200c, | |
2180 | .enable_mask = BIT(11), | |
2181 | .hw.init = &(struct clk_init_data){ | |
2182 | .name = "gcc_qupv3_wrap0_s1_clk", | |
ea434d7a DB |
2183 | .parent_hws = (const struct clk_hw*[]){ |
2184 | &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, | |
06391edd TD |
2185 | }, |
2186 | .num_parents = 1, | |
2187 | .flags = CLK_SET_RATE_PARENT, | |
2188 | .ops = &clk_branch2_ops, | |
2189 | }, | |
2190 | }, | |
2191 | }; | |
2192 | ||
2193 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { | |
2194 | .halt_reg = 0x17290, | |
2195 | .halt_check = BRANCH_HALT_VOTED, | |
2196 | .clkr = { | |
2197 | .enable_reg = 0x5200c, | |
2198 | .enable_mask = BIT(12), | |
2199 | .hw.init = &(struct clk_init_data){ | |
2200 | .name = "gcc_qupv3_wrap0_s2_clk", | |
ea434d7a DB |
2201 | .parent_hws = (const struct clk_hw*[]){ |
2202 | &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, | |
06391edd TD |
2203 | }, |
2204 | .num_parents = 1, | |
2205 | .flags = CLK_SET_RATE_PARENT, | |
2206 | .ops = &clk_branch2_ops, | |
2207 | }, | |
2208 | }, | |
2209 | }; | |
2210 | ||
2211 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { | |
2212 | .halt_reg = 0x173c0, | |
2213 | .halt_check = BRANCH_HALT_VOTED, | |
2214 | .clkr = { | |
2215 | .enable_reg = 0x5200c, | |
2216 | .enable_mask = BIT(13), | |
2217 | .hw.init = &(struct clk_init_data){ | |
2218 | .name = "gcc_qupv3_wrap0_s3_clk", | |
ea434d7a DB |
2219 | .parent_hws = (const struct clk_hw*[]){ |
2220 | &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, | |
06391edd TD |
2221 | }, |
2222 | .num_parents = 1, | |
2223 | .flags = CLK_SET_RATE_PARENT, | |
2224 | .ops = &clk_branch2_ops, | |
2225 | }, | |
2226 | }, | |
2227 | }; | |
2228 | ||
2229 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { | |
2230 | .halt_reg = 0x174f0, | |
2231 | .halt_check = BRANCH_HALT_VOTED, | |
2232 | .clkr = { | |
2233 | .enable_reg = 0x5200c, | |
2234 | .enable_mask = BIT(14), | |
2235 | .hw.init = &(struct clk_init_data){ | |
2236 | .name = "gcc_qupv3_wrap0_s4_clk", | |
ea434d7a DB |
2237 | .parent_hws = (const struct clk_hw*[]){ |
2238 | &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, | |
06391edd TD |
2239 | }, |
2240 | .num_parents = 1, | |
2241 | .flags = CLK_SET_RATE_PARENT, | |
2242 | .ops = &clk_branch2_ops, | |
2243 | }, | |
2244 | }, | |
2245 | }; | |
2246 | ||
2247 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { | |
2248 | .halt_reg = 0x17620, | |
2249 | .halt_check = BRANCH_HALT_VOTED, | |
2250 | .clkr = { | |
2251 | .enable_reg = 0x5200c, | |
2252 | .enable_mask = BIT(15), | |
2253 | .hw.init = &(struct clk_init_data){ | |
2254 | .name = "gcc_qupv3_wrap0_s5_clk", | |
ea434d7a DB |
2255 | .parent_hws = (const struct clk_hw*[]){ |
2256 | &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, | |
06391edd TD |
2257 | }, |
2258 | .num_parents = 1, | |
2259 | .flags = CLK_SET_RATE_PARENT, | |
2260 | .ops = &clk_branch2_ops, | |
2261 | }, | |
2262 | }, | |
2263 | }; | |
2264 | ||
2265 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { | |
2266 | .halt_reg = 0x17750, | |
2267 | .halt_check = BRANCH_HALT_VOTED, | |
2268 | .clkr = { | |
2269 | .enable_reg = 0x5200c, | |
2270 | .enable_mask = BIT(16), | |
2271 | .hw.init = &(struct clk_init_data){ | |
2272 | .name = "gcc_qupv3_wrap0_s6_clk", | |
ea434d7a DB |
2273 | .parent_hws = (const struct clk_hw*[]){ |
2274 | &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, | |
06391edd TD |
2275 | }, |
2276 | .num_parents = 1, | |
2277 | .flags = CLK_SET_RATE_PARENT, | |
2278 | .ops = &clk_branch2_ops, | |
2279 | }, | |
2280 | }, | |
2281 | }; | |
2282 | ||
2283 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { | |
2284 | .halt_reg = 0x17880, | |
2285 | .halt_check = BRANCH_HALT_VOTED, | |
2286 | .clkr = { | |
2287 | .enable_reg = 0x5200c, | |
2288 | .enable_mask = BIT(17), | |
2289 | .hw.init = &(struct clk_init_data){ | |
2290 | .name = "gcc_qupv3_wrap0_s7_clk", | |
ea434d7a DB |
2291 | .parent_hws = (const struct clk_hw*[]){ |
2292 | &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, | |
06391edd TD |
2293 | }, |
2294 | .num_parents = 1, | |
2295 | .flags = CLK_SET_RATE_PARENT, | |
2296 | .ops = &clk_branch2_ops, | |
2297 | }, | |
2298 | }, | |
2299 | }; | |
2300 | ||
2301 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { | |
2302 | .halt_reg = 0x18014, | |
2303 | .halt_check = BRANCH_HALT_VOTED, | |
2304 | .clkr = { | |
2305 | .enable_reg = 0x5200c, | |
2306 | .enable_mask = BIT(22), | |
2307 | .hw.init = &(struct clk_init_data){ | |
2308 | .name = "gcc_qupv3_wrap1_s0_clk", | |
ea434d7a DB |
2309 | .parent_hws = (const struct clk_hw*[]){ |
2310 | &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, | |
06391edd TD |
2311 | }, |
2312 | .num_parents = 1, | |
2313 | .flags = CLK_SET_RATE_PARENT, | |
2314 | .ops = &clk_branch2_ops, | |
2315 | }, | |
2316 | }, | |
2317 | }; | |
2318 | ||
2319 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { | |
2320 | .halt_reg = 0x18144, | |
2321 | .halt_check = BRANCH_HALT_VOTED, | |
2322 | .clkr = { | |
2323 | .enable_reg = 0x5200c, | |
2324 | .enable_mask = BIT(23), | |
2325 | .hw.init = &(struct clk_init_data){ | |
2326 | .name = "gcc_qupv3_wrap1_s1_clk", | |
ea434d7a DB |
2327 | .parent_hws = (const struct clk_hw*[]){ |
2328 | &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, | |
06391edd TD |
2329 | }, |
2330 | .num_parents = 1, | |
2331 | .flags = CLK_SET_RATE_PARENT, | |
2332 | .ops = &clk_branch2_ops, | |
2333 | }, | |
2334 | }, | |
2335 | }; | |
2336 | ||
2337 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { | |
2338 | .halt_reg = 0x18274, | |
2339 | .halt_check = BRANCH_HALT_VOTED, | |
2340 | .clkr = { | |
2341 | .enable_reg = 0x5200c, | |
2342 | .enable_mask = BIT(24), | |
2343 | .hw.init = &(struct clk_init_data){ | |
2344 | .name = "gcc_qupv3_wrap1_s2_clk", | |
ea434d7a DB |
2345 | .parent_hws = (const struct clk_hw*[]){ |
2346 | &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, | |
06391edd TD |
2347 | }, |
2348 | .num_parents = 1, | |
2349 | .flags = CLK_SET_RATE_PARENT, | |
2350 | .ops = &clk_branch2_ops, | |
2351 | }, | |
2352 | }, | |
2353 | }; | |
2354 | ||
2355 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { | |
2356 | .halt_reg = 0x183a4, | |
2357 | .halt_check = BRANCH_HALT_VOTED, | |
2358 | .clkr = { | |
2359 | .enable_reg = 0x5200c, | |
2360 | .enable_mask = BIT(25), | |
2361 | .hw.init = &(struct clk_init_data){ | |
2362 | .name = "gcc_qupv3_wrap1_s3_clk", | |
ea434d7a DB |
2363 | .parent_hws = (const struct clk_hw*[]){ |
2364 | &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, | |
06391edd TD |
2365 | }, |
2366 | .num_parents = 1, | |
2367 | .flags = CLK_SET_RATE_PARENT, | |
2368 | .ops = &clk_branch2_ops, | |
2369 | }, | |
2370 | }, | |
2371 | }; | |
2372 | ||
2373 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { | |
2374 | .halt_reg = 0x184d4, | |
2375 | .halt_check = BRANCH_HALT_VOTED, | |
2376 | .clkr = { | |
2377 | .enable_reg = 0x5200c, | |
2378 | .enable_mask = BIT(26), | |
2379 | .hw.init = &(struct clk_init_data){ | |
2380 | .name = "gcc_qupv3_wrap1_s4_clk", | |
ea434d7a DB |
2381 | .parent_hws = (const struct clk_hw*[]){ |
2382 | &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, | |
06391edd TD |
2383 | }, |
2384 | .num_parents = 1, | |
2385 | .flags = CLK_SET_RATE_PARENT, | |
2386 | .ops = &clk_branch2_ops, | |
2387 | }, | |
2388 | }, | |
2389 | }; | |
2390 | ||
2391 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { | |
2392 | .halt_reg = 0x18604, | |
2393 | .halt_check = BRANCH_HALT_VOTED, | |
2394 | .clkr = { | |
2395 | .enable_reg = 0x5200c, | |
2396 | .enable_mask = BIT(27), | |
2397 | .hw.init = &(struct clk_init_data){ | |
2398 | .name = "gcc_qupv3_wrap1_s5_clk", | |
ea434d7a DB |
2399 | .parent_hws = (const struct clk_hw*[]){ |
2400 | &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, | |
06391edd TD |
2401 | }, |
2402 | .num_parents = 1, | |
2403 | .flags = CLK_SET_RATE_PARENT, | |
2404 | .ops = &clk_branch2_ops, | |
2405 | }, | |
2406 | }, | |
2407 | }; | |
2408 | ||
2409 | static struct clk_branch gcc_qupv3_wrap1_s6_clk = { | |
2410 | .halt_reg = 0x18734, | |
2411 | .halt_check = BRANCH_HALT_VOTED, | |
2412 | .clkr = { | |
2413 | .enable_reg = 0x5200c, | |
2414 | .enable_mask = BIT(28), | |
2415 | .hw.init = &(struct clk_init_data){ | |
2416 | .name = "gcc_qupv3_wrap1_s6_clk", | |
ea434d7a DB |
2417 | .parent_hws = (const struct clk_hw*[]){ |
2418 | &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, | |
06391edd TD |
2419 | }, |
2420 | .num_parents = 1, | |
2421 | .flags = CLK_SET_RATE_PARENT, | |
2422 | .ops = &clk_branch2_ops, | |
2423 | }, | |
2424 | }, | |
2425 | }; | |
2426 | ||
2427 | static struct clk_branch gcc_qupv3_wrap1_s7_clk = { | |
2428 | .halt_reg = 0x18864, | |
2429 | .halt_check = BRANCH_HALT_VOTED, | |
2430 | .clkr = { | |
2431 | .enable_reg = 0x5200c, | |
2432 | .enable_mask = BIT(29), | |
2433 | .hw.init = &(struct clk_init_data){ | |
2434 | .name = "gcc_qupv3_wrap1_s7_clk", | |
ea434d7a DB |
2435 | .parent_hws = (const struct clk_hw*[]){ |
2436 | &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, | |
06391edd TD |
2437 | }, |
2438 | .num_parents = 1, | |
2439 | .flags = CLK_SET_RATE_PARENT, | |
2440 | .ops = &clk_branch2_ops, | |
2441 | }, | |
2442 | }, | |
2443 | }; | |
2444 | ||
2445 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { | |
2446 | .halt_reg = 0x17004, | |
2447 | .halt_check = BRANCH_HALT_VOTED, | |
2448 | .clkr = { | |
2449 | .enable_reg = 0x5200c, | |
2450 | .enable_mask = BIT(6), | |
2451 | .hw.init = &(struct clk_init_data){ | |
2452 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", | |
2453 | .ops = &clk_branch2_ops, | |
2454 | }, | |
2455 | }, | |
2456 | }; | |
2457 | ||
2458 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { | |
2459 | .halt_reg = 0x17008, | |
2460 | .halt_check = BRANCH_HALT_VOTED, | |
2461 | .hwcg_reg = 0x17008, | |
2462 | .hwcg_bit = 1, | |
2463 | .clkr = { | |
2464 | .enable_reg = 0x5200c, | |
2465 | .enable_mask = BIT(7), | |
2466 | .hw.init = &(struct clk_init_data){ | |
2467 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", | |
2468 | .ops = &clk_branch2_ops, | |
2469 | }, | |
2470 | }, | |
2471 | }; | |
2472 | ||
2473 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { | |
2474 | .halt_reg = 0x1800c, | |
2475 | .halt_check = BRANCH_HALT_VOTED, | |
2476 | .clkr = { | |
2477 | .enable_reg = 0x5200c, | |
2478 | .enable_mask = BIT(20), | |
2479 | .hw.init = &(struct clk_init_data){ | |
2480 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", | |
2481 | .ops = &clk_branch2_ops, | |
2482 | }, | |
2483 | }, | |
2484 | }; | |
2485 | ||
2486 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { | |
2487 | .halt_reg = 0x18010, | |
2488 | .halt_check = BRANCH_HALT_VOTED, | |
2489 | .hwcg_reg = 0x18010, | |
2490 | .hwcg_bit = 1, | |
2491 | .clkr = { | |
2492 | .enable_reg = 0x5200c, | |
2493 | .enable_mask = BIT(21), | |
2494 | .hw.init = &(struct clk_init_data){ | |
2495 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", | |
2496 | .ops = &clk_branch2_ops, | |
2497 | }, | |
2498 | }, | |
2499 | }; | |
2500 | ||
ae66b1fe RA |
2501 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
2502 | .halt_reg = 0x26008, | |
2503 | .halt_check = BRANCH_HALT, | |
2504 | .clkr = { | |
2505 | .enable_reg = 0x26008, | |
2506 | .enable_mask = BIT(0), | |
2507 | .hw.init = &(struct clk_init_data){ | |
2508 | .name = "gcc_sdcc1_ahb_clk", | |
2509 | .ops = &clk_branch2_ops, | |
2510 | }, | |
2511 | }, | |
2512 | }; | |
2513 | ||
2514 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
2515 | .halt_reg = 0x26004, | |
2516 | .halt_check = BRANCH_HALT, | |
2517 | .clkr = { | |
2518 | .enable_reg = 0x26004, | |
2519 | .enable_mask = BIT(0), | |
2520 | .hw.init = &(struct clk_init_data){ | |
2521 | .name = "gcc_sdcc1_apps_clk", | |
2522 | .parent_hws = (const struct clk_hw*[]){ | |
2523 | &gcc_sdcc1_apps_clk_src.clkr.hw, | |
2524 | }, | |
2525 | .num_parents = 1, | |
2526 | .flags = CLK_SET_RATE_PARENT, | |
2527 | .ops = &clk_branch2_ops, | |
2528 | }, | |
2529 | }, | |
2530 | }; | |
2531 | ||
2532 | static struct clk_branch gcc_sdcc1_ice_core_clk = { | |
2533 | .halt_reg = 0x2600c, | |
2534 | .halt_check = BRANCH_HALT, | |
2535 | .clkr = { | |
2536 | .enable_reg = 0x2600c, | |
2537 | .enable_mask = BIT(0), | |
2538 | .hw.init = &(struct clk_init_data){ | |
2539 | .name = "gcc_sdcc1_ice_core_clk", | |
2540 | .parent_hws = (const struct clk_hw*[]){ | |
2541 | &gcc_sdcc1_ice_core_clk_src.clkr.hw, | |
2542 | }, | |
2543 | .num_parents = 1, | |
2544 | .flags = CLK_SET_RATE_PARENT, | |
2545 | .ops = &clk_branch2_ops, | |
2546 | }, | |
2547 | }, | |
2548 | }; | |
2549 | ||
06391edd TD |
2550 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
2551 | .halt_reg = 0x14008, | |
2552 | .halt_check = BRANCH_HALT, | |
2553 | .clkr = { | |
2554 | .enable_reg = 0x14008, | |
2555 | .enable_mask = BIT(0), | |
2556 | .hw.init = &(struct clk_init_data){ | |
2557 | .name = "gcc_sdcc2_ahb_clk", | |
2558 | .ops = &clk_branch2_ops, | |
2559 | }, | |
2560 | }, | |
2561 | }; | |
2562 | ||
2563 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2564 | .halt_reg = 0x14004, | |
2565 | .halt_check = BRANCH_HALT, | |
2566 | .clkr = { | |
2567 | .enable_reg = 0x14004, | |
2568 | .enable_mask = BIT(0), | |
2569 | .hw.init = &(struct clk_init_data){ | |
2570 | .name = "gcc_sdcc2_apps_clk", | |
ea434d7a DB |
2571 | .parent_hws = (const struct clk_hw*[]){ |
2572 | &gcc_sdcc2_apps_clk_src.clkr.hw, | |
06391edd TD |
2573 | }, |
2574 | .num_parents = 1, | |
2575 | .flags = CLK_SET_RATE_PARENT, | |
2576 | .ops = &clk_branch2_ops, | |
2577 | }, | |
2578 | }, | |
2579 | }; | |
2580 | ||
2581 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2582 | .halt_reg = 0x16008, | |
2583 | .halt_check = BRANCH_HALT, | |
2584 | .clkr = { | |
2585 | .enable_reg = 0x16008, | |
2586 | .enable_mask = BIT(0), | |
2587 | .hw.init = &(struct clk_init_data){ | |
2588 | .name = "gcc_sdcc4_ahb_clk", | |
2589 | .ops = &clk_branch2_ops, | |
2590 | }, | |
2591 | }, | |
2592 | }; | |
2593 | ||
2594 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2595 | .halt_reg = 0x16004, | |
2596 | .halt_check = BRANCH_HALT, | |
2597 | .clkr = { | |
2598 | .enable_reg = 0x16004, | |
2599 | .enable_mask = BIT(0), | |
2600 | .hw.init = &(struct clk_init_data){ | |
2601 | .name = "gcc_sdcc4_apps_clk", | |
ea434d7a DB |
2602 | .parent_hws = (const struct clk_hw*[]){ |
2603 | &gcc_sdcc4_apps_clk_src.clkr.hw, | |
06391edd TD |
2604 | }, |
2605 | .num_parents = 1, | |
2606 | .flags = CLK_SET_RATE_PARENT, | |
2607 | .ops = &clk_branch2_ops, | |
2608 | }, | |
2609 | }, | |
2610 | }; | |
2611 | ||
ae66b1fe RA |
2612 | /* |
2613 | * The source clock frequencies are different for SDM670; define a child clock | |
2614 | * pointing to the source clock that uses SDM670 frequencies. | |
2615 | */ | |
2616 | static struct clk_branch gcc_sdm670_sdcc4_apps_clk = { | |
2617 | .halt_reg = 0x16004, | |
2618 | .halt_check = BRANCH_HALT, | |
2619 | .clkr = { | |
2620 | .enable_reg = 0x16004, | |
2621 | .enable_mask = BIT(0), | |
2622 | .hw.init = &(struct clk_init_data){ | |
2623 | .name = "gcc_sdcc4_apps_clk", | |
2624 | .parent_hws = (const struct clk_hw*[]){ | |
2625 | &gcc_sdm670_sdcc4_apps_clk_src.clkr.hw, | |
2626 | }, | |
2627 | .num_parents = 1, | |
2628 | .flags = CLK_SET_RATE_PARENT, | |
2629 | .ops = &clk_branch2_ops, | |
2630 | }, | |
2631 | }, | |
2632 | }; | |
2633 | ||
06391edd TD |
2634 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { |
2635 | .halt_reg = 0x414c, | |
2636 | .halt_check = BRANCH_HALT_VOTED, | |
2637 | .clkr = { | |
2638 | .enable_reg = 0x52004, | |
2639 | .enable_mask = BIT(0), | |
2640 | .hw.init = &(struct clk_init_data){ | |
2641 | .name = "gcc_sys_noc_cpuss_ahb_clk", | |
ea434d7a DB |
2642 | .parent_hws = (const struct clk_hw*[]){ |
2643 | &gcc_cpuss_ahb_clk_src.clkr.hw, | |
06391edd TD |
2644 | }, |
2645 | .num_parents = 1, | |
2646 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, | |
2647 | .ops = &clk_branch2_ops, | |
2648 | }, | |
2649 | }, | |
2650 | }; | |
2651 | ||
2652 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2653 | .halt_reg = 0x36004, | |
2654 | .halt_check = BRANCH_HALT, | |
2655 | .clkr = { | |
2656 | .enable_reg = 0x36004, | |
2657 | .enable_mask = BIT(0), | |
2658 | .hw.init = &(struct clk_init_data){ | |
2659 | .name = "gcc_tsif_ahb_clk", | |
2660 | .ops = &clk_branch2_ops, | |
2661 | }, | |
2662 | }, | |
2663 | }; | |
2664 | ||
2665 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { | |
2666 | .halt_reg = 0x3600c, | |
2667 | .halt_check = BRANCH_HALT, | |
2668 | .clkr = { | |
2669 | .enable_reg = 0x3600c, | |
2670 | .enable_mask = BIT(0), | |
2671 | .hw.init = &(struct clk_init_data){ | |
2672 | .name = "gcc_tsif_inactivity_timers_clk", | |
2673 | .ops = &clk_branch2_ops, | |
2674 | }, | |
2675 | }, | |
2676 | }; | |
2677 | ||
2678 | static struct clk_branch gcc_tsif_ref_clk = { | |
2679 | .halt_reg = 0x36008, | |
2680 | .halt_check = BRANCH_HALT, | |
2681 | .clkr = { | |
2682 | .enable_reg = 0x36008, | |
2683 | .enable_mask = BIT(0), | |
2684 | .hw.init = &(struct clk_init_data){ | |
2685 | .name = "gcc_tsif_ref_clk", | |
ea434d7a DB |
2686 | .parent_hws = (const struct clk_hw*[]){ |
2687 | &gcc_tsif_ref_clk_src.clkr.hw, | |
06391edd TD |
2688 | }, |
2689 | .num_parents = 1, | |
2690 | .flags = CLK_SET_RATE_PARENT, | |
2691 | .ops = &clk_branch2_ops, | |
2692 | }, | |
2693 | }, | |
2694 | }; | |
2695 | ||
2696 | static struct clk_branch gcc_ufs_card_ahb_clk = { | |
2697 | .halt_reg = 0x75010, | |
2698 | .halt_check = BRANCH_HALT, | |
2699 | .hwcg_reg = 0x75010, | |
2700 | .hwcg_bit = 1, | |
2701 | .clkr = { | |
2702 | .enable_reg = 0x75010, | |
2703 | .enable_mask = BIT(0), | |
2704 | .hw.init = &(struct clk_init_data){ | |
2705 | .name = "gcc_ufs_card_ahb_clk", | |
2706 | .ops = &clk_branch2_ops, | |
2707 | }, | |
2708 | }, | |
2709 | }; | |
2710 | ||
2711 | static struct clk_branch gcc_ufs_card_axi_clk = { | |
2712 | .halt_reg = 0x7500c, | |
2713 | .halt_check = BRANCH_HALT, | |
2714 | .hwcg_reg = 0x7500c, | |
2715 | .hwcg_bit = 1, | |
2716 | .clkr = { | |
2717 | .enable_reg = 0x7500c, | |
2718 | .enable_mask = BIT(0), | |
2719 | .hw.init = &(struct clk_init_data){ | |
2720 | .name = "gcc_ufs_card_axi_clk", | |
ea434d7a DB |
2721 | .parent_hws = (const struct clk_hw*[]){ |
2722 | &gcc_ufs_card_axi_clk_src.clkr.hw, | |
06391edd TD |
2723 | }, |
2724 | .num_parents = 1, | |
2725 | .flags = CLK_SET_RATE_PARENT, | |
2726 | .ops = &clk_branch2_ops, | |
2727 | }, | |
2728 | }, | |
2729 | }; | |
2730 | ||
2731 | static struct clk_branch gcc_ufs_card_clkref_clk = { | |
2732 | .halt_reg = 0x8c004, | |
2733 | .halt_check = BRANCH_HALT, | |
2734 | .clkr = { | |
2735 | .enable_reg = 0x8c004, | |
2736 | .enable_mask = BIT(0), | |
2737 | .hw.init = &(struct clk_init_data){ | |
2738 | .name = "gcc_ufs_card_clkref_clk", | |
2739 | .ops = &clk_branch2_ops, | |
2740 | }, | |
2741 | }, | |
2742 | }; | |
2743 | ||
2744 | static struct clk_branch gcc_ufs_card_ice_core_clk = { | |
2745 | .halt_reg = 0x75058, | |
2746 | .halt_check = BRANCH_HALT, | |
2747 | .hwcg_reg = 0x75058, | |
2748 | .hwcg_bit = 1, | |
2749 | .clkr = { | |
2750 | .enable_reg = 0x75058, | |
2751 | .enable_mask = BIT(0), | |
2752 | .hw.init = &(struct clk_init_data){ | |
2753 | .name = "gcc_ufs_card_ice_core_clk", | |
ea434d7a DB |
2754 | .parent_hws = (const struct clk_hw*[]){ |
2755 | &gcc_ufs_card_ice_core_clk_src.clkr.hw, | |
06391edd TD |
2756 | }, |
2757 | .num_parents = 1, | |
2758 | .flags = CLK_SET_RATE_PARENT, | |
2759 | .ops = &clk_branch2_ops, | |
2760 | }, | |
2761 | }, | |
2762 | }; | |
2763 | ||
2764 | static struct clk_branch gcc_ufs_card_phy_aux_clk = { | |
2765 | .halt_reg = 0x7508c, | |
2766 | .halt_check = BRANCH_HALT, | |
2767 | .hwcg_reg = 0x7508c, | |
2768 | .hwcg_bit = 1, | |
2769 | .clkr = { | |
2770 | .enable_reg = 0x7508c, | |
2771 | .enable_mask = BIT(0), | |
2772 | .hw.init = &(struct clk_init_data){ | |
2773 | .name = "gcc_ufs_card_phy_aux_clk", | |
ea434d7a DB |
2774 | .parent_hws = (const struct clk_hw*[]){ |
2775 | &gcc_ufs_card_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
2776 | }, |
2777 | .num_parents = 1, | |
2778 | .flags = CLK_SET_RATE_PARENT, | |
2779 | .ops = &clk_branch2_ops, | |
2780 | }, | |
2781 | }, | |
2782 | }; | |
2783 | ||
2784 | static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { | |
2785 | .halt_check = BRANCH_HALT_SKIP, | |
2786 | .clkr = { | |
2787 | .enable_reg = 0x75018, | |
2788 | .enable_mask = BIT(0), | |
2789 | .hw.init = &(struct clk_init_data){ | |
2790 | .name = "gcc_ufs_card_rx_symbol_0_clk", | |
2791 | .ops = &clk_branch2_ops, | |
2792 | }, | |
2793 | }, | |
2794 | }; | |
2795 | ||
2796 | static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { | |
2797 | .halt_check = BRANCH_HALT_SKIP, | |
2798 | .clkr = { | |
2799 | .enable_reg = 0x750a8, | |
2800 | .enable_mask = BIT(0), | |
2801 | .hw.init = &(struct clk_init_data){ | |
2802 | .name = "gcc_ufs_card_rx_symbol_1_clk", | |
2803 | .ops = &clk_branch2_ops, | |
2804 | }, | |
2805 | }, | |
2806 | }; | |
2807 | ||
2808 | static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { | |
2809 | .halt_check = BRANCH_HALT_SKIP, | |
2810 | .clkr = { | |
2811 | .enable_reg = 0x75014, | |
2812 | .enable_mask = BIT(0), | |
2813 | .hw.init = &(struct clk_init_data){ | |
2814 | .name = "gcc_ufs_card_tx_symbol_0_clk", | |
2815 | .ops = &clk_branch2_ops, | |
2816 | }, | |
2817 | }, | |
2818 | }; | |
2819 | ||
2820 | static struct clk_branch gcc_ufs_card_unipro_core_clk = { | |
2821 | .halt_reg = 0x75054, | |
2822 | .halt_check = BRANCH_HALT, | |
2823 | .hwcg_reg = 0x75054, | |
2824 | .hwcg_bit = 1, | |
2825 | .clkr = { | |
2826 | .enable_reg = 0x75054, | |
2827 | .enable_mask = BIT(0), | |
2828 | .hw.init = &(struct clk_init_data){ | |
2829 | .name = "gcc_ufs_card_unipro_core_clk", | |
ea434d7a DB |
2830 | .parent_hws = (const struct clk_hw*[]){ |
2831 | &gcc_ufs_card_unipro_core_clk_src.clkr.hw, | |
06391edd TD |
2832 | }, |
2833 | .num_parents = 1, | |
2834 | .flags = CLK_SET_RATE_PARENT, | |
2835 | .ops = &clk_branch2_ops, | |
2836 | }, | |
2837 | }, | |
2838 | }; | |
2839 | ||
2840 | static struct clk_branch gcc_ufs_mem_clkref_clk = { | |
2841 | .halt_reg = 0x8c000, | |
2842 | .halt_check = BRANCH_HALT, | |
2843 | .clkr = { | |
2844 | .enable_reg = 0x8c000, | |
2845 | .enable_mask = BIT(0), | |
2846 | .hw.init = &(struct clk_init_data){ | |
2847 | .name = "gcc_ufs_mem_clkref_clk", | |
2848 | .ops = &clk_branch2_ops, | |
2849 | }, | |
2850 | }, | |
2851 | }; | |
2852 | ||
2853 | static struct clk_branch gcc_ufs_phy_ahb_clk = { | |
2854 | .halt_reg = 0x77010, | |
2855 | .halt_check = BRANCH_HALT, | |
2856 | .hwcg_reg = 0x77010, | |
2857 | .hwcg_bit = 1, | |
2858 | .clkr = { | |
2859 | .enable_reg = 0x77010, | |
2860 | .enable_mask = BIT(0), | |
2861 | .hw.init = &(struct clk_init_data){ | |
2862 | .name = "gcc_ufs_phy_ahb_clk", | |
2863 | .ops = &clk_branch2_ops, | |
2864 | }, | |
2865 | }, | |
2866 | }; | |
2867 | ||
2868 | static struct clk_branch gcc_ufs_phy_axi_clk = { | |
2869 | .halt_reg = 0x7700c, | |
2870 | .halt_check = BRANCH_HALT, | |
2871 | .hwcg_reg = 0x7700c, | |
2872 | .hwcg_bit = 1, | |
2873 | .clkr = { | |
2874 | .enable_reg = 0x7700c, | |
2875 | .enable_mask = BIT(0), | |
2876 | .hw.init = &(struct clk_init_data){ | |
2877 | .name = "gcc_ufs_phy_axi_clk", | |
ea434d7a DB |
2878 | .parent_hws = (const struct clk_hw*[]){ |
2879 | &gcc_ufs_phy_axi_clk_src.clkr.hw, | |
06391edd TD |
2880 | }, |
2881 | .num_parents = 1, | |
2882 | .flags = CLK_SET_RATE_PARENT, | |
2883 | .ops = &clk_branch2_ops, | |
2884 | }, | |
2885 | }, | |
2886 | }; | |
2887 | ||
2888 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { | |
2889 | .halt_reg = 0x77058, | |
2890 | .halt_check = BRANCH_HALT, | |
2891 | .hwcg_reg = 0x77058, | |
2892 | .hwcg_bit = 1, | |
2893 | .clkr = { | |
2894 | .enable_reg = 0x77058, | |
2895 | .enable_mask = BIT(0), | |
2896 | .hw.init = &(struct clk_init_data){ | |
2897 | .name = "gcc_ufs_phy_ice_core_clk", | |
ea434d7a DB |
2898 | .parent_hws = (const struct clk_hw*[]){ |
2899 | &gcc_ufs_phy_ice_core_clk_src.clkr.hw, | |
06391edd TD |
2900 | }, |
2901 | .num_parents = 1, | |
2902 | .flags = CLK_SET_RATE_PARENT, | |
2903 | .ops = &clk_branch2_ops, | |
2904 | }, | |
2905 | }, | |
2906 | }; | |
2907 | ||
2908 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { | |
2909 | .halt_reg = 0x7708c, | |
2910 | .halt_check = BRANCH_HALT, | |
2911 | .hwcg_reg = 0x7708c, | |
2912 | .hwcg_bit = 1, | |
2913 | .clkr = { | |
2914 | .enable_reg = 0x7708c, | |
2915 | .enable_mask = BIT(0), | |
2916 | .hw.init = &(struct clk_init_data){ | |
2917 | .name = "gcc_ufs_phy_phy_aux_clk", | |
ea434d7a DB |
2918 | .parent_hws = (const struct clk_hw*[]){ |
2919 | &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
2920 | }, |
2921 | .num_parents = 1, | |
2922 | .flags = CLK_SET_RATE_PARENT, | |
2923 | .ops = &clk_branch2_ops, | |
2924 | }, | |
2925 | }, | |
2926 | }; | |
2927 | ||
2928 | static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { | |
2929 | .halt_check = BRANCH_HALT_SKIP, | |
2930 | .clkr = { | |
2931 | .enable_reg = 0x77018, | |
2932 | .enable_mask = BIT(0), | |
2933 | .hw.init = &(struct clk_init_data){ | |
2934 | .name = "gcc_ufs_phy_rx_symbol_0_clk", | |
2935 | .ops = &clk_branch2_ops, | |
2936 | }, | |
2937 | }, | |
2938 | }; | |
2939 | ||
2940 | static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { | |
2941 | .halt_check = BRANCH_HALT_SKIP, | |
2942 | .clkr = { | |
2943 | .enable_reg = 0x770a8, | |
2944 | .enable_mask = BIT(0), | |
2945 | .hw.init = &(struct clk_init_data){ | |
2946 | .name = "gcc_ufs_phy_rx_symbol_1_clk", | |
2947 | .ops = &clk_branch2_ops, | |
2948 | }, | |
2949 | }, | |
2950 | }; | |
2951 | ||
2952 | static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { | |
2953 | .halt_check = BRANCH_HALT_SKIP, | |
2954 | .clkr = { | |
2955 | .enable_reg = 0x77014, | |
2956 | .enable_mask = BIT(0), | |
2957 | .hw.init = &(struct clk_init_data){ | |
2958 | .name = "gcc_ufs_phy_tx_symbol_0_clk", | |
2959 | .ops = &clk_branch2_ops, | |
2960 | }, | |
2961 | }, | |
2962 | }; | |
2963 | ||
2964 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { | |
2965 | .halt_reg = 0x77054, | |
2966 | .halt_check = BRANCH_HALT, | |
2967 | .hwcg_reg = 0x77054, | |
2968 | .hwcg_bit = 1, | |
2969 | .clkr = { | |
2970 | .enable_reg = 0x77054, | |
2971 | .enable_mask = BIT(0), | |
2972 | .hw.init = &(struct clk_init_data){ | |
2973 | .name = "gcc_ufs_phy_unipro_core_clk", | |
ea434d7a DB |
2974 | .parent_hws = (const struct clk_hw*[]){ |
2975 | &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, | |
06391edd TD |
2976 | }, |
2977 | .num_parents = 1, | |
2978 | .flags = CLK_SET_RATE_PARENT, | |
2979 | .ops = &clk_branch2_ops, | |
2980 | }, | |
2981 | }, | |
2982 | }; | |
2983 | ||
2984 | static struct clk_branch gcc_usb30_prim_master_clk = { | |
2985 | .halt_reg = 0xf00c, | |
2986 | .halt_check = BRANCH_HALT, | |
2987 | .clkr = { | |
2988 | .enable_reg = 0xf00c, | |
2989 | .enable_mask = BIT(0), | |
2990 | .hw.init = &(struct clk_init_data){ | |
2991 | .name = "gcc_usb30_prim_master_clk", | |
ea434d7a DB |
2992 | .parent_hws = (const struct clk_hw*[]){ |
2993 | &gcc_usb30_prim_master_clk_src.clkr.hw, | |
06391edd TD |
2994 | }, |
2995 | .num_parents = 1, | |
2996 | .flags = CLK_SET_RATE_PARENT, | |
2997 | .ops = &clk_branch2_ops, | |
2998 | }, | |
2999 | }, | |
3000 | }; | |
3001 | ||
3002 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { | |
3003 | .halt_reg = 0xf014, | |
3004 | .halt_check = BRANCH_HALT, | |
3005 | .clkr = { | |
3006 | .enable_reg = 0xf014, | |
3007 | .enable_mask = BIT(0), | |
3008 | .hw.init = &(struct clk_init_data){ | |
3009 | .name = "gcc_usb30_prim_mock_utmi_clk", | |
ea434d7a DB |
3010 | .parent_hws = (const struct clk_hw*[]){ |
3011 | &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, | |
06391edd TD |
3012 | }, |
3013 | .num_parents = 1, | |
3014 | .flags = CLK_SET_RATE_PARENT, | |
3015 | .ops = &clk_branch2_ops, | |
3016 | }, | |
3017 | }, | |
3018 | }; | |
3019 | ||
3020 | static struct clk_branch gcc_usb30_prim_sleep_clk = { | |
3021 | .halt_reg = 0xf010, | |
3022 | .halt_check = BRANCH_HALT, | |
3023 | .clkr = { | |
3024 | .enable_reg = 0xf010, | |
3025 | .enable_mask = BIT(0), | |
3026 | .hw.init = &(struct clk_init_data){ | |
3027 | .name = "gcc_usb30_prim_sleep_clk", | |
3028 | .ops = &clk_branch2_ops, | |
3029 | }, | |
3030 | }, | |
3031 | }; | |
3032 | ||
3033 | static struct clk_branch gcc_usb30_sec_master_clk = { | |
3034 | .halt_reg = 0x1000c, | |
3035 | .halt_check = BRANCH_HALT, | |
3036 | .clkr = { | |
3037 | .enable_reg = 0x1000c, | |
3038 | .enable_mask = BIT(0), | |
3039 | .hw.init = &(struct clk_init_data){ | |
3040 | .name = "gcc_usb30_sec_master_clk", | |
ea434d7a DB |
3041 | .parent_hws = (const struct clk_hw*[]){ |
3042 | &gcc_usb30_sec_master_clk_src.clkr.hw, | |
06391edd TD |
3043 | }, |
3044 | .num_parents = 1, | |
3045 | .flags = CLK_SET_RATE_PARENT, | |
3046 | .ops = &clk_branch2_ops, | |
3047 | }, | |
3048 | }, | |
3049 | }; | |
3050 | ||
3051 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { | |
3052 | .halt_reg = 0x10014, | |
3053 | .halt_check = BRANCH_HALT, | |
3054 | .clkr = { | |
3055 | .enable_reg = 0x10014, | |
3056 | .enable_mask = BIT(0), | |
3057 | .hw.init = &(struct clk_init_data){ | |
3058 | .name = "gcc_usb30_sec_mock_utmi_clk", | |
ea434d7a DB |
3059 | .parent_hws = (const struct clk_hw*[]){ |
3060 | &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, | |
06391edd TD |
3061 | }, |
3062 | .num_parents = 1, | |
3063 | .flags = CLK_SET_RATE_PARENT, | |
3064 | .ops = &clk_branch2_ops, | |
3065 | }, | |
3066 | }, | |
3067 | }; | |
3068 | ||
3069 | static struct clk_branch gcc_usb30_sec_sleep_clk = { | |
3070 | .halt_reg = 0x10010, | |
3071 | .halt_check = BRANCH_HALT, | |
3072 | .clkr = { | |
3073 | .enable_reg = 0x10010, | |
3074 | .enable_mask = BIT(0), | |
3075 | .hw.init = &(struct clk_init_data){ | |
3076 | .name = "gcc_usb30_sec_sleep_clk", | |
3077 | .ops = &clk_branch2_ops, | |
3078 | }, | |
3079 | }, | |
3080 | }; | |
3081 | ||
3082 | static struct clk_branch gcc_usb3_prim_clkref_clk = { | |
3083 | .halt_reg = 0x8c008, | |
3084 | .halt_check = BRANCH_HALT, | |
3085 | .clkr = { | |
3086 | .enable_reg = 0x8c008, | |
3087 | .enable_mask = BIT(0), | |
3088 | .hw.init = &(struct clk_init_data){ | |
3089 | .name = "gcc_usb3_prim_clkref_clk", | |
3090 | .ops = &clk_branch2_ops, | |
3091 | }, | |
3092 | }, | |
3093 | }; | |
3094 | ||
3095 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { | |
3096 | .halt_reg = 0xf04c, | |
3097 | .halt_check = BRANCH_HALT, | |
3098 | .clkr = { | |
3099 | .enable_reg = 0xf04c, | |
3100 | .enable_mask = BIT(0), | |
3101 | .hw.init = &(struct clk_init_data){ | |
3102 | .name = "gcc_usb3_prim_phy_aux_clk", | |
ea434d7a DB |
3103 | .parent_hws = (const struct clk_hw*[]){ |
3104 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
3105 | }, |
3106 | .num_parents = 1, | |
3107 | .flags = CLK_SET_RATE_PARENT, | |
3108 | .ops = &clk_branch2_ops, | |
3109 | }, | |
3110 | }, | |
3111 | }; | |
3112 | ||
3113 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { | |
3114 | .halt_reg = 0xf050, | |
3115 | .halt_check = BRANCH_HALT, | |
3116 | .clkr = { | |
3117 | .enable_reg = 0xf050, | |
3118 | .enable_mask = BIT(0), | |
3119 | .hw.init = &(struct clk_init_data){ | |
3120 | .name = "gcc_usb3_prim_phy_com_aux_clk", | |
ea434d7a DB |
3121 | .parent_hws = (const struct clk_hw*[]){ |
3122 | &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
3123 | }, |
3124 | .num_parents = 1, | |
3125 | .flags = CLK_SET_RATE_PARENT, | |
3126 | .ops = &clk_branch2_ops, | |
3127 | }, | |
3128 | }, | |
3129 | }; | |
3130 | ||
3131 | static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { | |
3132 | .halt_check = BRANCH_HALT_SKIP, | |
3133 | .clkr = { | |
3134 | .enable_reg = 0xf054, | |
3135 | .enable_mask = BIT(0), | |
3136 | .hw.init = &(struct clk_init_data){ | |
3137 | .name = "gcc_usb3_prim_phy_pipe_clk", | |
3138 | .ops = &clk_branch2_ops, | |
3139 | }, | |
3140 | }, | |
3141 | }; | |
3142 | ||
3143 | static struct clk_branch gcc_usb3_sec_clkref_clk = { | |
3144 | .halt_reg = 0x8c028, | |
3145 | .halt_check = BRANCH_HALT, | |
3146 | .clkr = { | |
3147 | .enable_reg = 0x8c028, | |
3148 | .enable_mask = BIT(0), | |
3149 | .hw.init = &(struct clk_init_data){ | |
3150 | .name = "gcc_usb3_sec_clkref_clk", | |
3151 | .ops = &clk_branch2_ops, | |
3152 | }, | |
3153 | }, | |
3154 | }; | |
3155 | ||
3156 | static struct clk_branch gcc_usb3_sec_phy_aux_clk = { | |
3157 | .halt_reg = 0x1004c, | |
3158 | .halt_check = BRANCH_HALT, | |
3159 | .clkr = { | |
3160 | .enable_reg = 0x1004c, | |
3161 | .enable_mask = BIT(0), | |
3162 | .hw.init = &(struct clk_init_data){ | |
3163 | .name = "gcc_usb3_sec_phy_aux_clk", | |
ea434d7a DB |
3164 | .parent_hws = (const struct clk_hw*[]){ |
3165 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
3166 | }, |
3167 | .num_parents = 1, | |
3168 | .flags = CLK_SET_RATE_PARENT, | |
3169 | .ops = &clk_branch2_ops, | |
3170 | }, | |
3171 | }, | |
3172 | }; | |
3173 | ||
3174 | static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { | |
3175 | .halt_reg = 0x10050, | |
3176 | .halt_check = BRANCH_HALT, | |
3177 | .clkr = { | |
3178 | .enable_reg = 0x10050, | |
3179 | .enable_mask = BIT(0), | |
3180 | .hw.init = &(struct clk_init_data){ | |
3181 | .name = "gcc_usb3_sec_phy_com_aux_clk", | |
ea434d7a DB |
3182 | .parent_hws = (const struct clk_hw*[]){ |
3183 | &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, | |
06391edd TD |
3184 | }, |
3185 | .num_parents = 1, | |
3186 | .flags = CLK_SET_RATE_PARENT, | |
3187 | .ops = &clk_branch2_ops, | |
3188 | }, | |
3189 | }, | |
3190 | }; | |
3191 | ||
3192 | static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { | |
3193 | .halt_check = BRANCH_HALT_SKIP, | |
3194 | .clkr = { | |
3195 | .enable_reg = 0x10054, | |
3196 | .enable_mask = BIT(0), | |
3197 | .hw.init = &(struct clk_init_data){ | |
3198 | .name = "gcc_usb3_sec_phy_pipe_clk", | |
3199 | .ops = &clk_branch2_ops, | |
3200 | }, | |
3201 | }, | |
3202 | }; | |
3203 | ||
3204 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { | |
3205 | .halt_reg = 0x6a004, | |
3206 | .halt_check = BRANCH_HALT, | |
3207 | .hwcg_reg = 0x6a004, | |
3208 | .hwcg_bit = 1, | |
3209 | .clkr = { | |
3210 | .enable_reg = 0x6a004, | |
3211 | .enable_mask = BIT(0), | |
3212 | .hw.init = &(struct clk_init_data){ | |
3213 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", | |
3214 | .ops = &clk_branch2_ops, | |
3215 | }, | |
3216 | }, | |
3217 | }; | |
3218 | ||
3219 | static struct clk_branch gcc_vdda_vs_clk = { | |
3220 | .halt_reg = 0x7a00c, | |
3221 | .halt_check = BRANCH_HALT, | |
3222 | .clkr = { | |
3223 | .enable_reg = 0x7a00c, | |
3224 | .enable_mask = BIT(0), | |
3225 | .hw.init = &(struct clk_init_data){ | |
3226 | .name = "gcc_vdda_vs_clk", | |
ea434d7a DB |
3227 | .parent_hws = (const struct clk_hw*[]){ |
3228 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
3229 | }, |
3230 | .num_parents = 1, | |
3231 | .flags = CLK_SET_RATE_PARENT, | |
3232 | .ops = &clk_branch2_ops, | |
3233 | }, | |
3234 | }, | |
3235 | }; | |
3236 | ||
3237 | static struct clk_branch gcc_vddcx_vs_clk = { | |
3238 | .halt_reg = 0x7a004, | |
3239 | .halt_check = BRANCH_HALT, | |
3240 | .clkr = { | |
3241 | .enable_reg = 0x7a004, | |
3242 | .enable_mask = BIT(0), | |
3243 | .hw.init = &(struct clk_init_data){ | |
3244 | .name = "gcc_vddcx_vs_clk", | |
ea434d7a DB |
3245 | .parent_hws = (const struct clk_hw*[]){ |
3246 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
3247 | }, |
3248 | .num_parents = 1, | |
3249 | .flags = CLK_SET_RATE_PARENT, | |
3250 | .ops = &clk_branch2_ops, | |
3251 | }, | |
3252 | }, | |
3253 | }; | |
3254 | ||
3255 | static struct clk_branch gcc_vddmx_vs_clk = { | |
3256 | .halt_reg = 0x7a008, | |
3257 | .halt_check = BRANCH_HALT, | |
3258 | .clkr = { | |
3259 | .enable_reg = 0x7a008, | |
3260 | .enable_mask = BIT(0), | |
3261 | .hw.init = &(struct clk_init_data){ | |
3262 | .name = "gcc_vddmx_vs_clk", | |
ea434d7a DB |
3263 | .parent_hws = (const struct clk_hw*[]){ |
3264 | &gcc_vsensor_clk_src.clkr.hw, | |
06391edd TD |
3265 | }, |
3266 | .num_parents = 1, | |
3267 | .flags = CLK_SET_RATE_PARENT, | |
3268 | .ops = &clk_branch2_ops, | |
3269 | }, | |
3270 | }, | |
3271 | }; | |
3272 | ||
3273 | static struct clk_branch gcc_video_ahb_clk = { | |
3274 | .halt_reg = 0xb004, | |
3275 | .halt_check = BRANCH_HALT, | |
3276 | .hwcg_reg = 0xb004, | |
3277 | .hwcg_bit = 1, | |
3278 | .clkr = { | |
3279 | .enable_reg = 0xb004, | |
3280 | .enable_mask = BIT(0), | |
3281 | .hw.init = &(struct clk_init_data){ | |
3282 | .name = "gcc_video_ahb_clk", | |
cfb8282e | 3283 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
3284 | .ops = &clk_branch2_ops, |
3285 | }, | |
3286 | }, | |
3287 | }; | |
3288 | ||
3289 | static struct clk_branch gcc_video_axi_clk = { | |
3290 | .halt_reg = 0xb01c, | |
3291 | .halt_check = BRANCH_VOTED, | |
3292 | .clkr = { | |
3293 | .enable_reg = 0xb01c, | |
3294 | .enable_mask = BIT(0), | |
3295 | .hw.init = &(struct clk_init_data){ | |
3296 | .name = "gcc_video_axi_clk", | |
3297 | .ops = &clk_branch2_ops, | |
3298 | }, | |
3299 | }, | |
3300 | }; | |
3301 | ||
3302 | static struct clk_branch gcc_video_xo_clk = { | |
3303 | .halt_reg = 0xb028, | |
3304 | .halt_check = BRANCH_HALT, | |
3305 | .clkr = { | |
3306 | .enable_reg = 0xb028, | |
3307 | .enable_mask = BIT(0), | |
3308 | .hw.init = &(struct clk_init_data){ | |
3309 | .name = "gcc_video_xo_clk", | |
cfb8282e | 3310 | .flags = CLK_IS_CRITICAL, |
06391edd TD |
3311 | .ops = &clk_branch2_ops, |
3312 | }, | |
3313 | }, | |
3314 | }; | |
3315 | ||
3316 | static struct clk_branch gcc_vs_ctrl_ahb_clk = { | |
3317 | .halt_reg = 0x7a014, | |
3318 | .halt_check = BRANCH_HALT, | |
3319 | .hwcg_reg = 0x7a014, | |
3320 | .hwcg_bit = 1, | |
3321 | .clkr = { | |
3322 | .enable_reg = 0x7a014, | |
3323 | .enable_mask = BIT(0), | |
3324 | .hw.init = &(struct clk_init_data){ | |
3325 | .name = "gcc_vs_ctrl_ahb_clk", | |
3326 | .ops = &clk_branch2_ops, | |
3327 | }, | |
3328 | }, | |
3329 | }; | |
3330 | ||
3331 | static struct clk_branch gcc_vs_ctrl_clk = { | |
3332 | .halt_reg = 0x7a010, | |
3333 | .halt_check = BRANCH_HALT, | |
3334 | .clkr = { | |
3335 | .enable_reg = 0x7a010, | |
3336 | .enable_mask = BIT(0), | |
3337 | .hw.init = &(struct clk_init_data){ | |
3338 | .name = "gcc_vs_ctrl_clk", | |
ea434d7a DB |
3339 | .parent_hws = (const struct clk_hw*[]){ |
3340 | &gcc_vs_ctrl_clk_src.clkr.hw, | |
06391edd TD |
3341 | }, |
3342 | .num_parents = 1, | |
3343 | .flags = CLK_SET_RATE_PARENT, | |
3344 | .ops = &clk_branch2_ops, | |
3345 | }, | |
3346 | }, | |
3347 | }; | |
3348 | ||
cfb8282e AN |
3349 | static struct clk_branch gcc_cpuss_dvm_bus_clk = { |
3350 | .halt_reg = 0x48190, | |
3351 | .halt_check = BRANCH_HALT, | |
3352 | .clkr = { | |
3353 | .enable_reg = 0x48190, | |
3354 | .enable_mask = BIT(0), | |
3355 | .hw.init = &(struct clk_init_data){ | |
3356 | .name = "gcc_cpuss_dvm_bus_clk", | |
3357 | .flags = CLK_IS_CRITICAL, | |
3358 | .ops = &clk_branch2_ops, | |
3359 | }, | |
3360 | }, | |
3361 | }; | |
3362 | ||
3363 | static struct clk_branch gcc_cpuss_gnoc_clk = { | |
3364 | .halt_reg = 0x48004, | |
3365 | .halt_check = BRANCH_HALT_VOTED, | |
3366 | .hwcg_reg = 0x48004, | |
3367 | .hwcg_bit = 1, | |
3368 | .clkr = { | |
3369 | .enable_reg = 0x52004, | |
3370 | .enable_mask = BIT(22), | |
3371 | .hw.init = &(struct clk_init_data){ | |
3372 | .name = "gcc_cpuss_gnoc_clk", | |
3373 | .flags = CLK_IS_CRITICAL, | |
3374 | .ops = &clk_branch2_ops, | |
3375 | }, | |
3376 | }, | |
3377 | }; | |
3378 | ||
8d3e5b9c TD |
3379 | /* TODO: Remove after DTS updated to protect these */ |
3380 | #ifdef CONFIG_SDM_LPASSCC_845 | |
3381 | static struct clk_branch gcc_lpass_q6_axi_clk = { | |
3382 | .halt_reg = 0x47000, | |
3383 | .halt_check = BRANCH_HALT, | |
3384 | .clkr = { | |
3385 | .enable_reg = 0x47000, | |
3386 | .enable_mask = BIT(0), | |
3387 | .hw.init = &(struct clk_init_data){ | |
3388 | .name = "gcc_lpass_q6_axi_clk", | |
3389 | .flags = CLK_IS_CRITICAL, | |
3390 | .ops = &clk_branch2_ops, | |
3391 | }, | |
3392 | }, | |
3393 | }; | |
3394 | ||
3395 | static struct clk_branch gcc_lpass_sway_clk = { | |
3396 | .halt_reg = 0x47008, | |
3397 | .halt_check = BRANCH_HALT, | |
3398 | .clkr = { | |
3399 | .enable_reg = 0x47008, | |
3400 | .enable_mask = BIT(0), | |
3401 | .hw.init = &(struct clk_init_data){ | |
3402 | .name = "gcc_lpass_sway_clk", | |
3403 | .flags = CLK_IS_CRITICAL, | |
3404 | .ops = &clk_branch2_ops, | |
3405 | }, | |
3406 | }, | |
3407 | }; | |
3408 | #endif | |
3409 | ||
06391edd TD |
3410 | static struct gdsc pcie_0_gdsc = { |
3411 | .gdscr = 0x6b004, | |
3412 | .pd = { | |
3413 | .name = "pcie_0_gdsc", | |
3414 | }, | |
3415 | .pwrsts = PWRSTS_OFF_ON, | |
3416 | .flags = POLL_CFG_GDSCR, | |
3417 | }; | |
3418 | ||
3419 | static struct gdsc pcie_1_gdsc = { | |
3420 | .gdscr = 0x8d004, | |
3421 | .pd = { | |
3422 | .name = "pcie_1_gdsc", | |
3423 | }, | |
3424 | .pwrsts = PWRSTS_OFF_ON, | |
3425 | .flags = POLL_CFG_GDSCR, | |
3426 | }; | |
3427 | ||
3428 | static struct gdsc ufs_card_gdsc = { | |
3429 | .gdscr = 0x75004, | |
3430 | .pd = { | |
3431 | .name = "ufs_card_gdsc", | |
3432 | }, | |
3433 | .pwrsts = PWRSTS_OFF_ON, | |
3434 | .flags = POLL_CFG_GDSCR, | |
3435 | }; | |
3436 | ||
3437 | static struct gdsc ufs_phy_gdsc = { | |
3438 | .gdscr = 0x77004, | |
3439 | .pd = { | |
3440 | .name = "ufs_phy_gdsc", | |
3441 | }, | |
3442 | .pwrsts = PWRSTS_OFF_ON, | |
3443 | .flags = POLL_CFG_GDSCR, | |
3444 | }; | |
3445 | ||
3446 | static struct gdsc usb30_prim_gdsc = { | |
3447 | .gdscr = 0xf004, | |
3448 | .pd = { | |
3449 | .name = "usb30_prim_gdsc", | |
3450 | }, | |
3451 | .pwrsts = PWRSTS_OFF_ON, | |
3452 | .flags = POLL_CFG_GDSCR, | |
3453 | }; | |
3454 | ||
3455 | static struct gdsc usb30_sec_gdsc = { | |
3456 | .gdscr = 0x10004, | |
3457 | .pd = { | |
3458 | .name = "usb30_sec_gdsc", | |
3459 | }, | |
3460 | .pwrsts = PWRSTS_OFF_ON, | |
3461 | .flags = POLL_CFG_GDSCR, | |
3462 | }; | |
3463 | ||
3464 | static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { | |
3465 | .gdscr = 0x7d030, | |
3466 | .pd = { | |
3467 | .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", | |
3468 | }, | |
3469 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3470 | .flags = VOTABLE, |
06391edd TD |
3471 | }; |
3472 | ||
3473 | static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { | |
3474 | .gdscr = 0x7d03c, | |
3475 | .pd = { | |
3476 | .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", | |
3477 | }, | |
3478 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3479 | .flags = VOTABLE, |
06391edd TD |
3480 | }; |
3481 | ||
3482 | static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { | |
3483 | .gdscr = 0x7d034, | |
3484 | .pd = { | |
3485 | .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", | |
3486 | }, | |
3487 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3488 | .flags = VOTABLE, |
06391edd TD |
3489 | }; |
3490 | ||
3491 | static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { | |
3492 | .gdscr = 0x7d038, | |
3493 | .pd = { | |
3494 | .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", | |
3495 | }, | |
3496 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3497 | .flags = VOTABLE, |
06391edd TD |
3498 | }; |
3499 | ||
3500 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { | |
3501 | .gdscr = 0x7d040, | |
3502 | .pd = { | |
3503 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", | |
3504 | }, | |
3505 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3506 | .flags = VOTABLE, |
06391edd TD |
3507 | }; |
3508 | ||
3509 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { | |
3510 | .gdscr = 0x7d048, | |
3511 | .pd = { | |
3512 | .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", | |
3513 | }, | |
3514 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3515 | .flags = VOTABLE, |
06391edd TD |
3516 | }; |
3517 | ||
3518 | static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { | |
3519 | .gdscr = 0x7d044, | |
3520 | .pd = { | |
3521 | .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", | |
3522 | }, | |
3523 | .pwrsts = PWRSTS_OFF_ON, | |
5e82548e | 3524 | .flags = VOTABLE, |
06391edd TD |
3525 | }; |
3526 | ||
ae66b1fe RA |
3527 | static struct clk_regmap *gcc_sdm670_clocks[] = { |
3528 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, | |
3529 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, | |
3530 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, | |
3531 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3532 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, | |
3533 | [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, | |
3534 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, | |
3535 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
3536 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
3537 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
3538 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
3539 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, | |
3540 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, | |
3541 | [GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr, | |
3542 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr, | |
3543 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, | |
3544 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, | |
3545 | [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, | |
3546 | [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, | |
3547 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, | |
3548 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, | |
3549 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3550 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
3551 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3552 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
3553 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3554 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
3555 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, | |
3556 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, | |
3557 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, | |
3558 | [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, | |
3559 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
3560 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
3561 | [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, | |
3562 | [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, | |
3563 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, | |
3564 | [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, | |
3565 | [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, | |
3566 | [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, | |
3567 | [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, | |
3568 | [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, | |
3569 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3570 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
3571 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3572 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
3573 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
3574 | [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, | |
3575 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, | |
3576 | [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, | |
3577 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
3578 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
3579 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
3580 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
3581 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
3582 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
3583 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
3584 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
3585 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
3586 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
3587 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
3588 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
3589 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, | |
3590 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, | |
3591 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, | |
3592 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, | |
3593 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
3594 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
3595 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
3596 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
3597 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
3598 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
3599 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
3600 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
3601 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
3602 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
3603 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
3604 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
3605 | [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, | |
3606 | [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, | |
3607 | [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, | |
3608 | [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, | |
3609 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
3610 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
3611 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
3612 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
3613 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, | |
3614 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
3615 | [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, | |
3616 | [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, | |
3617 | [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, | |
3618 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3619 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3620 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
3621 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3622 | [GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr, | |
3623 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr, | |
3624 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, | |
3625 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
3626 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = | |
3627 | &gcc_tsif_inactivity_timers_clk.clkr, | |
3628 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
3629 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, | |
3630 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, | |
3631 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
3632 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
3633 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
3634 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
3635 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
3636 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
3637 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
3638 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, | |
3639 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, | |
3640 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
3641 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = | |
3642 | &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
3643 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
3644 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
3645 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
3646 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = | |
3647 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
3648 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
3649 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, | |
3650 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, | |
3651 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
3652 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
3653 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, | |
3654 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, | |
3655 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, | |
3656 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, | |
3657 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, | |
3658 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, | |
3659 | [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, | |
3660 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, | |
3661 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, | |
3662 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, | |
3663 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, | |
3664 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, | |
3665 | [GPLL0] = &gpll0.clkr, | |
3666 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, | |
3667 | [GPLL4] = &gpll4.clkr, | |
3668 | [GPLL6] = &gpll6.clkr, | |
3669 | [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, | |
3670 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, | |
3671 | [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, | |
3672 | [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, | |
3673 | [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, | |
3674 | }; | |
3675 | ||
06391edd TD |
3676 | static struct clk_regmap *gcc_sdm845_clocks[] = { |
3677 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, | |
3678 | [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, | |
3679 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, | |
3680 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, | |
3681 | [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, | |
3682 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, | |
3683 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3684 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, | |
3685 | [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, | |
3686 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, | |
3687 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
3688 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
3689 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
3690 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, | |
3691 | [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, | |
3692 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, | |
3693 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, | |
3694 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, | |
3695 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, | |
3696 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, | |
3697 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, | |
3698 | [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, | |
3699 | [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, | |
3700 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, | |
3701 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, | |
3702 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3703 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, | |
3704 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3705 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, | |
3706 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3707 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, | |
3708 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, | |
3709 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, | |
3710 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, | |
3711 | [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, | |
3712 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, | |
3713 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, | |
3714 | [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, | |
3715 | [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, | |
3716 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, | |
3717 | [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, | |
3718 | [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, | |
3719 | [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, | |
3720 | [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, | |
3721 | [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, | |
3722 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, | |
3723 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, | |
3724 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
3725 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, | |
3726 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
3727 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
3728 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
3729 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, | |
3730 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, | |
3731 | [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, | |
3732 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, | |
3733 | [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, | |
3734 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, | |
3735 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, | |
3736 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, | |
3737 | [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, | |
3738 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, | |
3739 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, | |
3740 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, | |
3741 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3742 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, | |
3743 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3744 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, | |
3745 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
3746 | [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, | |
3747 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, | |
3748 | [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, | |
3749 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, | |
3750 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, | |
3751 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, | |
3752 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, | |
3753 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, | |
3754 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, | |
3755 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, | |
3756 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, | |
3757 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, | |
3758 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, | |
3759 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, | |
3760 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, | |
3761 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, | |
3762 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, | |
3763 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, | |
3764 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, | |
3765 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, | |
3766 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, | |
3767 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, | |
3768 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, | |
3769 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, | |
3770 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, | |
3771 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, | |
3772 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, | |
3773 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, | |
3774 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, | |
3775 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, | |
3776 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, | |
3777 | [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, | |
3778 | [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, | |
3779 | [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, | |
3780 | [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, | |
3781 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, | |
3782 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, | |
3783 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, | |
3784 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, | |
3785 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3786 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3787 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, | |
3788 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3789 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
3790 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, | |
3791 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, | |
3792 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
3793 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = | |
3794 | &gcc_tsif_inactivity_timers_clk.clkr, | |
3795 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
3796 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, | |
3797 | [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, | |
3798 | [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, | |
3799 | [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, | |
3800 | [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, | |
3801 | [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, | |
3802 | [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, | |
3803 | [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, | |
3804 | [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, | |
3805 | [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, | |
3806 | [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, | |
3807 | [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, | |
3808 | [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, | |
3809 | [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = | |
3810 | &gcc_ufs_card_unipro_core_clk_src.clkr, | |
3811 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, | |
3812 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, | |
3813 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, | |
3814 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, | |
3815 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, | |
3816 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, | |
3817 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, | |
3818 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, | |
3819 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, | |
3820 | [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, | |
3821 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, | |
3822 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, | |
3823 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = | |
3824 | &gcc_ufs_phy_unipro_core_clk_src.clkr, | |
3825 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, | |
3826 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, | |
3827 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, | |
3828 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = | |
3829 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, | |
3830 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, | |
3831 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, | |
3832 | [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, | |
3833 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, | |
3834 | [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = | |
3835 | &gcc_usb30_sec_mock_utmi_clk_src.clkr, | |
3836 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, | |
3837 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, | |
3838 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, | |
3839 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, | |
3840 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, | |
3841 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, | |
3842 | [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, | |
3843 | [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, | |
3844 | [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, | |
3845 | [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, | |
3846 | [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, | |
3847 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, | |
3848 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, | |
3849 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, | |
3850 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, | |
3851 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, | |
3852 | [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, | |
3853 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, | |
3854 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, | |
3855 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, | |
3856 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, | |
3857 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, | |
3858 | [GPLL0] = &gpll0.clkr, | |
3859 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, | |
3860 | [GPLL4] = &gpll4.clkr, | |
cfb8282e AN |
3861 | [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, |
3862 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, | |
4f83d9b8 DA |
3863 | [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, |
3864 | [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, | |
3865 | [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, | |
8d3e5b9c TD |
3866 | #ifdef CONFIG_SDM_LPASSCC_845 |
3867 | [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, | |
3868 | [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, | |
3869 | #endif | |
06391edd TD |
3870 | }; |
3871 | ||
3872 | static const struct qcom_reset_map gcc_sdm845_resets[] = { | |
3873 | [GCC_MMSS_BCR] = { 0xb000 }, | |
3874 | [GCC_PCIE_0_BCR] = { 0x6b000 }, | |
3875 | [GCC_PCIE_1_BCR] = { 0x8d000 }, | |
3876 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, | |
3877 | [GCC_PDM_BCR] = { 0x33000 }, | |
3878 | [GCC_PRNG_BCR] = { 0x34000 }, | |
3879 | [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, | |
3880 | [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, | |
3881 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, | |
3882 | [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, | |
3883 | [GCC_SDCC2_BCR] = { 0x14000 }, | |
3884 | [GCC_SDCC4_BCR] = { 0x16000 }, | |
3885 | [GCC_TSIF_BCR] = { 0x36000 }, | |
3886 | [GCC_UFS_CARD_BCR] = { 0x75000 }, | |
3887 | [GCC_UFS_PHY_BCR] = { 0x77000 }, | |
3888 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, | |
3889 | [GCC_USB30_SEC_BCR] = { 0x10000 }, | |
3890 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, | |
3891 | [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, | |
3892 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, | |
3893 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, | |
3894 | [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, | |
3895 | [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, | |
3896 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, | |
3897 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, | |
3898 | [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, | |
3899 | }; | |
3900 | ||
ae66b1fe RA |
3901 | static struct gdsc *gcc_sdm670_gdscs[] = { |
3902 | [UFS_PHY_GDSC] = &ufs_phy_gdsc, | |
3903 | [USB30_PRIM_GDSC] = &usb30_prim_gdsc, | |
3904 | [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = | |
3905 | &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, | |
3906 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = | |
3907 | &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, | |
3908 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = | |
3909 | &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, | |
3910 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = | |
3911 | &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, | |
3912 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = | |
3913 | &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, | |
3914 | [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, | |
3915 | }; | |
3916 | ||
06391edd TD |
3917 | static struct gdsc *gcc_sdm845_gdscs[] = { |
3918 | [PCIE_0_GDSC] = &pcie_0_gdsc, | |
3919 | [PCIE_1_GDSC] = &pcie_1_gdsc, | |
3920 | [UFS_CARD_GDSC] = &ufs_card_gdsc, | |
3921 | [UFS_PHY_GDSC] = &ufs_phy_gdsc, | |
3922 | [USB30_PRIM_GDSC] = &usb30_prim_gdsc, | |
3923 | [USB30_SEC_GDSC] = &usb30_sec_gdsc, | |
3924 | [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = | |
3925 | &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, | |
3926 | [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = | |
3927 | &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, | |
3928 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = | |
3929 | &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, | |
3930 | [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = | |
3931 | &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, | |
3932 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = | |
3933 | &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, | |
3934 | [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = | |
3935 | &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, | |
3936 | [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, | |
3937 | }; | |
3938 | ||
3939 | static const struct regmap_config gcc_sdm845_regmap_config = { | |
3940 | .reg_bits = 32, | |
3941 | .reg_stride = 4, | |
3942 | .val_bits = 32, | |
3943 | .max_register = 0x182090, | |
3944 | .fast_io = true, | |
3945 | }; | |
3946 | ||
ae66b1fe RA |
3947 | static const struct qcom_cc_desc gcc_sdm670_desc = { |
3948 | .config = &gcc_sdm845_regmap_config, | |
3949 | .clks = gcc_sdm670_clocks, | |
3950 | .num_clks = ARRAY_SIZE(gcc_sdm670_clocks), | |
3951 | /* Snapdragon 670 can function without its own exclusive resets. */ | |
3952 | .resets = gcc_sdm845_resets, | |
3953 | .num_resets = ARRAY_SIZE(gcc_sdm845_resets), | |
3954 | .gdscs = gcc_sdm670_gdscs, | |
3955 | .num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs), | |
3956 | }; | |
3957 | ||
06391edd TD |
3958 | static const struct qcom_cc_desc gcc_sdm845_desc = { |
3959 | .config = &gcc_sdm845_regmap_config, | |
3960 | .clks = gcc_sdm845_clocks, | |
3961 | .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), | |
3962 | .resets = gcc_sdm845_resets, | |
3963 | .num_resets = ARRAY_SIZE(gcc_sdm845_resets), | |
3964 | .gdscs = gcc_sdm845_gdscs, | |
3965 | .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs), | |
3966 | }; | |
3967 | ||
3968 | static const struct of_device_id gcc_sdm845_match_table[] = { | |
ae66b1fe | 3969 | { .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc }, |
8e90216d | 3970 | { .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc }, |
06391edd TD |
3971 | { } |
3972 | }; | |
3973 | MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); | |
3974 | ||
8b69c6db | 3975 | static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { |
1a1c7821 TD |
3976 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), |
3977 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), | |
3978 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), | |
3979 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), | |
3980 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), | |
3981 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), | |
3982 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), | |
3983 | DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), | |
3984 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), | |
3985 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), | |
3986 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), | |
3987 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), | |
3988 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), | |
3989 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), | |
3990 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), | |
3991 | DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), | |
8b69c6db TD |
3992 | }; |
3993 | ||
06391edd TD |
3994 | static int gcc_sdm845_probe(struct platform_device *pdev) |
3995 | { | |
8e90216d | 3996 | const struct qcom_cc_desc *gcc_desc; |
06391edd | 3997 | struct regmap *regmap; |
8b69c6db | 3998 | int ret; |
06391edd TD |
3999 | |
4000 | regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); | |
4001 | if (IS_ERR(regmap)) | |
4002 | return PTR_ERR(regmap); | |
4003 | ||
4004 | /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ | |
4005 | regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); | |
4006 | regmap_update_bits(regmap, 0x71028, 0x3, 0x3); | |
4007 | ||
8b69c6db TD |
4008 | ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, |
4009 | ARRAY_SIZE(gcc_dfs_clocks)); | |
4010 | if (ret) | |
4011 | return ret; | |
4012 | ||
8e90216d | 4013 | gcc_desc = of_device_get_match_data(&pdev->dev); |
9f93a0a4 | 4014 | return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap); |
06391edd TD |
4015 | } |
4016 | ||
4017 | static struct platform_driver gcc_sdm845_driver = { | |
4018 | .probe = gcc_sdm845_probe, | |
4019 | .driver = { | |
4020 | .name = "gcc-sdm845", | |
4021 | .of_match_table = gcc_sdm845_match_table, | |
4022 | }, | |
4023 | }; | |
4024 | ||
4025 | static int __init gcc_sdm845_init(void) | |
4026 | { | |
4027 | return platform_driver_register(&gcc_sdm845_driver); | |
4028 | } | |
b418bab4 | 4029 | core_initcall(gcc_sdm845_init); |
06391edd TD |
4030 | |
4031 | static void __exit gcc_sdm845_exit(void) | |
4032 | { | |
4033 | platform_driver_unregister(&gcc_sdm845_driver); | |
4034 | } | |
4035 | module_exit(gcc_sdm845_exit); | |
4036 | ||
4037 | MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); | |
4038 | MODULE_LICENSE("GPL v2"); | |
4039 | MODULE_ALIAS("platform:gcc-sdm845"); | |
1d9054e3 | 4040 | MODULE_SOFTDEP("pre: rpmhpd"); |