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b1e010c0 SB |
1 | /* |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,gcc-msm8996.h> | |
26 | ||
27 | #include "common.h" | |
28 | #include "clk-regmap.h" | |
29 | #include "clk-alpha-pll.h" | |
30 | #include "clk-rcg.h" | |
31 | #include "clk-branch.h" | |
32 | #include "reset.h" | |
52111672 | 33 | #include "gdsc.h" |
b1e010c0 SB |
34 | |
35 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } | |
36 | ||
37 | enum { | |
38 | P_XO, | |
39 | P_GPLL0, | |
40 | P_GPLL2, | |
41 | P_GPLL3, | |
42 | P_GPLL1, | |
43 | P_GPLL2_EARLY, | |
44 | P_GPLL0_EARLY_DIV, | |
45 | P_SLEEP_CLK, | |
46 | P_GPLL4, | |
47 | P_AUD_REF_CLK, | |
48 | P_GPLL1_EARLY_DIV | |
49 | }; | |
50 | ||
51 | static const struct parent_map gcc_sleep_clk_map[] = { | |
52 | { P_SLEEP_CLK, 5 } | |
53 | }; | |
54 | ||
55 | static const char * const gcc_sleep_clk[] = { | |
56 | "sleep_clk" | |
57 | }; | |
58 | ||
59 | static const struct parent_map gcc_xo_gpll0_map[] = { | |
60 | { P_XO, 0 }, | |
61 | { P_GPLL0, 1 } | |
62 | }; | |
63 | ||
64 | static const char * const gcc_xo_gpll0[] = { | |
65 | "xo", | |
66 | "gpll0" | |
67 | }; | |
68 | ||
69 | static const struct parent_map gcc_xo_sleep_clk_map[] = { | |
70 | { P_XO, 0 }, | |
71 | { P_SLEEP_CLK, 5 } | |
72 | }; | |
73 | ||
74 | static const char * const gcc_xo_sleep_clk[] = { | |
75 | "xo", | |
76 | "sleep_clk" | |
77 | }; | |
78 | ||
79 | static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { | |
80 | { P_XO, 0 }, | |
81 | { P_GPLL0, 1 }, | |
82 | { P_GPLL0_EARLY_DIV, 6 } | |
83 | }; | |
84 | ||
85 | static const char * const gcc_xo_gpll0_gpll0_early_div[] = { | |
86 | "xo", | |
87 | "gpll0", | |
88 | "gpll0_early_div" | |
89 | }; | |
90 | ||
91 | static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { | |
92 | { P_XO, 0 }, | |
93 | { P_GPLL0, 1 }, | |
94 | { P_GPLL4, 5 } | |
95 | }; | |
96 | ||
97 | static const char * const gcc_xo_gpll0_gpll4[] = { | |
98 | "xo", | |
99 | "gpll0", | |
100 | "gpll4" | |
101 | }; | |
102 | ||
103 | static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { | |
104 | { P_XO, 0 }, | |
105 | { P_GPLL0, 1 }, | |
106 | { P_AUD_REF_CLK, 2 } | |
107 | }; | |
108 | ||
109 | static const char * const gcc_xo_gpll0_aud_ref_clk[] = { | |
110 | "xo", | |
111 | "gpll0", | |
112 | "aud_ref_clk" | |
113 | }; | |
114 | ||
115 | static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { | |
116 | { P_XO, 0 }, | |
117 | { P_GPLL0, 1 }, | |
118 | { P_SLEEP_CLK, 5 }, | |
119 | { P_GPLL0_EARLY_DIV, 6 } | |
120 | }; | |
121 | ||
122 | static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { | |
123 | "xo", | |
124 | "gpll0", | |
125 | "sleep_clk", | |
126 | "gpll0_early_div" | |
127 | }; | |
128 | ||
129 | static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { | |
130 | { P_XO, 0 }, | |
131 | { P_GPLL0, 1 }, | |
132 | { P_GPLL4, 5 }, | |
133 | { P_GPLL0_EARLY_DIV, 6 } | |
134 | }; | |
135 | ||
136 | static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { | |
137 | "xo", | |
138 | "gpll0", | |
139 | "gpll4", | |
140 | "gpll0_early_div" | |
141 | }; | |
142 | ||
143 | static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = { | |
144 | { P_XO, 0 }, | |
145 | { P_GPLL0, 1 }, | |
146 | { P_GPLL2, 2 }, | |
147 | { P_GPLL3, 3 }, | |
148 | { P_GPLL0_EARLY_DIV, 6 } | |
149 | }; | |
150 | ||
151 | static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { | |
152 | "xo", | |
153 | "gpll0", | |
154 | "gpll2", | |
155 | "gpll3", | |
156 | "gpll0_early_div" | |
157 | }; | |
158 | ||
159 | static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = { | |
160 | { P_XO, 0 }, | |
161 | { P_GPLL0, 1 }, | |
162 | { P_GPLL1_EARLY_DIV, 3 }, | |
163 | { P_GPLL1, 4 }, | |
164 | { P_GPLL4, 5 }, | |
165 | { P_GPLL0_EARLY_DIV, 6 } | |
166 | }; | |
167 | ||
168 | static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = { | |
169 | "xo", | |
170 | "gpll0", | |
171 | "gpll1_early_div", | |
172 | "gpll1", | |
173 | "gpll4", | |
174 | "gpll0_early_div" | |
175 | }; | |
176 | ||
177 | static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = { | |
178 | { P_XO, 0 }, | |
179 | { P_GPLL0, 1 }, | |
180 | { P_GPLL2, 2 }, | |
181 | { P_GPLL3, 3 }, | |
182 | { P_GPLL1, 4 }, | |
183 | { P_GPLL2_EARLY, 5 }, | |
184 | { P_GPLL0_EARLY_DIV, 6 } | |
185 | }; | |
186 | ||
187 | static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = { | |
188 | "xo", | |
189 | "gpll0", | |
190 | "gpll2", | |
191 | "gpll3", | |
192 | "gpll1", | |
193 | "gpll2_early", | |
194 | "gpll0_early_div" | |
195 | }; | |
196 | ||
197 | static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { | |
198 | { P_XO, 0 }, | |
199 | { P_GPLL0, 1 }, | |
200 | { P_GPLL2, 2 }, | |
201 | { P_GPLL3, 3 }, | |
202 | { P_GPLL1, 4 }, | |
203 | { P_GPLL4, 5 }, | |
204 | { P_GPLL0_EARLY_DIV, 6 } | |
205 | }; | |
206 | ||
207 | static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = { | |
208 | "xo", | |
209 | "gpll0", | |
210 | "gpll2", | |
211 | "gpll3", | |
212 | "gpll1", | |
213 | "gpll4", | |
214 | "gpll0_early_div" | |
215 | }; | |
216 | ||
217 | static struct clk_fixed_factor xo = { | |
218 | .mult = 1, | |
219 | .div = 1, | |
220 | .hw.init = &(struct clk_init_data){ | |
221 | .name = "xo", | |
222 | .parent_names = (const char *[]){ "xo_board" }, | |
223 | .num_parents = 1, | |
224 | .ops = &clk_fixed_factor_ops, | |
225 | }, | |
226 | }; | |
227 | ||
228 | static struct clk_alpha_pll gpll0_early = { | |
229 | .offset = 0x00000, | |
230 | .clkr = { | |
231 | .enable_reg = 0x52000, | |
232 | .enable_mask = BIT(0), | |
233 | .hw.init = &(struct clk_init_data){ | |
234 | .name = "gpll0_early", | |
235 | .parent_names = (const char *[]){ "xo" }, | |
236 | .num_parents = 1, | |
237 | .ops = &clk_alpha_pll_ops, | |
238 | }, | |
239 | }, | |
240 | }; | |
241 | ||
242 | static struct clk_fixed_factor gpll0_early_div = { | |
243 | .mult = 1, | |
244 | .div = 2, | |
245 | .hw.init = &(struct clk_init_data){ | |
246 | .name = "gpll0_early_div", | |
247 | .parent_names = (const char *[]){ "gpll0_early" }, | |
248 | .num_parents = 1, | |
249 | .ops = &clk_fixed_factor_ops, | |
250 | }, | |
251 | }; | |
252 | ||
253 | static struct clk_alpha_pll_postdiv gpll0 = { | |
254 | .offset = 0x00000, | |
255 | .clkr.hw.init = &(struct clk_init_data){ | |
256 | .name = "gpll0", | |
257 | .parent_names = (const char *[]){ "gpll0_early" }, | |
258 | .num_parents = 1, | |
259 | .ops = &clk_alpha_pll_postdiv_ops, | |
260 | }, | |
261 | }; | |
262 | ||
263 | static struct clk_alpha_pll gpll4_early = { | |
264 | .offset = 0x77000, | |
265 | .clkr = { | |
266 | .enable_reg = 0x52000, | |
267 | .enable_mask = BIT(4), | |
268 | .hw.init = &(struct clk_init_data){ | |
269 | .name = "gpll4_early", | |
270 | .parent_names = (const char *[]){ "xo" }, | |
271 | .num_parents = 1, | |
272 | .ops = &clk_alpha_pll_ops, | |
273 | }, | |
274 | }, | |
275 | }; | |
276 | ||
277 | static struct clk_alpha_pll_postdiv gpll4 = { | |
278 | .offset = 0x77000, | |
279 | .clkr.hw.init = &(struct clk_init_data){ | |
280 | .name = "gpll4", | |
281 | .parent_names = (const char *[]){ "gpll4_early" }, | |
282 | .num_parents = 1, | |
283 | .ops = &clk_alpha_pll_postdiv_ops, | |
284 | }, | |
285 | }; | |
286 | ||
287 | static const struct freq_tbl ftbl_system_noc_clk_src[] = { | |
288 | F(19200000, P_XO, 1, 0, 0), | |
289 | F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), | |
290 | F(100000000, P_GPLL0, 6, 0, 0), | |
291 | F(150000000, P_GPLL0, 4, 0, 0), | |
292 | F(200000000, P_GPLL0, 3, 0, 0), | |
293 | F(240000000, P_GPLL0, 2.5, 0, 0), | |
294 | { } | |
295 | }; | |
296 | ||
297 | static struct clk_rcg2 system_noc_clk_src = { | |
298 | .cmd_rcgr = 0x0401c, | |
299 | .hid_width = 5, | |
300 | .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map, | |
301 | .freq_tbl = ftbl_system_noc_clk_src, | |
302 | .clkr.hw.init = &(struct clk_init_data){ | |
303 | .name = "system_noc_clk_src", | |
304 | .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, | |
305 | .num_parents = 7, | |
306 | .ops = &clk_rcg2_ops, | |
307 | }, | |
308 | }; | |
309 | ||
310 | static const struct freq_tbl ftbl_config_noc_clk_src[] = { | |
311 | F(19200000, P_XO, 1, 0, 0), | |
312 | F(37500000, P_GPLL0, 16, 0, 0), | |
313 | F(75000000, P_GPLL0, 8, 0, 0), | |
314 | { } | |
315 | }; | |
316 | ||
317 | static struct clk_rcg2 config_noc_clk_src = { | |
318 | .cmd_rcgr = 0x0500c, | |
319 | .hid_width = 5, | |
320 | .parent_map = gcc_xo_gpll0_map, | |
321 | .freq_tbl = ftbl_config_noc_clk_src, | |
322 | .clkr.hw.init = &(struct clk_init_data){ | |
323 | .name = "config_noc_clk_src", | |
324 | .parent_names = gcc_xo_gpll0, | |
325 | .num_parents = 2, | |
326 | .ops = &clk_rcg2_ops, | |
327 | }, | |
328 | }; | |
329 | ||
330 | static const struct freq_tbl ftbl_periph_noc_clk_src[] = { | |
331 | F(19200000, P_XO, 1, 0, 0), | |
332 | F(37500000, P_GPLL0, 16, 0, 0), | |
333 | F(50000000, P_GPLL0, 12, 0, 0), | |
334 | F(75000000, P_GPLL0, 8, 0, 0), | |
335 | F(100000000, P_GPLL0, 6, 0, 0), | |
336 | { } | |
337 | }; | |
338 | ||
339 | static struct clk_rcg2 periph_noc_clk_src = { | |
340 | .cmd_rcgr = 0x06014, | |
341 | .hid_width = 5, | |
342 | .parent_map = gcc_xo_gpll0_map, | |
343 | .freq_tbl = ftbl_periph_noc_clk_src, | |
344 | .clkr.hw.init = &(struct clk_init_data){ | |
345 | .name = "periph_noc_clk_src", | |
346 | .parent_names = gcc_xo_gpll0, | |
347 | .num_parents = 2, | |
348 | .ops = &clk_rcg2_ops, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static const struct freq_tbl ftbl_usb30_master_clk_src[] = { | |
353 | F(19200000, P_XO, 1, 0, 0), | |
354 | F(120000000, P_GPLL0, 5, 0, 0), | |
355 | F(150000000, P_GPLL0, 4, 0, 0), | |
356 | { } | |
357 | }; | |
358 | ||
359 | static struct clk_rcg2 usb30_master_clk_src = { | |
360 | .cmd_rcgr = 0x0f014, | |
361 | .mnd_width = 8, | |
362 | .hid_width = 5, | |
363 | .parent_map = gcc_xo_gpll0_gpll0_early_div_map, | |
364 | .freq_tbl = ftbl_usb30_master_clk_src, | |
365 | .clkr.hw.init = &(struct clk_init_data){ | |
366 | .name = "usb30_master_clk_src", | |
367 | .parent_names = gcc_xo_gpll0_gpll0_early_div, | |
368 | .num_parents = 3, | |
369 | .ops = &clk_rcg2_ops, | |
370 | }, | |
371 | }; | |
372 | ||
373 | static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { | |
374 | F(19200000, P_XO, 1, 0, 0), | |
375 | { } | |
376 | }; | |
377 | ||
378 | static struct clk_rcg2 usb30_mock_utmi_clk_src = { | |
379 | .cmd_rcgr = 0x0f028, | |
380 | .hid_width = 5, | |
381 | .parent_map = gcc_xo_gpll0_gpll0_early_div_map, | |
382 | .freq_tbl = ftbl_usb30_mock_utmi_clk_src, | |
383 | .clkr.hw.init = &(struct clk_init_data){ | |
384 | .name = "usb30_mock_utmi_clk_src", | |
385 | .parent_names = gcc_xo_gpll0_gpll0_early_div, | |
386 | .num_parents = 3, | |
387 | .ops = &clk_rcg2_ops, | |
388 | }, | |
389 | }; | |
390 | ||
391 | static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { | |
392 | F(1200000, P_XO, 16, 0, 0), | |
393 | { } | |
394 | }; | |
395 | ||
396 | static struct clk_rcg2 usb3_phy_aux_clk_src = { | |
397 | .cmd_rcgr = 0x5000c, | |
398 | .hid_width = 5, | |
399 | .parent_map = gcc_xo_sleep_clk_map, | |
400 | .freq_tbl = ftbl_usb3_phy_aux_clk_src, | |
401 | .clkr.hw.init = &(struct clk_init_data){ | |
402 | .name = "usb3_phy_aux_clk_src", | |
403 | .parent_names = gcc_xo_sleep_clk, | |
404 | .num_parents = 2, | |
405 | .ops = &clk_rcg2_ops, | |
406 | }, | |
407 | }; | |
408 | ||
409 | static const struct freq_tbl ftbl_usb20_master_clk_src[] = { | |
410 | F(120000000, P_GPLL0, 5, 0, 0), | |
411 | { } | |
412 | }; | |
413 | ||
414 | static struct clk_rcg2 usb20_master_clk_src = { | |
415 | .cmd_rcgr = 0x12010, | |
416 | .mnd_width = 8, | |
417 | .hid_width = 5, | |
418 | .parent_map = gcc_xo_gpll0_gpll0_early_div_map, | |
419 | .freq_tbl = ftbl_usb20_master_clk_src, | |
420 | .clkr.hw.init = &(struct clk_init_data){ | |
421 | .name = "usb20_master_clk_src", | |
422 | .parent_names = gcc_xo_gpll0_gpll0_early_div, | |
423 | .num_parents = 3, | |
424 | .ops = &clk_rcg2_ops, | |
425 | }, | |
426 | }; | |
427 | ||
428 | static struct clk_rcg2 usb20_mock_utmi_clk_src = { | |
429 | .cmd_rcgr = 0x12024, | |
430 | .hid_width = 5, | |
431 | .parent_map = gcc_xo_gpll0_gpll0_early_div_map, | |
432 | .freq_tbl = ftbl_usb30_mock_utmi_clk_src, | |
433 | .clkr.hw.init = &(struct clk_init_data){ | |
434 | .name = "usb20_mock_utmi_clk_src", | |
435 | .parent_names = gcc_xo_gpll0_gpll0_early_div, | |
436 | .num_parents = 3, | |
437 | .ops = &clk_rcg2_ops, | |
438 | }, | |
439 | }; | |
440 | ||
441 | static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { | |
442 | F(144000, P_XO, 16, 3, 25), | |
443 | F(400000, P_XO, 12, 1, 4), | |
444 | F(20000000, P_GPLL0, 15, 1, 2), | |
445 | F(25000000, P_GPLL0, 12, 1, 2), | |
446 | F(50000000, P_GPLL0, 12, 0, 0), | |
447 | F(96000000, P_GPLL4, 4, 0, 0), | |
448 | F(192000000, P_GPLL4, 2, 0, 0), | |
449 | F(384000000, P_GPLL4, 1, 0, 0), | |
450 | { } | |
451 | }; | |
452 | ||
453 | static struct clk_rcg2 sdcc1_apps_clk_src = { | |
454 | .cmd_rcgr = 0x13010, | |
455 | .mnd_width = 8, | |
456 | .hid_width = 5, | |
457 | .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map, | |
458 | .freq_tbl = ftbl_sdcc1_apps_clk_src, | |
459 | .clkr.hw.init = &(struct clk_init_data){ | |
460 | .name = "sdcc1_apps_clk_src", | |
461 | .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, | |
462 | .num_parents = 4, | |
463 | .ops = &clk_rcg2_ops, | |
464 | }, | |
465 | }; | |
466 | ||
467 | static struct clk_rcg2 sdcc1_ice_core_clk_src = { | |
468 | .cmd_rcgr = 0x13024, | |
469 | .hid_width = 5, | |
470 | .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map, | |
471 | .clkr.hw.init = &(struct clk_init_data){ | |
472 | .name = "sdcc1_ice_core_clk_src", | |
473 | .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, | |
474 | .num_parents = 4, | |
475 | .ops = &clk_rcg2_ops, | |
476 | }, | |
477 | }; | |
478 | ||
479 | static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { | |
480 | F(144000, P_XO, 16, 3, 25), | |
481 | F(400000, P_XO, 12, 1, 4), | |
482 | F(20000000, P_GPLL0, 15, 1, 2), | |
483 | F(25000000, P_GPLL0, 12, 1, 2), | |
484 | F(50000000, P_GPLL0, 12, 0, 0), | |
485 | F(100000000, P_GPLL0, 6, 0, 0), | |
486 | F(200000000, P_GPLL0, 3, 0, 0), | |
487 | { } | |
488 | }; | |
489 | ||
490 | static struct clk_rcg2 sdcc2_apps_clk_src = { | |
491 | .cmd_rcgr = 0x14010, | |
492 | .mnd_width = 8, | |
493 | .hid_width = 5, | |
494 | .parent_map = gcc_xo_gpll0_gpll4_map, | |
495 | .freq_tbl = ftbl_sdcc2_apps_clk_src, | |
496 | .clkr.hw.init = &(struct clk_init_data){ | |
497 | .name = "sdcc2_apps_clk_src", | |
498 | .parent_names = gcc_xo_gpll0_gpll4, | |
499 | .num_parents = 3, | |
500 | .ops = &clk_rcg2_ops, | |
501 | }, | |
502 | }; | |
503 | ||
504 | static struct clk_rcg2 sdcc3_apps_clk_src = { | |
505 | .cmd_rcgr = 0x15010, | |
506 | .mnd_width = 8, | |
507 | .hid_width = 5, | |
508 | .parent_map = gcc_xo_gpll0_gpll4_map, | |
509 | .freq_tbl = ftbl_sdcc2_apps_clk_src, | |
510 | .clkr.hw.init = &(struct clk_init_data){ | |
511 | .name = "sdcc3_apps_clk_src", | |
512 | .parent_names = gcc_xo_gpll0_gpll4, | |
513 | .num_parents = 3, | |
514 | .ops = &clk_rcg2_ops, | |
515 | }, | |
516 | }; | |
517 | ||
518 | static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { | |
519 | F(144000, P_XO, 16, 3, 25), | |
520 | F(400000, P_XO, 12, 1, 4), | |
521 | F(20000000, P_GPLL0, 15, 1, 2), | |
522 | F(25000000, P_GPLL0, 12, 1, 2), | |
523 | F(50000000, P_GPLL0, 12, 0, 0), | |
524 | F(100000000, P_GPLL0, 6, 0, 0), | |
525 | { } | |
526 | }; | |
527 | ||
528 | static struct clk_rcg2 sdcc4_apps_clk_src = { | |
529 | .cmd_rcgr = 0x16010, | |
530 | .mnd_width = 8, | |
531 | .hid_width = 5, | |
532 | .parent_map = gcc_xo_gpll0_map, | |
533 | .freq_tbl = ftbl_sdcc4_apps_clk_src, | |
534 | .clkr.hw.init = &(struct clk_init_data){ | |
535 | .name = "sdcc4_apps_clk_src", | |
536 | .parent_names = gcc_xo_gpll0, | |
537 | .num_parents = 2, | |
538 | .ops = &clk_rcg2_ops, | |
539 | }, | |
540 | }; | |
541 | ||
542 | static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { | |
543 | F(960000, P_XO, 10, 1, 2), | |
544 | F(4800000, P_XO, 4, 0, 0), | |
545 | F(9600000, P_XO, 2, 0, 0), | |
546 | F(15000000, P_GPLL0, 10, 1, 4), | |
547 | F(19200000, P_XO, 1, 0, 0), | |
548 | F(25000000, P_GPLL0, 12, 1, 2), | |
549 | F(50000000, P_GPLL0, 12, 0, 0), | |
550 | { } | |
551 | }; | |
552 | ||
553 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { | |
554 | .cmd_rcgr = 0x1900c, | |
555 | .mnd_width = 8, | |
556 | .hid_width = 5, | |
557 | .parent_map = gcc_xo_gpll0_map, | |
558 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
559 | .clkr.hw.init = &(struct clk_init_data){ | |
560 | .name = "blsp1_qup1_spi_apps_clk_src", | |
561 | .parent_names = gcc_xo_gpll0, | |
562 | .num_parents = 2, | |
563 | .ops = &clk_rcg2_ops, | |
564 | }, | |
565 | }; | |
566 | ||
567 | static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { | |
568 | F(19200000, P_XO, 1, 0, 0), | |
569 | F(50000000, P_GPLL0, 12, 0, 0), | |
570 | { } | |
571 | }; | |
572 | ||
573 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { | |
574 | .cmd_rcgr = 0x19020, | |
575 | .hid_width = 5, | |
576 | .parent_map = gcc_xo_gpll0_map, | |
577 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
578 | .clkr.hw.init = &(struct clk_init_data){ | |
579 | .name = "blsp1_qup1_i2c_apps_clk_src", | |
580 | .parent_names = gcc_xo_gpll0, | |
581 | .num_parents = 2, | |
582 | .ops = &clk_rcg2_ops, | |
583 | }, | |
584 | }; | |
585 | ||
586 | static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { | |
587 | F(3686400, P_GPLL0, 1, 96, 15625), | |
588 | F(7372800, P_GPLL0, 1, 192, 15625), | |
589 | F(14745600, P_GPLL0, 1, 384, 15625), | |
590 | F(16000000, P_GPLL0, 5, 2, 15), | |
591 | F(19200000, P_XO, 1, 0, 0), | |
592 | F(24000000, P_GPLL0, 5, 1, 5), | |
593 | F(32000000, P_GPLL0, 1, 4, 75), | |
594 | F(40000000, P_GPLL0, 15, 0, 0), | |
595 | F(46400000, P_GPLL0, 1, 29, 375), | |
596 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
597 | F(51200000, P_GPLL0, 1, 32, 375), | |
598 | F(56000000, P_GPLL0, 1, 7, 75), | |
599 | F(58982400, P_GPLL0, 1, 1536, 15625), | |
600 | F(60000000, P_GPLL0, 10, 0, 0), | |
601 | F(63157895, P_GPLL0, 9.5, 0, 0), | |
602 | { } | |
603 | }; | |
604 | ||
605 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { | |
606 | .cmd_rcgr = 0x1a00c, | |
607 | .mnd_width = 16, | |
608 | .hid_width = 5, | |
609 | .parent_map = gcc_xo_gpll0_map, | |
610 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
611 | .clkr.hw.init = &(struct clk_init_data){ | |
612 | .name = "blsp1_uart1_apps_clk_src", | |
613 | .parent_names = gcc_xo_gpll0, | |
614 | .num_parents = 2, | |
615 | .ops = &clk_rcg2_ops, | |
616 | }, | |
617 | }; | |
618 | ||
619 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { | |
620 | .cmd_rcgr = 0x1b00c, | |
621 | .mnd_width = 8, | |
622 | .hid_width = 5, | |
623 | .parent_map = gcc_xo_gpll0_map, | |
624 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
625 | .clkr.hw.init = &(struct clk_init_data){ | |
626 | .name = "blsp1_qup2_spi_apps_clk_src", | |
627 | .parent_names = gcc_xo_gpll0, | |
628 | .num_parents = 2, | |
629 | .ops = &clk_rcg2_ops, | |
630 | }, | |
631 | }; | |
632 | ||
633 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { | |
634 | .cmd_rcgr = 0x1b020, | |
635 | .hid_width = 5, | |
636 | .parent_map = gcc_xo_gpll0_map, | |
637 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
638 | .clkr.hw.init = &(struct clk_init_data){ | |
639 | .name = "blsp1_qup2_i2c_apps_clk_src", | |
640 | .parent_names = gcc_xo_gpll0, | |
641 | .num_parents = 2, | |
642 | .ops = &clk_rcg2_ops, | |
643 | }, | |
644 | }; | |
645 | ||
646 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { | |
647 | .cmd_rcgr = 0x1c00c, | |
648 | .mnd_width = 16, | |
649 | .hid_width = 5, | |
650 | .parent_map = gcc_xo_gpll0_map, | |
651 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
652 | .clkr.hw.init = &(struct clk_init_data){ | |
653 | .name = "blsp1_uart2_apps_clk_src", | |
654 | .parent_names = gcc_xo_gpll0, | |
655 | .num_parents = 2, | |
656 | .ops = &clk_rcg2_ops, | |
657 | }, | |
658 | }; | |
659 | ||
660 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { | |
661 | .cmd_rcgr = 0x1d00c, | |
662 | .mnd_width = 8, | |
663 | .hid_width = 5, | |
664 | .parent_map = gcc_xo_gpll0_map, | |
665 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
666 | .clkr.hw.init = &(struct clk_init_data){ | |
667 | .name = "blsp1_qup3_spi_apps_clk_src", | |
668 | .parent_names = gcc_xo_gpll0, | |
669 | .num_parents = 2, | |
670 | .ops = &clk_rcg2_ops, | |
671 | }, | |
672 | }; | |
673 | ||
674 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { | |
675 | .cmd_rcgr = 0x1d020, | |
676 | .hid_width = 5, | |
677 | .parent_map = gcc_xo_gpll0_map, | |
678 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
679 | .clkr.hw.init = &(struct clk_init_data){ | |
680 | .name = "blsp1_qup3_i2c_apps_clk_src", | |
681 | .parent_names = gcc_xo_gpll0, | |
682 | .num_parents = 2, | |
683 | .ops = &clk_rcg2_ops, | |
684 | }, | |
685 | }; | |
686 | ||
687 | static struct clk_rcg2 blsp1_uart3_apps_clk_src = { | |
688 | .cmd_rcgr = 0x1e00c, | |
689 | .mnd_width = 16, | |
690 | .hid_width = 5, | |
691 | .parent_map = gcc_xo_gpll0_map, | |
692 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
693 | .clkr.hw.init = &(struct clk_init_data){ | |
694 | .name = "blsp1_uart3_apps_clk_src", | |
695 | .parent_names = gcc_xo_gpll0, | |
696 | .num_parents = 2, | |
697 | .ops = &clk_rcg2_ops, | |
698 | }, | |
699 | }; | |
700 | ||
701 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { | |
702 | .cmd_rcgr = 0x1f00c, | |
703 | .mnd_width = 8, | |
704 | .hid_width = 5, | |
705 | .parent_map = gcc_xo_gpll0_map, | |
706 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
707 | .clkr.hw.init = &(struct clk_init_data){ | |
708 | .name = "blsp1_qup4_spi_apps_clk_src", | |
709 | .parent_names = gcc_xo_gpll0, | |
710 | .num_parents = 2, | |
711 | .ops = &clk_rcg2_ops, | |
712 | }, | |
713 | }; | |
714 | ||
715 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { | |
716 | .cmd_rcgr = 0x1f020, | |
717 | .hid_width = 5, | |
718 | .parent_map = gcc_xo_gpll0_map, | |
719 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
720 | .clkr.hw.init = &(struct clk_init_data){ | |
721 | .name = "blsp1_qup4_i2c_apps_clk_src", | |
722 | .parent_names = gcc_xo_gpll0, | |
723 | .num_parents = 2, | |
724 | .ops = &clk_rcg2_ops, | |
725 | }, | |
726 | }; | |
727 | ||
728 | static struct clk_rcg2 blsp1_uart4_apps_clk_src = { | |
729 | .cmd_rcgr = 0x2000c, | |
730 | .mnd_width = 16, | |
731 | .hid_width = 5, | |
732 | .parent_map = gcc_xo_gpll0_map, | |
733 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
734 | .clkr.hw.init = &(struct clk_init_data){ | |
735 | .name = "blsp1_uart4_apps_clk_src", | |
736 | .parent_names = gcc_xo_gpll0, | |
737 | .num_parents = 2, | |
738 | .ops = &clk_rcg2_ops, | |
739 | }, | |
740 | }; | |
741 | ||
742 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { | |
743 | .cmd_rcgr = 0x2100c, | |
744 | .mnd_width = 8, | |
745 | .hid_width = 5, | |
746 | .parent_map = gcc_xo_gpll0_map, | |
747 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
748 | .clkr.hw.init = &(struct clk_init_data){ | |
749 | .name = "blsp1_qup5_spi_apps_clk_src", | |
750 | .parent_names = gcc_xo_gpll0, | |
751 | .num_parents = 2, | |
752 | .ops = &clk_rcg2_ops, | |
753 | }, | |
754 | }; | |
755 | ||
756 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { | |
757 | .cmd_rcgr = 0x21020, | |
758 | .hid_width = 5, | |
759 | .parent_map = gcc_xo_gpll0_map, | |
760 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
761 | .clkr.hw.init = &(struct clk_init_data){ | |
762 | .name = "blsp1_qup5_i2c_apps_clk_src", | |
763 | .parent_names = gcc_xo_gpll0, | |
764 | .num_parents = 2, | |
765 | .ops = &clk_rcg2_ops, | |
766 | }, | |
767 | }; | |
768 | ||
769 | static struct clk_rcg2 blsp1_uart5_apps_clk_src = { | |
770 | .cmd_rcgr = 0x2200c, | |
771 | .mnd_width = 16, | |
772 | .hid_width = 5, | |
773 | .parent_map = gcc_xo_gpll0_map, | |
774 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
775 | .clkr.hw.init = &(struct clk_init_data){ | |
776 | .name = "blsp1_uart5_apps_clk_src", | |
777 | .parent_names = gcc_xo_gpll0, | |
778 | .num_parents = 2, | |
779 | .ops = &clk_rcg2_ops, | |
780 | }, | |
781 | }; | |
782 | ||
783 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { | |
784 | .cmd_rcgr = 0x2300c, | |
785 | .mnd_width = 8, | |
786 | .hid_width = 5, | |
787 | .parent_map = gcc_xo_gpll0_map, | |
788 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
789 | .clkr.hw.init = &(struct clk_init_data){ | |
790 | .name = "blsp1_qup6_spi_apps_clk_src", | |
791 | .parent_names = gcc_xo_gpll0, | |
792 | .num_parents = 2, | |
793 | .ops = &clk_rcg2_ops, | |
794 | }, | |
795 | }; | |
796 | ||
797 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { | |
798 | .cmd_rcgr = 0x23020, | |
799 | .hid_width = 5, | |
800 | .parent_map = gcc_xo_gpll0_map, | |
801 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
802 | .clkr.hw.init = &(struct clk_init_data){ | |
803 | .name = "blsp1_qup6_i2c_apps_clk_src", | |
804 | .parent_names = gcc_xo_gpll0, | |
805 | .num_parents = 2, | |
806 | .ops = &clk_rcg2_ops, | |
807 | }, | |
808 | }; | |
809 | ||
810 | static struct clk_rcg2 blsp1_uart6_apps_clk_src = { | |
811 | .cmd_rcgr = 0x2400c, | |
812 | .mnd_width = 16, | |
813 | .hid_width = 5, | |
814 | .parent_map = gcc_xo_gpll0_map, | |
815 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
816 | .clkr.hw.init = &(struct clk_init_data){ | |
817 | .name = "blsp1_uart6_apps_clk_src", | |
818 | .parent_names = gcc_xo_gpll0, | |
819 | .num_parents = 2, | |
820 | .ops = &clk_rcg2_ops, | |
821 | }, | |
822 | }; | |
823 | ||
824 | static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { | |
825 | .cmd_rcgr = 0x2600c, | |
826 | .mnd_width = 8, | |
827 | .hid_width = 5, | |
828 | .parent_map = gcc_xo_gpll0_map, | |
829 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
830 | .clkr.hw.init = &(struct clk_init_data){ | |
831 | .name = "blsp2_qup1_spi_apps_clk_src", | |
832 | .parent_names = gcc_xo_gpll0, | |
833 | .num_parents = 2, | |
834 | .ops = &clk_rcg2_ops, | |
835 | }, | |
836 | }; | |
837 | ||
838 | static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { | |
839 | .cmd_rcgr = 0x26020, | |
840 | .hid_width = 5, | |
841 | .parent_map = gcc_xo_gpll0_map, | |
842 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
843 | .clkr.hw.init = &(struct clk_init_data){ | |
844 | .name = "blsp2_qup1_i2c_apps_clk_src", | |
845 | .parent_names = gcc_xo_gpll0, | |
846 | .num_parents = 2, | |
847 | .ops = &clk_rcg2_ops, | |
848 | }, | |
849 | }; | |
850 | ||
851 | static struct clk_rcg2 blsp2_uart1_apps_clk_src = { | |
852 | .cmd_rcgr = 0x2700c, | |
853 | .mnd_width = 16, | |
854 | .hid_width = 5, | |
855 | .parent_map = gcc_xo_gpll0_map, | |
856 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
857 | .clkr.hw.init = &(struct clk_init_data){ | |
858 | .name = "blsp2_uart1_apps_clk_src", | |
859 | .parent_names = gcc_xo_gpll0, | |
860 | .num_parents = 2, | |
861 | .ops = &clk_rcg2_ops, | |
862 | }, | |
863 | }; | |
864 | ||
865 | static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { | |
866 | .cmd_rcgr = 0x2800c, | |
867 | .mnd_width = 8, | |
868 | .hid_width = 5, | |
869 | .parent_map = gcc_xo_gpll0_map, | |
870 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
871 | .clkr.hw.init = &(struct clk_init_data){ | |
872 | .name = "blsp2_qup2_spi_apps_clk_src", | |
873 | .parent_names = gcc_xo_gpll0, | |
874 | .num_parents = 2, | |
875 | .ops = &clk_rcg2_ops, | |
876 | }, | |
877 | }; | |
878 | ||
879 | static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { | |
880 | .cmd_rcgr = 0x28020, | |
881 | .hid_width = 5, | |
882 | .parent_map = gcc_xo_gpll0_map, | |
883 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
884 | .clkr.hw.init = &(struct clk_init_data){ | |
885 | .name = "blsp2_qup2_i2c_apps_clk_src", | |
886 | .parent_names = gcc_xo_gpll0, | |
887 | .num_parents = 2, | |
888 | .ops = &clk_rcg2_ops, | |
889 | }, | |
890 | }; | |
891 | ||
892 | static struct clk_rcg2 blsp2_uart2_apps_clk_src = { | |
893 | .cmd_rcgr = 0x2900c, | |
894 | .mnd_width = 16, | |
895 | .hid_width = 5, | |
896 | .parent_map = gcc_xo_gpll0_map, | |
897 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
898 | .clkr.hw.init = &(struct clk_init_data){ | |
899 | .name = "blsp2_uart2_apps_clk_src", | |
900 | .parent_names = gcc_xo_gpll0, | |
901 | .num_parents = 2, | |
902 | .ops = &clk_rcg2_ops, | |
903 | }, | |
904 | }; | |
905 | ||
906 | static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { | |
907 | .cmd_rcgr = 0x2a00c, | |
908 | .mnd_width = 8, | |
909 | .hid_width = 5, | |
910 | .parent_map = gcc_xo_gpll0_map, | |
911 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
912 | .clkr.hw.init = &(struct clk_init_data){ | |
913 | .name = "blsp2_qup3_spi_apps_clk_src", | |
914 | .parent_names = gcc_xo_gpll0, | |
915 | .num_parents = 2, | |
916 | .ops = &clk_rcg2_ops, | |
917 | }, | |
918 | }; | |
919 | ||
920 | static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { | |
921 | .cmd_rcgr = 0x2a020, | |
922 | .hid_width = 5, | |
923 | .parent_map = gcc_xo_gpll0_map, | |
924 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
925 | .clkr.hw.init = &(struct clk_init_data){ | |
926 | .name = "blsp2_qup3_i2c_apps_clk_src", | |
927 | .parent_names = gcc_xo_gpll0, | |
928 | .num_parents = 2, | |
929 | .ops = &clk_rcg2_ops, | |
930 | }, | |
931 | }; | |
932 | ||
933 | static struct clk_rcg2 blsp2_uart3_apps_clk_src = { | |
934 | .cmd_rcgr = 0x2b00c, | |
935 | .mnd_width = 16, | |
936 | .hid_width = 5, | |
937 | .parent_map = gcc_xo_gpll0_map, | |
938 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
939 | .clkr.hw.init = &(struct clk_init_data){ | |
940 | .name = "blsp2_uart3_apps_clk_src", | |
941 | .parent_names = gcc_xo_gpll0, | |
942 | .num_parents = 2, | |
943 | .ops = &clk_rcg2_ops, | |
944 | }, | |
945 | }; | |
946 | ||
947 | static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { | |
948 | .cmd_rcgr = 0x2c00c, | |
949 | .mnd_width = 8, | |
950 | .hid_width = 5, | |
951 | .parent_map = gcc_xo_gpll0_map, | |
952 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
953 | .clkr.hw.init = &(struct clk_init_data){ | |
954 | .name = "blsp2_qup4_spi_apps_clk_src", | |
955 | .parent_names = gcc_xo_gpll0, | |
956 | .num_parents = 2, | |
957 | .ops = &clk_rcg2_ops, | |
958 | }, | |
959 | }; | |
960 | ||
961 | static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { | |
962 | .cmd_rcgr = 0x2c020, | |
963 | .hid_width = 5, | |
964 | .parent_map = gcc_xo_gpll0_map, | |
965 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
966 | .clkr.hw.init = &(struct clk_init_data){ | |
967 | .name = "blsp2_qup4_i2c_apps_clk_src", | |
968 | .parent_names = gcc_xo_gpll0, | |
969 | .num_parents = 2, | |
970 | .ops = &clk_rcg2_ops, | |
971 | }, | |
972 | }; | |
973 | ||
974 | static struct clk_rcg2 blsp2_uart4_apps_clk_src = { | |
975 | .cmd_rcgr = 0x2d00c, | |
976 | .mnd_width = 16, | |
977 | .hid_width = 5, | |
978 | .parent_map = gcc_xo_gpll0_map, | |
979 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
980 | .clkr.hw.init = &(struct clk_init_data){ | |
981 | .name = "blsp2_uart4_apps_clk_src", | |
982 | .parent_names = gcc_xo_gpll0, | |
983 | .num_parents = 2, | |
984 | .ops = &clk_rcg2_ops, | |
985 | }, | |
986 | }; | |
987 | ||
988 | static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { | |
989 | .cmd_rcgr = 0x2e00c, | |
990 | .mnd_width = 8, | |
991 | .hid_width = 5, | |
992 | .parent_map = gcc_xo_gpll0_map, | |
993 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
994 | .clkr.hw.init = &(struct clk_init_data){ | |
995 | .name = "blsp2_qup5_spi_apps_clk_src", | |
996 | .parent_names = gcc_xo_gpll0, | |
997 | .num_parents = 2, | |
998 | .ops = &clk_rcg2_ops, | |
999 | }, | |
1000 | }; | |
1001 | ||
1002 | static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { | |
1003 | .cmd_rcgr = 0x2e020, | |
1004 | .hid_width = 5, | |
1005 | .parent_map = gcc_xo_gpll0_map, | |
1006 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
1007 | .clkr.hw.init = &(struct clk_init_data){ | |
1008 | .name = "blsp2_qup5_i2c_apps_clk_src", | |
1009 | .parent_names = gcc_xo_gpll0, | |
1010 | .num_parents = 2, | |
1011 | .ops = &clk_rcg2_ops, | |
1012 | }, | |
1013 | }; | |
1014 | ||
1015 | static struct clk_rcg2 blsp2_uart5_apps_clk_src = { | |
1016 | .cmd_rcgr = 0x2f00c, | |
1017 | .mnd_width = 16, | |
1018 | .hid_width = 5, | |
1019 | .parent_map = gcc_xo_gpll0_map, | |
1020 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
1021 | .clkr.hw.init = &(struct clk_init_data){ | |
1022 | .name = "blsp2_uart5_apps_clk_src", | |
1023 | .parent_names = gcc_xo_gpll0, | |
1024 | .num_parents = 2, | |
1025 | .ops = &clk_rcg2_ops, | |
1026 | }, | |
1027 | }; | |
1028 | ||
1029 | static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { | |
1030 | .cmd_rcgr = 0x3000c, | |
1031 | .mnd_width = 8, | |
1032 | .hid_width = 5, | |
1033 | .parent_map = gcc_xo_gpll0_map, | |
1034 | .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, | |
1035 | .clkr.hw.init = &(struct clk_init_data){ | |
1036 | .name = "blsp2_qup6_spi_apps_clk_src", | |
1037 | .parent_names = gcc_xo_gpll0, | |
1038 | .num_parents = 2, | |
1039 | .ops = &clk_rcg2_ops, | |
1040 | }, | |
1041 | }; | |
1042 | ||
1043 | static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { | |
1044 | .cmd_rcgr = 0x30020, | |
1045 | .hid_width = 5, | |
1046 | .parent_map = gcc_xo_gpll0_map, | |
1047 | .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, | |
1048 | .clkr.hw.init = &(struct clk_init_data){ | |
1049 | .name = "blsp2_qup6_i2c_apps_clk_src", | |
1050 | .parent_names = gcc_xo_gpll0, | |
1051 | .num_parents = 2, | |
1052 | .ops = &clk_rcg2_ops, | |
1053 | }, | |
1054 | }; | |
1055 | ||
1056 | static struct clk_rcg2 blsp2_uart6_apps_clk_src = { | |
1057 | .cmd_rcgr = 0x3100c, | |
1058 | .mnd_width = 16, | |
1059 | .hid_width = 5, | |
1060 | .parent_map = gcc_xo_gpll0_map, | |
1061 | .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, | |
1062 | .clkr.hw.init = &(struct clk_init_data){ | |
1063 | .name = "blsp2_uart6_apps_clk_src", | |
1064 | .parent_names = gcc_xo_gpll0, | |
1065 | .num_parents = 2, | |
1066 | .ops = &clk_rcg2_ops, | |
1067 | }, | |
1068 | }; | |
1069 | ||
1070 | static const struct freq_tbl ftbl_pdm2_clk_src[] = { | |
1071 | F(60000000, P_GPLL0, 10, 0, 0), | |
1072 | { } | |
1073 | }; | |
1074 | ||
1075 | static struct clk_rcg2 pdm2_clk_src = { | |
1076 | .cmd_rcgr = 0x33010, | |
1077 | .hid_width = 5, | |
1078 | .parent_map = gcc_xo_gpll0_map, | |
1079 | .freq_tbl = ftbl_pdm2_clk_src, | |
1080 | .clkr.hw.init = &(struct clk_init_data){ | |
1081 | .name = "pdm2_clk_src", | |
1082 | .parent_names = gcc_xo_gpll0, | |
1083 | .num_parents = 2, | |
1084 | .ops = &clk_rcg2_ops, | |
1085 | }, | |
1086 | }; | |
1087 | ||
1088 | static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { | |
1089 | F(105495, P_XO, 1, 1, 182), | |
1090 | { } | |
1091 | }; | |
1092 | ||
1093 | static struct clk_rcg2 tsif_ref_clk_src = { | |
1094 | .cmd_rcgr = 0x36010, | |
1095 | .mnd_width = 8, | |
1096 | .hid_width = 5, | |
1097 | .parent_map = gcc_xo_gpll0_aud_ref_clk_map, | |
1098 | .freq_tbl = ftbl_tsif_ref_clk_src, | |
1099 | .clkr.hw.init = &(struct clk_init_data){ | |
1100 | .name = "tsif_ref_clk_src", | |
1101 | .parent_names = gcc_xo_gpll0_aud_ref_clk, | |
1102 | .num_parents = 3, | |
1103 | .ops = &clk_rcg2_ops, | |
1104 | }, | |
1105 | }; | |
1106 | ||
1107 | static struct clk_rcg2 gcc_sleep_clk_src = { | |
1108 | .cmd_rcgr = 0x43014, | |
1109 | .hid_width = 5, | |
1110 | .parent_map = gcc_sleep_clk_map, | |
1111 | .clkr.hw.init = &(struct clk_init_data){ | |
1112 | .name = "gcc_sleep_clk_src", | |
1113 | .parent_names = gcc_sleep_clk, | |
1114 | .num_parents = 1, | |
1115 | .ops = &clk_rcg2_ops, | |
1116 | }, | |
1117 | }; | |
1118 | ||
1119 | static struct clk_rcg2 hmss_rbcpr_clk_src = { | |
1120 | .cmd_rcgr = 0x48040, | |
1121 | .hid_width = 5, | |
1122 | .parent_map = gcc_xo_gpll0_map, | |
1123 | .freq_tbl = ftbl_usb30_mock_utmi_clk_src, | |
1124 | .clkr.hw.init = &(struct clk_init_data){ | |
1125 | .name = "hmss_rbcpr_clk_src", | |
1126 | .parent_names = gcc_xo_gpll0, | |
1127 | .num_parents = 2, | |
1128 | .ops = &clk_rcg2_ops, | |
1129 | }, | |
1130 | }; | |
1131 | ||
1132 | static struct clk_rcg2 hmss_gpll0_clk_src = { | |
1133 | .cmd_rcgr = 0x48058, | |
1134 | .hid_width = 5, | |
1135 | .parent_map = gcc_xo_gpll0_map, | |
1136 | .clkr.hw.init = &(struct clk_init_data){ | |
1137 | .name = "hmss_gpll0_clk_src", | |
1138 | .parent_names = gcc_xo_gpll0, | |
1139 | .num_parents = 2, | |
1140 | .ops = &clk_rcg2_ops, | |
1141 | }, | |
1142 | }; | |
1143 | ||
1144 | static const struct freq_tbl ftbl_gp1_clk_src[] = { | |
1145 | F(19200000, P_XO, 1, 0, 0), | |
1146 | F(100000000, P_GPLL0, 6, 0, 0), | |
1147 | F(200000000, P_GPLL0, 3, 0, 0), | |
1148 | { } | |
1149 | }; | |
1150 | ||
1151 | static struct clk_rcg2 gp1_clk_src = { | |
1152 | .cmd_rcgr = 0x64004, | |
1153 | .mnd_width = 8, | |
1154 | .hid_width = 5, | |
1155 | .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map, | |
1156 | .freq_tbl = ftbl_gp1_clk_src, | |
1157 | .clkr.hw.init = &(struct clk_init_data){ | |
1158 | .name = "gp1_clk_src", | |
1159 | .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, | |
1160 | .num_parents = 4, | |
1161 | .ops = &clk_rcg2_ops, | |
1162 | }, | |
1163 | }; | |
1164 | ||
1165 | static struct clk_rcg2 gp2_clk_src = { | |
1166 | .cmd_rcgr = 0x65004, | |
1167 | .mnd_width = 8, | |
1168 | .hid_width = 5, | |
1169 | .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map, | |
1170 | .freq_tbl = ftbl_gp1_clk_src, | |
1171 | .clkr.hw.init = &(struct clk_init_data){ | |
1172 | .name = "gp2_clk_src", | |
1173 | .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, | |
1174 | .num_parents = 4, | |
1175 | .ops = &clk_rcg2_ops, | |
1176 | }, | |
1177 | }; | |
1178 | ||
1179 | static struct clk_rcg2 gp3_clk_src = { | |
1180 | .cmd_rcgr = 0x66004, | |
1181 | .mnd_width = 8, | |
1182 | .hid_width = 5, | |
1183 | .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map, | |
1184 | .freq_tbl = ftbl_gp1_clk_src, | |
1185 | .clkr.hw.init = &(struct clk_init_data){ | |
1186 | .name = "gp3_clk_src", | |
1187 | .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, | |
1188 | .num_parents = 4, | |
1189 | .ops = &clk_rcg2_ops, | |
1190 | }, | |
1191 | }; | |
1192 | ||
1193 | static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { | |
1194 | F(1010526, P_XO, 1, 1, 19), | |
1195 | { } | |
1196 | }; | |
1197 | ||
1198 | static struct clk_rcg2 pcie_aux_clk_src = { | |
1199 | .cmd_rcgr = 0x6c000, | |
1200 | .mnd_width = 16, | |
1201 | .hid_width = 5, | |
1202 | .parent_map = gcc_xo_sleep_clk_map, | |
1203 | .freq_tbl = ftbl_pcie_aux_clk_src, | |
1204 | .clkr.hw.init = &(struct clk_init_data){ | |
1205 | .name = "pcie_aux_clk_src", | |
1206 | .parent_names = gcc_xo_sleep_clk, | |
1207 | .num_parents = 2, | |
1208 | .ops = &clk_rcg2_ops, | |
1209 | }, | |
1210 | }; | |
1211 | ||
1212 | static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { | |
1213 | F(100000000, P_GPLL0, 6, 0, 0), | |
1214 | F(200000000, P_GPLL0, 3, 0, 0), | |
1215 | F(240000000, P_GPLL0, 2.5, 0, 0), | |
1216 | { } | |
1217 | }; | |
1218 | ||
1219 | static struct clk_rcg2 ufs_axi_clk_src = { | |
1220 | .cmd_rcgr = 0x75024, | |
1221 | .mnd_width = 8, | |
1222 | .hid_width = 5, | |
1223 | .parent_map = gcc_xo_gpll0_map, | |
1224 | .freq_tbl = ftbl_ufs_axi_clk_src, | |
1225 | .clkr.hw.init = &(struct clk_init_data){ | |
1226 | .name = "ufs_axi_clk_src", | |
1227 | .parent_names = gcc_xo_gpll0, | |
1228 | .num_parents = 2, | |
1229 | .ops = &clk_rcg2_ops, | |
1230 | }, | |
1231 | }; | |
1232 | ||
1233 | static struct clk_rcg2 ufs_ice_core_clk_src = { | |
1234 | .cmd_rcgr = 0x76014, | |
1235 | .hid_width = 5, | |
1236 | .parent_map = gcc_xo_gpll0_map, | |
1237 | .clkr.hw.init = &(struct clk_init_data){ | |
1238 | .name = "ufs_ice_core_clk_src", | |
1239 | .parent_names = gcc_xo_gpll0, | |
1240 | .num_parents = 2, | |
1241 | .ops = &clk_rcg2_ops, | |
1242 | }, | |
1243 | }; | |
1244 | ||
1245 | static struct clk_rcg2 qspi_ser_clk_src = { | |
1246 | .cmd_rcgr = 0x8b00c, | |
1247 | .hid_width = 5, | |
1248 | .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map, | |
1249 | .clkr.hw.init = &(struct clk_init_data){ | |
1250 | .name = "qspi_ser_clk_src", | |
1251 | .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, | |
1252 | .num_parents = 6, | |
1253 | .ops = &clk_rcg2_ops, | |
1254 | }, | |
1255 | }; | |
1256 | ||
1257 | static struct clk_branch gcc_sys_noc_usb3_axi_clk = { | |
1258 | .halt_reg = 0x0f03c, | |
1259 | .clkr = { | |
1260 | .enable_reg = 0x0f03c, | |
1261 | .enable_mask = BIT(0), | |
1262 | .hw.init = &(struct clk_init_data){ | |
1263 | .name = "gcc_sys_noc_usb3_axi_clk", | |
1264 | .parent_names = (const char *[]){ "usb30_master_clk_src" }, | |
1265 | .num_parents = 1, | |
1266 | .flags = CLK_SET_RATE_PARENT, | |
1267 | .ops = &clk_branch2_ops, | |
1268 | }, | |
1269 | }, | |
1270 | }; | |
1271 | ||
1272 | static struct clk_branch gcc_sys_noc_ufs_axi_clk = { | |
1273 | .halt_reg = 0x75038, | |
1274 | .clkr = { | |
1275 | .enable_reg = 0x75038, | |
1276 | .enable_mask = BIT(0), | |
1277 | .hw.init = &(struct clk_init_data){ | |
1278 | .name = "gcc_sys_noc_ufs_axi_clk", | |
1279 | .parent_names = (const char *[]){ "ufs_axi_clk_src" }, | |
1280 | .num_parents = 1, | |
1281 | .flags = CLK_SET_RATE_PARENT, | |
1282 | .ops = &clk_branch2_ops, | |
1283 | }, | |
1284 | }, | |
1285 | }; | |
1286 | ||
1287 | static struct clk_branch gcc_periph_noc_usb20_ahb_clk = { | |
1288 | .halt_reg = 0x6010, | |
1289 | .clkr = { | |
1290 | .enable_reg = 0x6010, | |
1291 | .enable_mask = BIT(0), | |
1292 | .hw.init = &(struct clk_init_data){ | |
1293 | .name = "gcc_periph_noc_usb20_ahb_clk", | |
1294 | .parent_names = (const char *[]){ "usb20_master_clk_src" }, | |
1295 | .num_parents = 1, | |
1296 | .flags = CLK_SET_RATE_PARENT, | |
1297 | .ops = &clk_branch2_ops, | |
1298 | }, | |
1299 | }, | |
1300 | }; | |
1301 | ||
1302 | static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { | |
1303 | .halt_reg = 0x9008, | |
1304 | .clkr = { | |
1305 | .enable_reg = 0x9008, | |
1306 | .enable_mask = BIT(0), | |
1307 | .hw.init = &(struct clk_init_data){ | |
1308 | .name = "gcc_mmss_noc_cfg_ahb_clk", | |
1309 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
1310 | .num_parents = 1, | |
1311 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1312 | .ops = &clk_branch2_ops, | |
1313 | }, | |
1314 | }, | |
1315 | }; | |
1316 | ||
1317 | static struct clk_branch gcc_mmss_bimc_gfx_clk = { | |
1318 | .halt_reg = 0x9010, | |
1319 | .clkr = { | |
1320 | .enable_reg = 0x9010, | |
1321 | .enable_mask = BIT(0), | |
1322 | .hw.init = &(struct clk_init_data){ | |
1323 | .name = "gcc_mmss_bimc_gfx_clk", | |
81925c5e | 1324 | .flags = CLK_SET_RATE_PARENT, |
b1e010c0 SB |
1325 | .ops = &clk_branch2_ops, |
1326 | }, | |
1327 | }, | |
1328 | }; | |
1329 | ||
1330 | static struct clk_branch gcc_usb30_master_clk = { | |
1331 | .halt_reg = 0x0f008, | |
1332 | .clkr = { | |
1333 | .enable_reg = 0x0f008, | |
1334 | .enable_mask = BIT(0), | |
1335 | .hw.init = &(struct clk_init_data){ | |
1336 | .name = "gcc_usb30_master_clk", | |
1337 | .parent_names = (const char *[]){ "usb30_master_clk_src" }, | |
1338 | .num_parents = 1, | |
1339 | .flags = CLK_SET_RATE_PARENT, | |
1340 | .ops = &clk_branch2_ops, | |
1341 | }, | |
1342 | }, | |
1343 | }; | |
1344 | ||
1345 | static struct clk_branch gcc_usb30_sleep_clk = { | |
1346 | .halt_reg = 0x0f00c, | |
1347 | .clkr = { | |
1348 | .enable_reg = 0x0f00c, | |
1349 | .enable_mask = BIT(0), | |
1350 | .hw.init = &(struct clk_init_data){ | |
1351 | .name = "gcc_usb30_sleep_clk", | |
1352 | .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, | |
1353 | .num_parents = 1, | |
1354 | .flags = CLK_SET_RATE_PARENT, | |
1355 | .ops = &clk_branch2_ops, | |
1356 | }, | |
1357 | }, | |
1358 | }; | |
1359 | ||
1360 | static struct clk_branch gcc_usb30_mock_utmi_clk = { | |
1361 | .halt_reg = 0x0f010, | |
1362 | .clkr = { | |
1363 | .enable_reg = 0x0f010, | |
1364 | .enable_mask = BIT(0), | |
1365 | .hw.init = &(struct clk_init_data){ | |
1366 | .name = "gcc_usb30_mock_utmi_clk", | |
1367 | .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" }, | |
1368 | .num_parents = 1, | |
1369 | .flags = CLK_SET_RATE_PARENT, | |
1370 | .ops = &clk_branch2_ops, | |
1371 | }, | |
1372 | }, | |
1373 | }; | |
1374 | ||
1375 | static struct clk_branch gcc_usb3_phy_aux_clk = { | |
1376 | .halt_reg = 0x50000, | |
1377 | .clkr = { | |
1378 | .enable_reg = 0x50000, | |
1379 | .enable_mask = BIT(0), | |
1380 | .hw.init = &(struct clk_init_data){ | |
1381 | .name = "gcc_usb3_phy_aux_clk", | |
1382 | .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" }, | |
1383 | .num_parents = 1, | |
1384 | .flags = CLK_SET_RATE_PARENT, | |
1385 | .ops = &clk_branch2_ops, | |
1386 | }, | |
1387 | }, | |
1388 | }; | |
1389 | ||
1390 | static struct clk_branch gcc_usb3_phy_pipe_clk = { | |
1391 | .halt_reg = 0x50004, | |
1392 | .clkr = { | |
1393 | .enable_reg = 0x50004, | |
1394 | .enable_mask = BIT(0), | |
1395 | .hw.init = &(struct clk_init_data){ | |
1396 | .name = "gcc_usb3_phy_pipe_clk", | |
1397 | .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" }, | |
1398 | .num_parents = 1, | |
1399 | .flags = CLK_SET_RATE_PARENT, | |
1400 | .ops = &clk_branch2_ops, | |
1401 | }, | |
1402 | }, | |
1403 | }; | |
1404 | ||
1405 | static struct clk_branch gcc_usb20_master_clk = { | |
1406 | .halt_reg = 0x12004, | |
1407 | .clkr = { | |
1408 | .enable_reg = 0x12004, | |
1409 | .enable_mask = BIT(0), | |
1410 | .hw.init = &(struct clk_init_data){ | |
1411 | .name = "gcc_usb20_master_clk", | |
1412 | .parent_names = (const char *[]){ "usb20_master_clk_src" }, | |
1413 | .num_parents = 1, | |
1414 | .flags = CLK_SET_RATE_PARENT, | |
1415 | .ops = &clk_branch2_ops, | |
1416 | }, | |
1417 | }, | |
1418 | }; | |
1419 | ||
1420 | static struct clk_branch gcc_usb20_sleep_clk = { | |
1421 | .halt_reg = 0x12008, | |
1422 | .clkr = { | |
1423 | .enable_reg = 0x12008, | |
1424 | .enable_mask = BIT(0), | |
1425 | .hw.init = &(struct clk_init_data){ | |
1426 | .name = "gcc_usb20_sleep_clk", | |
1427 | .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, | |
1428 | .num_parents = 1, | |
1429 | .flags = CLK_SET_RATE_PARENT, | |
1430 | .ops = &clk_branch2_ops, | |
1431 | }, | |
1432 | }, | |
1433 | }; | |
1434 | ||
1435 | static struct clk_branch gcc_usb20_mock_utmi_clk = { | |
1436 | .halt_reg = 0x1200c, | |
1437 | .clkr = { | |
1438 | .enable_reg = 0x1200c, | |
1439 | .enable_mask = BIT(0), | |
1440 | .hw.init = &(struct clk_init_data){ | |
1441 | .name = "gcc_usb20_mock_utmi_clk", | |
1442 | .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" }, | |
1443 | .num_parents = 1, | |
1444 | .flags = CLK_SET_RATE_PARENT, | |
1445 | .ops = &clk_branch2_ops, | |
1446 | }, | |
1447 | }, | |
1448 | }; | |
1449 | ||
1450 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { | |
1451 | .halt_reg = 0x6a004, | |
1452 | .clkr = { | |
1453 | .enable_reg = 0x6a004, | |
1454 | .enable_mask = BIT(0), | |
1455 | .hw.init = &(struct clk_init_data){ | |
1456 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", | |
1457 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1458 | .num_parents = 1, | |
1459 | .flags = CLK_SET_RATE_PARENT, | |
1460 | .ops = &clk_branch2_ops, | |
1461 | }, | |
1462 | }, | |
1463 | }; | |
1464 | ||
1465 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
1466 | .halt_reg = 0x13004, | |
1467 | .clkr = { | |
1468 | .enable_reg = 0x13004, | |
1469 | .enable_mask = BIT(0), | |
1470 | .hw.init = &(struct clk_init_data){ | |
1471 | .name = "gcc_sdcc1_apps_clk", | |
1472 | .parent_names = (const char *[]){ "sdcc1_apps_clk_src" }, | |
1473 | .num_parents = 1, | |
1474 | .flags = CLK_SET_RATE_PARENT, | |
1475 | .ops = &clk_branch2_ops, | |
1476 | }, | |
1477 | }, | |
1478 | }; | |
1479 | ||
1480 | static struct clk_branch gcc_sdcc1_ahb_clk = { | |
1481 | .halt_reg = 0x13008, | |
1482 | .clkr = { | |
1483 | .enable_reg = 0x13008, | |
1484 | .enable_mask = BIT(0), | |
1485 | .hw.init = &(struct clk_init_data){ | |
1486 | .name = "gcc_sdcc1_ahb_clk", | |
1487 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1488 | .num_parents = 1, | |
1489 | .flags = CLK_SET_RATE_PARENT, | |
1490 | .ops = &clk_branch2_ops, | |
1491 | }, | |
1492 | }, | |
1493 | }; | |
1494 | ||
1495 | static struct clk_branch gcc_sdcc1_ice_core_clk = { | |
1496 | .halt_reg = 0x13038, | |
1497 | .clkr = { | |
1498 | .enable_reg = 0x13038, | |
1499 | .enable_mask = BIT(0), | |
1500 | .hw.init = &(struct clk_init_data){ | |
1501 | .name = "gcc_sdcc1_ice_core_clk", | |
1502 | .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" }, | |
1503 | .num_parents = 1, | |
1504 | .flags = CLK_SET_RATE_PARENT, | |
1505 | .ops = &clk_branch2_ops, | |
1506 | }, | |
1507 | }, | |
1508 | }; | |
1509 | ||
1510 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
1511 | .halt_reg = 0x14004, | |
1512 | .clkr = { | |
1513 | .enable_reg = 0x14004, | |
1514 | .enable_mask = BIT(0), | |
1515 | .hw.init = &(struct clk_init_data){ | |
1516 | .name = "gcc_sdcc2_apps_clk", | |
1517 | .parent_names = (const char *[]){ "sdcc2_apps_clk_src" }, | |
1518 | .num_parents = 1, | |
1519 | .flags = CLK_SET_RATE_PARENT, | |
1520 | .ops = &clk_branch2_ops, | |
1521 | }, | |
1522 | }, | |
1523 | }; | |
1524 | ||
1525 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
1526 | .halt_reg = 0x14008, | |
1527 | .clkr = { | |
1528 | .enable_reg = 0x14008, | |
1529 | .enable_mask = BIT(0), | |
1530 | .hw.init = &(struct clk_init_data){ | |
1531 | .name = "gcc_sdcc2_ahb_clk", | |
1532 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1533 | .num_parents = 1, | |
1534 | .flags = CLK_SET_RATE_PARENT, | |
1535 | .ops = &clk_branch2_ops, | |
1536 | }, | |
1537 | }, | |
1538 | }; | |
1539 | ||
1540 | static struct clk_branch gcc_sdcc3_apps_clk = { | |
1541 | .halt_reg = 0x15004, | |
1542 | .clkr = { | |
1543 | .enable_reg = 0x15004, | |
1544 | .enable_mask = BIT(0), | |
1545 | .hw.init = &(struct clk_init_data){ | |
1546 | .name = "gcc_sdcc3_apps_clk", | |
1547 | .parent_names = (const char *[]){ "sdcc3_apps_clk_src" }, | |
1548 | .num_parents = 1, | |
1549 | .flags = CLK_SET_RATE_PARENT, | |
1550 | .ops = &clk_branch2_ops, | |
1551 | }, | |
1552 | }, | |
1553 | }; | |
1554 | ||
1555 | static struct clk_branch gcc_sdcc3_ahb_clk = { | |
1556 | .halt_reg = 0x15008, | |
1557 | .clkr = { | |
1558 | .enable_reg = 0x15008, | |
1559 | .enable_mask = BIT(0), | |
1560 | .hw.init = &(struct clk_init_data){ | |
1561 | .name = "gcc_sdcc3_ahb_clk", | |
1562 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1563 | .num_parents = 1, | |
1564 | .flags = CLK_SET_RATE_PARENT, | |
1565 | .ops = &clk_branch2_ops, | |
1566 | }, | |
1567 | }, | |
1568 | }; | |
1569 | ||
1570 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
1571 | .halt_reg = 0x16004, | |
1572 | .clkr = { | |
1573 | .enable_reg = 0x16004, | |
1574 | .enable_mask = BIT(0), | |
1575 | .hw.init = &(struct clk_init_data){ | |
1576 | .name = "gcc_sdcc4_apps_clk", | |
1577 | .parent_names = (const char *[]){ "sdcc4_apps_clk_src" }, | |
1578 | .num_parents = 1, | |
1579 | .flags = CLK_SET_RATE_PARENT, | |
1580 | .ops = &clk_branch2_ops, | |
1581 | }, | |
1582 | }, | |
1583 | }; | |
1584 | ||
1585 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
1586 | .halt_reg = 0x16008, | |
1587 | .clkr = { | |
1588 | .enable_reg = 0x16008, | |
1589 | .enable_mask = BIT(0), | |
1590 | .hw.init = &(struct clk_init_data){ | |
1591 | .name = "gcc_sdcc4_ahb_clk", | |
1592 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1593 | .num_parents = 1, | |
1594 | .flags = CLK_SET_RATE_PARENT, | |
1595 | .ops = &clk_branch2_ops, | |
1596 | }, | |
1597 | }, | |
1598 | }; | |
1599 | ||
1600 | static struct clk_branch gcc_blsp1_ahb_clk = { | |
1601 | .halt_reg = 0x17004, | |
1602 | .halt_check = BRANCH_HALT_VOTED, | |
1603 | .clkr = { | |
1604 | .enable_reg = 0x52004, | |
1605 | .enable_mask = BIT(17), | |
1606 | .hw.init = &(struct clk_init_data){ | |
1607 | .name = "gcc_blsp1_ahb_clk", | |
1608 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1609 | .num_parents = 1, | |
1610 | .flags = CLK_SET_RATE_PARENT, | |
1611 | .ops = &clk_branch2_ops, | |
1612 | }, | |
1613 | }, | |
1614 | }; | |
1615 | ||
1616 | static struct clk_branch gcc_blsp1_sleep_clk = { | |
1617 | .halt_reg = 0x17008, | |
1618 | .halt_check = BRANCH_HALT_VOTED, | |
1619 | .clkr = { | |
1620 | .enable_reg = 0x52004, | |
1621 | .enable_mask = BIT(16), | |
1622 | .hw.init = &(struct clk_init_data){ | |
1623 | .name = "gcc_blsp1_sleep_clk", | |
1624 | .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, | |
1625 | .num_parents = 1, | |
1626 | .flags = CLK_SET_RATE_PARENT, | |
1627 | .ops = &clk_branch2_ops, | |
1628 | }, | |
1629 | }, | |
1630 | }; | |
1631 | ||
1632 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { | |
1633 | .halt_reg = 0x19004, | |
1634 | .clkr = { | |
1635 | .enable_reg = 0x19004, | |
1636 | .enable_mask = BIT(0), | |
1637 | .hw.init = &(struct clk_init_data){ | |
1638 | .name = "gcc_blsp1_qup1_spi_apps_clk", | |
1639 | .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" }, | |
1640 | .num_parents = 1, | |
1641 | .flags = CLK_SET_RATE_PARENT, | |
1642 | .ops = &clk_branch2_ops, | |
1643 | }, | |
1644 | }, | |
1645 | }; | |
1646 | ||
1647 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { | |
1648 | .halt_reg = 0x19008, | |
1649 | .clkr = { | |
1650 | .enable_reg = 0x19008, | |
1651 | .enable_mask = BIT(0), | |
1652 | .hw.init = &(struct clk_init_data){ | |
1653 | .name = "gcc_blsp1_qup1_i2c_apps_clk", | |
1654 | .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" }, | |
1655 | .num_parents = 1, | |
1656 | .flags = CLK_SET_RATE_PARENT, | |
1657 | .ops = &clk_branch2_ops, | |
1658 | }, | |
1659 | }, | |
1660 | }; | |
1661 | ||
1662 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { | |
1663 | .halt_reg = 0x1a004, | |
1664 | .clkr = { | |
1665 | .enable_reg = 0x1a004, | |
1666 | .enable_mask = BIT(0), | |
1667 | .hw.init = &(struct clk_init_data){ | |
1668 | .name = "gcc_blsp1_uart1_apps_clk", | |
1669 | .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" }, | |
1670 | .num_parents = 1, | |
1671 | .flags = CLK_SET_RATE_PARENT, | |
1672 | .ops = &clk_branch2_ops, | |
1673 | }, | |
1674 | }, | |
1675 | }; | |
1676 | ||
1677 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { | |
1678 | .halt_reg = 0x1b004, | |
1679 | .clkr = { | |
1680 | .enable_reg = 0x1b004, | |
1681 | .enable_mask = BIT(0), | |
1682 | .hw.init = &(struct clk_init_data){ | |
1683 | .name = "gcc_blsp1_qup2_spi_apps_clk", | |
1684 | .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" }, | |
1685 | .num_parents = 1, | |
1686 | .flags = CLK_SET_RATE_PARENT, | |
1687 | .ops = &clk_branch2_ops, | |
1688 | }, | |
1689 | }, | |
1690 | }; | |
1691 | ||
1692 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { | |
1693 | .halt_reg = 0x1b008, | |
1694 | .clkr = { | |
1695 | .enable_reg = 0x1b008, | |
1696 | .enable_mask = BIT(0), | |
1697 | .hw.init = &(struct clk_init_data){ | |
1698 | .name = "gcc_blsp1_qup2_i2c_apps_clk", | |
1699 | .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" }, | |
1700 | .num_parents = 1, | |
1701 | .flags = CLK_SET_RATE_PARENT, | |
1702 | .ops = &clk_branch2_ops, | |
1703 | }, | |
1704 | }, | |
1705 | }; | |
1706 | ||
1707 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { | |
1708 | .halt_reg = 0x1c004, | |
1709 | .clkr = { | |
1710 | .enable_reg = 0x1c004, | |
1711 | .enable_mask = BIT(0), | |
1712 | .hw.init = &(struct clk_init_data){ | |
1713 | .name = "gcc_blsp1_uart2_apps_clk", | |
1714 | .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" }, | |
1715 | .num_parents = 1, | |
1716 | .flags = CLK_SET_RATE_PARENT, | |
1717 | .ops = &clk_branch2_ops, | |
1718 | }, | |
1719 | }, | |
1720 | }; | |
1721 | ||
1722 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { | |
1723 | .halt_reg = 0x1d004, | |
1724 | .clkr = { | |
1725 | .enable_reg = 0x1d004, | |
1726 | .enable_mask = BIT(0), | |
1727 | .hw.init = &(struct clk_init_data){ | |
1728 | .name = "gcc_blsp1_qup3_spi_apps_clk", | |
1729 | .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" }, | |
1730 | .num_parents = 1, | |
1731 | .flags = CLK_SET_RATE_PARENT, | |
1732 | .ops = &clk_branch2_ops, | |
1733 | }, | |
1734 | }, | |
1735 | }; | |
1736 | ||
1737 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { | |
1738 | .halt_reg = 0x1d008, | |
1739 | .clkr = { | |
1740 | .enable_reg = 0x1d008, | |
1741 | .enable_mask = BIT(0), | |
1742 | .hw.init = &(struct clk_init_data){ | |
1743 | .name = "gcc_blsp1_qup3_i2c_apps_clk", | |
1744 | .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" }, | |
1745 | .num_parents = 1, | |
1746 | .flags = CLK_SET_RATE_PARENT, | |
1747 | .ops = &clk_branch2_ops, | |
1748 | }, | |
1749 | }, | |
1750 | }; | |
1751 | ||
1752 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { | |
1753 | .halt_reg = 0x1e004, | |
1754 | .clkr = { | |
1755 | .enable_reg = 0x1e004, | |
1756 | .enable_mask = BIT(0), | |
1757 | .hw.init = &(struct clk_init_data){ | |
1758 | .name = "gcc_blsp1_uart3_apps_clk", | |
1759 | .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" }, | |
1760 | .num_parents = 1, | |
1761 | .flags = CLK_SET_RATE_PARENT, | |
1762 | .ops = &clk_branch2_ops, | |
1763 | }, | |
1764 | }, | |
1765 | }; | |
1766 | ||
1767 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { | |
1768 | .halt_reg = 0x1f004, | |
1769 | .clkr = { | |
1770 | .enable_reg = 0x1f004, | |
1771 | .enable_mask = BIT(0), | |
1772 | .hw.init = &(struct clk_init_data){ | |
1773 | .name = "gcc_blsp1_qup4_spi_apps_clk", | |
1774 | .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" }, | |
1775 | .num_parents = 1, | |
1776 | .flags = CLK_SET_RATE_PARENT, | |
1777 | .ops = &clk_branch2_ops, | |
1778 | }, | |
1779 | }, | |
1780 | }; | |
1781 | ||
1782 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { | |
1783 | .halt_reg = 0x1f008, | |
1784 | .clkr = { | |
1785 | .enable_reg = 0x1f008, | |
1786 | .enable_mask = BIT(0), | |
1787 | .hw.init = &(struct clk_init_data){ | |
1788 | .name = "gcc_blsp1_qup4_i2c_apps_clk", | |
1789 | .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" }, | |
1790 | .num_parents = 1, | |
1791 | .flags = CLK_SET_RATE_PARENT, | |
1792 | .ops = &clk_branch2_ops, | |
1793 | }, | |
1794 | }, | |
1795 | }; | |
1796 | ||
1797 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { | |
1798 | .halt_reg = 0x20004, | |
1799 | .clkr = { | |
1800 | .enable_reg = 0x20004, | |
1801 | .enable_mask = BIT(0), | |
1802 | .hw.init = &(struct clk_init_data){ | |
1803 | .name = "gcc_blsp1_uart4_apps_clk", | |
1804 | .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" }, | |
1805 | .num_parents = 1, | |
1806 | .flags = CLK_SET_RATE_PARENT, | |
1807 | .ops = &clk_branch2_ops, | |
1808 | }, | |
1809 | }, | |
1810 | }; | |
1811 | ||
1812 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { | |
1813 | .halt_reg = 0x21004, | |
1814 | .clkr = { | |
1815 | .enable_reg = 0x21004, | |
1816 | .enable_mask = BIT(0), | |
1817 | .hw.init = &(struct clk_init_data){ | |
1818 | .name = "gcc_blsp1_qup5_spi_apps_clk", | |
1819 | .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" }, | |
1820 | .num_parents = 1, | |
1821 | .flags = CLK_SET_RATE_PARENT, | |
1822 | .ops = &clk_branch2_ops, | |
1823 | }, | |
1824 | }, | |
1825 | }; | |
1826 | ||
1827 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { | |
1828 | .halt_reg = 0x21008, | |
1829 | .clkr = { | |
1830 | .enable_reg = 0x21008, | |
1831 | .enable_mask = BIT(0), | |
1832 | .hw.init = &(struct clk_init_data){ | |
1833 | .name = "gcc_blsp1_qup5_i2c_apps_clk", | |
1834 | .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" }, | |
1835 | .num_parents = 1, | |
1836 | .flags = CLK_SET_RATE_PARENT, | |
1837 | .ops = &clk_branch2_ops, | |
1838 | }, | |
1839 | }, | |
1840 | }; | |
1841 | ||
1842 | static struct clk_branch gcc_blsp1_uart5_apps_clk = { | |
1843 | .halt_reg = 0x22004, | |
1844 | .clkr = { | |
1845 | .enable_reg = 0x22004, | |
1846 | .enable_mask = BIT(0), | |
1847 | .hw.init = &(struct clk_init_data){ | |
1848 | .name = "gcc_blsp1_uart5_apps_clk", | |
1849 | .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" }, | |
1850 | .num_parents = 1, | |
1851 | .flags = CLK_SET_RATE_PARENT, | |
1852 | .ops = &clk_branch2_ops, | |
1853 | }, | |
1854 | }, | |
1855 | }; | |
1856 | ||
1857 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { | |
1858 | .halt_reg = 0x23004, | |
1859 | .clkr = { | |
1860 | .enable_reg = 0x23004, | |
1861 | .enable_mask = BIT(0), | |
1862 | .hw.init = &(struct clk_init_data){ | |
1863 | .name = "gcc_blsp1_qup6_spi_apps_clk", | |
1864 | .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" }, | |
1865 | .num_parents = 1, | |
1866 | .flags = CLK_SET_RATE_PARENT, | |
1867 | .ops = &clk_branch2_ops, | |
1868 | }, | |
1869 | }, | |
1870 | }; | |
1871 | ||
1872 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { | |
1873 | .halt_reg = 0x23008, | |
1874 | .clkr = { | |
1875 | .enable_reg = 0x23008, | |
1876 | .enable_mask = BIT(0), | |
1877 | .hw.init = &(struct clk_init_data){ | |
1878 | .name = "gcc_blsp1_qup6_i2c_apps_clk", | |
1879 | .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" }, | |
1880 | .num_parents = 1, | |
1881 | .flags = CLK_SET_RATE_PARENT, | |
1882 | .ops = &clk_branch2_ops, | |
1883 | }, | |
1884 | }, | |
1885 | }; | |
1886 | ||
1887 | static struct clk_branch gcc_blsp1_uart6_apps_clk = { | |
1888 | .halt_reg = 0x24004, | |
1889 | .clkr = { | |
1890 | .enable_reg = 0x24004, | |
1891 | .enable_mask = BIT(0), | |
1892 | .hw.init = &(struct clk_init_data){ | |
1893 | .name = "gcc_blsp1_uart6_apps_clk", | |
1894 | .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" }, | |
1895 | .num_parents = 1, | |
1896 | .flags = CLK_SET_RATE_PARENT, | |
1897 | .ops = &clk_branch2_ops, | |
1898 | }, | |
1899 | }, | |
1900 | }; | |
1901 | ||
1902 | static struct clk_branch gcc_blsp2_ahb_clk = { | |
1903 | .halt_reg = 0x25004, | |
1904 | .halt_check = BRANCH_HALT_VOTED, | |
1905 | .clkr = { | |
1906 | .enable_reg = 0x52004, | |
1907 | .enable_mask = BIT(15), | |
1908 | .hw.init = &(struct clk_init_data){ | |
1909 | .name = "gcc_blsp2_ahb_clk", | |
1910 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
1911 | .num_parents = 1, | |
1912 | .flags = CLK_SET_RATE_PARENT, | |
1913 | .ops = &clk_branch2_ops, | |
1914 | }, | |
1915 | }, | |
1916 | }; | |
1917 | ||
1918 | static struct clk_branch gcc_blsp2_sleep_clk = { | |
1919 | .halt_reg = 0x25008, | |
1920 | .halt_check = BRANCH_HALT_VOTED, | |
1921 | .clkr = { | |
1922 | .enable_reg = 0x52004, | |
1923 | .enable_mask = BIT(14), | |
1924 | .hw.init = &(struct clk_init_data){ | |
1925 | .name = "gcc_blsp2_sleep_clk", | |
1926 | .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, | |
1927 | .num_parents = 1, | |
1928 | .flags = CLK_SET_RATE_PARENT, | |
1929 | .ops = &clk_branch2_ops, | |
1930 | }, | |
1931 | }, | |
1932 | }; | |
1933 | ||
1934 | static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { | |
1935 | .halt_reg = 0x26004, | |
1936 | .clkr = { | |
1937 | .enable_reg = 0x26004, | |
1938 | .enable_mask = BIT(0), | |
1939 | .hw.init = &(struct clk_init_data){ | |
1940 | .name = "gcc_blsp2_qup1_spi_apps_clk", | |
1941 | .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" }, | |
1942 | .num_parents = 1, | |
1943 | .flags = CLK_SET_RATE_PARENT, | |
1944 | .ops = &clk_branch2_ops, | |
1945 | }, | |
1946 | }, | |
1947 | }; | |
1948 | ||
1949 | static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { | |
1950 | .halt_reg = 0x26008, | |
1951 | .clkr = { | |
1952 | .enable_reg = 0x26008, | |
1953 | .enable_mask = BIT(0), | |
1954 | .hw.init = &(struct clk_init_data){ | |
1955 | .name = "gcc_blsp2_qup1_i2c_apps_clk", | |
1956 | .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" }, | |
1957 | .num_parents = 1, | |
1958 | .flags = CLK_SET_RATE_PARENT, | |
1959 | .ops = &clk_branch2_ops, | |
1960 | }, | |
1961 | }, | |
1962 | }; | |
1963 | ||
1964 | static struct clk_branch gcc_blsp2_uart1_apps_clk = { | |
1965 | .halt_reg = 0x27004, | |
1966 | .clkr = { | |
1967 | .enable_reg = 0x27004, | |
1968 | .enable_mask = BIT(0), | |
1969 | .hw.init = &(struct clk_init_data){ | |
1970 | .name = "gcc_blsp2_uart1_apps_clk", | |
1971 | .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" }, | |
1972 | .num_parents = 1, | |
1973 | .flags = CLK_SET_RATE_PARENT, | |
1974 | .ops = &clk_branch2_ops, | |
1975 | }, | |
1976 | }, | |
1977 | }; | |
1978 | ||
1979 | static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { | |
1980 | .halt_reg = 0x28004, | |
1981 | .clkr = { | |
1982 | .enable_reg = 0x28004, | |
1983 | .enable_mask = BIT(0), | |
1984 | .hw.init = &(struct clk_init_data){ | |
1985 | .name = "gcc_blsp2_qup2_spi_apps_clk", | |
1986 | .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" }, | |
1987 | .num_parents = 1, | |
1988 | .flags = CLK_SET_RATE_PARENT, | |
1989 | .ops = &clk_branch2_ops, | |
1990 | }, | |
1991 | }, | |
1992 | }; | |
1993 | ||
1994 | static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { | |
1995 | .halt_reg = 0x28008, | |
1996 | .clkr = { | |
1997 | .enable_reg = 0x28008, | |
1998 | .enable_mask = BIT(0), | |
1999 | .hw.init = &(struct clk_init_data){ | |
2000 | .name = "gcc_blsp2_qup2_i2c_apps_clk", | |
2001 | .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" }, | |
2002 | .num_parents = 1, | |
2003 | .flags = CLK_SET_RATE_PARENT, | |
2004 | .ops = &clk_branch2_ops, | |
2005 | }, | |
2006 | }, | |
2007 | }; | |
2008 | ||
2009 | static struct clk_branch gcc_blsp2_uart2_apps_clk = { | |
2010 | .halt_reg = 0x29004, | |
2011 | .clkr = { | |
2012 | .enable_reg = 0x29004, | |
2013 | .enable_mask = BIT(0), | |
2014 | .hw.init = &(struct clk_init_data){ | |
2015 | .name = "gcc_blsp2_uart2_apps_clk", | |
2016 | .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" }, | |
2017 | .num_parents = 1, | |
2018 | .flags = CLK_SET_RATE_PARENT, | |
2019 | .ops = &clk_branch2_ops, | |
2020 | }, | |
2021 | }, | |
2022 | }; | |
2023 | ||
2024 | static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { | |
2025 | .halt_reg = 0x2a004, | |
2026 | .clkr = { | |
2027 | .enable_reg = 0x2a004, | |
2028 | .enable_mask = BIT(0), | |
2029 | .hw.init = &(struct clk_init_data){ | |
2030 | .name = "gcc_blsp2_qup3_spi_apps_clk", | |
2031 | .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" }, | |
2032 | .num_parents = 1, | |
2033 | .flags = CLK_SET_RATE_PARENT, | |
2034 | .ops = &clk_branch2_ops, | |
2035 | }, | |
2036 | }, | |
2037 | }; | |
2038 | ||
2039 | static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { | |
2040 | .halt_reg = 0x2a008, | |
2041 | .clkr = { | |
2042 | .enable_reg = 0x2a008, | |
2043 | .enable_mask = BIT(0), | |
2044 | .hw.init = &(struct clk_init_data){ | |
2045 | .name = "gcc_blsp2_qup3_i2c_apps_clk", | |
2046 | .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" }, | |
2047 | .num_parents = 1, | |
2048 | .flags = CLK_SET_RATE_PARENT, | |
2049 | .ops = &clk_branch2_ops, | |
2050 | }, | |
2051 | }, | |
2052 | }; | |
2053 | ||
2054 | static struct clk_branch gcc_blsp2_uart3_apps_clk = { | |
2055 | .halt_reg = 0x2b004, | |
2056 | .clkr = { | |
2057 | .enable_reg = 0x2b004, | |
2058 | .enable_mask = BIT(0), | |
2059 | .hw.init = &(struct clk_init_data){ | |
2060 | .name = "gcc_blsp2_uart3_apps_clk", | |
2061 | .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" }, | |
2062 | .num_parents = 1, | |
2063 | .flags = CLK_SET_RATE_PARENT, | |
2064 | .ops = &clk_branch2_ops, | |
2065 | }, | |
2066 | }, | |
2067 | }; | |
2068 | ||
2069 | static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { | |
2070 | .halt_reg = 0x2c004, | |
2071 | .clkr = { | |
2072 | .enable_reg = 0x2c004, | |
2073 | .enable_mask = BIT(0), | |
2074 | .hw.init = &(struct clk_init_data){ | |
2075 | .name = "gcc_blsp2_qup4_spi_apps_clk", | |
2076 | .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" }, | |
2077 | .num_parents = 1, | |
2078 | .flags = CLK_SET_RATE_PARENT, | |
2079 | .ops = &clk_branch2_ops, | |
2080 | }, | |
2081 | }, | |
2082 | }; | |
2083 | ||
2084 | static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { | |
2085 | .halt_reg = 0x2c008, | |
2086 | .clkr = { | |
2087 | .enable_reg = 0x2c008, | |
2088 | .enable_mask = BIT(0), | |
2089 | .hw.init = &(struct clk_init_data){ | |
2090 | .name = "gcc_blsp2_qup4_i2c_apps_clk", | |
2091 | .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" }, | |
2092 | .num_parents = 1, | |
2093 | .flags = CLK_SET_RATE_PARENT, | |
2094 | .ops = &clk_branch2_ops, | |
2095 | }, | |
2096 | }, | |
2097 | }; | |
2098 | ||
2099 | static struct clk_branch gcc_blsp2_uart4_apps_clk = { | |
2100 | .halt_reg = 0x2d004, | |
2101 | .clkr = { | |
2102 | .enable_reg = 0x2d004, | |
2103 | .enable_mask = BIT(0), | |
2104 | .hw.init = &(struct clk_init_data){ | |
2105 | .name = "gcc_blsp2_uart4_apps_clk", | |
2106 | .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" }, | |
2107 | .num_parents = 1, | |
2108 | .flags = CLK_SET_RATE_PARENT, | |
2109 | .ops = &clk_branch2_ops, | |
2110 | }, | |
2111 | }, | |
2112 | }; | |
2113 | ||
2114 | static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { | |
2115 | .halt_reg = 0x2e004, | |
2116 | .clkr = { | |
2117 | .enable_reg = 0x2e004, | |
2118 | .enable_mask = BIT(0), | |
2119 | .hw.init = &(struct clk_init_data){ | |
2120 | .name = "gcc_blsp2_qup5_spi_apps_clk", | |
2121 | .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" }, | |
2122 | .num_parents = 1, | |
2123 | .flags = CLK_SET_RATE_PARENT, | |
2124 | .ops = &clk_branch2_ops, | |
2125 | }, | |
2126 | }, | |
2127 | }; | |
2128 | ||
2129 | static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { | |
2130 | .halt_reg = 0x2e008, | |
2131 | .clkr = { | |
2132 | .enable_reg = 0x2e008, | |
2133 | .enable_mask = BIT(0), | |
2134 | .hw.init = &(struct clk_init_data){ | |
2135 | .name = "gcc_blsp2_qup5_i2c_apps_clk", | |
2136 | .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" }, | |
2137 | .num_parents = 1, | |
2138 | .flags = CLK_SET_RATE_PARENT, | |
2139 | .ops = &clk_branch2_ops, | |
2140 | }, | |
2141 | }, | |
2142 | }; | |
2143 | ||
2144 | static struct clk_branch gcc_blsp2_uart5_apps_clk = { | |
2145 | .halt_reg = 0x2f004, | |
2146 | .clkr = { | |
2147 | .enable_reg = 0x2f004, | |
2148 | .enable_mask = BIT(0), | |
2149 | .hw.init = &(struct clk_init_data){ | |
2150 | .name = "gcc_blsp2_uart5_apps_clk", | |
2151 | .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" }, | |
2152 | .num_parents = 1, | |
2153 | .flags = CLK_SET_RATE_PARENT, | |
2154 | .ops = &clk_branch2_ops, | |
2155 | }, | |
2156 | }, | |
2157 | }; | |
2158 | ||
2159 | static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { | |
2160 | .halt_reg = 0x30004, | |
2161 | .clkr = { | |
2162 | .enable_reg = 0x30004, | |
2163 | .enable_mask = BIT(0), | |
2164 | .hw.init = &(struct clk_init_data){ | |
2165 | .name = "gcc_blsp2_qup6_spi_apps_clk", | |
2166 | .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" }, | |
2167 | .num_parents = 1, | |
2168 | .flags = CLK_SET_RATE_PARENT, | |
2169 | .ops = &clk_branch2_ops, | |
2170 | }, | |
2171 | }, | |
2172 | }; | |
2173 | ||
2174 | static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { | |
2175 | .halt_reg = 0x30008, | |
2176 | .clkr = { | |
2177 | .enable_reg = 0x30008, | |
2178 | .enable_mask = BIT(0), | |
2179 | .hw.init = &(struct clk_init_data){ | |
2180 | .name = "gcc_blsp2_qup6_i2c_apps_clk", | |
2181 | .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" }, | |
2182 | .num_parents = 1, | |
2183 | .flags = CLK_SET_RATE_PARENT, | |
2184 | .ops = &clk_branch2_ops, | |
2185 | }, | |
2186 | }, | |
2187 | }; | |
2188 | ||
2189 | static struct clk_branch gcc_blsp2_uart6_apps_clk = { | |
2190 | .halt_reg = 0x31004, | |
2191 | .clkr = { | |
2192 | .enable_reg = 0x31004, | |
2193 | .enable_mask = BIT(0), | |
2194 | .hw.init = &(struct clk_init_data){ | |
2195 | .name = "gcc_blsp2_uart6_apps_clk", | |
2196 | .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" }, | |
2197 | .num_parents = 1, | |
2198 | .flags = CLK_SET_RATE_PARENT, | |
2199 | .ops = &clk_branch2_ops, | |
2200 | }, | |
2201 | }, | |
2202 | }; | |
2203 | ||
2204 | static struct clk_branch gcc_pdm_ahb_clk = { | |
2205 | .halt_reg = 0x33004, | |
2206 | .clkr = { | |
2207 | .enable_reg = 0x33004, | |
2208 | .enable_mask = BIT(0), | |
2209 | .hw.init = &(struct clk_init_data){ | |
2210 | .name = "gcc_pdm_ahb_clk", | |
2211 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
2212 | .num_parents = 1, | |
2213 | .flags = CLK_SET_RATE_PARENT, | |
2214 | .ops = &clk_branch2_ops, | |
2215 | }, | |
2216 | }, | |
2217 | }; | |
2218 | ||
2219 | static struct clk_branch gcc_pdm2_clk = { | |
2220 | .halt_reg = 0x3300c, | |
2221 | .clkr = { | |
2222 | .enable_reg = 0x3300c, | |
2223 | .enable_mask = BIT(0), | |
2224 | .hw.init = &(struct clk_init_data){ | |
2225 | .name = "gcc_pdm2_clk", | |
2226 | .parent_names = (const char *[]){ "pdm2_clk_src" }, | |
2227 | .num_parents = 1, | |
2228 | .flags = CLK_SET_RATE_PARENT, | |
2229 | .ops = &clk_branch2_ops, | |
2230 | }, | |
2231 | }, | |
2232 | }; | |
2233 | ||
2234 | static struct clk_branch gcc_prng_ahb_clk = { | |
2235 | .halt_reg = 0x34004, | |
2236 | .halt_check = BRANCH_HALT_VOTED, | |
2237 | .clkr = { | |
2238 | .enable_reg = 0x52004, | |
2239 | .enable_mask = BIT(13), | |
2240 | .hw.init = &(struct clk_init_data){ | |
2241 | .name = "gcc_prng_ahb_clk", | |
2242 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2243 | .num_parents = 1, | |
2244 | .flags = CLK_SET_RATE_PARENT, | |
2245 | .ops = &clk_branch2_ops, | |
2246 | }, | |
2247 | }, | |
2248 | }; | |
2249 | ||
2250 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2251 | .halt_reg = 0x36004, | |
2252 | .clkr = { | |
2253 | .enable_reg = 0x36004, | |
2254 | .enable_mask = BIT(0), | |
2255 | .hw.init = &(struct clk_init_data){ | |
2256 | .name = "gcc_tsif_ahb_clk", | |
2257 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
2258 | .num_parents = 1, | |
2259 | .flags = CLK_SET_RATE_PARENT, | |
2260 | .ops = &clk_branch2_ops, | |
2261 | }, | |
2262 | }, | |
2263 | }; | |
2264 | ||
2265 | static struct clk_branch gcc_tsif_ref_clk = { | |
2266 | .halt_reg = 0x36008, | |
2267 | .clkr = { | |
2268 | .enable_reg = 0x36008, | |
2269 | .enable_mask = BIT(0), | |
2270 | .hw.init = &(struct clk_init_data){ | |
2271 | .name = "gcc_tsif_ref_clk", | |
2272 | .parent_names = (const char *[]){ "tsif_ref_clk_src" }, | |
2273 | .num_parents = 1, | |
2274 | .flags = CLK_SET_RATE_PARENT, | |
2275 | .ops = &clk_branch2_ops, | |
2276 | }, | |
2277 | }, | |
2278 | }; | |
2279 | ||
2280 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { | |
2281 | .halt_reg = 0x3600c, | |
2282 | .clkr = { | |
2283 | .enable_reg = 0x3600c, | |
2284 | .enable_mask = BIT(0), | |
2285 | .hw.init = &(struct clk_init_data){ | |
2286 | .name = "gcc_tsif_inactivity_timers_clk", | |
2287 | .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, | |
2288 | .num_parents = 1, | |
2289 | .flags = CLK_SET_RATE_PARENT, | |
2290 | .ops = &clk_branch2_ops, | |
2291 | }, | |
2292 | }, | |
2293 | }; | |
2294 | ||
2295 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
2296 | .halt_reg = 0x38004, | |
2297 | .halt_check = BRANCH_HALT_VOTED, | |
2298 | .clkr = { | |
2299 | .enable_reg = 0x52004, | |
2300 | .enable_mask = BIT(10), | |
2301 | .hw.init = &(struct clk_init_data){ | |
2302 | .name = "gcc_boot_rom_ahb_clk", | |
2303 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2304 | .num_parents = 1, | |
2305 | .flags = CLK_SET_RATE_PARENT, | |
2306 | .ops = &clk_branch2_ops, | |
2307 | }, | |
2308 | }, | |
2309 | }; | |
2310 | ||
2311 | static struct clk_branch gcc_bimc_gfx_clk = { | |
2312 | .halt_reg = 0x46018, | |
2313 | .clkr = { | |
2314 | .enable_reg = 0x46018, | |
2315 | .enable_mask = BIT(0), | |
2316 | .hw.init = &(struct clk_init_data){ | |
2317 | .name = "gcc_bimc_gfx_clk", | |
81925c5e | 2318 | .flags = CLK_SET_RATE_PARENT, |
b1e010c0 SB |
2319 | .ops = &clk_branch2_ops, |
2320 | }, | |
2321 | }, | |
2322 | }; | |
2323 | ||
2324 | static struct clk_branch gcc_hmss_rbcpr_clk = { | |
2325 | .halt_reg = 0x4800c, | |
2326 | .clkr = { | |
2327 | .enable_reg = 0x4800c, | |
2328 | .enable_mask = BIT(0), | |
2329 | .hw.init = &(struct clk_init_data){ | |
2330 | .name = "gcc_hmss_rbcpr_clk", | |
2331 | .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" }, | |
2332 | .num_parents = 1, | |
2333 | .flags = CLK_SET_RATE_PARENT, | |
2334 | .ops = &clk_branch2_ops, | |
2335 | }, | |
2336 | }, | |
2337 | }; | |
2338 | ||
2339 | static struct clk_branch gcc_gp1_clk = { | |
2340 | .halt_reg = 0x64000, | |
2341 | .clkr = { | |
2342 | .enable_reg = 0x64000, | |
2343 | .enable_mask = BIT(0), | |
2344 | .hw.init = &(struct clk_init_data){ | |
2345 | .name = "gcc_gp1_clk", | |
2346 | .parent_names = (const char *[]){ "gp1_clk_src" }, | |
2347 | .num_parents = 1, | |
2348 | .flags = CLK_SET_RATE_PARENT, | |
2349 | .ops = &clk_branch2_ops, | |
2350 | }, | |
2351 | }, | |
2352 | }; | |
2353 | ||
2354 | static struct clk_branch gcc_gp2_clk = { | |
2355 | .halt_reg = 0x65000, | |
2356 | .clkr = { | |
2357 | .enable_reg = 0x65000, | |
2358 | .enable_mask = BIT(0), | |
2359 | .hw.init = &(struct clk_init_data){ | |
2360 | .name = "gcc_gp2_clk", | |
2361 | .parent_names = (const char *[]){ "gp2_clk_src" }, | |
2362 | .num_parents = 1, | |
2363 | .flags = CLK_SET_RATE_PARENT, | |
2364 | .ops = &clk_branch2_ops, | |
2365 | }, | |
2366 | }, | |
2367 | }; | |
2368 | ||
2369 | static struct clk_branch gcc_gp3_clk = { | |
2370 | .halt_reg = 0x66000, | |
2371 | .clkr = { | |
2372 | .enable_reg = 0x66000, | |
2373 | .enable_mask = BIT(0), | |
2374 | .hw.init = &(struct clk_init_data){ | |
2375 | .name = "gcc_gp3_clk", | |
2376 | .parent_names = (const char *[]){ "gp3_clk_src" }, | |
2377 | .num_parents = 1, | |
2378 | .flags = CLK_SET_RATE_PARENT, | |
2379 | .ops = &clk_branch2_ops, | |
2380 | }, | |
2381 | }, | |
2382 | }; | |
2383 | ||
2384 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
2385 | .halt_reg = 0x6b008, | |
2386 | .clkr = { | |
2387 | .enable_reg = 0x6b008, | |
2388 | .enable_mask = BIT(0), | |
2389 | .hw.init = &(struct clk_init_data){ | |
2390 | .name = "gcc_pcie_0_slv_axi_clk", | |
2391 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2392 | .num_parents = 1, | |
2393 | .flags = CLK_SET_RATE_PARENT, | |
2394 | .ops = &clk_branch2_ops, | |
2395 | }, | |
2396 | }, | |
2397 | }; | |
2398 | ||
2399 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
2400 | .halt_reg = 0x6b00c, | |
2401 | .clkr = { | |
2402 | .enable_reg = 0x6b00c, | |
2403 | .enable_mask = BIT(0), | |
2404 | .hw.init = &(struct clk_init_data){ | |
2405 | .name = "gcc_pcie_0_mstr_axi_clk", | |
2406 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2407 | .num_parents = 1, | |
2408 | .flags = CLK_SET_RATE_PARENT, | |
2409 | .ops = &clk_branch2_ops, | |
2410 | }, | |
2411 | }, | |
2412 | }; | |
2413 | ||
2414 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
2415 | .halt_reg = 0x6b010, | |
2416 | .clkr = { | |
2417 | .enable_reg = 0x6b010, | |
2418 | .enable_mask = BIT(0), | |
2419 | .hw.init = &(struct clk_init_data){ | |
2420 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
2421 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2422 | .num_parents = 1, | |
2423 | .flags = CLK_SET_RATE_PARENT, | |
2424 | .ops = &clk_branch2_ops, | |
2425 | }, | |
2426 | }, | |
2427 | }; | |
2428 | ||
2429 | static struct clk_branch gcc_pcie_0_aux_clk = { | |
2430 | .halt_reg = 0x6b014, | |
2431 | .clkr = { | |
2432 | .enable_reg = 0x6b014, | |
2433 | .enable_mask = BIT(0), | |
2434 | .hw.init = &(struct clk_init_data){ | |
2435 | .name = "gcc_pcie_0_aux_clk", | |
2436 | .parent_names = (const char *[]){ "pcie_aux_clk_src" }, | |
2437 | .num_parents = 1, | |
2438 | .flags = CLK_SET_RATE_PARENT, | |
2439 | .ops = &clk_branch2_ops, | |
2440 | }, | |
2441 | }, | |
2442 | }; | |
2443 | ||
2444 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
2445 | .halt_reg = 0x6b018, | |
2446 | .clkr = { | |
2447 | .enable_reg = 0x6b018, | |
2448 | .enable_mask = BIT(0), | |
2449 | .hw.init = &(struct clk_init_data){ | |
2450 | .name = "gcc_pcie_0_pipe_clk", | |
2451 | .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" }, | |
2452 | .num_parents = 1, | |
2453 | .flags = CLK_SET_RATE_PARENT, | |
2454 | .ops = &clk_branch2_ops, | |
2455 | }, | |
2456 | }, | |
2457 | }; | |
2458 | ||
2459 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { | |
2460 | .halt_reg = 0x6d008, | |
2461 | .clkr = { | |
2462 | .enable_reg = 0x6d008, | |
2463 | .enable_mask = BIT(0), | |
2464 | .hw.init = &(struct clk_init_data){ | |
2465 | .name = "gcc_pcie_1_slv_axi_clk", | |
2466 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2467 | .num_parents = 1, | |
2468 | .flags = CLK_SET_RATE_PARENT, | |
2469 | .ops = &clk_branch2_ops, | |
2470 | }, | |
2471 | }, | |
2472 | }; | |
2473 | ||
2474 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { | |
2475 | .halt_reg = 0x6d00c, | |
2476 | .clkr = { | |
2477 | .enable_reg = 0x6d00c, | |
2478 | .enable_mask = BIT(0), | |
2479 | .hw.init = &(struct clk_init_data){ | |
2480 | .name = "gcc_pcie_1_mstr_axi_clk", | |
2481 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2482 | .num_parents = 1, | |
2483 | .flags = CLK_SET_RATE_PARENT, | |
2484 | .ops = &clk_branch2_ops, | |
2485 | }, | |
2486 | }, | |
2487 | }; | |
2488 | ||
2489 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { | |
2490 | .halt_reg = 0x6d010, | |
2491 | .clkr = { | |
2492 | .enable_reg = 0x6d010, | |
2493 | .enable_mask = BIT(0), | |
2494 | .hw.init = &(struct clk_init_data){ | |
2495 | .name = "gcc_pcie_1_cfg_ahb_clk", | |
2496 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2497 | .num_parents = 1, | |
2498 | .flags = CLK_SET_RATE_PARENT, | |
2499 | .ops = &clk_branch2_ops, | |
2500 | }, | |
2501 | }, | |
2502 | }; | |
2503 | ||
2504 | static struct clk_branch gcc_pcie_1_aux_clk = { | |
2505 | .halt_reg = 0x6d014, | |
2506 | .clkr = { | |
2507 | .enable_reg = 0x6d014, | |
2508 | .enable_mask = BIT(0), | |
2509 | .hw.init = &(struct clk_init_data){ | |
2510 | .name = "gcc_pcie_1_aux_clk", | |
2511 | .parent_names = (const char *[]){ "pcie_aux_clk_src" }, | |
2512 | .num_parents = 1, | |
2513 | .flags = CLK_SET_RATE_PARENT, | |
2514 | .ops = &clk_branch2_ops, | |
2515 | }, | |
2516 | }, | |
2517 | }; | |
2518 | ||
2519 | static struct clk_branch gcc_pcie_1_pipe_clk = { | |
2520 | .halt_reg = 0x6d018, | |
2521 | .clkr = { | |
2522 | .enable_reg = 0x6d018, | |
2523 | .enable_mask = BIT(0), | |
2524 | .hw.init = &(struct clk_init_data){ | |
2525 | .name = "gcc_pcie_1_pipe_clk", | |
2526 | .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" }, | |
2527 | .num_parents = 1, | |
2528 | .flags = CLK_SET_RATE_PARENT, | |
2529 | .ops = &clk_branch2_ops, | |
2530 | }, | |
2531 | }, | |
2532 | }; | |
2533 | ||
2534 | static struct clk_branch gcc_pcie_2_slv_axi_clk = { | |
2535 | .halt_reg = 0x6e008, | |
2536 | .clkr = { | |
2537 | .enable_reg = 0x6e008, | |
2538 | .enable_mask = BIT(0), | |
2539 | .hw.init = &(struct clk_init_data){ | |
2540 | .name = "gcc_pcie_2_slv_axi_clk", | |
2541 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2542 | .num_parents = 1, | |
2543 | .flags = CLK_SET_RATE_PARENT, | |
2544 | .ops = &clk_branch2_ops, | |
2545 | }, | |
2546 | }, | |
2547 | }; | |
2548 | ||
2549 | static struct clk_branch gcc_pcie_2_mstr_axi_clk = { | |
2550 | .halt_reg = 0x6e00c, | |
2551 | .clkr = { | |
2552 | .enable_reg = 0x6e00c, | |
2553 | .enable_mask = BIT(0), | |
2554 | .hw.init = &(struct clk_init_data){ | |
2555 | .name = "gcc_pcie_2_mstr_axi_clk", | |
2556 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2557 | .num_parents = 1, | |
2558 | .flags = CLK_SET_RATE_PARENT, | |
2559 | .ops = &clk_branch2_ops, | |
2560 | }, | |
2561 | }, | |
2562 | }; | |
2563 | ||
2564 | static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { | |
2565 | .halt_reg = 0x6e010, | |
2566 | .clkr = { | |
2567 | .enable_reg = 0x6e010, | |
2568 | .enable_mask = BIT(0), | |
2569 | .hw.init = &(struct clk_init_data){ | |
2570 | .name = "gcc_pcie_2_cfg_ahb_clk", | |
2571 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2572 | .num_parents = 1, | |
2573 | .flags = CLK_SET_RATE_PARENT, | |
2574 | .ops = &clk_branch2_ops, | |
2575 | }, | |
2576 | }, | |
2577 | }; | |
2578 | ||
2579 | static struct clk_branch gcc_pcie_2_aux_clk = { | |
2580 | .halt_reg = 0x6e014, | |
2581 | .clkr = { | |
2582 | .enable_reg = 0x6e014, | |
2583 | .enable_mask = BIT(0), | |
2584 | .hw.init = &(struct clk_init_data){ | |
2585 | .name = "gcc_pcie_2_aux_clk", | |
2586 | .parent_names = (const char *[]){ "pcie_aux_clk_src" }, | |
2587 | .num_parents = 1, | |
2588 | .flags = CLK_SET_RATE_PARENT, | |
2589 | .ops = &clk_branch2_ops, | |
2590 | }, | |
2591 | }, | |
2592 | }; | |
2593 | ||
2594 | static struct clk_branch gcc_pcie_2_pipe_clk = { | |
2595 | .halt_reg = 0x6e108, | |
2596 | .clkr = { | |
2597 | .enable_reg = 0x6e108, | |
2598 | .enable_mask = BIT(0), | |
2599 | .hw.init = &(struct clk_init_data){ | |
2600 | .name = "gcc_pcie_2_pipe_clk", | |
2601 | .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" }, | |
2602 | .num_parents = 1, | |
2603 | .flags = CLK_SET_RATE_PARENT, | |
2604 | .ops = &clk_branch2_ops, | |
2605 | }, | |
2606 | }, | |
2607 | }; | |
2608 | ||
2609 | static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { | |
2610 | .halt_reg = 0x6f004, | |
2611 | .clkr = { | |
2612 | .enable_reg = 0x6f004, | |
2613 | .enable_mask = BIT(0), | |
2614 | .hw.init = &(struct clk_init_data){ | |
2615 | .name = "gcc_pcie_phy_cfg_ahb_clk", | |
2616 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2617 | .num_parents = 1, | |
2618 | .flags = CLK_SET_RATE_PARENT, | |
2619 | .ops = &clk_branch2_ops, | |
2620 | }, | |
2621 | }, | |
2622 | }; | |
2623 | ||
2624 | static struct clk_branch gcc_pcie_phy_aux_clk = { | |
2625 | .halt_reg = 0x6f008, | |
2626 | .clkr = { | |
2627 | .enable_reg = 0x6f008, | |
2628 | .enable_mask = BIT(0), | |
2629 | .hw.init = &(struct clk_init_data){ | |
2630 | .name = "gcc_pcie_phy_aux_clk", | |
2631 | .parent_names = (const char *[]){ "pcie_aux_clk_src" }, | |
2632 | .num_parents = 1, | |
2633 | .flags = CLK_SET_RATE_PARENT, | |
2634 | .ops = &clk_branch2_ops, | |
2635 | }, | |
2636 | }, | |
2637 | }; | |
2638 | ||
2639 | static struct clk_branch gcc_ufs_axi_clk = { | |
2640 | .halt_reg = 0x75008, | |
2641 | .clkr = { | |
2642 | .enable_reg = 0x75008, | |
2643 | .enable_mask = BIT(0), | |
2644 | .hw.init = &(struct clk_init_data){ | |
2645 | .name = "gcc_ufs_axi_clk", | |
2646 | .parent_names = (const char *[]){ "ufs_axi_clk_src" }, | |
2647 | .num_parents = 1, | |
2648 | .flags = CLK_SET_RATE_PARENT, | |
2649 | .ops = &clk_branch2_ops, | |
2650 | }, | |
2651 | }, | |
2652 | }; | |
2653 | ||
2654 | static struct clk_branch gcc_ufs_ahb_clk = { | |
2655 | .halt_reg = 0x7500c, | |
2656 | .clkr = { | |
2657 | .enable_reg = 0x7500c, | |
2658 | .enable_mask = BIT(0), | |
2659 | .hw.init = &(struct clk_init_data){ | |
2660 | .name = "gcc_ufs_ahb_clk", | |
2661 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2662 | .num_parents = 1, | |
2663 | .flags = CLK_SET_RATE_PARENT, | |
2664 | .ops = &clk_branch2_ops, | |
2665 | }, | |
2666 | }, | |
2667 | }; | |
2668 | ||
2669 | static struct clk_fixed_factor ufs_tx_cfg_clk_src = { | |
2670 | .mult = 1, | |
2671 | .div = 16, | |
2672 | .hw.init = &(struct clk_init_data){ | |
2673 | .name = "ufs_tx_cfg_clk_src", | |
2674 | .parent_names = (const char *[]){ "ufs_axi_clk_src" }, | |
2675 | .num_parents = 1, | |
2676 | .flags = CLK_SET_RATE_PARENT, | |
2677 | .ops = &clk_fixed_factor_ops, | |
2678 | }, | |
2679 | }; | |
2680 | ||
2681 | static struct clk_branch gcc_ufs_tx_cfg_clk = { | |
2682 | .halt_reg = 0x75010, | |
2683 | .clkr = { | |
2684 | .enable_reg = 0x75010, | |
2685 | .enable_mask = BIT(0), | |
2686 | .hw.init = &(struct clk_init_data){ | |
2687 | .name = "gcc_ufs_tx_cfg_clk", | |
2688 | .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" }, | |
2689 | .num_parents = 1, | |
2690 | .flags = CLK_SET_RATE_PARENT, | |
2691 | .ops = &clk_branch2_ops, | |
2692 | }, | |
2693 | }, | |
2694 | }; | |
2695 | ||
2696 | static struct clk_fixed_factor ufs_rx_cfg_clk_src = { | |
2697 | .mult = 1, | |
2698 | .div = 16, | |
2699 | .hw.init = &(struct clk_init_data){ | |
2700 | .name = "ufs_rx_cfg_clk_src", | |
2701 | .parent_names = (const char *[]){ "ufs_axi_clk_src" }, | |
2702 | .num_parents = 1, | |
2703 | .flags = CLK_SET_RATE_PARENT, | |
2704 | .ops = &clk_fixed_factor_ops, | |
2705 | }, | |
2706 | }; | |
2707 | ||
2708 | static struct clk_branch gcc_ufs_rx_cfg_clk = { | |
2709 | .halt_reg = 0x75014, | |
2710 | .clkr = { | |
2711 | .enable_reg = 0x75014, | |
2712 | .enable_mask = BIT(0), | |
2713 | .hw.init = &(struct clk_init_data){ | |
2714 | .name = "gcc_ufs_rx_cfg_clk", | |
2715 | .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" }, | |
2716 | .num_parents = 1, | |
2717 | .flags = CLK_SET_RATE_PARENT, | |
2718 | .ops = &clk_branch2_ops, | |
2719 | }, | |
2720 | }, | |
2721 | }; | |
2722 | ||
2723 | static struct clk_branch gcc_ufs_tx_symbol_0_clk = { | |
2724 | .halt_reg = 0x75018, | |
2725 | .clkr = { | |
2726 | .enable_reg = 0x75018, | |
2727 | .enable_mask = BIT(0), | |
2728 | .hw.init = &(struct clk_init_data){ | |
2729 | .name = "gcc_ufs_tx_symbol_0_clk", | |
2730 | .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" }, | |
2731 | .num_parents = 1, | |
2732 | .flags = CLK_SET_RATE_PARENT, | |
2733 | .ops = &clk_branch2_ops, | |
2734 | }, | |
2735 | }, | |
2736 | }; | |
2737 | ||
2738 | static struct clk_branch gcc_ufs_rx_symbol_0_clk = { | |
2739 | .halt_reg = 0x7501c, | |
2740 | .clkr = { | |
2741 | .enable_reg = 0x7501c, | |
2742 | .enable_mask = BIT(0), | |
2743 | .hw.init = &(struct clk_init_data){ | |
2744 | .name = "gcc_ufs_rx_symbol_0_clk", | |
2745 | .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" }, | |
2746 | .num_parents = 1, | |
2747 | .flags = CLK_SET_RATE_PARENT, | |
2748 | .ops = &clk_branch2_ops, | |
2749 | }, | |
2750 | }, | |
2751 | }; | |
2752 | ||
2753 | static struct clk_branch gcc_ufs_rx_symbol_1_clk = { | |
2754 | .halt_reg = 0x75020, | |
2755 | .clkr = { | |
2756 | .enable_reg = 0x75020, | |
2757 | .enable_mask = BIT(0), | |
2758 | .hw.init = &(struct clk_init_data){ | |
2759 | .name = "gcc_ufs_rx_symbol_1_clk", | |
2760 | .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" }, | |
2761 | .num_parents = 1, | |
2762 | .flags = CLK_SET_RATE_PARENT, | |
2763 | .ops = &clk_branch2_ops, | |
2764 | }, | |
2765 | }, | |
2766 | }; | |
2767 | ||
2768 | static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = { | |
2769 | .mult = 1, | |
2770 | .div = 2, | |
2771 | .hw.init = &(struct clk_init_data){ | |
2772 | .name = "ufs_ice_core_postdiv_clk_src", | |
2773 | .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, | |
2774 | .num_parents = 1, | |
2775 | .flags = CLK_SET_RATE_PARENT, | |
2776 | .ops = &clk_fixed_factor_ops, | |
2777 | }, | |
2778 | }; | |
2779 | ||
2780 | static struct clk_branch gcc_ufs_unipro_core_clk = { | |
2781 | .halt_reg = 0x7600c, | |
2782 | .clkr = { | |
2783 | .enable_reg = 0x7600c, | |
2784 | .enable_mask = BIT(0), | |
2785 | .hw.init = &(struct clk_init_data){ | |
2786 | .name = "gcc_ufs_unipro_core_clk", | |
2787 | .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" }, | |
2788 | .num_parents = 1, | |
2789 | .flags = CLK_SET_RATE_PARENT, | |
2790 | .ops = &clk_branch2_ops, | |
2791 | }, | |
2792 | }, | |
2793 | }; | |
2794 | ||
2795 | static struct clk_branch gcc_ufs_ice_core_clk = { | |
2796 | .halt_reg = 0x76010, | |
2797 | .clkr = { | |
2798 | .enable_reg = 0x76010, | |
2799 | .enable_mask = BIT(0), | |
2800 | .hw.init = &(struct clk_init_data){ | |
2801 | .name = "gcc_ufs_ice_core_clk", | |
2802 | .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, | |
2803 | .num_parents = 1, | |
2804 | .flags = CLK_SET_RATE_PARENT, | |
2805 | .ops = &clk_branch2_ops, | |
2806 | }, | |
2807 | }, | |
2808 | }; | |
2809 | ||
2810 | static struct clk_branch gcc_ufs_sys_clk_core_clk = { | |
2811 | .halt_check = BRANCH_HALT_DELAY, | |
2812 | .clkr = { | |
2813 | .enable_reg = 0x76030, | |
2814 | .enable_mask = BIT(0), | |
2815 | .hw.init = &(struct clk_init_data){ | |
2816 | .name = "gcc_ufs_sys_clk_core_clk", | |
2817 | .ops = &clk_branch2_ops, | |
b1e010c0 SB |
2818 | }, |
2819 | }, | |
2820 | }; | |
2821 | ||
2822 | static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = { | |
2823 | .halt_check = BRANCH_HALT_DELAY, | |
2824 | .clkr = { | |
2825 | .enable_reg = 0x76034, | |
2826 | .enable_mask = BIT(0), | |
2827 | .hw.init = &(struct clk_init_data){ | |
2828 | .name = "gcc_ufs_tx_symbol_clk_core_clk", | |
2829 | .ops = &clk_branch2_ops, | |
b1e010c0 SB |
2830 | }, |
2831 | }, | |
2832 | }; | |
2833 | ||
2834 | static struct clk_branch gcc_aggre0_snoc_axi_clk = { | |
2835 | .halt_reg = 0x81008, | |
2836 | .clkr = { | |
2837 | .enable_reg = 0x81008, | |
2838 | .enable_mask = BIT(0), | |
2839 | .hw.init = &(struct clk_init_data){ | |
2840 | .name = "gcc_aggre0_snoc_axi_clk", | |
2841 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2842 | .num_parents = 1, | |
2843 | .flags = CLK_SET_RATE_PARENT, | |
2844 | .ops = &clk_branch2_ops, | |
2845 | }, | |
2846 | }, | |
2847 | }; | |
2848 | ||
2849 | static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { | |
2850 | .halt_reg = 0x8100c, | |
2851 | .clkr = { | |
2852 | .enable_reg = 0x8100c, | |
2853 | .enable_mask = BIT(0), | |
2854 | .hw.init = &(struct clk_init_data){ | |
2855 | .name = "gcc_aggre0_cnoc_ahb_clk", | |
2856 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2857 | .num_parents = 1, | |
2858 | .flags = CLK_SET_RATE_PARENT, | |
2859 | .ops = &clk_branch2_ops, | |
2860 | }, | |
2861 | }, | |
2862 | }; | |
2863 | ||
2864 | static struct clk_branch gcc_smmu_aggre0_axi_clk = { | |
2865 | .halt_reg = 0x81014, | |
2866 | .clkr = { | |
2867 | .enable_reg = 0x81014, | |
2868 | .enable_mask = BIT(0), | |
2869 | .hw.init = &(struct clk_init_data){ | |
2870 | .name = "gcc_smmu_aggre0_axi_clk", | |
2871 | .parent_names = (const char *[]){ "system_noc_clk_src" }, | |
2872 | .num_parents = 1, | |
2873 | .flags = CLK_SET_RATE_PARENT, | |
2874 | .ops = &clk_branch2_ops, | |
2875 | }, | |
2876 | }, | |
2877 | }; | |
2878 | ||
2879 | static struct clk_branch gcc_smmu_aggre0_ahb_clk = { | |
2880 | .halt_reg = 0x81018, | |
2881 | .clkr = { | |
2882 | .enable_reg = 0x81018, | |
2883 | .enable_mask = BIT(0), | |
2884 | .hw.init = &(struct clk_init_data){ | |
2885 | .name = "gcc_smmu_aggre0_ahb_clk", | |
2886 | .parent_names = (const char *[]){ "config_noc_clk_src" }, | |
2887 | .num_parents = 1, | |
2888 | .flags = CLK_SET_RATE_PARENT, | |
2889 | .ops = &clk_branch2_ops, | |
2890 | }, | |
2891 | }, | |
2892 | }; | |
2893 | ||
2894 | static struct clk_branch gcc_aggre1_pnoc_ahb_clk = { | |
2895 | .halt_reg = 0x82014, | |
2896 | .clkr = { | |
2897 | .enable_reg = 0x82014, | |
2898 | .enable_mask = BIT(0), | |
2899 | .hw.init = &(struct clk_init_data){ | |
2900 | .name = "gcc_aggre1_pnoc_ahb_clk", | |
2901 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
2902 | .num_parents = 1, | |
2903 | .flags = CLK_SET_RATE_PARENT, | |
2904 | .ops = &clk_branch2_ops, | |
2905 | }, | |
2906 | }, | |
2907 | }; | |
2908 | ||
2909 | static struct clk_branch gcc_aggre2_ufs_axi_clk = { | |
2910 | .halt_reg = 0x83014, | |
2911 | .clkr = { | |
2912 | .enable_reg = 0x83014, | |
2913 | .enable_mask = BIT(0), | |
2914 | .hw.init = &(struct clk_init_data){ | |
2915 | .name = "gcc_aggre2_ufs_axi_clk", | |
2916 | .parent_names = (const char *[]){ "ufs_axi_clk_src" }, | |
2917 | .num_parents = 1, | |
2918 | .flags = CLK_SET_RATE_PARENT, | |
2919 | .ops = &clk_branch2_ops, | |
2920 | }, | |
2921 | }, | |
2922 | }; | |
2923 | ||
2924 | static struct clk_branch gcc_aggre2_usb3_axi_clk = { | |
2925 | .halt_reg = 0x83018, | |
2926 | .clkr = { | |
2927 | .enable_reg = 0x83018, | |
2928 | .enable_mask = BIT(0), | |
2929 | .hw.init = &(struct clk_init_data){ | |
2930 | .name = "gcc_aggre2_usb3_axi_clk", | |
2931 | .parent_names = (const char *[]){ "usb30_master_clk_src" }, | |
2932 | .num_parents = 1, | |
2933 | .flags = CLK_SET_RATE_PARENT, | |
2934 | .ops = &clk_branch2_ops, | |
2935 | }, | |
2936 | }, | |
2937 | }; | |
2938 | ||
2939 | static struct clk_branch gcc_qspi_ahb_clk = { | |
2940 | .halt_reg = 0x8b004, | |
2941 | .clkr = { | |
2942 | .enable_reg = 0x8b004, | |
2943 | .enable_mask = BIT(0), | |
2944 | .hw.init = &(struct clk_init_data){ | |
2945 | .name = "gcc_qspi_ahb_clk", | |
2946 | .parent_names = (const char *[]){ "periph_noc_clk_src" }, | |
2947 | .num_parents = 1, | |
2948 | .flags = CLK_SET_RATE_PARENT, | |
2949 | .ops = &clk_branch2_ops, | |
2950 | }, | |
2951 | }, | |
2952 | }; | |
2953 | ||
2954 | static struct clk_branch gcc_qspi_ser_clk = { | |
2955 | .halt_reg = 0x8b008, | |
2956 | .clkr = { | |
2957 | .enable_reg = 0x8b008, | |
2958 | .enable_mask = BIT(0), | |
2959 | .hw.init = &(struct clk_init_data){ | |
2960 | .name = "gcc_qspi_ser_clk", | |
2961 | .parent_names = (const char *[]){ "qspi_ser_clk_src" }, | |
2962 | .num_parents = 1, | |
2963 | .flags = CLK_SET_RATE_PARENT, | |
2964 | .ops = &clk_branch2_ops, | |
2965 | }, | |
2966 | }, | |
2967 | }; | |
2968 | ||
2969 | static struct clk_branch gcc_usb3_clkref_clk = { | |
2970 | .halt_reg = 0x8800C, | |
2971 | .clkr = { | |
2972 | .enable_reg = 0x8800C, | |
2973 | .enable_mask = BIT(0), | |
2974 | .hw.init = &(struct clk_init_data){ | |
2975 | .name = "gcc_usb3_clkref_clk", | |
2976 | .parent_names = (const char *[]){ "xo" }, | |
2977 | .num_parents = 1, | |
2978 | .ops = &clk_branch2_ops, | |
2979 | }, | |
2980 | }, | |
2981 | }; | |
2982 | ||
2983 | static struct clk_branch gcc_hdmi_clkref_clk = { | |
2984 | .halt_reg = 0x88000, | |
2985 | .clkr = { | |
2986 | .enable_reg = 0x88000, | |
2987 | .enable_mask = BIT(0), | |
2988 | .hw.init = &(struct clk_init_data){ | |
2989 | .name = "gcc_hdmi_clkref_clk", | |
2990 | .parent_names = (const char *[]){ "xo" }, | |
2991 | .num_parents = 1, | |
2992 | .ops = &clk_branch2_ops, | |
2993 | }, | |
2994 | }, | |
2995 | }; | |
2996 | ||
2997 | static struct clk_branch gcc_ufs_clkref_clk = { | |
2998 | .halt_reg = 0x88008, | |
2999 | .clkr = { | |
3000 | .enable_reg = 0x88008, | |
3001 | .enable_mask = BIT(0), | |
3002 | .hw.init = &(struct clk_init_data){ | |
3003 | .name = "gcc_ufs_clkref_clk", | |
3004 | .parent_names = (const char *[]){ "xo" }, | |
3005 | .num_parents = 1, | |
3006 | .ops = &clk_branch2_ops, | |
3007 | }, | |
3008 | }, | |
3009 | }; | |
3010 | ||
3011 | static struct clk_branch gcc_pcie_clkref_clk = { | |
3012 | .halt_reg = 0x88010, | |
3013 | .clkr = { | |
3014 | .enable_reg = 0x88010, | |
3015 | .enable_mask = BIT(0), | |
3016 | .hw.init = &(struct clk_init_data){ | |
3017 | .name = "gcc_pcie_clkref_clk", | |
3018 | .parent_names = (const char *[]){ "xo" }, | |
3019 | .num_parents = 1, | |
3020 | .ops = &clk_branch2_ops, | |
3021 | }, | |
3022 | }, | |
3023 | }; | |
3024 | ||
3025 | static struct clk_branch gcc_rx2_usb2_clkref_clk = { | |
3026 | .halt_reg = 0x88014, | |
3027 | .clkr = { | |
3028 | .enable_reg = 0x88014, | |
3029 | .enable_mask = BIT(0), | |
3030 | .hw.init = &(struct clk_init_data){ | |
3031 | .name = "gcc_rx2_usb2_clkref_clk", | |
3032 | .parent_names = (const char *[]){ "xo" }, | |
3033 | .num_parents = 1, | |
3034 | .ops = &clk_branch2_ops, | |
3035 | }, | |
3036 | }, | |
3037 | }; | |
3038 | ||
3039 | static struct clk_branch gcc_rx1_usb2_clkref_clk = { | |
3040 | .halt_reg = 0x88018, | |
3041 | .clkr = { | |
3042 | .enable_reg = 0x88018, | |
3043 | .enable_mask = BIT(0), | |
3044 | .hw.init = &(struct clk_init_data){ | |
3045 | .name = "gcc_rx1_usb2_clkref_clk", | |
3046 | .parent_names = (const char *[]){ "xo" }, | |
3047 | .num_parents = 1, | |
3048 | .ops = &clk_branch2_ops, | |
3049 | }, | |
3050 | }, | |
3051 | }; | |
3052 | ||
3053 | static struct clk_hw *gcc_msm8996_hws[] = { | |
3054 | &xo.hw, | |
3055 | &gpll0_early_div.hw, | |
3056 | &ufs_tx_cfg_clk_src.hw, | |
3057 | &ufs_rx_cfg_clk_src.hw, | |
3058 | &ufs_ice_core_postdiv_clk_src.hw, | |
3059 | }; | |
3060 | ||
52111672 RN |
3061 | static struct gdsc aggre0_noc_gdsc = { |
3062 | .gdscr = 0x81004, | |
3063 | .gds_hw_ctrl = 0x81028, | |
3064 | .pd = { | |
3065 | .name = "aggre0_noc", | |
3066 | }, | |
3067 | .pwrsts = PWRSTS_OFF_ON, | |
3068 | .flags = VOTABLE, | |
3069 | }; | |
3070 | ||
3071 | static struct gdsc hlos1_vote_aggre0_noc_gdsc = { | |
3072 | .gdscr = 0x7d024, | |
3073 | .pd = { | |
3074 | .name = "hlos1_vote_aggre0_noc", | |
3075 | }, | |
3076 | .pwrsts = PWRSTS_OFF_ON, | |
3077 | .flags = VOTABLE, | |
3078 | }; | |
3079 | ||
3080 | static struct gdsc hlos1_vote_lpass_adsp_gdsc = { | |
3081 | .gdscr = 0x7d034, | |
3082 | .pd = { | |
3083 | .name = "hlos1_vote_lpass_adsp", | |
3084 | }, | |
3085 | .pwrsts = PWRSTS_OFF_ON, | |
3086 | .flags = VOTABLE, | |
3087 | }; | |
3088 | ||
3089 | static struct gdsc hlos1_vote_lpass_core_gdsc = { | |
3090 | .gdscr = 0x7d038, | |
3091 | .pd = { | |
3092 | .name = "hlos1_vote_lpass_core", | |
3093 | }, | |
3094 | .pwrsts = PWRSTS_OFF_ON, | |
3095 | .flags = VOTABLE, | |
3096 | }; | |
3097 | ||
3098 | static struct gdsc usb30_gdsc = { | |
3099 | .gdscr = 0xf004, | |
3100 | .pd = { | |
3101 | .name = "usb30", | |
3102 | }, | |
3103 | .pwrsts = PWRSTS_OFF_ON, | |
3104 | }; | |
3105 | ||
3106 | static struct gdsc pcie0_gdsc = { | |
3107 | .gdscr = 0x6b004, | |
3108 | .pd = { | |
3109 | .name = "pcie0", | |
3110 | }, | |
3111 | .pwrsts = PWRSTS_OFF_ON, | |
3112 | }; | |
3113 | ||
3114 | static struct gdsc pcie1_gdsc = { | |
3115 | .gdscr = 0x6d004, | |
3116 | .pd = { | |
3117 | .name = "pcie1", | |
3118 | }, | |
3119 | .pwrsts = PWRSTS_OFF_ON, | |
3120 | }; | |
3121 | ||
3122 | static struct gdsc pcie2_gdsc = { | |
3123 | .gdscr = 0x6e004, | |
3124 | .pd = { | |
3125 | .name = "pcie2", | |
3126 | }, | |
3127 | .pwrsts = PWRSTS_OFF_ON, | |
3128 | }; | |
3129 | ||
3130 | static struct gdsc ufs_gdsc = { | |
3131 | .gdscr = 0x75004, | |
3132 | .pd = { | |
3133 | .name = "ufs", | |
3134 | }, | |
3135 | .pwrsts = PWRSTS_OFF_ON, | |
3136 | }; | |
3137 | ||
b1e010c0 SB |
3138 | static struct clk_regmap *gcc_msm8996_clocks[] = { |
3139 | [GPLL0_EARLY] = &gpll0_early.clkr, | |
3140 | [GPLL0] = &gpll0.clkr, | |
3141 | [GPLL4_EARLY] = &gpll4_early.clkr, | |
3142 | [GPLL4] = &gpll4.clkr, | |
3143 | [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, | |
3144 | [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, | |
3145 | [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, | |
3146 | [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, | |
3147 | [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, | |
3148 | [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, | |
3149 | [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, | |
3150 | [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, | |
3151 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, | |
3152 | [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, | |
3153 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, | |
3154 | [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, | |
3155 | [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, | |
3156 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, | |
3157 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, | |
3158 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, | |
3159 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, | |
3160 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, | |
3161 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, | |
3162 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, | |
3163 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, | |
3164 | [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, | |
3165 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, | |
3166 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, | |
3167 | [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, | |
3168 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, | |
3169 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, | |
3170 | [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, | |
3171 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, | |
3172 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, | |
3173 | [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, | |
3174 | [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, | |
3175 | [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, | |
3176 | [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, | |
3177 | [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, | |
3178 | [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, | |
3179 | [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, | |
3180 | [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, | |
3181 | [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, | |
3182 | [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, | |
3183 | [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, | |
3184 | [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, | |
3185 | [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, | |
3186 | [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, | |
3187 | [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, | |
3188 | [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, | |
3189 | [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, | |
3190 | [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, | |
3191 | [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, | |
3192 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, | |
3193 | [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, | |
3194 | [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, | |
3195 | [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, | |
3196 | [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, | |
3197 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, | |
3198 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, | |
3199 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, | |
3200 | [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, | |
3201 | [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, | |
3202 | [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, | |
3203 | [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, | |
3204 | [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, | |
3205 | [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, | |
3206 | [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr, | |
3207 | [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, | |
3208 | [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr, | |
3209 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, | |
3210 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, | |
3211 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, | |
3212 | [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, | |
3213 | [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, | |
3214 | [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, | |
3215 | [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, | |
3216 | [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, | |
3217 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, | |
3218 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
3219 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, | |
3220 | [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, | |
3221 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3222 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3223 | [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, | |
3224 | [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, | |
3225 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
3226 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3227 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, | |
3228 | [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, | |
3229 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, | |
3230 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, | |
3231 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, | |
3232 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, | |
3233 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, | |
3234 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, | |
3235 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, | |
3236 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, | |
3237 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, | |
3238 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, | |
3239 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, | |
3240 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, | |
3241 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, | |
3242 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, | |
3243 | [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, | |
3244 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, | |
3245 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, | |
3246 | [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, | |
3247 | [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, | |
3248 | [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, | |
3249 | [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, | |
3250 | [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, | |
3251 | [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, | |
3252 | [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, | |
3253 | [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, | |
3254 | [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, | |
3255 | [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, | |
3256 | [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, | |
3257 | [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, | |
3258 | [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, | |
3259 | [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, | |
3260 | [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, | |
3261 | [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, | |
3262 | [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, | |
3263 | [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, | |
3264 | [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, | |
3265 | [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, | |
3266 | [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, | |
3267 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3268 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
3269 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
3270 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
3271 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
3272 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, | |
3273 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3274 | [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, | |
3275 | [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, | |
3276 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3277 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3278 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3279 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
3280 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
3281 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
3282 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, | |
3283 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
3284 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, | |
3285 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, | |
3286 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, | |
3287 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, | |
3288 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, | |
3289 | [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, | |
3290 | [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, | |
3291 | [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, | |
3292 | [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, | |
3293 | [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, | |
3294 | [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr, | |
3295 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, | |
3296 | [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, | |
3297 | [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, | |
3298 | [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, | |
3299 | [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, | |
3300 | [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, | |
3301 | [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, | |
3302 | [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, | |
3303 | [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, | |
3304 | [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, | |
3305 | [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr, | |
3306 | [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr, | |
3307 | [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr, | |
3308 | [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr, | |
3309 | [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr, | |
3310 | [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr, | |
3311 | [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr, | |
3312 | [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, | |
3313 | [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, | |
3314 | [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, | |
3315 | [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, | |
3316 | [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, | |
3317 | [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, | |
3318 | [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, | |
3319 | [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, | |
3320 | [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr, | |
3321 | [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, | |
3322 | }; | |
3323 | ||
52111672 RN |
3324 | static struct gdsc *gcc_msm8996_gdscs[] = { |
3325 | [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc, | |
3326 | [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc, | |
3327 | [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc, | |
3328 | [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc, | |
3329 | [USB30_GDSC] = &usb30_gdsc, | |
3330 | [PCIE0_GDSC] = &pcie0_gdsc, | |
3331 | [PCIE1_GDSC] = &pcie1_gdsc, | |
3332 | [PCIE2_GDSC] = &pcie2_gdsc, | |
3333 | [UFS_GDSC] = &ufs_gdsc, | |
3334 | }; | |
3335 | ||
b1e010c0 SB |
3336 | static const struct qcom_reset_map gcc_msm8996_resets[] = { |
3337 | [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, | |
3338 | [GCC_CONFIG_NOC_BCR] = { 0x5000 }, | |
3339 | [GCC_PERIPH_NOC_BCR] = { 0x6000 }, | |
3340 | [GCC_IMEM_BCR] = { 0x8000 }, | |
3341 | [GCC_MMSS_BCR] = { 0x9000 }, | |
3342 | [GCC_PIMEM_BCR] = { 0x0a000 }, | |
3343 | [GCC_QDSS_BCR] = { 0x0c000 }, | |
3344 | [GCC_USB_30_BCR] = { 0x0f000 }, | |
3345 | [GCC_USB_20_BCR] = { 0x12000 }, | |
3346 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 }, | |
3347 | [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c }, | |
3348 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, | |
3349 | [GCC_SDCC1_BCR] = { 0x13000 }, | |
3350 | [GCC_SDCC2_BCR] = { 0x14000 }, | |
3351 | [GCC_SDCC3_BCR] = { 0x15000 }, | |
3352 | [GCC_SDCC4_BCR] = { 0x16000 }, | |
3353 | [GCC_BLSP1_BCR] = { 0x17000 }, | |
3354 | [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, | |
3355 | [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, | |
3356 | [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, | |
3357 | [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, | |
3358 | [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, | |
3359 | [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, | |
3360 | [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, | |
3361 | [GCC_BLSP1_UART4_BCR] = { 0x20000 }, | |
3362 | [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, | |
3363 | [GCC_BLSP1_UART5_BCR] = { 0x22000 }, | |
3364 | [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, | |
3365 | [GCC_BLSP1_UART6_BCR] = { 0x24000 }, | |
3366 | [GCC_BLSP2_BCR] = { 0x25000 }, | |
3367 | [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, | |
3368 | [GCC_BLSP2_UART1_BCR] = { 0x27000 }, | |
3369 | [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, | |
3370 | [GCC_BLSP2_UART2_BCR] = { 0x29000 }, | |
3371 | [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, | |
3372 | [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, | |
3373 | [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, | |
3374 | [GCC_BLSP2_UART4_BCR] = { 0x2d000 }, | |
3375 | [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, | |
3376 | [GCC_BLSP2_UART5_BCR] = { 0x2f000 }, | |
3377 | [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, | |
3378 | [GCC_BLSP2_UART6_BCR] = { 0x31000 }, | |
3379 | [GCC_PDM_BCR] = { 0x33000 }, | |
3380 | [GCC_PRNG_BCR] = { 0x34000 }, | |
3381 | [GCC_TSIF_BCR] = { 0x36000 }, | |
3382 | [GCC_TCSR_BCR] = { 0x37000 }, | |
3383 | [GCC_BOOT_ROM_BCR] = { 0x38000 }, | |
3384 | [GCC_MSG_RAM_BCR] = { 0x39000 }, | |
3385 | [GCC_TLMM_BCR] = { 0x3a000 }, | |
3386 | [GCC_MPM_BCR] = { 0x3b000 }, | |
3387 | [GCC_SEC_CTRL_BCR] = { 0x3d000 }, | |
3388 | [GCC_SPMI_BCR] = { 0x3f000 }, | |
3389 | [GCC_SPDM_BCR] = { 0x40000 }, | |
3390 | [GCC_CE1_BCR] = { 0x41000 }, | |
3391 | [GCC_BIMC_BCR] = { 0x44000 }, | |
3392 | [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, | |
3393 | [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 }, | |
3394 | [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 }, | |
3395 | [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 }, | |
3396 | [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 }, | |
3397 | [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, | |
3398 | [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 }, | |
3399 | [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 }, | |
3400 | [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 }, | |
3401 | [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 }, | |
3402 | [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, | |
3403 | [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, | |
3404 | [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, | |
3405 | [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, | |
3406 | [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, | |
3407 | [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, | |
3408 | [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, | |
3409 | [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, | |
3410 | [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, | |
3411 | [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, | |
3412 | [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 }, | |
3413 | [GCC_APB2JTAG_BCR] = { 0x4c000 }, | |
3414 | [GCC_RBCPR_CX_BCR] = { 0x4e000 }, | |
3415 | [GCC_RBCPR_MX_BCR] = { 0x4f000 }, | |
3416 | [GCC_PCIE_0_BCR] = { 0x6b000 }, | |
3417 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, | |
3418 | [GCC_PCIE_1_BCR] = { 0x6d000 }, | |
3419 | [GCC_PCIE_1_PHY_BCR] = { 0x6d038 }, | |
3420 | [GCC_PCIE_2_BCR] = { 0x6e000 }, | |
3421 | [GCC_PCIE_2_PHY_BCR] = { 0x6e038 }, | |
3422 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, | |
3423 | [GCC_DCD_BCR] = { 0x70000 }, | |
3424 | [GCC_OBT_ODT_BCR] = { 0x73000 }, | |
3425 | [GCC_UFS_BCR] = { 0x75000 }, | |
3426 | [GCC_SSC_BCR] = { 0x63000 }, | |
3427 | [GCC_VS_BCR] = { 0x7a000 }, | |
3428 | [GCC_AGGRE0_NOC_BCR] = { 0x81000 }, | |
3429 | [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, | |
3430 | [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, | |
3431 | [GCC_DCC_BCR] = { 0x84000 }, | |
3432 | [GCC_IPA_BCR] = { 0x89000 }, | |
3433 | [GCC_QSPI_BCR] = { 0x8b000 }, | |
3434 | [GCC_SKL_BCR] = { 0x8c000 }, | |
3435 | [GCC_MSMPU_BCR] = { 0x8d000 }, | |
3436 | [GCC_MSS_Q6_BCR] = { 0x8e000 }, | |
3437 | [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 }, | |
3438 | }; | |
3439 | ||
3440 | static const struct regmap_config gcc_msm8996_regmap_config = { | |
3441 | .reg_bits = 32, | |
3442 | .reg_stride = 4, | |
3443 | .val_bits = 32, | |
3444 | .max_register = 0x8f010, | |
3445 | .fast_io = true, | |
3446 | }; | |
3447 | ||
3448 | static const struct qcom_cc_desc gcc_msm8996_desc = { | |
3449 | .config = &gcc_msm8996_regmap_config, | |
3450 | .clks = gcc_msm8996_clocks, | |
3451 | .num_clks = ARRAY_SIZE(gcc_msm8996_clocks), | |
3452 | .resets = gcc_msm8996_resets, | |
3453 | .num_resets = ARRAY_SIZE(gcc_msm8996_resets), | |
52111672 RN |
3454 | .gdscs = gcc_msm8996_gdscs, |
3455 | .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs), | |
b1e010c0 SB |
3456 | }; |
3457 | ||
3458 | static const struct of_device_id gcc_msm8996_match_table[] = { | |
3459 | { .compatible = "qcom,gcc-msm8996" }, | |
3460 | { } | |
3461 | }; | |
3462 | MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table); | |
3463 | ||
3464 | static int gcc_msm8996_probe(struct platform_device *pdev) | |
3465 | { | |
3466 | struct clk *clk; | |
3467 | struct device *dev = &pdev->dev; | |
3468 | int i; | |
3469 | struct regmap *regmap; | |
3470 | ||
3471 | regmap = qcom_cc_map(pdev, &gcc_msm8996_desc); | |
3472 | if (IS_ERR(regmap)) | |
3473 | return PTR_ERR(regmap); | |
3474 | ||
3475 | /* | |
3476 | * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be | |
3477 | * turned off by hardware during certain apps low power modes. | |
3478 | */ | |
3479 | regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); | |
3480 | ||
3481 | for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) { | |
3482 | clk = devm_clk_register(dev, gcc_msm8996_hws[i]); | |
3483 | if (IS_ERR(clk)) | |
3484 | return PTR_ERR(clk); | |
3485 | } | |
3486 | ||
3487 | return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap); | |
3488 | } | |
3489 | ||
3490 | static struct platform_driver gcc_msm8996_driver = { | |
3491 | .probe = gcc_msm8996_probe, | |
3492 | .driver = { | |
3493 | .name = "gcc-msm8996", | |
3494 | .of_match_table = gcc_msm8996_match_table, | |
3495 | }, | |
3496 | }; | |
3497 | ||
3498 | static int __init gcc_msm8996_init(void) | |
3499 | { | |
3500 | return platform_driver_register(&gcc_msm8996_driver); | |
3501 | } | |
3502 | core_initcall(gcc_msm8996_init); | |
3503 | ||
3504 | static void __exit gcc_msm8996_exit(void) | |
3505 | { | |
3506 | platform_driver_unregister(&gcc_msm8996_driver); | |
3507 | } | |
3508 | module_exit(gcc_msm8996_exit); | |
3509 | ||
3510 | MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver"); | |
3511 | MODULE_LICENSE("GPL v2"); | |
3512 | MODULE_ALIAS("platform:gcc-msm8996"); |