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d33faa9e SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> | |
26 | #include <dt-bindings/reset/qcom,gcc-msm8974.h> | |
27 | ||
49fc825f | 28 | #include "common.h" |
d33faa9e SB |
29 | #include "clk-regmap.h" |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
34 | ||
35 | #define P_XO 0 | |
36 | #define P_GPLL0 1 | |
37 | #define P_GPLL1 1 | |
c685841e | 38 | #define P_GPLL4 2 |
d33faa9e SB |
39 | |
40 | static const u8 gcc_xo_gpll0_map[] = { | |
41 | [P_XO] = 0, | |
42 | [P_GPLL0] = 1, | |
43 | }; | |
44 | ||
45 | static const char *gcc_xo_gpll0[] = { | |
46 | "xo", | |
47 | "gpll0_vote", | |
48 | }; | |
49 | ||
c685841e SB |
50 | static const u8 gcc_xo_gpll0_gpll4_map[] = { |
51 | [P_XO] = 0, | |
52 | [P_GPLL0] = 1, | |
53 | [P_GPLL4] = 5, | |
54 | }; | |
55 | ||
56 | static const char *gcc_xo_gpll0_gpll4[] = { | |
57 | "xo", | |
58 | "gpll0_vote", | |
59 | "gpll4_vote", | |
60 | }; | |
61 | ||
d33faa9e SB |
62 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
63 | ||
64 | static struct clk_pll gpll0 = { | |
65 | .l_reg = 0x0004, | |
66 | .m_reg = 0x0008, | |
67 | .n_reg = 0x000c, | |
68 | .config_reg = 0x0014, | |
69 | .mode_reg = 0x0000, | |
70 | .status_reg = 0x001c, | |
71 | .status_bit = 17, | |
72 | .clkr.hw.init = &(struct clk_init_data){ | |
73 | .name = "gpll0", | |
74 | .parent_names = (const char *[]){ "xo" }, | |
75 | .num_parents = 1, | |
76 | .ops = &clk_pll_ops, | |
77 | }, | |
78 | }; | |
79 | ||
80 | static struct clk_regmap gpll0_vote = { | |
81 | .enable_reg = 0x1480, | |
82 | .enable_mask = BIT(0), | |
83 | .hw.init = &(struct clk_init_data){ | |
84 | .name = "gpll0_vote", | |
85 | .parent_names = (const char *[]){ "gpll0" }, | |
86 | .num_parents = 1, | |
87 | .ops = &clk_pll_vote_ops, | |
88 | }, | |
89 | }; | |
90 | ||
91 | static struct clk_rcg2 config_noc_clk_src = { | |
92 | .cmd_rcgr = 0x0150, | |
93 | .hid_width = 5, | |
94 | .parent_map = gcc_xo_gpll0_map, | |
95 | .clkr.hw.init = &(struct clk_init_data){ | |
96 | .name = "config_noc_clk_src", | |
97 | .parent_names = gcc_xo_gpll0, | |
98 | .num_parents = 2, | |
99 | .ops = &clk_rcg2_ops, | |
100 | }, | |
101 | }; | |
102 | ||
103 | static struct clk_rcg2 periph_noc_clk_src = { | |
104 | .cmd_rcgr = 0x0190, | |
105 | .hid_width = 5, | |
106 | .parent_map = gcc_xo_gpll0_map, | |
107 | .clkr.hw.init = &(struct clk_init_data){ | |
108 | .name = "periph_noc_clk_src", | |
109 | .parent_names = gcc_xo_gpll0, | |
110 | .num_parents = 2, | |
111 | .ops = &clk_rcg2_ops, | |
112 | }, | |
113 | }; | |
114 | ||
115 | static struct clk_rcg2 system_noc_clk_src = { | |
116 | .cmd_rcgr = 0x0120, | |
117 | .hid_width = 5, | |
118 | .parent_map = gcc_xo_gpll0_map, | |
119 | .clkr.hw.init = &(struct clk_init_data){ | |
120 | .name = "system_noc_clk_src", | |
121 | .parent_names = gcc_xo_gpll0, | |
122 | .num_parents = 2, | |
123 | .ops = &clk_rcg2_ops, | |
124 | }, | |
125 | }; | |
126 | ||
127 | static struct clk_pll gpll1 = { | |
128 | .l_reg = 0x0044, | |
129 | .m_reg = 0x0048, | |
130 | .n_reg = 0x004c, | |
131 | .config_reg = 0x0054, | |
132 | .mode_reg = 0x0040, | |
133 | .status_reg = 0x005c, | |
134 | .status_bit = 17, | |
135 | .clkr.hw.init = &(struct clk_init_data){ | |
136 | .name = "gpll1", | |
137 | .parent_names = (const char *[]){ "xo" }, | |
138 | .num_parents = 1, | |
139 | .ops = &clk_pll_ops, | |
140 | }, | |
141 | }; | |
142 | ||
143 | static struct clk_regmap gpll1_vote = { | |
144 | .enable_reg = 0x1480, | |
145 | .enable_mask = BIT(1), | |
146 | .hw.init = &(struct clk_init_data){ | |
147 | .name = "gpll1_vote", | |
148 | .parent_names = (const char *[]){ "gpll1" }, | |
149 | .num_parents = 1, | |
150 | .ops = &clk_pll_vote_ops, | |
151 | }, | |
152 | }; | |
153 | ||
c685841e SB |
154 | static struct clk_pll gpll4 = { |
155 | .l_reg = 0x1dc4, | |
156 | .m_reg = 0x1dc8, | |
157 | .n_reg = 0x1dcc, | |
158 | .config_reg = 0x1dd4, | |
159 | .mode_reg = 0x1dc0, | |
160 | .status_reg = 0x1ddc, | |
161 | .status_bit = 17, | |
162 | .clkr.hw.init = &(struct clk_init_data){ | |
163 | .name = "gpll4", | |
164 | .parent_names = (const char *[]){ "xo" }, | |
165 | .num_parents = 1, | |
166 | .ops = &clk_pll_ops, | |
167 | }, | |
168 | }; | |
169 | ||
170 | static struct clk_regmap gpll4_vote = { | |
171 | .enable_reg = 0x1480, | |
172 | .enable_mask = BIT(4), | |
173 | .hw.init = &(struct clk_init_data){ | |
174 | .name = "gpll4_vote", | |
175 | .parent_names = (const char *[]){ "gpll4" }, | |
176 | .num_parents = 1, | |
177 | .ops = &clk_pll_vote_ops, | |
178 | }, | |
179 | }; | |
180 | ||
d33faa9e SB |
181 | static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { |
182 | F(125000000, P_GPLL0, 1, 5, 24), | |
183 | { } | |
184 | }; | |
185 | ||
186 | static struct clk_rcg2 usb30_master_clk_src = { | |
187 | .cmd_rcgr = 0x03d4, | |
188 | .mnd_width = 8, | |
189 | .hid_width = 5, | |
190 | .parent_map = gcc_xo_gpll0_map, | |
191 | .freq_tbl = ftbl_gcc_usb30_master_clk, | |
192 | .clkr.hw.init = &(struct clk_init_data){ | |
193 | .name = "usb30_master_clk_src", | |
194 | .parent_names = gcc_xo_gpll0, | |
195 | .num_parents = 2, | |
196 | .ops = &clk_rcg2_ops, | |
197 | }, | |
198 | }; | |
199 | ||
200 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { | |
201 | F(19200000, P_XO, 1, 0, 0), | |
202 | F(37500000, P_GPLL0, 16, 0, 0), | |
203 | F(50000000, P_GPLL0, 12, 0, 0), | |
204 | { } | |
205 | }; | |
206 | ||
207 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { | |
208 | .cmd_rcgr = 0x0660, | |
209 | .hid_width = 5, | |
210 | .parent_map = gcc_xo_gpll0_map, | |
211 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
212 | .clkr.hw.init = &(struct clk_init_data){ | |
213 | .name = "blsp1_qup1_i2c_apps_clk_src", | |
214 | .parent_names = gcc_xo_gpll0, | |
215 | .num_parents = 2, | |
216 | .ops = &clk_rcg2_ops, | |
217 | }, | |
218 | }; | |
219 | ||
220 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { | |
221 | F(960000, P_XO, 10, 1, 2), | |
222 | F(4800000, P_XO, 4, 0, 0), | |
223 | F(9600000, P_XO, 2, 0, 0), | |
224 | F(15000000, P_GPLL0, 10, 1, 4), | |
225 | F(19200000, P_XO, 1, 0, 0), | |
226 | F(25000000, P_GPLL0, 12, 1, 2), | |
227 | F(50000000, P_GPLL0, 12, 0, 0), | |
228 | { } | |
229 | }; | |
230 | ||
231 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { | |
232 | .cmd_rcgr = 0x064c, | |
233 | .mnd_width = 8, | |
234 | .hid_width = 5, | |
235 | .parent_map = gcc_xo_gpll0_map, | |
236 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
237 | .clkr.hw.init = &(struct clk_init_data){ | |
238 | .name = "blsp1_qup1_spi_apps_clk_src", | |
239 | .parent_names = gcc_xo_gpll0, | |
240 | .num_parents = 2, | |
241 | .ops = &clk_rcg2_ops, | |
242 | }, | |
243 | }; | |
244 | ||
245 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { | |
246 | .cmd_rcgr = 0x06e0, | |
247 | .hid_width = 5, | |
248 | .parent_map = gcc_xo_gpll0_map, | |
249 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
250 | .clkr.hw.init = &(struct clk_init_data){ | |
251 | .name = "blsp1_qup2_i2c_apps_clk_src", | |
252 | .parent_names = gcc_xo_gpll0, | |
253 | .num_parents = 2, | |
254 | .ops = &clk_rcg2_ops, | |
255 | }, | |
256 | }; | |
257 | ||
258 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { | |
259 | .cmd_rcgr = 0x06cc, | |
260 | .mnd_width = 8, | |
261 | .hid_width = 5, | |
262 | .parent_map = gcc_xo_gpll0_map, | |
263 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
264 | .clkr.hw.init = &(struct clk_init_data){ | |
265 | .name = "blsp1_qup2_spi_apps_clk_src", | |
266 | .parent_names = gcc_xo_gpll0, | |
267 | .num_parents = 2, | |
268 | .ops = &clk_rcg2_ops, | |
269 | }, | |
270 | }; | |
271 | ||
272 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { | |
273 | .cmd_rcgr = 0x0760, | |
274 | .hid_width = 5, | |
275 | .parent_map = gcc_xo_gpll0_map, | |
276 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
277 | .clkr.hw.init = &(struct clk_init_data){ | |
278 | .name = "blsp1_qup3_i2c_apps_clk_src", | |
279 | .parent_names = gcc_xo_gpll0, | |
280 | .num_parents = 2, | |
281 | .ops = &clk_rcg2_ops, | |
282 | }, | |
283 | }; | |
284 | ||
285 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { | |
286 | .cmd_rcgr = 0x074c, | |
287 | .mnd_width = 8, | |
288 | .hid_width = 5, | |
289 | .parent_map = gcc_xo_gpll0_map, | |
290 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
291 | .clkr.hw.init = &(struct clk_init_data){ | |
292 | .name = "blsp1_qup3_spi_apps_clk_src", | |
293 | .parent_names = gcc_xo_gpll0, | |
294 | .num_parents = 2, | |
295 | .ops = &clk_rcg2_ops, | |
296 | }, | |
297 | }; | |
298 | ||
299 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { | |
300 | .cmd_rcgr = 0x07e0, | |
301 | .hid_width = 5, | |
302 | .parent_map = gcc_xo_gpll0_map, | |
303 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
304 | .clkr.hw.init = &(struct clk_init_data){ | |
305 | .name = "blsp1_qup4_i2c_apps_clk_src", | |
306 | .parent_names = gcc_xo_gpll0, | |
307 | .num_parents = 2, | |
308 | .ops = &clk_rcg2_ops, | |
309 | }, | |
310 | }; | |
311 | ||
312 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { | |
313 | .cmd_rcgr = 0x07cc, | |
314 | .mnd_width = 8, | |
315 | .hid_width = 5, | |
316 | .parent_map = gcc_xo_gpll0_map, | |
317 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
318 | .clkr.hw.init = &(struct clk_init_data){ | |
319 | .name = "blsp1_qup4_spi_apps_clk_src", | |
320 | .parent_names = gcc_xo_gpll0, | |
321 | .num_parents = 2, | |
322 | .ops = &clk_rcg2_ops, | |
323 | }, | |
324 | }; | |
325 | ||
326 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { | |
327 | .cmd_rcgr = 0x0860, | |
328 | .hid_width = 5, | |
329 | .parent_map = gcc_xo_gpll0_map, | |
330 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
331 | .clkr.hw.init = &(struct clk_init_data){ | |
332 | .name = "blsp1_qup5_i2c_apps_clk_src", | |
333 | .parent_names = gcc_xo_gpll0, | |
334 | .num_parents = 2, | |
335 | .ops = &clk_rcg2_ops, | |
336 | }, | |
337 | }; | |
338 | ||
339 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { | |
340 | .cmd_rcgr = 0x084c, | |
341 | .mnd_width = 8, | |
342 | .hid_width = 5, | |
343 | .parent_map = gcc_xo_gpll0_map, | |
344 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
345 | .clkr.hw.init = &(struct clk_init_data){ | |
346 | .name = "blsp1_qup5_spi_apps_clk_src", | |
347 | .parent_names = gcc_xo_gpll0, | |
348 | .num_parents = 2, | |
349 | .ops = &clk_rcg2_ops, | |
350 | }, | |
351 | }; | |
352 | ||
353 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { | |
354 | .cmd_rcgr = 0x08e0, | |
355 | .hid_width = 5, | |
356 | .parent_map = gcc_xo_gpll0_map, | |
357 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
358 | .clkr.hw.init = &(struct clk_init_data){ | |
359 | .name = "blsp1_qup6_i2c_apps_clk_src", | |
360 | .parent_names = gcc_xo_gpll0, | |
361 | .num_parents = 2, | |
362 | .ops = &clk_rcg2_ops, | |
363 | }, | |
364 | }; | |
365 | ||
366 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { | |
367 | .cmd_rcgr = 0x08cc, | |
368 | .mnd_width = 8, | |
369 | .hid_width = 5, | |
370 | .parent_map = gcc_xo_gpll0_map, | |
371 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
372 | .clkr.hw.init = &(struct clk_init_data){ | |
373 | .name = "blsp1_qup6_spi_apps_clk_src", | |
374 | .parent_names = gcc_xo_gpll0, | |
375 | .num_parents = 2, | |
376 | .ops = &clk_rcg2_ops, | |
377 | }, | |
378 | }; | |
379 | ||
380 | static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { | |
381 | F(3686400, P_GPLL0, 1, 96, 15625), | |
382 | F(7372800, P_GPLL0, 1, 192, 15625), | |
383 | F(14745600, P_GPLL0, 1, 384, 15625), | |
384 | F(16000000, P_GPLL0, 5, 2, 15), | |
385 | F(19200000, P_XO, 1, 0, 0), | |
386 | F(24000000, P_GPLL0, 5, 1, 5), | |
387 | F(32000000, P_GPLL0, 1, 4, 75), | |
388 | F(40000000, P_GPLL0, 15, 0, 0), | |
389 | F(46400000, P_GPLL0, 1, 29, 375), | |
390 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
391 | F(51200000, P_GPLL0, 1, 32, 375), | |
392 | F(56000000, P_GPLL0, 1, 7, 75), | |
393 | F(58982400, P_GPLL0, 1, 1536, 15625), | |
394 | F(60000000, P_GPLL0, 10, 0, 0), | |
395 | F(63160000, P_GPLL0, 9.5, 0, 0), | |
396 | { } | |
397 | }; | |
398 | ||
399 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { | |
400 | .cmd_rcgr = 0x068c, | |
401 | .mnd_width = 16, | |
402 | .hid_width = 5, | |
403 | .parent_map = gcc_xo_gpll0_map, | |
404 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
405 | .clkr.hw.init = &(struct clk_init_data){ | |
406 | .name = "blsp1_uart1_apps_clk_src", | |
407 | .parent_names = gcc_xo_gpll0, | |
408 | .num_parents = 2, | |
409 | .ops = &clk_rcg2_ops, | |
410 | }, | |
411 | }; | |
412 | ||
413 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { | |
414 | .cmd_rcgr = 0x070c, | |
415 | .mnd_width = 16, | |
416 | .hid_width = 5, | |
417 | .parent_map = gcc_xo_gpll0_map, | |
418 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
419 | .clkr.hw.init = &(struct clk_init_data){ | |
420 | .name = "blsp1_uart2_apps_clk_src", | |
421 | .parent_names = gcc_xo_gpll0, | |
422 | .num_parents = 2, | |
423 | .ops = &clk_rcg2_ops, | |
424 | }, | |
425 | }; | |
426 | ||
427 | static struct clk_rcg2 blsp1_uart3_apps_clk_src = { | |
428 | .cmd_rcgr = 0x078c, | |
429 | .mnd_width = 16, | |
430 | .hid_width = 5, | |
431 | .parent_map = gcc_xo_gpll0_map, | |
432 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
433 | .clkr.hw.init = &(struct clk_init_data){ | |
434 | .name = "blsp1_uart3_apps_clk_src", | |
435 | .parent_names = gcc_xo_gpll0, | |
436 | .num_parents = 2, | |
437 | .ops = &clk_rcg2_ops, | |
438 | }, | |
439 | }; | |
440 | ||
441 | static struct clk_rcg2 blsp1_uart4_apps_clk_src = { | |
442 | .cmd_rcgr = 0x080c, | |
443 | .mnd_width = 16, | |
444 | .hid_width = 5, | |
445 | .parent_map = gcc_xo_gpll0_map, | |
446 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
447 | .clkr.hw.init = &(struct clk_init_data){ | |
448 | .name = "blsp1_uart4_apps_clk_src", | |
449 | .parent_names = gcc_xo_gpll0, | |
450 | .num_parents = 2, | |
451 | .ops = &clk_rcg2_ops, | |
452 | }, | |
453 | }; | |
454 | ||
455 | static struct clk_rcg2 blsp1_uart5_apps_clk_src = { | |
456 | .cmd_rcgr = 0x088c, | |
457 | .mnd_width = 16, | |
458 | .hid_width = 5, | |
459 | .parent_map = gcc_xo_gpll0_map, | |
460 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
461 | .clkr.hw.init = &(struct clk_init_data){ | |
462 | .name = "blsp1_uart5_apps_clk_src", | |
463 | .parent_names = gcc_xo_gpll0, | |
464 | .num_parents = 2, | |
465 | .ops = &clk_rcg2_ops, | |
466 | }, | |
467 | }; | |
468 | ||
469 | static struct clk_rcg2 blsp1_uart6_apps_clk_src = { | |
470 | .cmd_rcgr = 0x090c, | |
471 | .mnd_width = 16, | |
472 | .hid_width = 5, | |
473 | .parent_map = gcc_xo_gpll0_map, | |
474 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
475 | .clkr.hw.init = &(struct clk_init_data){ | |
476 | .name = "blsp1_uart6_apps_clk_src", | |
477 | .parent_names = gcc_xo_gpll0, | |
478 | .num_parents = 2, | |
479 | .ops = &clk_rcg2_ops, | |
480 | }, | |
481 | }; | |
482 | ||
483 | static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { | |
484 | .cmd_rcgr = 0x09a0, | |
485 | .hid_width = 5, | |
486 | .parent_map = gcc_xo_gpll0_map, | |
487 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
488 | .clkr.hw.init = &(struct clk_init_data){ | |
489 | .name = "blsp2_qup1_i2c_apps_clk_src", | |
490 | .parent_names = gcc_xo_gpll0, | |
491 | .num_parents = 2, | |
492 | .ops = &clk_rcg2_ops, | |
493 | }, | |
494 | }; | |
495 | ||
496 | static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { | |
497 | .cmd_rcgr = 0x098c, | |
498 | .mnd_width = 8, | |
499 | .hid_width = 5, | |
500 | .parent_map = gcc_xo_gpll0_map, | |
501 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
502 | .clkr.hw.init = &(struct clk_init_data){ | |
503 | .name = "blsp2_qup1_spi_apps_clk_src", | |
504 | .parent_names = gcc_xo_gpll0, | |
505 | .num_parents = 2, | |
506 | .ops = &clk_rcg2_ops, | |
507 | }, | |
508 | }; | |
509 | ||
510 | static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { | |
511 | .cmd_rcgr = 0x0a20, | |
512 | .hid_width = 5, | |
513 | .parent_map = gcc_xo_gpll0_map, | |
514 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
515 | .clkr.hw.init = &(struct clk_init_data){ | |
516 | .name = "blsp2_qup2_i2c_apps_clk_src", | |
517 | .parent_names = gcc_xo_gpll0, | |
518 | .num_parents = 2, | |
519 | .ops = &clk_rcg2_ops, | |
520 | }, | |
521 | }; | |
522 | ||
523 | static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { | |
524 | .cmd_rcgr = 0x0a0c, | |
525 | .mnd_width = 8, | |
526 | .hid_width = 5, | |
527 | .parent_map = gcc_xo_gpll0_map, | |
528 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
529 | .clkr.hw.init = &(struct clk_init_data){ | |
530 | .name = "blsp2_qup2_spi_apps_clk_src", | |
531 | .parent_names = gcc_xo_gpll0, | |
532 | .num_parents = 2, | |
533 | .ops = &clk_rcg2_ops, | |
534 | }, | |
535 | }; | |
536 | ||
537 | static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { | |
538 | .cmd_rcgr = 0x0aa0, | |
539 | .hid_width = 5, | |
540 | .parent_map = gcc_xo_gpll0_map, | |
541 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
542 | .clkr.hw.init = &(struct clk_init_data){ | |
543 | .name = "blsp2_qup3_i2c_apps_clk_src", | |
544 | .parent_names = gcc_xo_gpll0, | |
545 | .num_parents = 2, | |
546 | .ops = &clk_rcg2_ops, | |
547 | }, | |
548 | }; | |
549 | ||
550 | static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { | |
551 | .cmd_rcgr = 0x0a8c, | |
552 | .mnd_width = 8, | |
553 | .hid_width = 5, | |
554 | .parent_map = gcc_xo_gpll0_map, | |
555 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
556 | .clkr.hw.init = &(struct clk_init_data){ | |
557 | .name = "blsp2_qup3_spi_apps_clk_src", | |
558 | .parent_names = gcc_xo_gpll0, | |
559 | .num_parents = 2, | |
560 | .ops = &clk_rcg2_ops, | |
561 | }, | |
562 | }; | |
563 | ||
564 | static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { | |
565 | .cmd_rcgr = 0x0b20, | |
566 | .hid_width = 5, | |
567 | .parent_map = gcc_xo_gpll0_map, | |
568 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
569 | .clkr.hw.init = &(struct clk_init_data){ | |
570 | .name = "blsp2_qup4_i2c_apps_clk_src", | |
571 | .parent_names = gcc_xo_gpll0, | |
572 | .num_parents = 2, | |
573 | .ops = &clk_rcg2_ops, | |
574 | }, | |
575 | }; | |
576 | ||
577 | static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { | |
578 | .cmd_rcgr = 0x0b0c, | |
579 | .mnd_width = 8, | |
580 | .hid_width = 5, | |
581 | .parent_map = gcc_xo_gpll0_map, | |
582 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
583 | .clkr.hw.init = &(struct clk_init_data){ | |
584 | .name = "blsp2_qup4_spi_apps_clk_src", | |
585 | .parent_names = gcc_xo_gpll0, | |
586 | .num_parents = 2, | |
587 | .ops = &clk_rcg2_ops, | |
588 | }, | |
589 | }; | |
590 | ||
591 | static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { | |
592 | .cmd_rcgr = 0x0ba0, | |
593 | .hid_width = 5, | |
594 | .parent_map = gcc_xo_gpll0_map, | |
595 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
596 | .clkr.hw.init = &(struct clk_init_data){ | |
597 | .name = "blsp2_qup5_i2c_apps_clk_src", | |
598 | .parent_names = gcc_xo_gpll0, | |
599 | .num_parents = 2, | |
600 | .ops = &clk_rcg2_ops, | |
601 | }, | |
602 | }; | |
603 | ||
604 | static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { | |
605 | .cmd_rcgr = 0x0b8c, | |
606 | .mnd_width = 8, | |
607 | .hid_width = 5, | |
608 | .parent_map = gcc_xo_gpll0_map, | |
609 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
610 | .clkr.hw.init = &(struct clk_init_data){ | |
611 | .name = "blsp2_qup5_spi_apps_clk_src", | |
612 | .parent_names = gcc_xo_gpll0, | |
613 | .num_parents = 2, | |
614 | .ops = &clk_rcg2_ops, | |
615 | }, | |
616 | }; | |
617 | ||
618 | static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { | |
619 | .cmd_rcgr = 0x0c20, | |
620 | .hid_width = 5, | |
621 | .parent_map = gcc_xo_gpll0_map, | |
622 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
623 | .clkr.hw.init = &(struct clk_init_data){ | |
624 | .name = "blsp2_qup6_i2c_apps_clk_src", | |
625 | .parent_names = gcc_xo_gpll0, | |
626 | .num_parents = 2, | |
627 | .ops = &clk_rcg2_ops, | |
628 | }, | |
629 | }; | |
630 | ||
631 | static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { | |
632 | .cmd_rcgr = 0x0c0c, | |
633 | .mnd_width = 8, | |
634 | .hid_width = 5, | |
635 | .parent_map = gcc_xo_gpll0_map, | |
636 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
637 | .clkr.hw.init = &(struct clk_init_data){ | |
638 | .name = "blsp2_qup6_spi_apps_clk_src", | |
639 | .parent_names = gcc_xo_gpll0, | |
640 | .num_parents = 2, | |
641 | .ops = &clk_rcg2_ops, | |
642 | }, | |
643 | }; | |
644 | ||
645 | static struct clk_rcg2 blsp2_uart1_apps_clk_src = { | |
646 | .cmd_rcgr = 0x09cc, | |
647 | .mnd_width = 16, | |
648 | .hid_width = 5, | |
649 | .parent_map = gcc_xo_gpll0_map, | |
650 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
651 | .clkr.hw.init = &(struct clk_init_data){ | |
652 | .name = "blsp2_uart1_apps_clk_src", | |
653 | .parent_names = gcc_xo_gpll0, | |
654 | .num_parents = 2, | |
655 | .ops = &clk_rcg2_ops, | |
656 | }, | |
657 | }; | |
658 | ||
659 | static struct clk_rcg2 blsp2_uart2_apps_clk_src = { | |
660 | .cmd_rcgr = 0x0a4c, | |
661 | .mnd_width = 16, | |
662 | .hid_width = 5, | |
663 | .parent_map = gcc_xo_gpll0_map, | |
664 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
665 | .clkr.hw.init = &(struct clk_init_data){ | |
666 | .name = "blsp2_uart2_apps_clk_src", | |
667 | .parent_names = gcc_xo_gpll0, | |
668 | .num_parents = 2, | |
669 | .ops = &clk_rcg2_ops, | |
670 | }, | |
671 | }; | |
672 | ||
673 | static struct clk_rcg2 blsp2_uart3_apps_clk_src = { | |
674 | .cmd_rcgr = 0x0acc, | |
675 | .mnd_width = 16, | |
676 | .hid_width = 5, | |
677 | .parent_map = gcc_xo_gpll0_map, | |
678 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
679 | .clkr.hw.init = &(struct clk_init_data){ | |
680 | .name = "blsp2_uart3_apps_clk_src", | |
681 | .parent_names = gcc_xo_gpll0, | |
682 | .num_parents = 2, | |
683 | .ops = &clk_rcg2_ops, | |
684 | }, | |
685 | }; | |
686 | ||
687 | static struct clk_rcg2 blsp2_uart4_apps_clk_src = { | |
688 | .cmd_rcgr = 0x0b4c, | |
689 | .mnd_width = 16, | |
690 | .hid_width = 5, | |
691 | .parent_map = gcc_xo_gpll0_map, | |
692 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
693 | .clkr.hw.init = &(struct clk_init_data){ | |
694 | .name = "blsp2_uart4_apps_clk_src", | |
695 | .parent_names = gcc_xo_gpll0, | |
696 | .num_parents = 2, | |
697 | .ops = &clk_rcg2_ops, | |
698 | }, | |
699 | }; | |
700 | ||
701 | static struct clk_rcg2 blsp2_uart5_apps_clk_src = { | |
702 | .cmd_rcgr = 0x0bcc, | |
703 | .mnd_width = 16, | |
704 | .hid_width = 5, | |
705 | .parent_map = gcc_xo_gpll0_map, | |
706 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
707 | .clkr.hw.init = &(struct clk_init_data){ | |
708 | .name = "blsp2_uart5_apps_clk_src", | |
709 | .parent_names = gcc_xo_gpll0, | |
710 | .num_parents = 2, | |
711 | .ops = &clk_rcg2_ops, | |
712 | }, | |
713 | }; | |
714 | ||
715 | static struct clk_rcg2 blsp2_uart6_apps_clk_src = { | |
716 | .cmd_rcgr = 0x0c4c, | |
717 | .mnd_width = 16, | |
718 | .hid_width = 5, | |
719 | .parent_map = gcc_xo_gpll0_map, | |
720 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
721 | .clkr.hw.init = &(struct clk_init_data){ | |
722 | .name = "blsp2_uart6_apps_clk_src", | |
723 | .parent_names = gcc_xo_gpll0, | |
724 | .num_parents = 2, | |
725 | .ops = &clk_rcg2_ops, | |
726 | }, | |
727 | }; | |
728 | ||
729 | static const struct freq_tbl ftbl_gcc_ce1_clk[] = { | |
730 | F(50000000, P_GPLL0, 12, 0, 0), | |
731 | F(75000000, P_GPLL0, 8, 0, 0), | |
732 | F(100000000, P_GPLL0, 6, 0, 0), | |
733 | F(150000000, P_GPLL0, 4, 0, 0), | |
734 | { } | |
735 | }; | |
736 | ||
737 | static struct clk_rcg2 ce1_clk_src = { | |
738 | .cmd_rcgr = 0x1050, | |
739 | .hid_width = 5, | |
740 | .parent_map = gcc_xo_gpll0_map, | |
741 | .freq_tbl = ftbl_gcc_ce1_clk, | |
742 | .clkr.hw.init = &(struct clk_init_data){ | |
743 | .name = "ce1_clk_src", | |
744 | .parent_names = gcc_xo_gpll0, | |
745 | .num_parents = 2, | |
746 | .ops = &clk_rcg2_ops, | |
747 | }, | |
748 | }; | |
749 | ||
750 | static const struct freq_tbl ftbl_gcc_ce2_clk[] = { | |
751 | F(50000000, P_GPLL0, 12, 0, 0), | |
752 | F(75000000, P_GPLL0, 8, 0, 0), | |
753 | F(100000000, P_GPLL0, 6, 0, 0), | |
754 | F(150000000, P_GPLL0, 4, 0, 0), | |
755 | { } | |
756 | }; | |
757 | ||
758 | static struct clk_rcg2 ce2_clk_src = { | |
759 | .cmd_rcgr = 0x1090, | |
760 | .hid_width = 5, | |
761 | .parent_map = gcc_xo_gpll0_map, | |
762 | .freq_tbl = ftbl_gcc_ce2_clk, | |
763 | .clkr.hw.init = &(struct clk_init_data){ | |
764 | .name = "ce2_clk_src", | |
765 | .parent_names = gcc_xo_gpll0, | |
766 | .num_parents = 2, | |
767 | .ops = &clk_rcg2_ops, | |
768 | }, | |
769 | }; | |
770 | ||
771 | static const struct freq_tbl ftbl_gcc_gp_clk[] = { | |
772 | F(4800000, P_XO, 4, 0, 0), | |
773 | F(6000000, P_GPLL0, 10, 1, 10), | |
774 | F(6750000, P_GPLL0, 1, 1, 89), | |
775 | F(8000000, P_GPLL0, 15, 1, 5), | |
776 | F(9600000, P_XO, 2, 0, 0), | |
777 | F(16000000, P_GPLL0, 1, 2, 75), | |
778 | F(19200000, P_XO, 1, 0, 0), | |
779 | F(24000000, P_GPLL0, 5, 1, 5), | |
780 | { } | |
781 | }; | |
782 | ||
783 | ||
784 | static struct clk_rcg2 gp1_clk_src = { | |
785 | .cmd_rcgr = 0x1904, | |
786 | .mnd_width = 8, | |
787 | .hid_width = 5, | |
788 | .parent_map = gcc_xo_gpll0_map, | |
789 | .freq_tbl = ftbl_gcc_gp_clk, | |
790 | .clkr.hw.init = &(struct clk_init_data){ | |
791 | .name = "gp1_clk_src", | |
792 | .parent_names = gcc_xo_gpll0, | |
793 | .num_parents = 2, | |
794 | .ops = &clk_rcg2_ops, | |
795 | }, | |
796 | }; | |
797 | ||
798 | static struct clk_rcg2 gp2_clk_src = { | |
799 | .cmd_rcgr = 0x1944, | |
800 | .mnd_width = 8, | |
801 | .hid_width = 5, | |
802 | .parent_map = gcc_xo_gpll0_map, | |
803 | .freq_tbl = ftbl_gcc_gp_clk, | |
804 | .clkr.hw.init = &(struct clk_init_data){ | |
805 | .name = "gp2_clk_src", | |
806 | .parent_names = gcc_xo_gpll0, | |
807 | .num_parents = 2, | |
808 | .ops = &clk_rcg2_ops, | |
809 | }, | |
810 | }; | |
811 | ||
812 | static struct clk_rcg2 gp3_clk_src = { | |
813 | .cmd_rcgr = 0x1984, | |
814 | .mnd_width = 8, | |
815 | .hid_width = 5, | |
816 | .parent_map = gcc_xo_gpll0_map, | |
817 | .freq_tbl = ftbl_gcc_gp_clk, | |
818 | .clkr.hw.init = &(struct clk_init_data){ | |
819 | .name = "gp3_clk_src", | |
820 | .parent_names = gcc_xo_gpll0, | |
821 | .num_parents = 2, | |
822 | .ops = &clk_rcg2_ops, | |
823 | }, | |
824 | }; | |
825 | ||
826 | static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { | |
827 | F(60000000, P_GPLL0, 10, 0, 0), | |
828 | { } | |
829 | }; | |
830 | ||
831 | static struct clk_rcg2 pdm2_clk_src = { | |
832 | .cmd_rcgr = 0x0cd0, | |
833 | .hid_width = 5, | |
834 | .parent_map = gcc_xo_gpll0_map, | |
835 | .freq_tbl = ftbl_gcc_pdm2_clk, | |
836 | .clkr.hw.init = &(struct clk_init_data){ | |
837 | .name = "pdm2_clk_src", | |
838 | .parent_names = gcc_xo_gpll0, | |
839 | .num_parents = 2, | |
840 | .ops = &clk_rcg2_ops, | |
841 | }, | |
842 | }; | |
843 | ||
844 | static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { | |
845 | F(144000, P_XO, 16, 3, 25), | |
846 | F(400000, P_XO, 12, 1, 4), | |
847 | F(20000000, P_GPLL0, 15, 1, 2), | |
848 | F(25000000, P_GPLL0, 12, 1, 2), | |
849 | F(50000000, P_GPLL0, 12, 0, 0), | |
850 | F(100000000, P_GPLL0, 6, 0, 0), | |
851 | F(200000000, P_GPLL0, 3, 0, 0), | |
852 | { } | |
853 | }; | |
854 | ||
c685841e SB |
855 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { |
856 | F(144000, P_XO, 16, 3, 25), | |
857 | F(400000, P_XO, 12, 1, 4), | |
858 | F(20000000, P_GPLL0, 15, 1, 2), | |
859 | F(25000000, P_GPLL0, 12, 1, 2), | |
860 | F(50000000, P_GPLL0, 12, 0, 0), | |
861 | F(100000000, P_GPLL0, 6, 0, 0), | |
862 | F(192000000, P_GPLL4, 4, 0, 0), | |
863 | F(200000000, P_GPLL0, 3, 0, 0), | |
864 | F(384000000, P_GPLL4, 2, 0, 0), | |
865 | { } | |
866 | }; | |
867 | ||
868 | static struct clk_init_data sdcc1_apps_clk_src_init = { | |
869 | .name = "sdcc1_apps_clk_src", | |
870 | .parent_names = gcc_xo_gpll0, | |
871 | .num_parents = 2, | |
872 | .ops = &clk_rcg2_ops, | |
873 | }; | |
874 | ||
d33faa9e SB |
875 | static struct clk_rcg2 sdcc1_apps_clk_src = { |
876 | .cmd_rcgr = 0x04d0, | |
877 | .mnd_width = 8, | |
878 | .hid_width = 5, | |
879 | .parent_map = gcc_xo_gpll0_map, | |
880 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
c685841e | 881 | .clkr.hw.init = &sdcc1_apps_clk_src_init, |
d33faa9e SB |
882 | }; |
883 | ||
884 | static struct clk_rcg2 sdcc2_apps_clk_src = { | |
885 | .cmd_rcgr = 0x0510, | |
886 | .mnd_width = 8, | |
887 | .hid_width = 5, | |
888 | .parent_map = gcc_xo_gpll0_map, | |
889 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
890 | .clkr.hw.init = &(struct clk_init_data){ | |
891 | .name = "sdcc2_apps_clk_src", | |
892 | .parent_names = gcc_xo_gpll0, | |
893 | .num_parents = 2, | |
894 | .ops = &clk_rcg2_ops, | |
895 | }, | |
896 | }; | |
897 | ||
898 | static struct clk_rcg2 sdcc3_apps_clk_src = { | |
899 | .cmd_rcgr = 0x0550, | |
900 | .mnd_width = 8, | |
901 | .hid_width = 5, | |
902 | .parent_map = gcc_xo_gpll0_map, | |
903 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
904 | .clkr.hw.init = &(struct clk_init_data){ | |
905 | .name = "sdcc3_apps_clk_src", | |
906 | .parent_names = gcc_xo_gpll0, | |
907 | .num_parents = 2, | |
908 | .ops = &clk_rcg2_ops, | |
909 | }, | |
910 | }; | |
911 | ||
912 | static struct clk_rcg2 sdcc4_apps_clk_src = { | |
913 | .cmd_rcgr = 0x0590, | |
914 | .mnd_width = 8, | |
915 | .hid_width = 5, | |
916 | .parent_map = gcc_xo_gpll0_map, | |
917 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
918 | .clkr.hw.init = &(struct clk_init_data){ | |
919 | .name = "sdcc4_apps_clk_src", | |
920 | .parent_names = gcc_xo_gpll0, | |
921 | .num_parents = 2, | |
922 | .ops = &clk_rcg2_ops, | |
923 | }, | |
924 | }; | |
925 | ||
926 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { | |
927 | F(105000, P_XO, 2, 1, 91), | |
928 | { } | |
929 | }; | |
930 | ||
931 | static struct clk_rcg2 tsif_ref_clk_src = { | |
932 | .cmd_rcgr = 0x0d90, | |
933 | .mnd_width = 8, | |
934 | .hid_width = 5, | |
935 | .parent_map = gcc_xo_gpll0_map, | |
936 | .freq_tbl = ftbl_gcc_tsif_ref_clk, | |
937 | .clkr.hw.init = &(struct clk_init_data){ | |
938 | .name = "tsif_ref_clk_src", | |
939 | .parent_names = gcc_xo_gpll0, | |
940 | .num_parents = 2, | |
941 | .ops = &clk_rcg2_ops, | |
942 | }, | |
943 | }; | |
944 | ||
945 | static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { | |
946 | F(60000000, P_GPLL0, 10, 0, 0), | |
947 | { } | |
948 | }; | |
949 | ||
950 | static struct clk_rcg2 usb30_mock_utmi_clk_src = { | |
951 | .cmd_rcgr = 0x03e8, | |
952 | .hid_width = 5, | |
953 | .parent_map = gcc_xo_gpll0_map, | |
954 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, | |
955 | .clkr.hw.init = &(struct clk_init_data){ | |
956 | .name = "usb30_mock_utmi_clk_src", | |
957 | .parent_names = gcc_xo_gpll0, | |
958 | .num_parents = 2, | |
959 | .ops = &clk_rcg2_ops, | |
960 | }, | |
961 | }; | |
962 | ||
963 | static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { | |
964 | F(60000000, P_GPLL0, 10, 0, 0), | |
965 | F(75000000, P_GPLL0, 8, 0, 0), | |
966 | { } | |
967 | }; | |
968 | ||
969 | static struct clk_rcg2 usb_hs_system_clk_src = { | |
970 | .cmd_rcgr = 0x0490, | |
971 | .hid_width = 5, | |
972 | .parent_map = gcc_xo_gpll0_map, | |
973 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, | |
974 | .clkr.hw.init = &(struct clk_init_data){ | |
975 | .name = "usb_hs_system_clk_src", | |
976 | .parent_names = gcc_xo_gpll0, | |
977 | .num_parents = 2, | |
978 | .ops = &clk_rcg2_ops, | |
979 | }, | |
980 | }; | |
981 | ||
982 | static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { | |
983 | F(480000000, P_GPLL1, 1, 0, 0), | |
984 | { } | |
985 | }; | |
986 | ||
987 | static u8 usb_hsic_clk_src_map[] = { | |
988 | [P_XO] = 0, | |
989 | [P_GPLL1] = 4, | |
990 | }; | |
991 | ||
992 | static struct clk_rcg2 usb_hsic_clk_src = { | |
993 | .cmd_rcgr = 0x0440, | |
994 | .hid_width = 5, | |
995 | .parent_map = usb_hsic_clk_src_map, | |
996 | .freq_tbl = ftbl_gcc_usb_hsic_clk, | |
997 | .clkr.hw.init = &(struct clk_init_data){ | |
998 | .name = "usb_hsic_clk_src", | |
999 | .parent_names = (const char *[]){ | |
1000 | "xo", | |
1001 | "gpll1_vote", | |
1002 | }, | |
1003 | .num_parents = 2, | |
1004 | .ops = &clk_rcg2_ops, | |
1005 | }, | |
1006 | }; | |
1007 | ||
1008 | static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { | |
1009 | F(9600000, P_XO, 2, 0, 0), | |
1010 | { } | |
1011 | }; | |
1012 | ||
1013 | static struct clk_rcg2 usb_hsic_io_cal_clk_src = { | |
1014 | .cmd_rcgr = 0x0458, | |
1015 | .hid_width = 5, | |
1016 | .parent_map = gcc_xo_gpll0_map, | |
1017 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, | |
1018 | .clkr.hw.init = &(struct clk_init_data){ | |
1019 | .name = "usb_hsic_io_cal_clk_src", | |
1020 | .parent_names = gcc_xo_gpll0, | |
1021 | .num_parents = 1, | |
1022 | .ops = &clk_rcg2_ops, | |
1023 | }, | |
1024 | }; | |
1025 | ||
1026 | static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { | |
1027 | F(60000000, P_GPLL0, 10, 0, 0), | |
1028 | F(75000000, P_GPLL0, 8, 0, 0), | |
1029 | { } | |
1030 | }; | |
1031 | ||
1032 | static struct clk_rcg2 usb_hsic_system_clk_src = { | |
1033 | .cmd_rcgr = 0x041c, | |
1034 | .hid_width = 5, | |
1035 | .parent_map = gcc_xo_gpll0_map, | |
1036 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, | |
1037 | .clkr.hw.init = &(struct clk_init_data){ | |
1038 | .name = "usb_hsic_system_clk_src", | |
1039 | .parent_names = gcc_xo_gpll0, | |
1040 | .num_parents = 2, | |
1041 | .ops = &clk_rcg2_ops, | |
1042 | }, | |
1043 | }; | |
1044 | ||
1045 | static struct clk_regmap gcc_mmss_gpll0_clk_src = { | |
1046 | .enable_reg = 0x1484, | |
1047 | .enable_mask = BIT(26), | |
1048 | .hw.init = &(struct clk_init_data){ | |
1049 | .name = "mmss_gpll0_vote", | |
1050 | .parent_names = (const char *[]){ | |
1051 | "gpll0_vote", | |
1052 | }, | |
1053 | .num_parents = 1, | |
1054 | .ops = &clk_branch_simple_ops, | |
1055 | }, | |
1056 | }; | |
1057 | ||
1058 | static struct clk_branch gcc_bam_dma_ahb_clk = { | |
1059 | .halt_reg = 0x0d44, | |
1060 | .halt_check = BRANCH_HALT_VOTED, | |
1061 | .clkr = { | |
1062 | .enable_reg = 0x1484, | |
1063 | .enable_mask = BIT(12), | |
1064 | .hw.init = &(struct clk_init_data){ | |
1065 | .name = "gcc_bam_dma_ahb_clk", | |
1066 | .parent_names = (const char *[]){ | |
1067 | "periph_noc_clk_src", | |
1068 | }, | |
1069 | .num_parents = 1, | |
1070 | .ops = &clk_branch2_ops, | |
1071 | }, | |
1072 | }, | |
1073 | }; | |
1074 | ||
1075 | static struct clk_branch gcc_blsp1_ahb_clk = { | |
1076 | .halt_reg = 0x05c4, | |
1077 | .halt_check = BRANCH_HALT_VOTED, | |
1078 | .clkr = { | |
1079 | .enable_reg = 0x1484, | |
1080 | .enable_mask = BIT(17), | |
1081 | .hw.init = &(struct clk_init_data){ | |
1082 | .name = "gcc_blsp1_ahb_clk", | |
1083 | .parent_names = (const char *[]){ | |
1084 | "periph_noc_clk_src", | |
1085 | }, | |
1086 | .num_parents = 1, | |
1087 | .ops = &clk_branch2_ops, | |
1088 | }, | |
1089 | }, | |
1090 | }; | |
1091 | ||
1092 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { | |
1093 | .halt_reg = 0x0648, | |
1094 | .clkr = { | |
1095 | .enable_reg = 0x0648, | |
1096 | .enable_mask = BIT(0), | |
1097 | .hw.init = &(struct clk_init_data){ | |
1098 | .name = "gcc_blsp1_qup1_i2c_apps_clk", | |
1099 | .parent_names = (const char *[]){ | |
1100 | "blsp1_qup1_i2c_apps_clk_src", | |
1101 | }, | |
1102 | .num_parents = 1, | |
1103 | .flags = CLK_SET_RATE_PARENT, | |
1104 | .ops = &clk_branch2_ops, | |
1105 | }, | |
1106 | }, | |
1107 | }; | |
1108 | ||
1109 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { | |
1110 | .halt_reg = 0x0644, | |
1111 | .clkr = { | |
1112 | .enable_reg = 0x0644, | |
1113 | .enable_mask = BIT(0), | |
1114 | .hw.init = &(struct clk_init_data){ | |
1115 | .name = "gcc_blsp1_qup1_spi_apps_clk", | |
1116 | .parent_names = (const char *[]){ | |
1117 | "blsp1_qup1_spi_apps_clk_src", | |
1118 | }, | |
1119 | .num_parents = 1, | |
1120 | .flags = CLK_SET_RATE_PARENT, | |
1121 | .ops = &clk_branch2_ops, | |
1122 | }, | |
1123 | }, | |
1124 | }; | |
1125 | ||
1126 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { | |
1127 | .halt_reg = 0x06c8, | |
1128 | .clkr = { | |
1129 | .enable_reg = 0x06c8, | |
1130 | .enable_mask = BIT(0), | |
1131 | .hw.init = &(struct clk_init_data){ | |
1132 | .name = "gcc_blsp1_qup2_i2c_apps_clk", | |
1133 | .parent_names = (const char *[]){ | |
1134 | "blsp1_qup2_i2c_apps_clk_src", | |
1135 | }, | |
1136 | .num_parents = 1, | |
1137 | .flags = CLK_SET_RATE_PARENT, | |
1138 | .ops = &clk_branch2_ops, | |
1139 | }, | |
1140 | }, | |
1141 | }; | |
1142 | ||
1143 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { | |
1144 | .halt_reg = 0x06c4, | |
1145 | .clkr = { | |
1146 | .enable_reg = 0x06c4, | |
1147 | .enable_mask = BIT(0), | |
1148 | .hw.init = &(struct clk_init_data){ | |
1149 | .name = "gcc_blsp1_qup2_spi_apps_clk", | |
1150 | .parent_names = (const char *[]){ | |
1151 | "blsp1_qup2_spi_apps_clk_src", | |
1152 | }, | |
1153 | .num_parents = 1, | |
1154 | .flags = CLK_SET_RATE_PARENT, | |
1155 | .ops = &clk_branch2_ops, | |
1156 | }, | |
1157 | }, | |
1158 | }; | |
1159 | ||
1160 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { | |
1161 | .halt_reg = 0x0748, | |
1162 | .clkr = { | |
1163 | .enable_reg = 0x0748, | |
1164 | .enable_mask = BIT(0), | |
1165 | .hw.init = &(struct clk_init_data){ | |
1166 | .name = "gcc_blsp1_qup3_i2c_apps_clk", | |
1167 | .parent_names = (const char *[]){ | |
1168 | "blsp1_qup3_i2c_apps_clk_src", | |
1169 | }, | |
1170 | .num_parents = 1, | |
1171 | .flags = CLK_SET_RATE_PARENT, | |
1172 | .ops = &clk_branch2_ops, | |
1173 | }, | |
1174 | }, | |
1175 | }; | |
1176 | ||
1177 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { | |
1178 | .halt_reg = 0x0744, | |
1179 | .clkr = { | |
1180 | .enable_reg = 0x0744, | |
1181 | .enable_mask = BIT(0), | |
1182 | .hw.init = &(struct clk_init_data){ | |
1183 | .name = "gcc_blsp1_qup3_spi_apps_clk", | |
1184 | .parent_names = (const char *[]){ | |
1185 | "blsp1_qup3_spi_apps_clk_src", | |
1186 | }, | |
1187 | .num_parents = 1, | |
1188 | .flags = CLK_SET_RATE_PARENT, | |
1189 | .ops = &clk_branch2_ops, | |
1190 | }, | |
1191 | }, | |
1192 | }; | |
1193 | ||
1194 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { | |
1195 | .halt_reg = 0x07c8, | |
1196 | .clkr = { | |
1197 | .enable_reg = 0x07c8, | |
1198 | .enable_mask = BIT(0), | |
1199 | .hw.init = &(struct clk_init_data){ | |
1200 | .name = "gcc_blsp1_qup4_i2c_apps_clk", | |
1201 | .parent_names = (const char *[]){ | |
1202 | "blsp1_qup4_i2c_apps_clk_src", | |
1203 | }, | |
1204 | .num_parents = 1, | |
1205 | .flags = CLK_SET_RATE_PARENT, | |
1206 | .ops = &clk_branch2_ops, | |
1207 | }, | |
1208 | }, | |
1209 | }; | |
1210 | ||
1211 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { | |
1212 | .halt_reg = 0x07c4, | |
1213 | .clkr = { | |
1214 | .enable_reg = 0x07c4, | |
1215 | .enable_mask = BIT(0), | |
1216 | .hw.init = &(struct clk_init_data){ | |
1217 | .name = "gcc_blsp1_qup4_spi_apps_clk", | |
1218 | .parent_names = (const char *[]){ | |
1219 | "blsp1_qup4_spi_apps_clk_src", | |
1220 | }, | |
1221 | .num_parents = 1, | |
1222 | .flags = CLK_SET_RATE_PARENT, | |
1223 | .ops = &clk_branch2_ops, | |
1224 | }, | |
1225 | }, | |
1226 | }; | |
1227 | ||
1228 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { | |
1229 | .halt_reg = 0x0848, | |
1230 | .clkr = { | |
1231 | .enable_reg = 0x0848, | |
1232 | .enable_mask = BIT(0), | |
1233 | .hw.init = &(struct clk_init_data){ | |
1234 | .name = "gcc_blsp1_qup5_i2c_apps_clk", | |
1235 | .parent_names = (const char *[]){ | |
1236 | "blsp1_qup5_i2c_apps_clk_src", | |
1237 | }, | |
1238 | .num_parents = 1, | |
1239 | .flags = CLK_SET_RATE_PARENT, | |
1240 | .ops = &clk_branch2_ops, | |
1241 | }, | |
1242 | }, | |
1243 | }; | |
1244 | ||
1245 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { | |
1246 | .halt_reg = 0x0844, | |
1247 | .clkr = { | |
1248 | .enable_reg = 0x0844, | |
1249 | .enable_mask = BIT(0), | |
1250 | .hw.init = &(struct clk_init_data){ | |
1251 | .name = "gcc_blsp1_qup5_spi_apps_clk", | |
1252 | .parent_names = (const char *[]){ | |
1253 | "blsp1_qup5_spi_apps_clk_src", | |
1254 | }, | |
1255 | .num_parents = 1, | |
1256 | .flags = CLK_SET_RATE_PARENT, | |
1257 | .ops = &clk_branch2_ops, | |
1258 | }, | |
1259 | }, | |
1260 | }; | |
1261 | ||
1262 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { | |
1263 | .halt_reg = 0x08c8, | |
1264 | .clkr = { | |
1265 | .enable_reg = 0x08c8, | |
1266 | .enable_mask = BIT(0), | |
1267 | .hw.init = &(struct clk_init_data){ | |
1268 | .name = "gcc_blsp1_qup6_i2c_apps_clk", | |
1269 | .parent_names = (const char *[]){ | |
1270 | "blsp1_qup6_i2c_apps_clk_src", | |
1271 | }, | |
1272 | .num_parents = 1, | |
1273 | .flags = CLK_SET_RATE_PARENT, | |
1274 | .ops = &clk_branch2_ops, | |
1275 | }, | |
1276 | }, | |
1277 | }; | |
1278 | ||
1279 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { | |
1280 | .halt_reg = 0x08c4, | |
1281 | .clkr = { | |
1282 | .enable_reg = 0x08c4, | |
1283 | .enable_mask = BIT(0), | |
1284 | .hw.init = &(struct clk_init_data){ | |
1285 | .name = "gcc_blsp1_qup6_spi_apps_clk", | |
1286 | .parent_names = (const char *[]){ | |
1287 | "blsp1_qup6_spi_apps_clk_src", | |
1288 | }, | |
1289 | .num_parents = 1, | |
1290 | .flags = CLK_SET_RATE_PARENT, | |
1291 | .ops = &clk_branch2_ops, | |
1292 | }, | |
1293 | }, | |
1294 | }; | |
1295 | ||
1296 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { | |
1297 | .halt_reg = 0x0684, | |
1298 | .clkr = { | |
1299 | .enable_reg = 0x0684, | |
1300 | .enable_mask = BIT(0), | |
1301 | .hw.init = &(struct clk_init_data){ | |
1302 | .name = "gcc_blsp1_uart1_apps_clk", | |
1303 | .parent_names = (const char *[]){ | |
1304 | "blsp1_uart1_apps_clk_src", | |
1305 | }, | |
1306 | .num_parents = 1, | |
1307 | .flags = CLK_SET_RATE_PARENT, | |
1308 | .ops = &clk_branch2_ops, | |
1309 | }, | |
1310 | }, | |
1311 | }; | |
1312 | ||
1313 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { | |
1314 | .halt_reg = 0x0704, | |
1315 | .clkr = { | |
1316 | .enable_reg = 0x0704, | |
1317 | .enable_mask = BIT(0), | |
1318 | .hw.init = &(struct clk_init_data){ | |
1319 | .name = "gcc_blsp1_uart2_apps_clk", | |
1320 | .parent_names = (const char *[]){ | |
1321 | "blsp1_uart2_apps_clk_src", | |
1322 | }, | |
1323 | .num_parents = 1, | |
1324 | .flags = CLK_SET_RATE_PARENT, | |
1325 | .ops = &clk_branch2_ops, | |
1326 | }, | |
1327 | }, | |
1328 | }; | |
1329 | ||
1330 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { | |
1331 | .halt_reg = 0x0784, | |
1332 | .clkr = { | |
1333 | .enable_reg = 0x0784, | |
1334 | .enable_mask = BIT(0), | |
1335 | .hw.init = &(struct clk_init_data){ | |
1336 | .name = "gcc_blsp1_uart3_apps_clk", | |
1337 | .parent_names = (const char *[]){ | |
1338 | "blsp1_uart3_apps_clk_src", | |
1339 | }, | |
1340 | .num_parents = 1, | |
1341 | .flags = CLK_SET_RATE_PARENT, | |
1342 | .ops = &clk_branch2_ops, | |
1343 | }, | |
1344 | }, | |
1345 | }; | |
1346 | ||
1347 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { | |
1348 | .halt_reg = 0x0804, | |
1349 | .clkr = { | |
1350 | .enable_reg = 0x0804, | |
1351 | .enable_mask = BIT(0), | |
1352 | .hw.init = &(struct clk_init_data){ | |
1353 | .name = "gcc_blsp1_uart4_apps_clk", | |
1354 | .parent_names = (const char *[]){ | |
1355 | "blsp1_uart4_apps_clk_src", | |
1356 | }, | |
1357 | .num_parents = 1, | |
1358 | .flags = CLK_SET_RATE_PARENT, | |
1359 | .ops = &clk_branch2_ops, | |
1360 | }, | |
1361 | }, | |
1362 | }; | |
1363 | ||
1364 | static struct clk_branch gcc_blsp1_uart5_apps_clk = { | |
1365 | .halt_reg = 0x0884, | |
1366 | .clkr = { | |
1367 | .enable_reg = 0x0884, | |
1368 | .enable_mask = BIT(0), | |
1369 | .hw.init = &(struct clk_init_data){ | |
1370 | .name = "gcc_blsp1_uart5_apps_clk", | |
1371 | .parent_names = (const char *[]){ | |
1372 | "blsp1_uart5_apps_clk_src", | |
1373 | }, | |
1374 | .num_parents = 1, | |
1375 | .flags = CLK_SET_RATE_PARENT, | |
1376 | .ops = &clk_branch2_ops, | |
1377 | }, | |
1378 | }, | |
1379 | }; | |
1380 | ||
1381 | static struct clk_branch gcc_blsp1_uart6_apps_clk = { | |
1382 | .halt_reg = 0x0904, | |
1383 | .clkr = { | |
1384 | .enable_reg = 0x0904, | |
1385 | .enable_mask = BIT(0), | |
1386 | .hw.init = &(struct clk_init_data){ | |
1387 | .name = "gcc_blsp1_uart6_apps_clk", | |
1388 | .parent_names = (const char *[]){ | |
1389 | "blsp1_uart6_apps_clk_src", | |
1390 | }, | |
1391 | .num_parents = 1, | |
1392 | .flags = CLK_SET_RATE_PARENT, | |
1393 | .ops = &clk_branch2_ops, | |
1394 | }, | |
1395 | }, | |
1396 | }; | |
1397 | ||
1398 | static struct clk_branch gcc_blsp2_ahb_clk = { | |
63a00269 | 1399 | .halt_reg = 0x0944, |
d33faa9e SB |
1400 | .halt_check = BRANCH_HALT_VOTED, |
1401 | .clkr = { | |
1402 | .enable_reg = 0x1484, | |
1403 | .enable_mask = BIT(15), | |
1404 | .hw.init = &(struct clk_init_data){ | |
1405 | .name = "gcc_blsp2_ahb_clk", | |
1406 | .parent_names = (const char *[]){ | |
1407 | "periph_noc_clk_src", | |
1408 | }, | |
1409 | .num_parents = 1, | |
1410 | .ops = &clk_branch2_ops, | |
1411 | }, | |
1412 | }, | |
1413 | }; | |
1414 | ||
1415 | static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { | |
1416 | .halt_reg = 0x0988, | |
1417 | .clkr = { | |
1418 | .enable_reg = 0x0988, | |
1419 | .enable_mask = BIT(0), | |
1420 | .hw.init = &(struct clk_init_data){ | |
1421 | .name = "gcc_blsp2_qup1_i2c_apps_clk", | |
1422 | .parent_names = (const char *[]){ | |
1423 | "blsp2_qup1_i2c_apps_clk_src", | |
1424 | }, | |
1425 | .num_parents = 1, | |
1426 | .flags = CLK_SET_RATE_PARENT, | |
1427 | .ops = &clk_branch2_ops, | |
1428 | }, | |
1429 | }, | |
1430 | }; | |
1431 | ||
1432 | static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { | |
1433 | .halt_reg = 0x0984, | |
1434 | .clkr = { | |
1435 | .enable_reg = 0x0984, | |
1436 | .enable_mask = BIT(0), | |
1437 | .hw.init = &(struct clk_init_data){ | |
1438 | .name = "gcc_blsp2_qup1_spi_apps_clk", | |
1439 | .parent_names = (const char *[]){ | |
1440 | "blsp2_qup1_spi_apps_clk_src", | |
1441 | }, | |
1442 | .num_parents = 1, | |
1443 | .flags = CLK_SET_RATE_PARENT, | |
1444 | .ops = &clk_branch2_ops, | |
1445 | }, | |
1446 | }, | |
1447 | }; | |
1448 | ||
1449 | static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { | |
1450 | .halt_reg = 0x0a08, | |
1451 | .clkr = { | |
1452 | .enable_reg = 0x0a08, | |
1453 | .enable_mask = BIT(0), | |
1454 | .hw.init = &(struct clk_init_data){ | |
1455 | .name = "gcc_blsp2_qup2_i2c_apps_clk", | |
1456 | .parent_names = (const char *[]){ | |
1457 | "blsp2_qup2_i2c_apps_clk_src", | |
1458 | }, | |
1459 | .num_parents = 1, | |
1460 | .flags = CLK_SET_RATE_PARENT, | |
1461 | .ops = &clk_branch2_ops, | |
1462 | }, | |
1463 | }, | |
1464 | }; | |
1465 | ||
1466 | static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { | |
1467 | .halt_reg = 0x0a04, | |
1468 | .clkr = { | |
1469 | .enable_reg = 0x0a04, | |
1470 | .enable_mask = BIT(0), | |
1471 | .hw.init = &(struct clk_init_data){ | |
1472 | .name = "gcc_blsp2_qup2_spi_apps_clk", | |
1473 | .parent_names = (const char *[]){ | |
1474 | "blsp2_qup2_spi_apps_clk_src", | |
1475 | }, | |
1476 | .num_parents = 1, | |
1477 | .flags = CLK_SET_RATE_PARENT, | |
1478 | .ops = &clk_branch2_ops, | |
1479 | }, | |
1480 | }, | |
1481 | }; | |
1482 | ||
1483 | static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { | |
1484 | .halt_reg = 0x0a88, | |
1485 | .clkr = { | |
1486 | .enable_reg = 0x0a88, | |
1487 | .enable_mask = BIT(0), | |
1488 | .hw.init = &(struct clk_init_data){ | |
1489 | .name = "gcc_blsp2_qup3_i2c_apps_clk", | |
1490 | .parent_names = (const char *[]){ | |
1491 | "blsp2_qup3_i2c_apps_clk_src", | |
1492 | }, | |
1493 | .num_parents = 1, | |
1494 | .flags = CLK_SET_RATE_PARENT, | |
1495 | .ops = &clk_branch2_ops, | |
1496 | }, | |
1497 | }, | |
1498 | }; | |
1499 | ||
1500 | static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { | |
1501 | .halt_reg = 0x0a84, | |
1502 | .clkr = { | |
1503 | .enable_reg = 0x0a84, | |
1504 | .enable_mask = BIT(0), | |
1505 | .hw.init = &(struct clk_init_data){ | |
1506 | .name = "gcc_blsp2_qup3_spi_apps_clk", | |
1507 | .parent_names = (const char *[]){ | |
1508 | "blsp2_qup3_spi_apps_clk_src", | |
1509 | }, | |
1510 | .num_parents = 1, | |
1511 | .flags = CLK_SET_RATE_PARENT, | |
1512 | .ops = &clk_branch2_ops, | |
1513 | }, | |
1514 | }, | |
1515 | }; | |
1516 | ||
1517 | static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { | |
1518 | .halt_reg = 0x0b08, | |
1519 | .clkr = { | |
1520 | .enable_reg = 0x0b08, | |
1521 | .enable_mask = BIT(0), | |
1522 | .hw.init = &(struct clk_init_data){ | |
1523 | .name = "gcc_blsp2_qup4_i2c_apps_clk", | |
1524 | .parent_names = (const char *[]){ | |
1525 | "blsp2_qup4_i2c_apps_clk_src", | |
1526 | }, | |
1527 | .num_parents = 1, | |
1528 | .flags = CLK_SET_RATE_PARENT, | |
1529 | .ops = &clk_branch2_ops, | |
1530 | }, | |
1531 | }, | |
1532 | }; | |
1533 | ||
1534 | static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { | |
1535 | .halt_reg = 0x0b04, | |
1536 | .clkr = { | |
1537 | .enable_reg = 0x0b04, | |
1538 | .enable_mask = BIT(0), | |
1539 | .hw.init = &(struct clk_init_data){ | |
1540 | .name = "gcc_blsp2_qup4_spi_apps_clk", | |
1541 | .parent_names = (const char *[]){ | |
1542 | "blsp2_qup4_spi_apps_clk_src", | |
1543 | }, | |
1544 | .num_parents = 1, | |
1545 | .flags = CLK_SET_RATE_PARENT, | |
1546 | .ops = &clk_branch2_ops, | |
1547 | }, | |
1548 | }, | |
1549 | }; | |
1550 | ||
1551 | static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { | |
1552 | .halt_reg = 0x0b88, | |
1553 | .clkr = { | |
1554 | .enable_reg = 0x0b88, | |
1555 | .enable_mask = BIT(0), | |
1556 | .hw.init = &(struct clk_init_data){ | |
1557 | .name = "gcc_blsp2_qup5_i2c_apps_clk", | |
1558 | .parent_names = (const char *[]){ | |
1559 | "blsp2_qup5_i2c_apps_clk_src", | |
1560 | }, | |
1561 | .num_parents = 1, | |
1562 | .flags = CLK_SET_RATE_PARENT, | |
1563 | .ops = &clk_branch2_ops, | |
1564 | }, | |
1565 | }, | |
1566 | }; | |
1567 | ||
1568 | static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { | |
1569 | .halt_reg = 0x0b84, | |
1570 | .clkr = { | |
1571 | .enable_reg = 0x0b84, | |
1572 | .enable_mask = BIT(0), | |
1573 | .hw.init = &(struct clk_init_data){ | |
1574 | .name = "gcc_blsp2_qup5_spi_apps_clk", | |
1575 | .parent_names = (const char *[]){ | |
1576 | "blsp2_qup5_spi_apps_clk_src", | |
1577 | }, | |
1578 | .num_parents = 1, | |
1579 | .flags = CLK_SET_RATE_PARENT, | |
1580 | .ops = &clk_branch2_ops, | |
1581 | }, | |
1582 | }, | |
1583 | }; | |
1584 | ||
1585 | static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { | |
1586 | .halt_reg = 0x0c08, | |
1587 | .clkr = { | |
1588 | .enable_reg = 0x0c08, | |
1589 | .enable_mask = BIT(0), | |
1590 | .hw.init = &(struct clk_init_data){ | |
1591 | .name = "gcc_blsp2_qup6_i2c_apps_clk", | |
1592 | .parent_names = (const char *[]){ | |
1593 | "blsp2_qup6_i2c_apps_clk_src", | |
1594 | }, | |
1595 | .num_parents = 1, | |
1596 | .flags = CLK_SET_RATE_PARENT, | |
1597 | .ops = &clk_branch2_ops, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
1602 | static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { | |
1603 | .halt_reg = 0x0c04, | |
1604 | .clkr = { | |
1605 | .enable_reg = 0x0c04, | |
1606 | .enable_mask = BIT(0), | |
1607 | .hw.init = &(struct clk_init_data){ | |
1608 | .name = "gcc_blsp2_qup6_spi_apps_clk", | |
1609 | .parent_names = (const char *[]){ | |
1610 | "blsp2_qup6_spi_apps_clk_src", | |
1611 | }, | |
1612 | .num_parents = 1, | |
1613 | .flags = CLK_SET_RATE_PARENT, | |
1614 | .ops = &clk_branch2_ops, | |
1615 | }, | |
1616 | }, | |
1617 | }; | |
1618 | ||
1619 | static struct clk_branch gcc_blsp2_uart1_apps_clk = { | |
1620 | .halt_reg = 0x09c4, | |
1621 | .clkr = { | |
1622 | .enable_reg = 0x09c4, | |
1623 | .enable_mask = BIT(0), | |
1624 | .hw.init = &(struct clk_init_data){ | |
1625 | .name = "gcc_blsp2_uart1_apps_clk", | |
1626 | .parent_names = (const char *[]){ | |
1627 | "blsp2_uart1_apps_clk_src", | |
1628 | }, | |
1629 | .num_parents = 1, | |
1630 | .flags = CLK_SET_RATE_PARENT, | |
1631 | .ops = &clk_branch2_ops, | |
1632 | }, | |
1633 | }, | |
1634 | }; | |
1635 | ||
1636 | static struct clk_branch gcc_blsp2_uart2_apps_clk = { | |
1637 | .halt_reg = 0x0a44, | |
1638 | .clkr = { | |
1639 | .enable_reg = 0x0a44, | |
1640 | .enable_mask = BIT(0), | |
1641 | .hw.init = &(struct clk_init_data){ | |
1642 | .name = "gcc_blsp2_uart2_apps_clk", | |
1643 | .parent_names = (const char *[]){ | |
1644 | "blsp2_uart2_apps_clk_src", | |
1645 | }, | |
1646 | .num_parents = 1, | |
1647 | .flags = CLK_SET_RATE_PARENT, | |
1648 | .ops = &clk_branch2_ops, | |
1649 | }, | |
1650 | }, | |
1651 | }; | |
1652 | ||
1653 | static struct clk_branch gcc_blsp2_uart3_apps_clk = { | |
1654 | .halt_reg = 0x0ac4, | |
1655 | .clkr = { | |
1656 | .enable_reg = 0x0ac4, | |
1657 | .enable_mask = BIT(0), | |
1658 | .hw.init = &(struct clk_init_data){ | |
1659 | .name = "gcc_blsp2_uart3_apps_clk", | |
1660 | .parent_names = (const char *[]){ | |
1661 | "blsp2_uart3_apps_clk_src", | |
1662 | }, | |
1663 | .num_parents = 1, | |
1664 | .flags = CLK_SET_RATE_PARENT, | |
1665 | .ops = &clk_branch2_ops, | |
1666 | }, | |
1667 | }, | |
1668 | }; | |
1669 | ||
1670 | static struct clk_branch gcc_blsp2_uart4_apps_clk = { | |
1671 | .halt_reg = 0x0b44, | |
1672 | .clkr = { | |
1673 | .enable_reg = 0x0b44, | |
1674 | .enable_mask = BIT(0), | |
1675 | .hw.init = &(struct clk_init_data){ | |
1676 | .name = "gcc_blsp2_uart4_apps_clk", | |
1677 | .parent_names = (const char *[]){ | |
1678 | "blsp2_uart4_apps_clk_src", | |
1679 | }, | |
1680 | .num_parents = 1, | |
1681 | .flags = CLK_SET_RATE_PARENT, | |
1682 | .ops = &clk_branch2_ops, | |
1683 | }, | |
1684 | }, | |
1685 | }; | |
1686 | ||
1687 | static struct clk_branch gcc_blsp2_uart5_apps_clk = { | |
1688 | .halt_reg = 0x0bc4, | |
1689 | .clkr = { | |
1690 | .enable_reg = 0x0bc4, | |
1691 | .enable_mask = BIT(0), | |
1692 | .hw.init = &(struct clk_init_data){ | |
1693 | .name = "gcc_blsp2_uart5_apps_clk", | |
1694 | .parent_names = (const char *[]){ | |
1695 | "blsp2_uart5_apps_clk_src", | |
1696 | }, | |
1697 | .num_parents = 1, | |
1698 | .flags = CLK_SET_RATE_PARENT, | |
1699 | .ops = &clk_branch2_ops, | |
1700 | }, | |
1701 | }, | |
1702 | }; | |
1703 | ||
1704 | static struct clk_branch gcc_blsp2_uart6_apps_clk = { | |
1705 | .halt_reg = 0x0c44, | |
1706 | .clkr = { | |
1707 | .enable_reg = 0x0c44, | |
1708 | .enable_mask = BIT(0), | |
1709 | .hw.init = &(struct clk_init_data){ | |
1710 | .name = "gcc_blsp2_uart6_apps_clk", | |
1711 | .parent_names = (const char *[]){ | |
1712 | "blsp2_uart6_apps_clk_src", | |
1713 | }, | |
1714 | .num_parents = 1, | |
1715 | .flags = CLK_SET_RATE_PARENT, | |
1716 | .ops = &clk_branch2_ops, | |
1717 | }, | |
1718 | }, | |
1719 | }; | |
1720 | ||
1721 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
1722 | .halt_reg = 0x0e04, | |
1723 | .halt_check = BRANCH_HALT_VOTED, | |
1724 | .clkr = { | |
1725 | .enable_reg = 0x1484, | |
1726 | .enable_mask = BIT(10), | |
1727 | .hw.init = &(struct clk_init_data){ | |
1728 | .name = "gcc_boot_rom_ahb_clk", | |
1729 | .parent_names = (const char *[]){ | |
1730 | "config_noc_clk_src", | |
1731 | }, | |
1732 | .num_parents = 1, | |
1733 | .ops = &clk_branch2_ops, | |
1734 | }, | |
1735 | }, | |
1736 | }; | |
1737 | ||
1738 | static struct clk_branch gcc_ce1_ahb_clk = { | |
1739 | .halt_reg = 0x104c, | |
1740 | .halt_check = BRANCH_HALT_VOTED, | |
1741 | .clkr = { | |
1742 | .enable_reg = 0x1484, | |
1743 | .enable_mask = BIT(3), | |
1744 | .hw.init = &(struct clk_init_data){ | |
1745 | .name = "gcc_ce1_ahb_clk", | |
1746 | .parent_names = (const char *[]){ | |
1747 | "config_noc_clk_src", | |
1748 | }, | |
1749 | .num_parents = 1, | |
1750 | .ops = &clk_branch2_ops, | |
1751 | }, | |
1752 | }, | |
1753 | }; | |
1754 | ||
1755 | static struct clk_branch gcc_ce1_axi_clk = { | |
1756 | .halt_reg = 0x1048, | |
1757 | .halt_check = BRANCH_HALT_VOTED, | |
1758 | .clkr = { | |
1759 | .enable_reg = 0x1484, | |
1760 | .enable_mask = BIT(4), | |
1761 | .hw.init = &(struct clk_init_data){ | |
1762 | .name = "gcc_ce1_axi_clk", | |
1763 | .parent_names = (const char *[]){ | |
1764 | "system_noc_clk_src", | |
1765 | }, | |
1766 | .num_parents = 1, | |
1767 | .ops = &clk_branch2_ops, | |
1768 | }, | |
1769 | }, | |
1770 | }; | |
1771 | ||
1772 | static struct clk_branch gcc_ce1_clk = { | |
1773 | .halt_reg = 0x1050, | |
1774 | .halt_check = BRANCH_HALT_VOTED, | |
1775 | .clkr = { | |
1776 | .enable_reg = 0x1484, | |
1777 | .enable_mask = BIT(5), | |
1778 | .hw.init = &(struct clk_init_data){ | |
1779 | .name = "gcc_ce1_clk", | |
1780 | .parent_names = (const char *[]){ | |
1781 | "ce1_clk_src", | |
1782 | }, | |
1783 | .num_parents = 1, | |
1784 | .ops = &clk_branch2_ops, | |
1785 | }, | |
1786 | }, | |
1787 | }; | |
1788 | ||
1789 | static struct clk_branch gcc_ce2_ahb_clk = { | |
1790 | .halt_reg = 0x108c, | |
1791 | .halt_check = BRANCH_HALT_VOTED, | |
1792 | .clkr = { | |
1793 | .enable_reg = 0x1484, | |
1794 | .enable_mask = BIT(0), | |
1795 | .hw.init = &(struct clk_init_data){ | |
1796 | .name = "gcc_ce2_ahb_clk", | |
1797 | .parent_names = (const char *[]){ | |
1798 | "config_noc_clk_src", | |
1799 | }, | |
1800 | .num_parents = 1, | |
1801 | .ops = &clk_branch2_ops, | |
1802 | }, | |
1803 | }, | |
1804 | }; | |
1805 | ||
1806 | static struct clk_branch gcc_ce2_axi_clk = { | |
1807 | .halt_reg = 0x1088, | |
1808 | .halt_check = BRANCH_HALT_VOTED, | |
1809 | .clkr = { | |
1810 | .enable_reg = 0x1484, | |
1811 | .enable_mask = BIT(1), | |
1812 | .hw.init = &(struct clk_init_data){ | |
1813 | .name = "gcc_ce2_axi_clk", | |
1814 | .parent_names = (const char *[]){ | |
1815 | "system_noc_clk_src", | |
1816 | }, | |
1817 | .num_parents = 1, | |
1818 | .ops = &clk_branch2_ops, | |
1819 | }, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static struct clk_branch gcc_ce2_clk = { | |
1824 | .halt_reg = 0x1090, | |
1825 | .halt_check = BRANCH_HALT_VOTED, | |
1826 | .clkr = { | |
1827 | .enable_reg = 0x1484, | |
1828 | .enable_mask = BIT(2), | |
1829 | .hw.init = &(struct clk_init_data){ | |
1830 | .name = "gcc_ce2_clk", | |
1831 | .parent_names = (const char *[]){ | |
1832 | "ce2_clk_src", | |
1833 | }, | |
1834 | .num_parents = 1, | |
1835 | .flags = CLK_SET_RATE_PARENT, | |
1836 | .ops = &clk_branch2_ops, | |
1837 | }, | |
1838 | }, | |
1839 | }; | |
1840 | ||
1841 | static struct clk_branch gcc_gp1_clk = { | |
1842 | .halt_reg = 0x1900, | |
1843 | .clkr = { | |
1844 | .enable_reg = 0x1900, | |
1845 | .enable_mask = BIT(0), | |
1846 | .hw.init = &(struct clk_init_data){ | |
1847 | .name = "gcc_gp1_clk", | |
1848 | .parent_names = (const char *[]){ | |
1849 | "gp1_clk_src", | |
1850 | }, | |
1851 | .num_parents = 1, | |
1852 | .flags = CLK_SET_RATE_PARENT, | |
1853 | .ops = &clk_branch2_ops, | |
1854 | }, | |
1855 | }, | |
1856 | }; | |
1857 | ||
1858 | static struct clk_branch gcc_gp2_clk = { | |
1859 | .halt_reg = 0x1940, | |
1860 | .clkr = { | |
1861 | .enable_reg = 0x1940, | |
1862 | .enable_mask = BIT(0), | |
1863 | .hw.init = &(struct clk_init_data){ | |
1864 | .name = "gcc_gp2_clk", | |
1865 | .parent_names = (const char *[]){ | |
1866 | "gp2_clk_src", | |
1867 | }, | |
1868 | .num_parents = 1, | |
1869 | .flags = CLK_SET_RATE_PARENT, | |
1870 | .ops = &clk_branch2_ops, | |
1871 | }, | |
1872 | }, | |
1873 | }; | |
1874 | ||
1875 | static struct clk_branch gcc_gp3_clk = { | |
1876 | .halt_reg = 0x1980, | |
1877 | .clkr = { | |
1878 | .enable_reg = 0x1980, | |
1879 | .enable_mask = BIT(0), | |
1880 | .hw.init = &(struct clk_init_data){ | |
1881 | .name = "gcc_gp3_clk", | |
1882 | .parent_names = (const char *[]){ | |
1883 | "gp3_clk_src", | |
1884 | }, | |
1885 | .num_parents = 1, | |
1886 | .flags = CLK_SET_RATE_PARENT, | |
1887 | .ops = &clk_branch2_ops, | |
1888 | }, | |
1889 | }, | |
1890 | }; | |
1891 | ||
1892 | static struct clk_branch gcc_lpass_q6_axi_clk = { | |
1893 | .halt_reg = 0x11c0, | |
1894 | .clkr = { | |
1895 | .enable_reg = 0x11c0, | |
1896 | .enable_mask = BIT(0), | |
1897 | .hw.init = &(struct clk_init_data){ | |
1898 | .name = "gcc_lpass_q6_axi_clk", | |
1899 | .parent_names = (const char *[]){ | |
1900 | "system_noc_clk_src", | |
1901 | }, | |
1902 | .num_parents = 1, | |
1903 | .ops = &clk_branch2_ops, | |
1904 | }, | |
1905 | }, | |
1906 | }; | |
1907 | ||
1908 | static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { | |
1909 | .halt_reg = 0x024c, | |
1910 | .clkr = { | |
1911 | .enable_reg = 0x024c, | |
1912 | .enable_mask = BIT(0), | |
1913 | .hw.init = &(struct clk_init_data){ | |
1914 | .name = "gcc_mmss_noc_cfg_ahb_clk", | |
1915 | .parent_names = (const char *[]){ | |
1916 | "config_noc_clk_src", | |
1917 | }, | |
1918 | .num_parents = 1, | |
1919 | .ops = &clk_branch2_ops, | |
1920 | .flags = CLK_IGNORE_UNUSED, | |
1921 | }, | |
1922 | }, | |
1923 | }; | |
1924 | ||
1925 | static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { | |
1926 | .halt_reg = 0x0248, | |
1927 | .clkr = { | |
1928 | .enable_reg = 0x0248, | |
1929 | .enable_mask = BIT(0), | |
1930 | .hw.init = &(struct clk_init_data){ | |
1931 | .name = "gcc_ocmem_noc_cfg_ahb_clk", | |
1932 | .parent_names = (const char *[]){ | |
1933 | "config_noc_clk_src", | |
1934 | }, | |
1935 | .num_parents = 1, | |
1936 | .ops = &clk_branch2_ops, | |
1937 | }, | |
1938 | }, | |
1939 | }; | |
1940 | ||
1941 | static struct clk_branch gcc_mss_cfg_ahb_clk = { | |
1942 | .halt_reg = 0x0280, | |
1943 | .clkr = { | |
1944 | .enable_reg = 0x0280, | |
1945 | .enable_mask = BIT(0), | |
1946 | .hw.init = &(struct clk_init_data){ | |
1947 | .name = "gcc_mss_cfg_ahb_clk", | |
1948 | .parent_names = (const char *[]){ | |
1949 | "config_noc_clk_src", | |
1950 | }, | |
1951 | .num_parents = 1, | |
1952 | .ops = &clk_branch2_ops, | |
1953 | }, | |
1954 | }, | |
1955 | }; | |
1956 | ||
1957 | static struct clk_branch gcc_mss_q6_bimc_axi_clk = { | |
1958 | .halt_reg = 0x0284, | |
1959 | .clkr = { | |
1960 | .enable_reg = 0x0284, | |
1961 | .enable_mask = BIT(0), | |
1962 | .hw.init = &(struct clk_init_data){ | |
1963 | .name = "gcc_mss_q6_bimc_axi_clk", | |
1964 | .flags = CLK_IS_ROOT, | |
1965 | .ops = &clk_branch2_ops, | |
1966 | }, | |
1967 | }, | |
1968 | }; | |
1969 | ||
1970 | static struct clk_branch gcc_pdm2_clk = { | |
1971 | .halt_reg = 0x0ccc, | |
1972 | .clkr = { | |
1973 | .enable_reg = 0x0ccc, | |
1974 | .enable_mask = BIT(0), | |
1975 | .hw.init = &(struct clk_init_data){ | |
1976 | .name = "gcc_pdm2_clk", | |
1977 | .parent_names = (const char *[]){ | |
1978 | "pdm2_clk_src", | |
1979 | }, | |
1980 | .num_parents = 1, | |
1981 | .flags = CLK_SET_RATE_PARENT, | |
1982 | .ops = &clk_branch2_ops, | |
1983 | }, | |
1984 | }, | |
1985 | }; | |
1986 | ||
1987 | static struct clk_branch gcc_pdm_ahb_clk = { | |
1988 | .halt_reg = 0x0cc4, | |
1989 | .clkr = { | |
1990 | .enable_reg = 0x0cc4, | |
1991 | .enable_mask = BIT(0), | |
1992 | .hw.init = &(struct clk_init_data){ | |
1993 | .name = "gcc_pdm_ahb_clk", | |
1994 | .parent_names = (const char *[]){ | |
1995 | "periph_noc_clk_src", | |
1996 | }, | |
1997 | .num_parents = 1, | |
1998 | .ops = &clk_branch2_ops, | |
1999 | }, | |
2000 | }, | |
2001 | }; | |
2002 | ||
2003 | static struct clk_branch gcc_prng_ahb_clk = { | |
2004 | .halt_reg = 0x0d04, | |
2005 | .halt_check = BRANCH_HALT_VOTED, | |
2006 | .clkr = { | |
2007 | .enable_reg = 0x1484, | |
2008 | .enable_mask = BIT(13), | |
2009 | .hw.init = &(struct clk_init_data){ | |
2010 | .name = "gcc_prng_ahb_clk", | |
2011 | .parent_names = (const char *[]){ | |
2012 | "periph_noc_clk_src", | |
2013 | }, | |
2014 | .num_parents = 1, | |
2015 | .ops = &clk_branch2_ops, | |
2016 | }, | |
2017 | }, | |
2018 | }; | |
2019 | ||
2020 | static struct clk_branch gcc_sdcc1_ahb_clk = { | |
2021 | .halt_reg = 0x04c8, | |
2022 | .clkr = { | |
2023 | .enable_reg = 0x04c8, | |
2024 | .enable_mask = BIT(0), | |
2025 | .hw.init = &(struct clk_init_data){ | |
2026 | .name = "gcc_sdcc1_ahb_clk", | |
2027 | .parent_names = (const char *[]){ | |
2028 | "periph_noc_clk_src", | |
2029 | }, | |
2030 | .num_parents = 1, | |
2031 | .ops = &clk_branch2_ops, | |
2032 | }, | |
2033 | }, | |
2034 | }; | |
2035 | ||
2036 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
2037 | .halt_reg = 0x04c4, | |
2038 | .clkr = { | |
2039 | .enable_reg = 0x04c4, | |
2040 | .enable_mask = BIT(0), | |
2041 | .hw.init = &(struct clk_init_data){ | |
2042 | .name = "gcc_sdcc1_apps_clk", | |
2043 | .parent_names = (const char *[]){ | |
2044 | "sdcc1_apps_clk_src", | |
2045 | }, | |
2046 | .num_parents = 1, | |
2047 | .flags = CLK_SET_RATE_PARENT, | |
2048 | .ops = &clk_branch2_ops, | |
2049 | }, | |
2050 | }, | |
2051 | }; | |
2052 | ||
c685841e SB |
2053 | static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { |
2054 | .halt_reg = 0x04e8, | |
2055 | .clkr = { | |
2056 | .enable_reg = 0x04e8, | |
2057 | .enable_mask = BIT(0), | |
2058 | .hw.init = &(struct clk_init_data){ | |
2059 | .name = "gcc_sdcc1_cdccal_ff_clk", | |
2060 | .parent_names = (const char *[]){ | |
2061 | "xo" | |
2062 | }, | |
2063 | .num_parents = 1, | |
2064 | .ops = &clk_branch2_ops, | |
2065 | }, | |
2066 | }, | |
2067 | }; | |
2068 | ||
2069 | static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { | |
2070 | .halt_reg = 0x04e4, | |
2071 | .clkr = { | |
2072 | .enable_reg = 0x04e4, | |
2073 | .enable_mask = BIT(0), | |
2074 | .hw.init = &(struct clk_init_data){ | |
2075 | .name = "gcc_sdcc1_cdccal_sleep_clk", | |
2076 | .parent_names = (const char *[]){ | |
2077 | "sleep_clk_src" | |
2078 | }, | |
2079 | .num_parents = 1, | |
2080 | .ops = &clk_branch2_ops, | |
2081 | }, | |
2082 | }, | |
2083 | }; | |
2084 | ||
d33faa9e SB |
2085 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
2086 | .halt_reg = 0x0508, | |
2087 | .clkr = { | |
2088 | .enable_reg = 0x0508, | |
2089 | .enable_mask = BIT(0), | |
2090 | .hw.init = &(struct clk_init_data){ | |
2091 | .name = "gcc_sdcc2_ahb_clk", | |
2092 | .parent_names = (const char *[]){ | |
2093 | "periph_noc_clk_src", | |
2094 | }, | |
2095 | .num_parents = 1, | |
2096 | .ops = &clk_branch2_ops, | |
2097 | }, | |
2098 | }, | |
2099 | }; | |
2100 | ||
2101 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2102 | .halt_reg = 0x0504, | |
2103 | .clkr = { | |
2104 | .enable_reg = 0x0504, | |
2105 | .enable_mask = BIT(0), | |
2106 | .hw.init = &(struct clk_init_data){ | |
2107 | .name = "gcc_sdcc2_apps_clk", | |
2108 | .parent_names = (const char *[]){ | |
2109 | "sdcc2_apps_clk_src", | |
2110 | }, | |
2111 | .num_parents = 1, | |
2112 | .flags = CLK_SET_RATE_PARENT, | |
2113 | .ops = &clk_branch2_ops, | |
2114 | }, | |
2115 | }, | |
2116 | }; | |
2117 | ||
2118 | static struct clk_branch gcc_sdcc3_ahb_clk = { | |
2119 | .halt_reg = 0x0548, | |
2120 | .clkr = { | |
2121 | .enable_reg = 0x0548, | |
2122 | .enable_mask = BIT(0), | |
2123 | .hw.init = &(struct clk_init_data){ | |
2124 | .name = "gcc_sdcc3_ahb_clk", | |
2125 | .parent_names = (const char *[]){ | |
2126 | "periph_noc_clk_src", | |
2127 | }, | |
2128 | .num_parents = 1, | |
2129 | .ops = &clk_branch2_ops, | |
2130 | }, | |
2131 | }, | |
2132 | }; | |
2133 | ||
2134 | static struct clk_branch gcc_sdcc3_apps_clk = { | |
2135 | .halt_reg = 0x0544, | |
2136 | .clkr = { | |
2137 | .enable_reg = 0x0544, | |
2138 | .enable_mask = BIT(0), | |
2139 | .hw.init = &(struct clk_init_data){ | |
2140 | .name = "gcc_sdcc3_apps_clk", | |
2141 | .parent_names = (const char *[]){ | |
2142 | "sdcc3_apps_clk_src", | |
2143 | }, | |
2144 | .num_parents = 1, | |
2145 | .flags = CLK_SET_RATE_PARENT, | |
2146 | .ops = &clk_branch2_ops, | |
2147 | }, | |
2148 | }, | |
2149 | }; | |
2150 | ||
2151 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2152 | .halt_reg = 0x0588, | |
2153 | .clkr = { | |
2154 | .enable_reg = 0x0588, | |
2155 | .enable_mask = BIT(0), | |
2156 | .hw.init = &(struct clk_init_data){ | |
2157 | .name = "gcc_sdcc4_ahb_clk", | |
2158 | .parent_names = (const char *[]){ | |
2159 | "periph_noc_clk_src", | |
2160 | }, | |
2161 | .num_parents = 1, | |
2162 | .ops = &clk_branch2_ops, | |
2163 | }, | |
2164 | }, | |
2165 | }; | |
2166 | ||
2167 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2168 | .halt_reg = 0x0584, | |
2169 | .clkr = { | |
2170 | .enable_reg = 0x0584, | |
2171 | .enable_mask = BIT(0), | |
2172 | .hw.init = &(struct clk_init_data){ | |
2173 | .name = "gcc_sdcc4_apps_clk", | |
2174 | .parent_names = (const char *[]){ | |
2175 | "sdcc4_apps_clk_src", | |
2176 | }, | |
2177 | .num_parents = 1, | |
2178 | .flags = CLK_SET_RATE_PARENT, | |
2179 | .ops = &clk_branch2_ops, | |
2180 | }, | |
2181 | }, | |
2182 | }; | |
2183 | ||
2184 | static struct clk_branch gcc_sys_noc_usb3_axi_clk = { | |
2185 | .halt_reg = 0x0108, | |
2186 | .clkr = { | |
2187 | .enable_reg = 0x0108, | |
2188 | .enable_mask = BIT(0), | |
2189 | .hw.init = &(struct clk_init_data){ | |
2190 | .name = "gcc_sys_noc_usb3_axi_clk", | |
2191 | .parent_names = (const char *[]){ | |
2192 | "usb30_master_clk_src", | |
2193 | }, | |
2194 | .num_parents = 1, | |
2195 | .flags = CLK_SET_RATE_PARENT, | |
2196 | .ops = &clk_branch2_ops, | |
2197 | }, | |
2198 | }, | |
2199 | }; | |
2200 | ||
2201 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2202 | .halt_reg = 0x0d84, | |
2203 | .clkr = { | |
2204 | .enable_reg = 0x0d84, | |
2205 | .enable_mask = BIT(0), | |
2206 | .hw.init = &(struct clk_init_data){ | |
2207 | .name = "gcc_tsif_ahb_clk", | |
2208 | .parent_names = (const char *[]){ | |
2209 | "periph_noc_clk_src", | |
2210 | }, | |
2211 | .num_parents = 1, | |
2212 | .ops = &clk_branch2_ops, | |
2213 | }, | |
2214 | }, | |
2215 | }; | |
2216 | ||
2217 | static struct clk_branch gcc_tsif_ref_clk = { | |
2218 | .halt_reg = 0x0d88, | |
2219 | .clkr = { | |
2220 | .enable_reg = 0x0d88, | |
2221 | .enable_mask = BIT(0), | |
2222 | .hw.init = &(struct clk_init_data){ | |
2223 | .name = "gcc_tsif_ref_clk", | |
2224 | .parent_names = (const char *[]){ | |
2225 | "tsif_ref_clk_src", | |
2226 | }, | |
2227 | .num_parents = 1, | |
2228 | .flags = CLK_SET_RATE_PARENT, | |
2229 | .ops = &clk_branch2_ops, | |
2230 | }, | |
2231 | }, | |
2232 | }; | |
2233 | ||
2234 | static struct clk_branch gcc_usb2a_phy_sleep_clk = { | |
2235 | .halt_reg = 0x04ac, | |
2236 | .clkr = { | |
2237 | .enable_reg = 0x04ac, | |
2238 | .enable_mask = BIT(0), | |
2239 | .hw.init = &(struct clk_init_data){ | |
2240 | .name = "gcc_usb2a_phy_sleep_clk", | |
2241 | .parent_names = (const char *[]){ | |
2242 | "sleep_clk_src", | |
2243 | }, | |
2244 | .num_parents = 1, | |
2245 | .ops = &clk_branch2_ops, | |
2246 | }, | |
2247 | }, | |
2248 | }; | |
2249 | ||
2250 | static struct clk_branch gcc_usb2b_phy_sleep_clk = { | |
2251 | .halt_reg = 0x04b4, | |
2252 | .clkr = { | |
2253 | .enable_reg = 0x04b4, | |
2254 | .enable_mask = BIT(0), | |
2255 | .hw.init = &(struct clk_init_data){ | |
2256 | .name = "gcc_usb2b_phy_sleep_clk", | |
2257 | .parent_names = (const char *[]){ | |
2258 | "sleep_clk_src", | |
2259 | }, | |
2260 | .num_parents = 1, | |
2261 | .ops = &clk_branch2_ops, | |
2262 | }, | |
2263 | }, | |
2264 | }; | |
2265 | ||
2266 | static struct clk_branch gcc_usb30_master_clk = { | |
2267 | .halt_reg = 0x03c8, | |
2268 | .clkr = { | |
2269 | .enable_reg = 0x03c8, | |
2270 | .enable_mask = BIT(0), | |
2271 | .hw.init = &(struct clk_init_data){ | |
2272 | .name = "gcc_usb30_master_clk", | |
2273 | .parent_names = (const char *[]){ | |
2274 | "usb30_master_clk_src", | |
2275 | }, | |
2276 | .num_parents = 1, | |
2277 | .flags = CLK_SET_RATE_PARENT, | |
2278 | .ops = &clk_branch2_ops, | |
2279 | }, | |
2280 | }, | |
2281 | }; | |
2282 | ||
2283 | static struct clk_branch gcc_usb30_mock_utmi_clk = { | |
2284 | .halt_reg = 0x03d0, | |
2285 | .clkr = { | |
2286 | .enable_reg = 0x03d0, | |
2287 | .enable_mask = BIT(0), | |
2288 | .hw.init = &(struct clk_init_data){ | |
2289 | .name = "gcc_usb30_mock_utmi_clk", | |
2290 | .parent_names = (const char *[]){ | |
2291 | "usb30_mock_utmi_clk_src", | |
2292 | }, | |
2293 | .num_parents = 1, | |
2294 | .flags = CLK_SET_RATE_PARENT, | |
2295 | .ops = &clk_branch2_ops, | |
2296 | }, | |
2297 | }, | |
2298 | }; | |
2299 | ||
2300 | static struct clk_branch gcc_usb30_sleep_clk = { | |
2301 | .halt_reg = 0x03cc, | |
2302 | .clkr = { | |
2303 | .enable_reg = 0x03cc, | |
2304 | .enable_mask = BIT(0), | |
2305 | .hw.init = &(struct clk_init_data){ | |
2306 | .name = "gcc_usb30_sleep_clk", | |
2307 | .parent_names = (const char *[]){ | |
2308 | "sleep_clk_src", | |
2309 | }, | |
2310 | .num_parents = 1, | |
2311 | .ops = &clk_branch2_ops, | |
2312 | }, | |
2313 | }, | |
2314 | }; | |
2315 | ||
2316 | static struct clk_branch gcc_usb_hs_ahb_clk = { | |
2317 | .halt_reg = 0x0488, | |
2318 | .clkr = { | |
2319 | .enable_reg = 0x0488, | |
2320 | .enable_mask = BIT(0), | |
2321 | .hw.init = &(struct clk_init_data){ | |
2322 | .name = "gcc_usb_hs_ahb_clk", | |
2323 | .parent_names = (const char *[]){ | |
2324 | "periph_noc_clk_src", | |
2325 | }, | |
2326 | .num_parents = 1, | |
2327 | .ops = &clk_branch2_ops, | |
2328 | }, | |
2329 | }, | |
2330 | }; | |
2331 | ||
2332 | static struct clk_branch gcc_usb_hs_system_clk = { | |
2333 | .halt_reg = 0x0484, | |
2334 | .clkr = { | |
2335 | .enable_reg = 0x0484, | |
2336 | .enable_mask = BIT(0), | |
2337 | .hw.init = &(struct clk_init_data){ | |
2338 | .name = "gcc_usb_hs_system_clk", | |
2339 | .parent_names = (const char *[]){ | |
2340 | "usb_hs_system_clk_src", | |
2341 | }, | |
2342 | .num_parents = 1, | |
2343 | .flags = CLK_SET_RATE_PARENT, | |
2344 | .ops = &clk_branch2_ops, | |
2345 | }, | |
2346 | }, | |
2347 | }; | |
2348 | ||
2349 | static struct clk_branch gcc_usb_hsic_ahb_clk = { | |
2350 | .halt_reg = 0x0408, | |
2351 | .clkr = { | |
2352 | .enable_reg = 0x0408, | |
2353 | .enable_mask = BIT(0), | |
2354 | .hw.init = &(struct clk_init_data){ | |
2355 | .name = "gcc_usb_hsic_ahb_clk", | |
2356 | .parent_names = (const char *[]){ | |
2357 | "periph_noc_clk_src", | |
2358 | }, | |
2359 | .num_parents = 1, | |
2360 | .ops = &clk_branch2_ops, | |
2361 | }, | |
2362 | }, | |
2363 | }; | |
2364 | ||
2365 | static struct clk_branch gcc_usb_hsic_clk = { | |
2366 | .halt_reg = 0x0410, | |
2367 | .clkr = { | |
2368 | .enable_reg = 0x0410, | |
2369 | .enable_mask = BIT(0), | |
2370 | .hw.init = &(struct clk_init_data){ | |
2371 | .name = "gcc_usb_hsic_clk", | |
2372 | .parent_names = (const char *[]){ | |
2373 | "usb_hsic_clk_src", | |
2374 | }, | |
2375 | .num_parents = 1, | |
2376 | .flags = CLK_SET_RATE_PARENT, | |
2377 | .ops = &clk_branch2_ops, | |
2378 | }, | |
2379 | }, | |
2380 | }; | |
2381 | ||
2382 | static struct clk_branch gcc_usb_hsic_io_cal_clk = { | |
2383 | .halt_reg = 0x0414, | |
2384 | .clkr = { | |
2385 | .enable_reg = 0x0414, | |
2386 | .enable_mask = BIT(0), | |
2387 | .hw.init = &(struct clk_init_data){ | |
2388 | .name = "gcc_usb_hsic_io_cal_clk", | |
2389 | .parent_names = (const char *[]){ | |
2390 | "usb_hsic_io_cal_clk_src", | |
2391 | }, | |
2392 | .num_parents = 1, | |
2393 | .flags = CLK_SET_RATE_PARENT, | |
2394 | .ops = &clk_branch2_ops, | |
2395 | }, | |
2396 | }, | |
2397 | }; | |
2398 | ||
2399 | static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { | |
2400 | .halt_reg = 0x0418, | |
2401 | .clkr = { | |
2402 | .enable_reg = 0x0418, | |
2403 | .enable_mask = BIT(0), | |
2404 | .hw.init = &(struct clk_init_data){ | |
2405 | .name = "gcc_usb_hsic_io_cal_sleep_clk", | |
2406 | .parent_names = (const char *[]){ | |
2407 | "sleep_clk_src", | |
2408 | }, | |
2409 | .num_parents = 1, | |
2410 | .ops = &clk_branch2_ops, | |
2411 | }, | |
2412 | }, | |
2413 | }; | |
2414 | ||
2415 | static struct clk_branch gcc_usb_hsic_system_clk = { | |
2416 | .halt_reg = 0x040c, | |
2417 | .clkr = { | |
2418 | .enable_reg = 0x040c, | |
2419 | .enable_mask = BIT(0), | |
2420 | .hw.init = &(struct clk_init_data){ | |
2421 | .name = "gcc_usb_hsic_system_clk", | |
2422 | .parent_names = (const char *[]){ | |
2423 | "usb_hsic_system_clk_src", | |
2424 | }, | |
2425 | .num_parents = 1, | |
2426 | .flags = CLK_SET_RATE_PARENT, | |
2427 | .ops = &clk_branch2_ops, | |
2428 | }, | |
2429 | }, | |
2430 | }; | |
2431 | ||
2432 | static struct clk_regmap *gcc_msm8974_clocks[] = { | |
2433 | [GPLL0] = &gpll0.clkr, | |
2434 | [GPLL0_VOTE] = &gpll0_vote, | |
2435 | [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, | |
2436 | [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, | |
2437 | [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, | |
2438 | [GPLL1] = &gpll1.clkr, | |
2439 | [GPLL1_VOTE] = &gpll1_vote, | |
2440 | [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, | |
2441 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, | |
2442 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, | |
2443 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, | |
2444 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, | |
2445 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, | |
2446 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, | |
2447 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, | |
2448 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, | |
2449 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, | |
2450 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, | |
2451 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, | |
2452 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, | |
2453 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, | |
2454 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, | |
2455 | [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, | |
2456 | [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, | |
2457 | [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, | |
2458 | [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, | |
2459 | [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, | |
2460 | [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, | |
2461 | [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, | |
2462 | [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, | |
2463 | [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, | |
2464 | [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, | |
2465 | [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, | |
2466 | [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, | |
2467 | [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, | |
2468 | [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, | |
2469 | [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, | |
2470 | [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, | |
2471 | [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, | |
2472 | [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, | |
2473 | [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, | |
2474 | [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, | |
2475 | [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, | |
2476 | [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, | |
2477 | [CE1_CLK_SRC] = &ce1_clk_src.clkr, | |
2478 | [CE2_CLK_SRC] = &ce2_clk_src.clkr, | |
2479 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, | |
2480 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, | |
2481 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, | |
2482 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, | |
2483 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, | |
2484 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, | |
2485 | [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, | |
2486 | [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, | |
2487 | [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, | |
2488 | [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, | |
2489 | [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, | |
2490 | [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, | |
2491 | [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, | |
2492 | [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, | |
2493 | [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, | |
2494 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, | |
2495 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, | |
2496 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, | |
2497 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, | |
2498 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, | |
2499 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, | |
2500 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, | |
2501 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, | |
2502 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, | |
2503 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, | |
2504 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, | |
2505 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, | |
2506 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, | |
2507 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, | |
2508 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, | |
2509 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, | |
2510 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, | |
2511 | [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, | |
2512 | [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, | |
2513 | [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, | |
2514 | [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, | |
2515 | [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, | |
2516 | [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, | |
2517 | [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, | |
2518 | [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, | |
2519 | [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, | |
2520 | [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, | |
2521 | [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, | |
2522 | [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, | |
2523 | [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, | |
2524 | [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, | |
2525 | [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, | |
2526 | [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, | |
2527 | [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, | |
2528 | [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, | |
2529 | [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, | |
2530 | [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, | |
2531 | [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, | |
2532 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
2533 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
2534 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
2535 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
2536 | [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, | |
2537 | [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, | |
2538 | [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, | |
2539 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
2540 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
2541 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
2542 | [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, | |
2543 | [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, | |
2544 | [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, | |
2545 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, | |
2546 | [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, | |
2547 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, | |
2548 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
2549 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
2550 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, | |
2551 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
2552 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
2553 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
2554 | [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, | |
2555 | [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, | |
2556 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
2557 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
2558 | [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, | |
2559 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
2560 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
2561 | [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, | |
2562 | [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, | |
2563 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, | |
2564 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, | |
2565 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, | |
2566 | [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, | |
2567 | [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, | |
2568 | [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, | |
2569 | [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, | |
2570 | [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, | |
2571 | [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, | |
2572 | [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, | |
2573 | [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, | |
c685841e SB |
2574 | [GPLL4] = NULL, |
2575 | [GPLL4_VOTE] = NULL, | |
2576 | [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL, | |
2577 | [GCC_SDCC1_CDCCAL_FF_CLK] = NULL, | |
d33faa9e SB |
2578 | }; |
2579 | ||
2580 | static const struct qcom_reset_map gcc_msm8974_resets[] = { | |
2581 | [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, | |
2582 | [GCC_CONFIG_NOC_BCR] = { 0x0140 }, | |
2583 | [GCC_PERIPH_NOC_BCR] = { 0x0180 }, | |
2584 | [GCC_IMEM_BCR] = { 0x0200 }, | |
2585 | [GCC_MMSS_BCR] = { 0x0240 }, | |
2586 | [GCC_QDSS_BCR] = { 0x0300 }, | |
2587 | [GCC_USB_30_BCR] = { 0x03c0 }, | |
2588 | [GCC_USB3_PHY_BCR] = { 0x03fc }, | |
2589 | [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, | |
2590 | [GCC_USB_HS_BCR] = { 0x0480 }, | |
2591 | [GCC_USB2A_PHY_BCR] = { 0x04a8 }, | |
2592 | [GCC_USB2B_PHY_BCR] = { 0x04b0 }, | |
2593 | [GCC_SDCC1_BCR] = { 0x04c0 }, | |
2594 | [GCC_SDCC2_BCR] = { 0x0500 }, | |
2595 | [GCC_SDCC3_BCR] = { 0x0540 }, | |
2596 | [GCC_SDCC4_BCR] = { 0x0580 }, | |
2597 | [GCC_BLSP1_BCR] = { 0x05c0 }, | |
2598 | [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, | |
2599 | [GCC_BLSP1_UART1_BCR] = { 0x0680 }, | |
2600 | [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, | |
2601 | [GCC_BLSP1_UART2_BCR] = { 0x0700 }, | |
2602 | [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, | |
2603 | [GCC_BLSP1_UART3_BCR] = { 0x0780 }, | |
2604 | [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, | |
2605 | [GCC_BLSP1_UART4_BCR] = { 0x0800 }, | |
2606 | [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, | |
2607 | [GCC_BLSP1_UART5_BCR] = { 0x0880 }, | |
2608 | [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, | |
2609 | [GCC_BLSP1_UART6_BCR] = { 0x0900 }, | |
2610 | [GCC_BLSP2_BCR] = { 0x0940 }, | |
2611 | [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, | |
2612 | [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, | |
2613 | [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, | |
2614 | [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, | |
2615 | [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, | |
2616 | [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, | |
2617 | [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, | |
2618 | [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, | |
2619 | [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, | |
2620 | [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, | |
2621 | [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, | |
2622 | [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, | |
2623 | [GCC_PDM_BCR] = { 0x0cc0 }, | |
2624 | [GCC_BAM_DMA_BCR] = { 0x0d40 }, | |
2625 | [GCC_TSIF_BCR] = { 0x0d80 }, | |
2626 | [GCC_TCSR_BCR] = { 0x0dc0 }, | |
2627 | [GCC_BOOT_ROM_BCR] = { 0x0e00 }, | |
2628 | [GCC_MSG_RAM_BCR] = { 0x0e40 }, | |
2629 | [GCC_TLMM_BCR] = { 0x0e80 }, | |
2630 | [GCC_MPM_BCR] = { 0x0ec0 }, | |
2631 | [GCC_SEC_CTRL_BCR] = { 0x0f40 }, | |
2632 | [GCC_SPMI_BCR] = { 0x0fc0 }, | |
2633 | [GCC_SPDM_BCR] = { 0x1000 }, | |
2634 | [GCC_CE1_BCR] = { 0x1040 }, | |
2635 | [GCC_CE2_BCR] = { 0x1080 }, | |
2636 | [GCC_BIMC_BCR] = { 0x1100 }, | |
2637 | [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, | |
2638 | [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, | |
2639 | [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, | |
2640 | [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, | |
2641 | [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, | |
2642 | [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, | |
2643 | [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, | |
2644 | [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, | |
2645 | [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, | |
2646 | [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, | |
2647 | [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, | |
2648 | [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, | |
2649 | [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, | |
2650 | [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, | |
2651 | [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, | |
2652 | [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, | |
2653 | [GCC_DEHR_BCR] = { 0x1300 }, | |
2654 | [GCC_RBCPR_BCR] = { 0x1380 }, | |
2655 | [GCC_MSS_RESTART] = { 0x1680 }, | |
2656 | [GCC_LPASS_RESTART] = { 0x16c0 }, | |
2657 | [GCC_WCSS_RESTART] = { 0x1700 }, | |
2658 | [GCC_VENUS_RESTART] = { 0x1740 }, | |
2659 | }; | |
2660 | ||
2661 | static const struct regmap_config gcc_msm8974_regmap_config = { | |
2662 | .reg_bits = 32, | |
2663 | .reg_stride = 4, | |
2664 | .val_bits = 32, | |
2665 | .max_register = 0x1fc0, | |
2666 | .fast_io = true, | |
2667 | }; | |
2668 | ||
49fc825f SB |
2669 | static const struct qcom_cc_desc gcc_msm8974_desc = { |
2670 | .config = &gcc_msm8974_regmap_config, | |
2671 | .clks = gcc_msm8974_clocks, | |
2672 | .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), | |
2673 | .resets = gcc_msm8974_resets, | |
2674 | .num_resets = ARRAY_SIZE(gcc_msm8974_resets), | |
2675 | }; | |
2676 | ||
d33faa9e SB |
2677 | static const struct of_device_id gcc_msm8974_match_table[] = { |
2678 | { .compatible = "qcom,gcc-msm8974" }, | |
c685841e SB |
2679 | { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, |
2680 | { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, | |
d33faa9e SB |
2681 | { } |
2682 | }; | |
2683 | MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); | |
2684 | ||
c685841e SB |
2685 | static void msm8974_pro_clock_override(void) |
2686 | { | |
2687 | sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; | |
2688 | sdcc1_apps_clk_src_init.num_parents = 3; | |
2689 | sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; | |
2690 | sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; | |
2691 | ||
2692 | gcc_msm8974_clocks[GPLL4] = &gpll4.clkr; | |
2693 | gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote; | |
2694 | gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] = | |
2695 | &gcc_sdcc1_cdccal_sleep_clk.clkr; | |
2696 | gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] = | |
2697 | &gcc_sdcc1_cdccal_ff_clk.clkr; | |
2698 | } | |
2699 | ||
d33faa9e SB |
2700 | static int gcc_msm8974_probe(struct platform_device *pdev) |
2701 | { | |
d33faa9e | 2702 | struct clk *clk; |
49fc825f | 2703 | struct device *dev = &pdev->dev; |
c685841e SB |
2704 | bool pro; |
2705 | const struct of_device_id *id; | |
2706 | ||
2707 | id = of_match_device(gcc_msm8974_match_table, dev); | |
2708 | if (!id) | |
2709 | return -ENODEV; | |
2710 | pro = !!(id->data); | |
2711 | ||
2712 | if (pro) | |
2713 | msm8974_pro_clock_override(); | |
d33faa9e SB |
2714 | |
2715 | /* Temporary until RPM clocks supported */ | |
2716 | clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); | |
2717 | if (IS_ERR(clk)) | |
2718 | return PTR_ERR(clk); | |
2719 | ||
2720 | /* Should move to DT node? */ | |
2721 | clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, | |
2722 | CLK_IS_ROOT, 32768); | |
2723 | if (IS_ERR(clk)) | |
2724 | return PTR_ERR(clk); | |
2725 | ||
49fc825f | 2726 | return qcom_cc_probe(pdev, &gcc_msm8974_desc); |
d33faa9e SB |
2727 | } |
2728 | ||
2729 | static int gcc_msm8974_remove(struct platform_device *pdev) | |
2730 | { | |
49fc825f | 2731 | qcom_cc_remove(pdev); |
d33faa9e SB |
2732 | return 0; |
2733 | } | |
2734 | ||
2735 | static struct platform_driver gcc_msm8974_driver = { | |
2736 | .probe = gcc_msm8974_probe, | |
2737 | .remove = gcc_msm8974_remove, | |
2738 | .driver = { | |
2739 | .name = "gcc-msm8974", | |
d33faa9e SB |
2740 | .of_match_table = gcc_msm8974_match_table, |
2741 | }, | |
2742 | }; | |
2743 | ||
2744 | static int __init gcc_msm8974_init(void) | |
2745 | { | |
2746 | return platform_driver_register(&gcc_msm8974_driver); | |
2747 | } | |
2748 | core_initcall(gcc_msm8974_init); | |
2749 | ||
2750 | static void __exit gcc_msm8974_exit(void) | |
2751 | { | |
2752 | platform_driver_unregister(&gcc_msm8974_driver); | |
2753 | } | |
2754 | module_exit(gcc_msm8974_exit); | |
2755 | ||
2756 | MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver"); | |
2757 | MODULE_LICENSE("GPL v2"); | |
2758 | MODULE_ALIAS("platform:gcc-msm8974"); |