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0eeff27b SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | |
26 | #include <dt-bindings/reset/qcom,gcc-msm8660.h> | |
27 | ||
49fc825f | 28 | #include "common.h" |
0eeff27b SB |
29 | #include "clk-regmap.h" |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
34 | ||
35 | static struct clk_pll pll8 = { | |
36 | .l_reg = 0x3144, | |
37 | .m_reg = 0x3148, | |
38 | .n_reg = 0x314c, | |
39 | .config_reg = 0x3154, | |
40 | .mode_reg = 0x3140, | |
41 | .status_reg = 0x3158, | |
42 | .status_bit = 16, | |
43 | .clkr.hw.init = &(struct clk_init_data){ | |
44 | .name = "pll8", | |
45 | .parent_names = (const char *[]){ "pxo" }, | |
46 | .num_parents = 1, | |
47 | .ops = &clk_pll_ops, | |
48 | }, | |
49 | }; | |
50 | ||
51 | static struct clk_regmap pll8_vote = { | |
52 | .enable_reg = 0x34c0, | |
53 | .enable_mask = BIT(8), | |
54 | .hw.init = &(struct clk_init_data){ | |
55 | .name = "pll8_vote", | |
56 | .parent_names = (const char *[]){ "pll8" }, | |
57 | .num_parents = 1, | |
58 | .ops = &clk_pll_vote_ops, | |
59 | }, | |
60 | }; | |
61 | ||
293d2e97 GD |
62 | enum { |
63 | P_PXO, | |
64 | P_PLL8, | |
65 | P_CXO, | |
66 | }; | |
0eeff27b | 67 | |
293d2e97 GD |
68 | static const struct parent_map gcc_pxo_pll8_map[] = { |
69 | { P_PXO, 0 }, | |
70 | { P_PLL8, 3 } | |
0eeff27b SB |
71 | }; |
72 | ||
adb11a40 | 73 | static const char * const gcc_pxo_pll8[] = { |
0eeff27b SB |
74 | "pxo", |
75 | "pll8_vote", | |
76 | }; | |
77 | ||
293d2e97 GD |
78 | static const struct parent_map gcc_pxo_pll8_cxo_map[] = { |
79 | { P_PXO, 0 }, | |
80 | { P_PLL8, 3 }, | |
81 | { P_CXO, 5 } | |
0eeff27b SB |
82 | }; |
83 | ||
adb11a40 | 84 | static const char * const gcc_pxo_pll8_cxo[] = { |
0eeff27b SB |
85 | "pxo", |
86 | "pll8_vote", | |
87 | "cxo", | |
88 | }; | |
89 | ||
90 | static struct freq_tbl clk_tbl_gsbi_uart[] = { | |
91 | { 1843200, P_PLL8, 2, 6, 625 }, | |
92 | { 3686400, P_PLL8, 2, 12, 625 }, | |
93 | { 7372800, P_PLL8, 2, 24, 625 }, | |
94 | { 14745600, P_PLL8, 2, 48, 625 }, | |
95 | { 16000000, P_PLL8, 4, 1, 6 }, | |
96 | { 24000000, P_PLL8, 4, 1, 4 }, | |
97 | { 32000000, P_PLL8, 4, 1, 3 }, | |
98 | { 40000000, P_PLL8, 1, 5, 48 }, | |
99 | { 46400000, P_PLL8, 1, 29, 240 }, | |
100 | { 48000000, P_PLL8, 4, 1, 2 }, | |
101 | { 51200000, P_PLL8, 1, 2, 15 }, | |
102 | { 56000000, P_PLL8, 1, 7, 48 }, | |
103 | { 58982400, P_PLL8, 1, 96, 625 }, | |
104 | { 64000000, P_PLL8, 2, 1, 3 }, | |
105 | { } | |
106 | }; | |
107 | ||
108 | static struct clk_rcg gsbi1_uart_src = { | |
109 | .ns_reg = 0x29d4, | |
110 | .md_reg = 0x29d0, | |
111 | .mn = { | |
112 | .mnctr_en_bit = 8, | |
113 | .mnctr_reset_bit = 7, | |
114 | .mnctr_mode_shift = 5, | |
115 | .n_val_shift = 16, | |
116 | .m_val_shift = 16, | |
117 | .width = 16, | |
118 | }, | |
119 | .p = { | |
120 | .pre_div_shift = 3, | |
121 | .pre_div_width = 2, | |
122 | }, | |
123 | .s = { | |
124 | .src_sel_shift = 0, | |
125 | .parent_map = gcc_pxo_pll8_map, | |
126 | }, | |
127 | .freq_tbl = clk_tbl_gsbi_uart, | |
128 | .clkr = { | |
129 | .enable_reg = 0x29d4, | |
130 | .enable_mask = BIT(11), | |
131 | .hw.init = &(struct clk_init_data){ | |
132 | .name = "gsbi1_uart_src", | |
133 | .parent_names = gcc_pxo_pll8, | |
134 | .num_parents = 2, | |
135 | .ops = &clk_rcg_ops, | |
136 | .flags = CLK_SET_PARENT_GATE, | |
137 | }, | |
138 | }, | |
139 | }; | |
140 | ||
141 | static struct clk_branch gsbi1_uart_clk = { | |
142 | .halt_reg = 0x2fcc, | |
143 | .halt_bit = 10, | |
144 | .clkr = { | |
145 | .enable_reg = 0x29d4, | |
146 | .enable_mask = BIT(9), | |
147 | .hw.init = &(struct clk_init_data){ | |
148 | .name = "gsbi1_uart_clk", | |
149 | .parent_names = (const char *[]){ | |
150 | "gsbi1_uart_src", | |
151 | }, | |
152 | .num_parents = 1, | |
153 | .ops = &clk_branch_ops, | |
154 | .flags = CLK_SET_RATE_PARENT, | |
155 | }, | |
156 | }, | |
157 | }; | |
158 | ||
159 | static struct clk_rcg gsbi2_uart_src = { | |
160 | .ns_reg = 0x29f4, | |
161 | .md_reg = 0x29f0, | |
162 | .mn = { | |
163 | .mnctr_en_bit = 8, | |
164 | .mnctr_reset_bit = 7, | |
165 | .mnctr_mode_shift = 5, | |
166 | .n_val_shift = 16, | |
167 | .m_val_shift = 16, | |
168 | .width = 16, | |
169 | }, | |
170 | .p = { | |
171 | .pre_div_shift = 3, | |
172 | .pre_div_width = 2, | |
173 | }, | |
174 | .s = { | |
175 | .src_sel_shift = 0, | |
176 | .parent_map = gcc_pxo_pll8_map, | |
177 | }, | |
178 | .freq_tbl = clk_tbl_gsbi_uart, | |
179 | .clkr = { | |
180 | .enable_reg = 0x29f4, | |
181 | .enable_mask = BIT(11), | |
182 | .hw.init = &(struct clk_init_data){ | |
183 | .name = "gsbi2_uart_src", | |
184 | .parent_names = gcc_pxo_pll8, | |
185 | .num_parents = 2, | |
186 | .ops = &clk_rcg_ops, | |
187 | .flags = CLK_SET_PARENT_GATE, | |
188 | }, | |
189 | }, | |
190 | }; | |
191 | ||
192 | static struct clk_branch gsbi2_uart_clk = { | |
193 | .halt_reg = 0x2fcc, | |
194 | .halt_bit = 6, | |
195 | .clkr = { | |
196 | .enable_reg = 0x29f4, | |
197 | .enable_mask = BIT(9), | |
198 | .hw.init = &(struct clk_init_data){ | |
199 | .name = "gsbi2_uart_clk", | |
200 | .parent_names = (const char *[]){ | |
201 | "gsbi2_uart_src", | |
202 | }, | |
203 | .num_parents = 1, | |
204 | .ops = &clk_branch_ops, | |
205 | .flags = CLK_SET_RATE_PARENT, | |
206 | }, | |
207 | }, | |
208 | }; | |
209 | ||
210 | static struct clk_rcg gsbi3_uart_src = { | |
211 | .ns_reg = 0x2a14, | |
212 | .md_reg = 0x2a10, | |
213 | .mn = { | |
214 | .mnctr_en_bit = 8, | |
215 | .mnctr_reset_bit = 7, | |
216 | .mnctr_mode_shift = 5, | |
217 | .n_val_shift = 16, | |
218 | .m_val_shift = 16, | |
219 | .width = 16, | |
220 | }, | |
221 | .p = { | |
222 | .pre_div_shift = 3, | |
223 | .pre_div_width = 2, | |
224 | }, | |
225 | .s = { | |
226 | .src_sel_shift = 0, | |
227 | .parent_map = gcc_pxo_pll8_map, | |
228 | }, | |
229 | .freq_tbl = clk_tbl_gsbi_uart, | |
230 | .clkr = { | |
231 | .enable_reg = 0x2a14, | |
232 | .enable_mask = BIT(11), | |
233 | .hw.init = &(struct clk_init_data){ | |
234 | .name = "gsbi3_uart_src", | |
235 | .parent_names = gcc_pxo_pll8, | |
236 | .num_parents = 2, | |
237 | .ops = &clk_rcg_ops, | |
238 | .flags = CLK_SET_PARENT_GATE, | |
239 | }, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct clk_branch gsbi3_uart_clk = { | |
244 | .halt_reg = 0x2fcc, | |
245 | .halt_bit = 2, | |
246 | .clkr = { | |
247 | .enable_reg = 0x2a14, | |
248 | .enable_mask = BIT(9), | |
249 | .hw.init = &(struct clk_init_data){ | |
250 | .name = "gsbi3_uart_clk", | |
251 | .parent_names = (const char *[]){ | |
252 | "gsbi3_uart_src", | |
253 | }, | |
254 | .num_parents = 1, | |
255 | .ops = &clk_branch_ops, | |
256 | .flags = CLK_SET_RATE_PARENT, | |
257 | }, | |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct clk_rcg gsbi4_uart_src = { | |
262 | .ns_reg = 0x2a34, | |
263 | .md_reg = 0x2a30, | |
264 | .mn = { | |
265 | .mnctr_en_bit = 8, | |
266 | .mnctr_reset_bit = 7, | |
267 | .mnctr_mode_shift = 5, | |
268 | .n_val_shift = 16, | |
269 | .m_val_shift = 16, | |
270 | .width = 16, | |
271 | }, | |
272 | .p = { | |
273 | .pre_div_shift = 3, | |
274 | .pre_div_width = 2, | |
275 | }, | |
276 | .s = { | |
277 | .src_sel_shift = 0, | |
278 | .parent_map = gcc_pxo_pll8_map, | |
279 | }, | |
280 | .freq_tbl = clk_tbl_gsbi_uart, | |
281 | .clkr = { | |
282 | .enable_reg = 0x2a34, | |
283 | .enable_mask = BIT(11), | |
284 | .hw.init = &(struct clk_init_data){ | |
285 | .name = "gsbi4_uart_src", | |
286 | .parent_names = gcc_pxo_pll8, | |
287 | .num_parents = 2, | |
288 | .ops = &clk_rcg_ops, | |
289 | .flags = CLK_SET_PARENT_GATE, | |
290 | }, | |
291 | }, | |
292 | }; | |
293 | ||
294 | static struct clk_branch gsbi4_uart_clk = { | |
295 | .halt_reg = 0x2fd0, | |
296 | .halt_bit = 26, | |
297 | .clkr = { | |
298 | .enable_reg = 0x2a34, | |
299 | .enable_mask = BIT(9), | |
300 | .hw.init = &(struct clk_init_data){ | |
301 | .name = "gsbi4_uart_clk", | |
302 | .parent_names = (const char *[]){ | |
303 | "gsbi4_uart_src", | |
304 | }, | |
305 | .num_parents = 1, | |
306 | .ops = &clk_branch_ops, | |
307 | .flags = CLK_SET_RATE_PARENT, | |
308 | }, | |
309 | }, | |
310 | }; | |
311 | ||
312 | static struct clk_rcg gsbi5_uart_src = { | |
313 | .ns_reg = 0x2a54, | |
314 | .md_reg = 0x2a50, | |
315 | .mn = { | |
316 | .mnctr_en_bit = 8, | |
317 | .mnctr_reset_bit = 7, | |
318 | .mnctr_mode_shift = 5, | |
319 | .n_val_shift = 16, | |
320 | .m_val_shift = 16, | |
321 | .width = 16, | |
322 | }, | |
323 | .p = { | |
324 | .pre_div_shift = 3, | |
325 | .pre_div_width = 2, | |
326 | }, | |
327 | .s = { | |
328 | .src_sel_shift = 0, | |
329 | .parent_map = gcc_pxo_pll8_map, | |
330 | }, | |
331 | .freq_tbl = clk_tbl_gsbi_uart, | |
332 | .clkr = { | |
333 | .enable_reg = 0x2a54, | |
334 | .enable_mask = BIT(11), | |
335 | .hw.init = &(struct clk_init_data){ | |
336 | .name = "gsbi5_uart_src", | |
337 | .parent_names = gcc_pxo_pll8, | |
338 | .num_parents = 2, | |
339 | .ops = &clk_rcg_ops, | |
340 | .flags = CLK_SET_PARENT_GATE, | |
341 | }, | |
342 | }, | |
343 | }; | |
344 | ||
345 | static struct clk_branch gsbi5_uart_clk = { | |
346 | .halt_reg = 0x2fd0, | |
347 | .halt_bit = 22, | |
348 | .clkr = { | |
349 | .enable_reg = 0x2a54, | |
350 | .enable_mask = BIT(9), | |
351 | .hw.init = &(struct clk_init_data){ | |
352 | .name = "gsbi5_uart_clk", | |
353 | .parent_names = (const char *[]){ | |
354 | "gsbi5_uart_src", | |
355 | }, | |
356 | .num_parents = 1, | |
357 | .ops = &clk_branch_ops, | |
358 | .flags = CLK_SET_RATE_PARENT, | |
359 | }, | |
360 | }, | |
361 | }; | |
362 | ||
363 | static struct clk_rcg gsbi6_uart_src = { | |
364 | .ns_reg = 0x2a74, | |
365 | .md_reg = 0x2a70, | |
366 | .mn = { | |
367 | .mnctr_en_bit = 8, | |
368 | .mnctr_reset_bit = 7, | |
369 | .mnctr_mode_shift = 5, | |
370 | .n_val_shift = 16, | |
371 | .m_val_shift = 16, | |
372 | .width = 16, | |
373 | }, | |
374 | .p = { | |
375 | .pre_div_shift = 3, | |
376 | .pre_div_width = 2, | |
377 | }, | |
378 | .s = { | |
379 | .src_sel_shift = 0, | |
380 | .parent_map = gcc_pxo_pll8_map, | |
381 | }, | |
382 | .freq_tbl = clk_tbl_gsbi_uart, | |
383 | .clkr = { | |
384 | .enable_reg = 0x2a74, | |
385 | .enable_mask = BIT(11), | |
386 | .hw.init = &(struct clk_init_data){ | |
387 | .name = "gsbi6_uart_src", | |
388 | .parent_names = gcc_pxo_pll8, | |
389 | .num_parents = 2, | |
390 | .ops = &clk_rcg_ops, | |
391 | .flags = CLK_SET_PARENT_GATE, | |
392 | }, | |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct clk_branch gsbi6_uart_clk = { | |
397 | .halt_reg = 0x2fd0, | |
398 | .halt_bit = 18, | |
399 | .clkr = { | |
400 | .enable_reg = 0x2a74, | |
401 | .enable_mask = BIT(9), | |
402 | .hw.init = &(struct clk_init_data){ | |
403 | .name = "gsbi6_uart_clk", | |
404 | .parent_names = (const char *[]){ | |
405 | "gsbi6_uart_src", | |
406 | }, | |
407 | .num_parents = 1, | |
408 | .ops = &clk_branch_ops, | |
409 | .flags = CLK_SET_RATE_PARENT, | |
410 | }, | |
411 | }, | |
412 | }; | |
413 | ||
414 | static struct clk_rcg gsbi7_uart_src = { | |
415 | .ns_reg = 0x2a94, | |
416 | .md_reg = 0x2a90, | |
417 | .mn = { | |
418 | .mnctr_en_bit = 8, | |
419 | .mnctr_reset_bit = 7, | |
420 | .mnctr_mode_shift = 5, | |
421 | .n_val_shift = 16, | |
422 | .m_val_shift = 16, | |
423 | .width = 16, | |
424 | }, | |
425 | .p = { | |
426 | .pre_div_shift = 3, | |
427 | .pre_div_width = 2, | |
428 | }, | |
429 | .s = { | |
430 | .src_sel_shift = 0, | |
431 | .parent_map = gcc_pxo_pll8_map, | |
432 | }, | |
433 | .freq_tbl = clk_tbl_gsbi_uart, | |
434 | .clkr = { | |
435 | .enable_reg = 0x2a94, | |
436 | .enable_mask = BIT(11), | |
437 | .hw.init = &(struct clk_init_data){ | |
438 | .name = "gsbi7_uart_src", | |
439 | .parent_names = gcc_pxo_pll8, | |
440 | .num_parents = 2, | |
441 | .ops = &clk_rcg_ops, | |
442 | .flags = CLK_SET_PARENT_GATE, | |
443 | }, | |
444 | }, | |
445 | }; | |
446 | ||
447 | static struct clk_branch gsbi7_uart_clk = { | |
448 | .halt_reg = 0x2fd0, | |
449 | .halt_bit = 14, | |
450 | .clkr = { | |
451 | .enable_reg = 0x2a94, | |
452 | .enable_mask = BIT(9), | |
453 | .hw.init = &(struct clk_init_data){ | |
454 | .name = "gsbi7_uart_clk", | |
455 | .parent_names = (const char *[]){ | |
456 | "gsbi7_uart_src", | |
457 | }, | |
458 | .num_parents = 1, | |
459 | .ops = &clk_branch_ops, | |
460 | .flags = CLK_SET_RATE_PARENT, | |
461 | }, | |
462 | }, | |
463 | }; | |
464 | ||
465 | static struct clk_rcg gsbi8_uart_src = { | |
466 | .ns_reg = 0x2ab4, | |
467 | .md_reg = 0x2ab0, | |
468 | .mn = { | |
469 | .mnctr_en_bit = 8, | |
470 | .mnctr_reset_bit = 7, | |
471 | .mnctr_mode_shift = 5, | |
472 | .n_val_shift = 16, | |
473 | .m_val_shift = 16, | |
474 | .width = 16, | |
475 | }, | |
476 | .p = { | |
477 | .pre_div_shift = 3, | |
478 | .pre_div_width = 2, | |
479 | }, | |
480 | .s = { | |
481 | .src_sel_shift = 0, | |
482 | .parent_map = gcc_pxo_pll8_map, | |
483 | }, | |
484 | .freq_tbl = clk_tbl_gsbi_uart, | |
485 | .clkr = { | |
486 | .enable_reg = 0x2ab4, | |
487 | .enable_mask = BIT(11), | |
488 | .hw.init = &(struct clk_init_data){ | |
489 | .name = "gsbi8_uart_src", | |
490 | .parent_names = gcc_pxo_pll8, | |
491 | .num_parents = 2, | |
492 | .ops = &clk_rcg_ops, | |
493 | .flags = CLK_SET_PARENT_GATE, | |
494 | }, | |
495 | }, | |
496 | }; | |
497 | ||
498 | static struct clk_branch gsbi8_uart_clk = { | |
499 | .halt_reg = 0x2fd0, | |
500 | .halt_bit = 10, | |
501 | .clkr = { | |
502 | .enable_reg = 0x2ab4, | |
503 | .enable_mask = BIT(9), | |
504 | .hw.init = &(struct clk_init_data){ | |
505 | .name = "gsbi8_uart_clk", | |
506 | .parent_names = (const char *[]){ "gsbi8_uart_src" }, | |
507 | .num_parents = 1, | |
508 | .ops = &clk_branch_ops, | |
509 | .flags = CLK_SET_RATE_PARENT, | |
510 | }, | |
511 | }, | |
512 | }; | |
513 | ||
514 | static struct clk_rcg gsbi9_uart_src = { | |
515 | .ns_reg = 0x2ad4, | |
516 | .md_reg = 0x2ad0, | |
517 | .mn = { | |
518 | .mnctr_en_bit = 8, | |
519 | .mnctr_reset_bit = 7, | |
520 | .mnctr_mode_shift = 5, | |
521 | .n_val_shift = 16, | |
522 | .m_val_shift = 16, | |
523 | .width = 16, | |
524 | }, | |
525 | .p = { | |
526 | .pre_div_shift = 3, | |
527 | .pre_div_width = 2, | |
528 | }, | |
529 | .s = { | |
530 | .src_sel_shift = 0, | |
531 | .parent_map = gcc_pxo_pll8_map, | |
532 | }, | |
533 | .freq_tbl = clk_tbl_gsbi_uart, | |
534 | .clkr = { | |
535 | .enable_reg = 0x2ad4, | |
536 | .enable_mask = BIT(11), | |
537 | .hw.init = &(struct clk_init_data){ | |
538 | .name = "gsbi9_uart_src", | |
539 | .parent_names = gcc_pxo_pll8, | |
540 | .num_parents = 2, | |
541 | .ops = &clk_rcg_ops, | |
542 | .flags = CLK_SET_PARENT_GATE, | |
543 | }, | |
544 | }, | |
545 | }; | |
546 | ||
547 | static struct clk_branch gsbi9_uart_clk = { | |
548 | .halt_reg = 0x2fd0, | |
549 | .halt_bit = 6, | |
550 | .clkr = { | |
551 | .enable_reg = 0x2ad4, | |
552 | .enable_mask = BIT(9), | |
553 | .hw.init = &(struct clk_init_data){ | |
554 | .name = "gsbi9_uart_clk", | |
555 | .parent_names = (const char *[]){ "gsbi9_uart_src" }, | |
556 | .num_parents = 1, | |
557 | .ops = &clk_branch_ops, | |
558 | .flags = CLK_SET_RATE_PARENT, | |
559 | }, | |
560 | }, | |
561 | }; | |
562 | ||
563 | static struct clk_rcg gsbi10_uart_src = { | |
564 | .ns_reg = 0x2af4, | |
565 | .md_reg = 0x2af0, | |
566 | .mn = { | |
567 | .mnctr_en_bit = 8, | |
568 | .mnctr_reset_bit = 7, | |
569 | .mnctr_mode_shift = 5, | |
570 | .n_val_shift = 16, | |
571 | .m_val_shift = 16, | |
572 | .width = 16, | |
573 | }, | |
574 | .p = { | |
575 | .pre_div_shift = 3, | |
576 | .pre_div_width = 2, | |
577 | }, | |
578 | .s = { | |
579 | .src_sel_shift = 0, | |
580 | .parent_map = gcc_pxo_pll8_map, | |
581 | }, | |
582 | .freq_tbl = clk_tbl_gsbi_uart, | |
583 | .clkr = { | |
584 | .enable_reg = 0x2af4, | |
585 | .enable_mask = BIT(11), | |
586 | .hw.init = &(struct clk_init_data){ | |
587 | .name = "gsbi10_uart_src", | |
588 | .parent_names = gcc_pxo_pll8, | |
589 | .num_parents = 2, | |
590 | .ops = &clk_rcg_ops, | |
591 | .flags = CLK_SET_PARENT_GATE, | |
592 | }, | |
593 | }, | |
594 | }; | |
595 | ||
596 | static struct clk_branch gsbi10_uart_clk = { | |
597 | .halt_reg = 0x2fd0, | |
598 | .halt_bit = 2, | |
599 | .clkr = { | |
600 | .enable_reg = 0x2af4, | |
601 | .enable_mask = BIT(9), | |
602 | .hw.init = &(struct clk_init_data){ | |
603 | .name = "gsbi10_uart_clk", | |
604 | .parent_names = (const char *[]){ "gsbi10_uart_src" }, | |
605 | .num_parents = 1, | |
606 | .ops = &clk_branch_ops, | |
607 | .flags = CLK_SET_RATE_PARENT, | |
608 | }, | |
609 | }, | |
610 | }; | |
611 | ||
612 | static struct clk_rcg gsbi11_uart_src = { | |
613 | .ns_reg = 0x2b14, | |
614 | .md_reg = 0x2b10, | |
615 | .mn = { | |
616 | .mnctr_en_bit = 8, | |
617 | .mnctr_reset_bit = 7, | |
618 | .mnctr_mode_shift = 5, | |
619 | .n_val_shift = 16, | |
620 | .m_val_shift = 16, | |
621 | .width = 16, | |
622 | }, | |
623 | .p = { | |
624 | .pre_div_shift = 3, | |
625 | .pre_div_width = 2, | |
626 | }, | |
627 | .s = { | |
628 | .src_sel_shift = 0, | |
629 | .parent_map = gcc_pxo_pll8_map, | |
630 | }, | |
631 | .freq_tbl = clk_tbl_gsbi_uart, | |
632 | .clkr = { | |
633 | .enable_reg = 0x2b14, | |
634 | .enable_mask = BIT(11), | |
635 | .hw.init = &(struct clk_init_data){ | |
636 | .name = "gsbi11_uart_src", | |
637 | .parent_names = gcc_pxo_pll8, | |
638 | .num_parents = 2, | |
639 | .ops = &clk_rcg_ops, | |
640 | .flags = CLK_SET_PARENT_GATE, | |
641 | }, | |
642 | }, | |
643 | }; | |
644 | ||
645 | static struct clk_branch gsbi11_uart_clk = { | |
646 | .halt_reg = 0x2fd4, | |
647 | .halt_bit = 17, | |
648 | .clkr = { | |
649 | .enable_reg = 0x2b14, | |
650 | .enable_mask = BIT(9), | |
651 | .hw.init = &(struct clk_init_data){ | |
652 | .name = "gsbi11_uart_clk", | |
653 | .parent_names = (const char *[]){ "gsbi11_uart_src" }, | |
654 | .num_parents = 1, | |
655 | .ops = &clk_branch_ops, | |
656 | .flags = CLK_SET_RATE_PARENT, | |
657 | }, | |
658 | }, | |
659 | }; | |
660 | ||
661 | static struct clk_rcg gsbi12_uart_src = { | |
662 | .ns_reg = 0x2b34, | |
663 | .md_reg = 0x2b30, | |
664 | .mn = { | |
665 | .mnctr_en_bit = 8, | |
666 | .mnctr_reset_bit = 7, | |
667 | .mnctr_mode_shift = 5, | |
668 | .n_val_shift = 16, | |
669 | .m_val_shift = 16, | |
670 | .width = 16, | |
671 | }, | |
672 | .p = { | |
673 | .pre_div_shift = 3, | |
674 | .pre_div_width = 2, | |
675 | }, | |
676 | .s = { | |
677 | .src_sel_shift = 0, | |
678 | .parent_map = gcc_pxo_pll8_map, | |
679 | }, | |
680 | .freq_tbl = clk_tbl_gsbi_uart, | |
681 | .clkr = { | |
682 | .enable_reg = 0x2b34, | |
683 | .enable_mask = BIT(11), | |
684 | .hw.init = &(struct clk_init_data){ | |
685 | .name = "gsbi12_uart_src", | |
686 | .parent_names = gcc_pxo_pll8, | |
687 | .num_parents = 2, | |
688 | .ops = &clk_rcg_ops, | |
689 | .flags = CLK_SET_PARENT_GATE, | |
690 | }, | |
691 | }, | |
692 | }; | |
693 | ||
694 | static struct clk_branch gsbi12_uart_clk = { | |
695 | .halt_reg = 0x2fd4, | |
696 | .halt_bit = 13, | |
697 | .clkr = { | |
698 | .enable_reg = 0x2b34, | |
699 | .enable_mask = BIT(9), | |
700 | .hw.init = &(struct clk_init_data){ | |
701 | .name = "gsbi12_uart_clk", | |
702 | .parent_names = (const char *[]){ "gsbi12_uart_src" }, | |
703 | .num_parents = 1, | |
704 | .ops = &clk_branch_ops, | |
705 | .flags = CLK_SET_RATE_PARENT, | |
706 | }, | |
707 | }, | |
708 | }; | |
709 | ||
710 | static struct freq_tbl clk_tbl_gsbi_qup[] = { | |
711 | { 1100000, P_PXO, 1, 2, 49 }, | |
712 | { 5400000, P_PXO, 1, 1, 5 }, | |
713 | { 10800000, P_PXO, 1, 2, 5 }, | |
714 | { 15060000, P_PLL8, 1, 2, 51 }, | |
715 | { 24000000, P_PLL8, 4, 1, 4 }, | |
716 | { 25600000, P_PLL8, 1, 1, 15 }, | |
717 | { 27000000, P_PXO, 1, 0, 0 }, | |
718 | { 48000000, P_PLL8, 4, 1, 2 }, | |
719 | { 51200000, P_PLL8, 1, 2, 15 }, | |
720 | { } | |
721 | }; | |
722 | ||
723 | static struct clk_rcg gsbi1_qup_src = { | |
724 | .ns_reg = 0x29cc, | |
725 | .md_reg = 0x29c8, | |
726 | .mn = { | |
727 | .mnctr_en_bit = 8, | |
728 | .mnctr_reset_bit = 7, | |
729 | .mnctr_mode_shift = 5, | |
730 | .n_val_shift = 16, | |
731 | .m_val_shift = 16, | |
732 | .width = 8, | |
733 | }, | |
734 | .p = { | |
735 | .pre_div_shift = 3, | |
736 | .pre_div_width = 2, | |
737 | }, | |
738 | .s = { | |
739 | .src_sel_shift = 0, | |
740 | .parent_map = gcc_pxo_pll8_map, | |
741 | }, | |
742 | .freq_tbl = clk_tbl_gsbi_qup, | |
743 | .clkr = { | |
744 | .enable_reg = 0x29cc, | |
745 | .enable_mask = BIT(11), | |
746 | .hw.init = &(struct clk_init_data){ | |
747 | .name = "gsbi1_qup_src", | |
748 | .parent_names = gcc_pxo_pll8, | |
749 | .num_parents = 2, | |
750 | .ops = &clk_rcg_ops, | |
751 | .flags = CLK_SET_PARENT_GATE, | |
752 | }, | |
753 | }, | |
754 | }; | |
755 | ||
756 | static struct clk_branch gsbi1_qup_clk = { | |
757 | .halt_reg = 0x2fcc, | |
758 | .halt_bit = 9, | |
759 | .clkr = { | |
760 | .enable_reg = 0x29cc, | |
761 | .enable_mask = BIT(9), | |
762 | .hw.init = &(struct clk_init_data){ | |
763 | .name = "gsbi1_qup_clk", | |
764 | .parent_names = (const char *[]){ "gsbi1_qup_src" }, | |
765 | .num_parents = 1, | |
766 | .ops = &clk_branch_ops, | |
767 | .flags = CLK_SET_RATE_PARENT, | |
768 | }, | |
769 | }, | |
770 | }; | |
771 | ||
772 | static struct clk_rcg gsbi2_qup_src = { | |
773 | .ns_reg = 0x29ec, | |
774 | .md_reg = 0x29e8, | |
775 | .mn = { | |
776 | .mnctr_en_bit = 8, | |
777 | .mnctr_reset_bit = 7, | |
778 | .mnctr_mode_shift = 5, | |
779 | .n_val_shift = 16, | |
780 | .m_val_shift = 16, | |
781 | .width = 8, | |
782 | }, | |
783 | .p = { | |
784 | .pre_div_shift = 3, | |
785 | .pre_div_width = 2, | |
786 | }, | |
787 | .s = { | |
788 | .src_sel_shift = 0, | |
789 | .parent_map = gcc_pxo_pll8_map, | |
790 | }, | |
791 | .freq_tbl = clk_tbl_gsbi_qup, | |
792 | .clkr = { | |
793 | .enable_reg = 0x29ec, | |
794 | .enable_mask = BIT(11), | |
795 | .hw.init = &(struct clk_init_data){ | |
796 | .name = "gsbi2_qup_src", | |
797 | .parent_names = gcc_pxo_pll8, | |
798 | .num_parents = 2, | |
799 | .ops = &clk_rcg_ops, | |
800 | .flags = CLK_SET_PARENT_GATE, | |
801 | }, | |
802 | }, | |
803 | }; | |
804 | ||
805 | static struct clk_branch gsbi2_qup_clk = { | |
806 | .halt_reg = 0x2fcc, | |
807 | .halt_bit = 4, | |
808 | .clkr = { | |
809 | .enable_reg = 0x29ec, | |
810 | .enable_mask = BIT(9), | |
811 | .hw.init = &(struct clk_init_data){ | |
812 | .name = "gsbi2_qup_clk", | |
813 | .parent_names = (const char *[]){ "gsbi2_qup_src" }, | |
814 | .num_parents = 1, | |
815 | .ops = &clk_branch_ops, | |
816 | .flags = CLK_SET_RATE_PARENT, | |
817 | }, | |
818 | }, | |
819 | }; | |
820 | ||
821 | static struct clk_rcg gsbi3_qup_src = { | |
822 | .ns_reg = 0x2a0c, | |
823 | .md_reg = 0x2a08, | |
824 | .mn = { | |
825 | .mnctr_en_bit = 8, | |
826 | .mnctr_reset_bit = 7, | |
827 | .mnctr_mode_shift = 5, | |
828 | .n_val_shift = 16, | |
829 | .m_val_shift = 16, | |
830 | .width = 8, | |
831 | }, | |
832 | .p = { | |
833 | .pre_div_shift = 3, | |
834 | .pre_div_width = 2, | |
835 | }, | |
836 | .s = { | |
837 | .src_sel_shift = 0, | |
838 | .parent_map = gcc_pxo_pll8_map, | |
839 | }, | |
840 | .freq_tbl = clk_tbl_gsbi_qup, | |
841 | .clkr = { | |
842 | .enable_reg = 0x2a0c, | |
843 | .enable_mask = BIT(11), | |
844 | .hw.init = &(struct clk_init_data){ | |
845 | .name = "gsbi3_qup_src", | |
846 | .parent_names = gcc_pxo_pll8, | |
847 | .num_parents = 2, | |
848 | .ops = &clk_rcg_ops, | |
849 | .flags = CLK_SET_PARENT_GATE, | |
850 | }, | |
851 | }, | |
852 | }; | |
853 | ||
854 | static struct clk_branch gsbi3_qup_clk = { | |
855 | .halt_reg = 0x2fcc, | |
856 | .halt_bit = 0, | |
857 | .clkr = { | |
858 | .enable_reg = 0x2a0c, | |
859 | .enable_mask = BIT(9), | |
860 | .hw.init = &(struct clk_init_data){ | |
861 | .name = "gsbi3_qup_clk", | |
862 | .parent_names = (const char *[]){ "gsbi3_qup_src" }, | |
863 | .num_parents = 1, | |
864 | .ops = &clk_branch_ops, | |
865 | .flags = CLK_SET_RATE_PARENT, | |
866 | }, | |
867 | }, | |
868 | }; | |
869 | ||
870 | static struct clk_rcg gsbi4_qup_src = { | |
871 | .ns_reg = 0x2a2c, | |
872 | .md_reg = 0x2a28, | |
873 | .mn = { | |
874 | .mnctr_en_bit = 8, | |
875 | .mnctr_reset_bit = 7, | |
876 | .mnctr_mode_shift = 5, | |
877 | .n_val_shift = 16, | |
878 | .m_val_shift = 16, | |
879 | .width = 8, | |
880 | }, | |
881 | .p = { | |
882 | .pre_div_shift = 3, | |
883 | .pre_div_width = 2, | |
884 | }, | |
885 | .s = { | |
886 | .src_sel_shift = 0, | |
887 | .parent_map = gcc_pxo_pll8_map, | |
888 | }, | |
889 | .freq_tbl = clk_tbl_gsbi_qup, | |
890 | .clkr = { | |
891 | .enable_reg = 0x2a2c, | |
892 | .enable_mask = BIT(11), | |
893 | .hw.init = &(struct clk_init_data){ | |
894 | .name = "gsbi4_qup_src", | |
895 | .parent_names = gcc_pxo_pll8, | |
896 | .num_parents = 2, | |
897 | .ops = &clk_rcg_ops, | |
898 | .flags = CLK_SET_PARENT_GATE, | |
899 | }, | |
900 | }, | |
901 | }; | |
902 | ||
903 | static struct clk_branch gsbi4_qup_clk = { | |
904 | .halt_reg = 0x2fd0, | |
905 | .halt_bit = 24, | |
906 | .clkr = { | |
907 | .enable_reg = 0x2a2c, | |
908 | .enable_mask = BIT(9), | |
909 | .hw.init = &(struct clk_init_data){ | |
910 | .name = "gsbi4_qup_clk", | |
911 | .parent_names = (const char *[]){ "gsbi4_qup_src" }, | |
912 | .num_parents = 1, | |
913 | .ops = &clk_branch_ops, | |
914 | .flags = CLK_SET_RATE_PARENT, | |
915 | }, | |
916 | }, | |
917 | }; | |
918 | ||
919 | static struct clk_rcg gsbi5_qup_src = { | |
920 | .ns_reg = 0x2a4c, | |
921 | .md_reg = 0x2a48, | |
922 | .mn = { | |
923 | .mnctr_en_bit = 8, | |
924 | .mnctr_reset_bit = 7, | |
925 | .mnctr_mode_shift = 5, | |
926 | .n_val_shift = 16, | |
927 | .m_val_shift = 16, | |
928 | .width = 8, | |
929 | }, | |
930 | .p = { | |
931 | .pre_div_shift = 3, | |
932 | .pre_div_width = 2, | |
933 | }, | |
934 | .s = { | |
935 | .src_sel_shift = 0, | |
936 | .parent_map = gcc_pxo_pll8_map, | |
937 | }, | |
938 | .freq_tbl = clk_tbl_gsbi_qup, | |
939 | .clkr = { | |
940 | .enable_reg = 0x2a4c, | |
941 | .enable_mask = BIT(11), | |
942 | .hw.init = &(struct clk_init_data){ | |
943 | .name = "gsbi5_qup_src", | |
944 | .parent_names = gcc_pxo_pll8, | |
945 | .num_parents = 2, | |
946 | .ops = &clk_rcg_ops, | |
947 | .flags = CLK_SET_PARENT_GATE, | |
948 | }, | |
949 | }, | |
950 | }; | |
951 | ||
952 | static struct clk_branch gsbi5_qup_clk = { | |
953 | .halt_reg = 0x2fd0, | |
954 | .halt_bit = 20, | |
955 | .clkr = { | |
956 | .enable_reg = 0x2a4c, | |
957 | .enable_mask = BIT(9), | |
958 | .hw.init = &(struct clk_init_data){ | |
959 | .name = "gsbi5_qup_clk", | |
960 | .parent_names = (const char *[]){ "gsbi5_qup_src" }, | |
961 | .num_parents = 1, | |
962 | .ops = &clk_branch_ops, | |
963 | .flags = CLK_SET_RATE_PARENT, | |
964 | }, | |
965 | }, | |
966 | }; | |
967 | ||
968 | static struct clk_rcg gsbi6_qup_src = { | |
969 | .ns_reg = 0x2a6c, | |
970 | .md_reg = 0x2a68, | |
971 | .mn = { | |
972 | .mnctr_en_bit = 8, | |
973 | .mnctr_reset_bit = 7, | |
974 | .mnctr_mode_shift = 5, | |
975 | .n_val_shift = 16, | |
976 | .m_val_shift = 16, | |
977 | .width = 8, | |
978 | }, | |
979 | .p = { | |
980 | .pre_div_shift = 3, | |
981 | .pre_div_width = 2, | |
982 | }, | |
983 | .s = { | |
984 | .src_sel_shift = 0, | |
985 | .parent_map = gcc_pxo_pll8_map, | |
986 | }, | |
987 | .freq_tbl = clk_tbl_gsbi_qup, | |
988 | .clkr = { | |
989 | .enable_reg = 0x2a6c, | |
990 | .enable_mask = BIT(11), | |
991 | .hw.init = &(struct clk_init_data){ | |
992 | .name = "gsbi6_qup_src", | |
993 | .parent_names = gcc_pxo_pll8, | |
994 | .num_parents = 2, | |
995 | .ops = &clk_rcg_ops, | |
996 | .flags = CLK_SET_PARENT_GATE, | |
997 | }, | |
998 | }, | |
999 | }; | |
1000 | ||
1001 | static struct clk_branch gsbi6_qup_clk = { | |
1002 | .halt_reg = 0x2fd0, | |
1003 | .halt_bit = 16, | |
1004 | .clkr = { | |
1005 | .enable_reg = 0x2a6c, | |
1006 | .enable_mask = BIT(9), | |
1007 | .hw.init = &(struct clk_init_data){ | |
1008 | .name = "gsbi6_qup_clk", | |
1009 | .parent_names = (const char *[]){ "gsbi6_qup_src" }, | |
1010 | .num_parents = 1, | |
1011 | .ops = &clk_branch_ops, | |
1012 | .flags = CLK_SET_RATE_PARENT, | |
1013 | }, | |
1014 | }, | |
1015 | }; | |
1016 | ||
1017 | static struct clk_rcg gsbi7_qup_src = { | |
1018 | .ns_reg = 0x2a8c, | |
1019 | .md_reg = 0x2a88, | |
1020 | .mn = { | |
1021 | .mnctr_en_bit = 8, | |
1022 | .mnctr_reset_bit = 7, | |
1023 | .mnctr_mode_shift = 5, | |
1024 | .n_val_shift = 16, | |
1025 | .m_val_shift = 16, | |
1026 | .width = 8, | |
1027 | }, | |
1028 | .p = { | |
1029 | .pre_div_shift = 3, | |
1030 | .pre_div_width = 2, | |
1031 | }, | |
1032 | .s = { | |
1033 | .src_sel_shift = 0, | |
1034 | .parent_map = gcc_pxo_pll8_map, | |
1035 | }, | |
1036 | .freq_tbl = clk_tbl_gsbi_qup, | |
1037 | .clkr = { | |
1038 | .enable_reg = 0x2a8c, | |
1039 | .enable_mask = BIT(11), | |
1040 | .hw.init = &(struct clk_init_data){ | |
1041 | .name = "gsbi7_qup_src", | |
1042 | .parent_names = gcc_pxo_pll8, | |
1043 | .num_parents = 2, | |
1044 | .ops = &clk_rcg_ops, | |
1045 | .flags = CLK_SET_PARENT_GATE, | |
1046 | }, | |
1047 | }, | |
1048 | }; | |
1049 | ||
1050 | static struct clk_branch gsbi7_qup_clk = { | |
1051 | .halt_reg = 0x2fd0, | |
1052 | .halt_bit = 12, | |
1053 | .clkr = { | |
1054 | .enable_reg = 0x2a8c, | |
1055 | .enable_mask = BIT(9), | |
1056 | .hw.init = &(struct clk_init_data){ | |
1057 | .name = "gsbi7_qup_clk", | |
1058 | .parent_names = (const char *[]){ "gsbi7_qup_src" }, | |
1059 | .num_parents = 1, | |
1060 | .ops = &clk_branch_ops, | |
1061 | .flags = CLK_SET_RATE_PARENT, | |
1062 | }, | |
1063 | }, | |
1064 | }; | |
1065 | ||
1066 | static struct clk_rcg gsbi8_qup_src = { | |
1067 | .ns_reg = 0x2aac, | |
1068 | .md_reg = 0x2aa8, | |
1069 | .mn = { | |
1070 | .mnctr_en_bit = 8, | |
1071 | .mnctr_reset_bit = 7, | |
1072 | .mnctr_mode_shift = 5, | |
1073 | .n_val_shift = 16, | |
1074 | .m_val_shift = 16, | |
1075 | .width = 8, | |
1076 | }, | |
1077 | .p = { | |
1078 | .pre_div_shift = 3, | |
1079 | .pre_div_width = 2, | |
1080 | }, | |
1081 | .s = { | |
1082 | .src_sel_shift = 0, | |
1083 | .parent_map = gcc_pxo_pll8_map, | |
1084 | }, | |
1085 | .freq_tbl = clk_tbl_gsbi_qup, | |
1086 | .clkr = { | |
1087 | .enable_reg = 0x2aac, | |
1088 | .enable_mask = BIT(11), | |
1089 | .hw.init = &(struct clk_init_data){ | |
1090 | .name = "gsbi8_qup_src", | |
1091 | .parent_names = gcc_pxo_pll8, | |
1092 | .num_parents = 2, | |
1093 | .ops = &clk_rcg_ops, | |
1094 | .flags = CLK_SET_PARENT_GATE, | |
1095 | }, | |
1096 | }, | |
1097 | }; | |
1098 | ||
1099 | static struct clk_branch gsbi8_qup_clk = { | |
1100 | .halt_reg = 0x2fd0, | |
1101 | .halt_bit = 8, | |
1102 | .clkr = { | |
1103 | .enable_reg = 0x2aac, | |
1104 | .enable_mask = BIT(9), | |
1105 | .hw.init = &(struct clk_init_data){ | |
1106 | .name = "gsbi8_qup_clk", | |
1107 | .parent_names = (const char *[]){ "gsbi8_qup_src" }, | |
1108 | .num_parents = 1, | |
1109 | .ops = &clk_branch_ops, | |
1110 | .flags = CLK_SET_RATE_PARENT, | |
1111 | }, | |
1112 | }, | |
1113 | }; | |
1114 | ||
1115 | static struct clk_rcg gsbi9_qup_src = { | |
1116 | .ns_reg = 0x2acc, | |
1117 | .md_reg = 0x2ac8, | |
1118 | .mn = { | |
1119 | .mnctr_en_bit = 8, | |
1120 | .mnctr_reset_bit = 7, | |
1121 | .mnctr_mode_shift = 5, | |
1122 | .n_val_shift = 16, | |
1123 | .m_val_shift = 16, | |
1124 | .width = 8, | |
1125 | }, | |
1126 | .p = { | |
1127 | .pre_div_shift = 3, | |
1128 | .pre_div_width = 2, | |
1129 | }, | |
1130 | .s = { | |
1131 | .src_sel_shift = 0, | |
1132 | .parent_map = gcc_pxo_pll8_map, | |
1133 | }, | |
1134 | .freq_tbl = clk_tbl_gsbi_qup, | |
1135 | .clkr = { | |
1136 | .enable_reg = 0x2acc, | |
1137 | .enable_mask = BIT(11), | |
1138 | .hw.init = &(struct clk_init_data){ | |
1139 | .name = "gsbi9_qup_src", | |
1140 | .parent_names = gcc_pxo_pll8, | |
1141 | .num_parents = 2, | |
1142 | .ops = &clk_rcg_ops, | |
1143 | .flags = CLK_SET_PARENT_GATE, | |
1144 | }, | |
1145 | }, | |
1146 | }; | |
1147 | ||
1148 | static struct clk_branch gsbi9_qup_clk = { | |
1149 | .halt_reg = 0x2fd0, | |
1150 | .halt_bit = 4, | |
1151 | .clkr = { | |
1152 | .enable_reg = 0x2acc, | |
1153 | .enable_mask = BIT(9), | |
1154 | .hw.init = &(struct clk_init_data){ | |
1155 | .name = "gsbi9_qup_clk", | |
1156 | .parent_names = (const char *[]){ "gsbi9_qup_src" }, | |
1157 | .num_parents = 1, | |
1158 | .ops = &clk_branch_ops, | |
1159 | .flags = CLK_SET_RATE_PARENT, | |
1160 | }, | |
1161 | }, | |
1162 | }; | |
1163 | ||
1164 | static struct clk_rcg gsbi10_qup_src = { | |
1165 | .ns_reg = 0x2aec, | |
1166 | .md_reg = 0x2ae8, | |
1167 | .mn = { | |
1168 | .mnctr_en_bit = 8, | |
1169 | .mnctr_reset_bit = 7, | |
1170 | .mnctr_mode_shift = 5, | |
1171 | .n_val_shift = 16, | |
1172 | .m_val_shift = 16, | |
1173 | .width = 8, | |
1174 | }, | |
1175 | .p = { | |
1176 | .pre_div_shift = 3, | |
1177 | .pre_div_width = 2, | |
1178 | }, | |
1179 | .s = { | |
1180 | .src_sel_shift = 0, | |
1181 | .parent_map = gcc_pxo_pll8_map, | |
1182 | }, | |
1183 | .freq_tbl = clk_tbl_gsbi_qup, | |
1184 | .clkr = { | |
1185 | .enable_reg = 0x2aec, | |
1186 | .enable_mask = BIT(11), | |
1187 | .hw.init = &(struct clk_init_data){ | |
1188 | .name = "gsbi10_qup_src", | |
1189 | .parent_names = gcc_pxo_pll8, | |
1190 | .num_parents = 2, | |
1191 | .ops = &clk_rcg_ops, | |
1192 | .flags = CLK_SET_PARENT_GATE, | |
1193 | }, | |
1194 | }, | |
1195 | }; | |
1196 | ||
1197 | static struct clk_branch gsbi10_qup_clk = { | |
1198 | .halt_reg = 0x2fd0, | |
1199 | .halt_bit = 0, | |
1200 | .clkr = { | |
1201 | .enable_reg = 0x2aec, | |
1202 | .enable_mask = BIT(9), | |
1203 | .hw.init = &(struct clk_init_data){ | |
1204 | .name = "gsbi10_qup_clk", | |
1205 | .parent_names = (const char *[]){ "gsbi10_qup_src" }, | |
1206 | .num_parents = 1, | |
1207 | .ops = &clk_branch_ops, | |
1208 | .flags = CLK_SET_RATE_PARENT, | |
1209 | }, | |
1210 | }, | |
1211 | }; | |
1212 | ||
1213 | static struct clk_rcg gsbi11_qup_src = { | |
1214 | .ns_reg = 0x2b0c, | |
1215 | .md_reg = 0x2b08, | |
1216 | .mn = { | |
1217 | .mnctr_en_bit = 8, | |
1218 | .mnctr_reset_bit = 7, | |
1219 | .mnctr_mode_shift = 5, | |
1220 | .n_val_shift = 16, | |
1221 | .m_val_shift = 16, | |
1222 | .width = 8, | |
1223 | }, | |
1224 | .p = { | |
1225 | .pre_div_shift = 3, | |
1226 | .pre_div_width = 2, | |
1227 | }, | |
1228 | .s = { | |
1229 | .src_sel_shift = 0, | |
1230 | .parent_map = gcc_pxo_pll8_map, | |
1231 | }, | |
1232 | .freq_tbl = clk_tbl_gsbi_qup, | |
1233 | .clkr = { | |
1234 | .enable_reg = 0x2b0c, | |
1235 | .enable_mask = BIT(11), | |
1236 | .hw.init = &(struct clk_init_data){ | |
1237 | .name = "gsbi11_qup_src", | |
1238 | .parent_names = gcc_pxo_pll8, | |
1239 | .num_parents = 2, | |
1240 | .ops = &clk_rcg_ops, | |
1241 | .flags = CLK_SET_PARENT_GATE, | |
1242 | }, | |
1243 | }, | |
1244 | }; | |
1245 | ||
1246 | static struct clk_branch gsbi11_qup_clk = { | |
1247 | .halt_reg = 0x2fd4, | |
1248 | .halt_bit = 15, | |
1249 | .clkr = { | |
1250 | .enable_reg = 0x2b0c, | |
1251 | .enable_mask = BIT(9), | |
1252 | .hw.init = &(struct clk_init_data){ | |
1253 | .name = "gsbi11_qup_clk", | |
1254 | .parent_names = (const char *[]){ "gsbi11_qup_src" }, | |
1255 | .num_parents = 1, | |
1256 | .ops = &clk_branch_ops, | |
1257 | .flags = CLK_SET_RATE_PARENT, | |
1258 | }, | |
1259 | }, | |
1260 | }; | |
1261 | ||
1262 | static struct clk_rcg gsbi12_qup_src = { | |
1263 | .ns_reg = 0x2b2c, | |
1264 | .md_reg = 0x2b28, | |
1265 | .mn = { | |
1266 | .mnctr_en_bit = 8, | |
1267 | .mnctr_reset_bit = 7, | |
1268 | .mnctr_mode_shift = 5, | |
1269 | .n_val_shift = 16, | |
1270 | .m_val_shift = 16, | |
1271 | .width = 8, | |
1272 | }, | |
1273 | .p = { | |
1274 | .pre_div_shift = 3, | |
1275 | .pre_div_width = 2, | |
1276 | }, | |
1277 | .s = { | |
1278 | .src_sel_shift = 0, | |
1279 | .parent_map = gcc_pxo_pll8_map, | |
1280 | }, | |
1281 | .freq_tbl = clk_tbl_gsbi_qup, | |
1282 | .clkr = { | |
1283 | .enable_reg = 0x2b2c, | |
1284 | .enable_mask = BIT(11), | |
1285 | .hw.init = &(struct clk_init_data){ | |
1286 | .name = "gsbi12_qup_src", | |
1287 | .parent_names = gcc_pxo_pll8, | |
1288 | .num_parents = 2, | |
1289 | .ops = &clk_rcg_ops, | |
1290 | .flags = CLK_SET_PARENT_GATE, | |
1291 | }, | |
1292 | }, | |
1293 | }; | |
1294 | ||
1295 | static struct clk_branch gsbi12_qup_clk = { | |
1296 | .halt_reg = 0x2fd4, | |
1297 | .halt_bit = 11, | |
1298 | .clkr = { | |
1299 | .enable_reg = 0x2b2c, | |
1300 | .enable_mask = BIT(9), | |
1301 | .hw.init = &(struct clk_init_data){ | |
1302 | .name = "gsbi12_qup_clk", | |
1303 | .parent_names = (const char *[]){ "gsbi12_qup_src" }, | |
1304 | .num_parents = 1, | |
1305 | .ops = &clk_branch_ops, | |
1306 | .flags = CLK_SET_RATE_PARENT, | |
1307 | }, | |
1308 | }, | |
1309 | }; | |
1310 | ||
1311 | static const struct freq_tbl clk_tbl_gp[] = { | |
1312 | { 9600000, P_CXO, 2, 0, 0 }, | |
1313 | { 13500000, P_PXO, 2, 0, 0 }, | |
1314 | { 19200000, P_CXO, 1, 0, 0 }, | |
1315 | { 27000000, P_PXO, 1, 0, 0 }, | |
1316 | { 64000000, P_PLL8, 2, 1, 3 }, | |
1317 | { 76800000, P_PLL8, 1, 1, 5 }, | |
1318 | { 96000000, P_PLL8, 4, 0, 0 }, | |
1319 | { 128000000, P_PLL8, 3, 0, 0 }, | |
1320 | { 192000000, P_PLL8, 2, 0, 0 }, | |
1321 | { } | |
1322 | }; | |
1323 | ||
1324 | static struct clk_rcg gp0_src = { | |
1325 | .ns_reg = 0x2d24, | |
1326 | .md_reg = 0x2d00, | |
1327 | .mn = { | |
1328 | .mnctr_en_bit = 8, | |
1329 | .mnctr_reset_bit = 7, | |
1330 | .mnctr_mode_shift = 5, | |
1331 | .n_val_shift = 16, | |
1332 | .m_val_shift = 16, | |
1333 | .width = 8, | |
1334 | }, | |
1335 | .p = { | |
1336 | .pre_div_shift = 3, | |
1337 | .pre_div_width = 2, | |
1338 | }, | |
1339 | .s = { | |
1340 | .src_sel_shift = 0, | |
1341 | .parent_map = gcc_pxo_pll8_cxo_map, | |
1342 | }, | |
1343 | .freq_tbl = clk_tbl_gp, | |
1344 | .clkr = { | |
1345 | .enable_reg = 0x2d24, | |
1346 | .enable_mask = BIT(11), | |
1347 | .hw.init = &(struct clk_init_data){ | |
1348 | .name = "gp0_src", | |
1349 | .parent_names = gcc_pxo_pll8_cxo, | |
1350 | .num_parents = 3, | |
1351 | .ops = &clk_rcg_ops, | |
1352 | .flags = CLK_SET_PARENT_GATE, | |
1353 | }, | |
1354 | } | |
1355 | }; | |
1356 | ||
1357 | static struct clk_branch gp0_clk = { | |
1358 | .halt_reg = 0x2fd8, | |
1359 | .halt_bit = 7, | |
1360 | .clkr = { | |
1361 | .enable_reg = 0x2d24, | |
1362 | .enable_mask = BIT(9), | |
1363 | .hw.init = &(struct clk_init_data){ | |
1364 | .name = "gp0_clk", | |
1365 | .parent_names = (const char *[]){ "gp0_src" }, | |
1366 | .num_parents = 1, | |
1367 | .ops = &clk_branch_ops, | |
1368 | .flags = CLK_SET_RATE_PARENT, | |
1369 | }, | |
1370 | }, | |
1371 | }; | |
1372 | ||
1373 | static struct clk_rcg gp1_src = { | |
1374 | .ns_reg = 0x2d44, | |
1375 | .md_reg = 0x2d40, | |
1376 | .mn = { | |
1377 | .mnctr_en_bit = 8, | |
1378 | .mnctr_reset_bit = 7, | |
1379 | .mnctr_mode_shift = 5, | |
1380 | .n_val_shift = 16, | |
1381 | .m_val_shift = 16, | |
1382 | .width = 8, | |
1383 | }, | |
1384 | .p = { | |
1385 | .pre_div_shift = 3, | |
1386 | .pre_div_width = 2, | |
1387 | }, | |
1388 | .s = { | |
1389 | .src_sel_shift = 0, | |
1390 | .parent_map = gcc_pxo_pll8_cxo_map, | |
1391 | }, | |
1392 | .freq_tbl = clk_tbl_gp, | |
1393 | .clkr = { | |
1394 | .enable_reg = 0x2d44, | |
1395 | .enable_mask = BIT(11), | |
1396 | .hw.init = &(struct clk_init_data){ | |
1397 | .name = "gp1_src", | |
1398 | .parent_names = gcc_pxo_pll8_cxo, | |
1399 | .num_parents = 3, | |
1400 | .ops = &clk_rcg_ops, | |
1401 | .flags = CLK_SET_RATE_GATE, | |
1402 | }, | |
1403 | } | |
1404 | }; | |
1405 | ||
1406 | static struct clk_branch gp1_clk = { | |
1407 | .halt_reg = 0x2fd8, | |
1408 | .halt_bit = 6, | |
1409 | .clkr = { | |
1410 | .enable_reg = 0x2d44, | |
1411 | .enable_mask = BIT(9), | |
1412 | .hw.init = &(struct clk_init_data){ | |
1413 | .name = "gp1_clk", | |
1414 | .parent_names = (const char *[]){ "gp1_src" }, | |
1415 | .num_parents = 1, | |
1416 | .ops = &clk_branch_ops, | |
1417 | .flags = CLK_SET_RATE_PARENT, | |
1418 | }, | |
1419 | }, | |
1420 | }; | |
1421 | ||
1422 | static struct clk_rcg gp2_src = { | |
1423 | .ns_reg = 0x2d64, | |
1424 | .md_reg = 0x2d60, | |
1425 | .mn = { | |
1426 | .mnctr_en_bit = 8, | |
1427 | .mnctr_reset_bit = 7, | |
1428 | .mnctr_mode_shift = 5, | |
1429 | .n_val_shift = 16, | |
1430 | .m_val_shift = 16, | |
1431 | .width = 8, | |
1432 | }, | |
1433 | .p = { | |
1434 | .pre_div_shift = 3, | |
1435 | .pre_div_width = 2, | |
1436 | }, | |
1437 | .s = { | |
1438 | .src_sel_shift = 0, | |
1439 | .parent_map = gcc_pxo_pll8_cxo_map, | |
1440 | }, | |
1441 | .freq_tbl = clk_tbl_gp, | |
1442 | .clkr = { | |
1443 | .enable_reg = 0x2d64, | |
1444 | .enable_mask = BIT(11), | |
1445 | .hw.init = &(struct clk_init_data){ | |
1446 | .name = "gp2_src", | |
1447 | .parent_names = gcc_pxo_pll8_cxo, | |
1448 | .num_parents = 3, | |
1449 | .ops = &clk_rcg_ops, | |
1450 | .flags = CLK_SET_RATE_GATE, | |
1451 | }, | |
1452 | } | |
1453 | }; | |
1454 | ||
1455 | static struct clk_branch gp2_clk = { | |
1456 | .halt_reg = 0x2fd8, | |
1457 | .halt_bit = 5, | |
1458 | .clkr = { | |
1459 | .enable_reg = 0x2d64, | |
1460 | .enable_mask = BIT(9), | |
1461 | .hw.init = &(struct clk_init_data){ | |
1462 | .name = "gp2_clk", | |
1463 | .parent_names = (const char *[]){ "gp2_src" }, | |
1464 | .num_parents = 1, | |
1465 | .ops = &clk_branch_ops, | |
1466 | .flags = CLK_SET_RATE_PARENT, | |
1467 | }, | |
1468 | }, | |
1469 | }; | |
1470 | ||
1471 | static struct clk_branch pmem_clk = { | |
1472 | .hwcg_reg = 0x25a0, | |
1473 | .hwcg_bit = 6, | |
1474 | .halt_reg = 0x2fc8, | |
1475 | .halt_bit = 20, | |
1476 | .clkr = { | |
1477 | .enable_reg = 0x25a0, | |
1478 | .enable_mask = BIT(4), | |
1479 | .hw.init = &(struct clk_init_data){ | |
1480 | .name = "pmem_clk", | |
1481 | .ops = &clk_branch_ops, | |
0eeff27b SB |
1482 | }, |
1483 | }, | |
1484 | }; | |
1485 | ||
1486 | static struct clk_rcg prng_src = { | |
1487 | .ns_reg = 0x2e80, | |
1488 | .p = { | |
1489 | .pre_div_shift = 3, | |
1490 | .pre_div_width = 4, | |
1491 | }, | |
1492 | .s = { | |
1493 | .src_sel_shift = 0, | |
1494 | .parent_map = gcc_pxo_pll8_map, | |
1495 | }, | |
1496 | .clkr.hw = { | |
1497 | .init = &(struct clk_init_data){ | |
1498 | .name = "prng_src", | |
1499 | .parent_names = gcc_pxo_pll8, | |
1500 | .num_parents = 2, | |
1501 | .ops = &clk_rcg_ops, | |
1502 | }, | |
1503 | }, | |
1504 | }; | |
1505 | ||
1506 | static struct clk_branch prng_clk = { | |
1507 | .halt_reg = 0x2fd8, | |
1508 | .halt_check = BRANCH_HALT_VOTED, | |
1509 | .halt_bit = 10, | |
1510 | .clkr = { | |
1511 | .enable_reg = 0x3080, | |
1512 | .enable_mask = BIT(10), | |
1513 | .hw.init = &(struct clk_init_data){ | |
1514 | .name = "prng_clk", | |
1515 | .parent_names = (const char *[]){ "prng_src" }, | |
1516 | .num_parents = 1, | |
1517 | .ops = &clk_branch_ops, | |
1518 | }, | |
1519 | }, | |
1520 | }; | |
1521 | ||
1522 | static const struct freq_tbl clk_tbl_sdc[] = { | |
1523 | { 144000, P_PXO, 3, 2, 125 }, | |
1524 | { 400000, P_PLL8, 4, 1, 240 }, | |
1525 | { 16000000, P_PLL8, 4, 1, 6 }, | |
1526 | { 17070000, P_PLL8, 1, 2, 45 }, | |
1527 | { 20210000, P_PLL8, 1, 1, 19 }, | |
1528 | { 24000000, P_PLL8, 4, 1, 4 }, | |
1529 | { 48000000, P_PLL8, 4, 1, 2 }, | |
1530 | { } | |
1531 | }; | |
1532 | ||
1533 | static struct clk_rcg sdc1_src = { | |
1534 | .ns_reg = 0x282c, | |
1535 | .md_reg = 0x2828, | |
1536 | .mn = { | |
1537 | .mnctr_en_bit = 8, | |
1538 | .mnctr_reset_bit = 7, | |
1539 | .mnctr_mode_shift = 5, | |
1540 | .n_val_shift = 16, | |
1541 | .m_val_shift = 16, | |
1542 | .width = 8, | |
1543 | }, | |
1544 | .p = { | |
1545 | .pre_div_shift = 3, | |
1546 | .pre_div_width = 2, | |
1547 | }, | |
1548 | .s = { | |
1549 | .src_sel_shift = 0, | |
1550 | .parent_map = gcc_pxo_pll8_map, | |
1551 | }, | |
1552 | .freq_tbl = clk_tbl_sdc, | |
1553 | .clkr = { | |
1554 | .enable_reg = 0x282c, | |
1555 | .enable_mask = BIT(11), | |
1556 | .hw.init = &(struct clk_init_data){ | |
1557 | .name = "sdc1_src", | |
1558 | .parent_names = gcc_pxo_pll8, | |
1559 | .num_parents = 2, | |
1560 | .ops = &clk_rcg_ops, | |
0eeff27b SB |
1561 | }, |
1562 | } | |
1563 | }; | |
1564 | ||
1565 | static struct clk_branch sdc1_clk = { | |
1566 | .halt_reg = 0x2fc8, | |
1567 | .halt_bit = 6, | |
1568 | .clkr = { | |
1569 | .enable_reg = 0x282c, | |
1570 | .enable_mask = BIT(9), | |
1571 | .hw.init = &(struct clk_init_data){ | |
1572 | .name = "sdc1_clk", | |
1573 | .parent_names = (const char *[]){ "sdc1_src" }, | |
1574 | .num_parents = 1, | |
1575 | .ops = &clk_branch_ops, | |
1576 | .flags = CLK_SET_RATE_PARENT, | |
1577 | }, | |
1578 | }, | |
1579 | }; | |
1580 | ||
1581 | static struct clk_rcg sdc2_src = { | |
1582 | .ns_reg = 0x284c, | |
1583 | .md_reg = 0x2848, | |
1584 | .mn = { | |
1585 | .mnctr_en_bit = 8, | |
1586 | .mnctr_reset_bit = 7, | |
1587 | .mnctr_mode_shift = 5, | |
1588 | .n_val_shift = 16, | |
1589 | .m_val_shift = 16, | |
1590 | .width = 8, | |
1591 | }, | |
1592 | .p = { | |
1593 | .pre_div_shift = 3, | |
1594 | .pre_div_width = 2, | |
1595 | }, | |
1596 | .s = { | |
1597 | .src_sel_shift = 0, | |
1598 | .parent_map = gcc_pxo_pll8_map, | |
1599 | }, | |
1600 | .freq_tbl = clk_tbl_sdc, | |
1601 | .clkr = { | |
1602 | .enable_reg = 0x284c, | |
1603 | .enable_mask = BIT(11), | |
1604 | .hw.init = &(struct clk_init_data){ | |
1605 | .name = "sdc2_src", | |
1606 | .parent_names = gcc_pxo_pll8, | |
1607 | .num_parents = 2, | |
1608 | .ops = &clk_rcg_ops, | |
0eeff27b SB |
1609 | }, |
1610 | } | |
1611 | }; | |
1612 | ||
1613 | static struct clk_branch sdc2_clk = { | |
1614 | .halt_reg = 0x2fc8, | |
1615 | .halt_bit = 5, | |
1616 | .clkr = { | |
1617 | .enable_reg = 0x284c, | |
1618 | .enable_mask = BIT(9), | |
1619 | .hw.init = &(struct clk_init_data){ | |
1620 | .name = "sdc2_clk", | |
1621 | .parent_names = (const char *[]){ "sdc2_src" }, | |
1622 | .num_parents = 1, | |
1623 | .ops = &clk_branch_ops, | |
1624 | .flags = CLK_SET_RATE_PARENT, | |
1625 | }, | |
1626 | }, | |
1627 | }; | |
1628 | ||
1629 | static struct clk_rcg sdc3_src = { | |
1630 | .ns_reg = 0x286c, | |
1631 | .md_reg = 0x2868, | |
1632 | .mn = { | |
1633 | .mnctr_en_bit = 8, | |
1634 | .mnctr_reset_bit = 7, | |
1635 | .mnctr_mode_shift = 5, | |
1636 | .n_val_shift = 16, | |
1637 | .m_val_shift = 16, | |
1638 | .width = 8, | |
1639 | }, | |
1640 | .p = { | |
1641 | .pre_div_shift = 3, | |
1642 | .pre_div_width = 2, | |
1643 | }, | |
1644 | .s = { | |
1645 | .src_sel_shift = 0, | |
1646 | .parent_map = gcc_pxo_pll8_map, | |
1647 | }, | |
1648 | .freq_tbl = clk_tbl_sdc, | |
1649 | .clkr = { | |
1650 | .enable_reg = 0x286c, | |
1651 | .enable_mask = BIT(11), | |
1652 | .hw.init = &(struct clk_init_data){ | |
1653 | .name = "sdc3_src", | |
1654 | .parent_names = gcc_pxo_pll8, | |
1655 | .num_parents = 2, | |
1656 | .ops = &clk_rcg_ops, | |
0eeff27b SB |
1657 | }, |
1658 | } | |
1659 | }; | |
1660 | ||
1661 | static struct clk_branch sdc3_clk = { | |
1662 | .halt_reg = 0x2fc8, | |
1663 | .halt_bit = 4, | |
1664 | .clkr = { | |
1665 | .enable_reg = 0x286c, | |
1666 | .enable_mask = BIT(9), | |
1667 | .hw.init = &(struct clk_init_data){ | |
1668 | .name = "sdc3_clk", | |
1669 | .parent_names = (const char *[]){ "sdc3_src" }, | |
1670 | .num_parents = 1, | |
1671 | .ops = &clk_branch_ops, | |
1672 | .flags = CLK_SET_RATE_PARENT, | |
1673 | }, | |
1674 | }, | |
1675 | }; | |
1676 | ||
1677 | static struct clk_rcg sdc4_src = { | |
1678 | .ns_reg = 0x288c, | |
1679 | .md_reg = 0x2888, | |
1680 | .mn = { | |
1681 | .mnctr_en_bit = 8, | |
1682 | .mnctr_reset_bit = 7, | |
1683 | .mnctr_mode_shift = 5, | |
1684 | .n_val_shift = 16, | |
1685 | .m_val_shift = 16, | |
1686 | .width = 8, | |
1687 | }, | |
1688 | .p = { | |
1689 | .pre_div_shift = 3, | |
1690 | .pre_div_width = 2, | |
1691 | }, | |
1692 | .s = { | |
1693 | .src_sel_shift = 0, | |
1694 | .parent_map = gcc_pxo_pll8_map, | |
1695 | }, | |
1696 | .freq_tbl = clk_tbl_sdc, | |
1697 | .clkr = { | |
1698 | .enable_reg = 0x288c, | |
1699 | .enable_mask = BIT(11), | |
1700 | .hw.init = &(struct clk_init_data){ | |
1701 | .name = "sdc4_src", | |
1702 | .parent_names = gcc_pxo_pll8, | |
1703 | .num_parents = 2, | |
1704 | .ops = &clk_rcg_ops, | |
0eeff27b SB |
1705 | }, |
1706 | } | |
1707 | }; | |
1708 | ||
1709 | static struct clk_branch sdc4_clk = { | |
1710 | .halt_reg = 0x2fc8, | |
1711 | .halt_bit = 3, | |
1712 | .clkr = { | |
1713 | .enable_reg = 0x288c, | |
1714 | .enable_mask = BIT(9), | |
1715 | .hw.init = &(struct clk_init_data){ | |
1716 | .name = "sdc4_clk", | |
1717 | .parent_names = (const char *[]){ "sdc4_src" }, | |
1718 | .num_parents = 1, | |
1719 | .ops = &clk_branch_ops, | |
1720 | .flags = CLK_SET_RATE_PARENT, | |
1721 | }, | |
1722 | }, | |
1723 | }; | |
1724 | ||
1725 | static struct clk_rcg sdc5_src = { | |
1726 | .ns_reg = 0x28ac, | |
1727 | .md_reg = 0x28a8, | |
1728 | .mn = { | |
1729 | .mnctr_en_bit = 8, | |
1730 | .mnctr_reset_bit = 7, | |
1731 | .mnctr_mode_shift = 5, | |
1732 | .n_val_shift = 16, | |
1733 | .m_val_shift = 16, | |
1734 | .width = 8, | |
1735 | }, | |
1736 | .p = { | |
1737 | .pre_div_shift = 3, | |
1738 | .pre_div_width = 2, | |
1739 | }, | |
1740 | .s = { | |
1741 | .src_sel_shift = 0, | |
1742 | .parent_map = gcc_pxo_pll8_map, | |
1743 | }, | |
1744 | .freq_tbl = clk_tbl_sdc, | |
1745 | .clkr = { | |
1746 | .enable_reg = 0x28ac, | |
1747 | .enable_mask = BIT(11), | |
1748 | .hw.init = &(struct clk_init_data){ | |
1749 | .name = "sdc5_src", | |
1750 | .parent_names = gcc_pxo_pll8, | |
1751 | .num_parents = 2, | |
1752 | .ops = &clk_rcg_ops, | |
0eeff27b SB |
1753 | }, |
1754 | } | |
1755 | }; | |
1756 | ||
1757 | static struct clk_branch sdc5_clk = { | |
1758 | .halt_reg = 0x2fc8, | |
1759 | .halt_bit = 2, | |
1760 | .clkr = { | |
1761 | .enable_reg = 0x28ac, | |
1762 | .enable_mask = BIT(9), | |
1763 | .hw.init = &(struct clk_init_data){ | |
1764 | .name = "sdc5_clk", | |
1765 | .parent_names = (const char *[]){ "sdc5_src" }, | |
1766 | .num_parents = 1, | |
1767 | .ops = &clk_branch_ops, | |
1768 | .flags = CLK_SET_RATE_PARENT, | |
1769 | }, | |
1770 | }, | |
1771 | }; | |
1772 | ||
1773 | static const struct freq_tbl clk_tbl_tsif_ref[] = { | |
1774 | { 105000, P_PXO, 1, 1, 256 }, | |
1775 | { } | |
1776 | }; | |
1777 | ||
1778 | static struct clk_rcg tsif_ref_src = { | |
1779 | .ns_reg = 0x2710, | |
1780 | .md_reg = 0x270c, | |
1781 | .mn = { | |
1782 | .mnctr_en_bit = 8, | |
1783 | .mnctr_reset_bit = 7, | |
1784 | .mnctr_mode_shift = 5, | |
1785 | .n_val_shift = 16, | |
1786 | .m_val_shift = 16, | |
1787 | .width = 16, | |
1788 | }, | |
1789 | .p = { | |
1790 | .pre_div_shift = 3, | |
1791 | .pre_div_width = 2, | |
1792 | }, | |
1793 | .s = { | |
1794 | .src_sel_shift = 0, | |
1795 | .parent_map = gcc_pxo_pll8_map, | |
1796 | }, | |
1797 | .freq_tbl = clk_tbl_tsif_ref, | |
1798 | .clkr = { | |
1799 | .enable_reg = 0x2710, | |
1800 | .enable_mask = BIT(11), | |
1801 | .hw.init = &(struct clk_init_data){ | |
1802 | .name = "tsif_ref_src", | |
1803 | .parent_names = gcc_pxo_pll8, | |
1804 | .num_parents = 2, | |
1805 | .ops = &clk_rcg_ops, | |
1806 | .flags = CLK_SET_RATE_GATE, | |
1807 | }, | |
1808 | } | |
1809 | }; | |
1810 | ||
1811 | static struct clk_branch tsif_ref_clk = { | |
1812 | .halt_reg = 0x2fd4, | |
1813 | .halt_bit = 5, | |
1814 | .clkr = { | |
1815 | .enable_reg = 0x2710, | |
1816 | .enable_mask = BIT(9), | |
1817 | .hw.init = &(struct clk_init_data){ | |
1818 | .name = "tsif_ref_clk", | |
1819 | .parent_names = (const char *[]){ "tsif_ref_src" }, | |
1820 | .num_parents = 1, | |
1821 | .ops = &clk_branch_ops, | |
1822 | .flags = CLK_SET_RATE_PARENT, | |
1823 | }, | |
1824 | }, | |
1825 | }; | |
1826 | ||
1827 | static const struct freq_tbl clk_tbl_usb[] = { | |
1828 | { 60000000, P_PLL8, 1, 5, 32 }, | |
1829 | { } | |
1830 | }; | |
1831 | ||
1832 | static struct clk_rcg usb_hs1_xcvr_src = { | |
1833 | .ns_reg = 0x290c, | |
1834 | .md_reg = 0x2908, | |
1835 | .mn = { | |
1836 | .mnctr_en_bit = 8, | |
1837 | .mnctr_reset_bit = 7, | |
1838 | .mnctr_mode_shift = 5, | |
1839 | .n_val_shift = 16, | |
1840 | .m_val_shift = 16, | |
1841 | .width = 8, | |
1842 | }, | |
1843 | .p = { | |
1844 | .pre_div_shift = 3, | |
1845 | .pre_div_width = 2, | |
1846 | }, | |
1847 | .s = { | |
1848 | .src_sel_shift = 0, | |
1849 | .parent_map = gcc_pxo_pll8_map, | |
1850 | }, | |
1851 | .freq_tbl = clk_tbl_usb, | |
1852 | .clkr = { | |
1853 | .enable_reg = 0x290c, | |
1854 | .enable_mask = BIT(11), | |
1855 | .hw.init = &(struct clk_init_data){ | |
1856 | .name = "usb_hs1_xcvr_src", | |
1857 | .parent_names = gcc_pxo_pll8, | |
1858 | .num_parents = 2, | |
1859 | .ops = &clk_rcg_ops, | |
1860 | .flags = CLK_SET_RATE_GATE, | |
1861 | }, | |
1862 | } | |
1863 | }; | |
1864 | ||
1865 | static struct clk_branch usb_hs1_xcvr_clk = { | |
1866 | .halt_reg = 0x2fc8, | |
1867 | .halt_bit = 0, | |
1868 | .clkr = { | |
1869 | .enable_reg = 0x290c, | |
1870 | .enable_mask = BIT(9), | |
1871 | .hw.init = &(struct clk_init_data){ | |
1872 | .name = "usb_hs1_xcvr_clk", | |
1873 | .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, | |
1874 | .num_parents = 1, | |
1875 | .ops = &clk_branch_ops, | |
1876 | .flags = CLK_SET_RATE_PARENT, | |
1877 | }, | |
1878 | }, | |
1879 | }; | |
1880 | ||
1881 | static struct clk_rcg usb_fs1_xcvr_fs_src = { | |
1882 | .ns_reg = 0x2968, | |
1883 | .md_reg = 0x2964, | |
1884 | .mn = { | |
1885 | .mnctr_en_bit = 8, | |
1886 | .mnctr_reset_bit = 7, | |
1887 | .mnctr_mode_shift = 5, | |
1888 | .n_val_shift = 16, | |
1889 | .m_val_shift = 16, | |
1890 | .width = 8, | |
1891 | }, | |
1892 | .p = { | |
1893 | .pre_div_shift = 3, | |
1894 | .pre_div_width = 2, | |
1895 | }, | |
1896 | .s = { | |
1897 | .src_sel_shift = 0, | |
1898 | .parent_map = gcc_pxo_pll8_map, | |
1899 | }, | |
1900 | .freq_tbl = clk_tbl_usb, | |
1901 | .clkr = { | |
1902 | .enable_reg = 0x2968, | |
1903 | .enable_mask = BIT(11), | |
1904 | .hw.init = &(struct clk_init_data){ | |
1905 | .name = "usb_fs1_xcvr_fs_src", | |
1906 | .parent_names = gcc_pxo_pll8, | |
1907 | .num_parents = 2, | |
1908 | .ops = &clk_rcg_ops, | |
1909 | .flags = CLK_SET_RATE_GATE, | |
1910 | }, | |
1911 | } | |
1912 | }; | |
1913 | ||
adb11a40 | 1914 | static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; |
0eeff27b SB |
1915 | |
1916 | static struct clk_branch usb_fs1_xcvr_fs_clk = { | |
1917 | .halt_reg = 0x2fcc, | |
1918 | .halt_bit = 15, | |
1919 | .clkr = { | |
1920 | .enable_reg = 0x2968, | |
1921 | .enable_mask = BIT(9), | |
1922 | .hw.init = &(struct clk_init_data){ | |
1923 | .name = "usb_fs1_xcvr_fs_clk", | |
1924 | .parent_names = usb_fs1_xcvr_fs_src_p, | |
1925 | .num_parents = 1, | |
1926 | .ops = &clk_branch_ops, | |
1927 | .flags = CLK_SET_RATE_PARENT, | |
1928 | }, | |
1929 | }, | |
1930 | }; | |
1931 | ||
1932 | static struct clk_branch usb_fs1_system_clk = { | |
1933 | .halt_reg = 0x2fcc, | |
1934 | .halt_bit = 16, | |
1935 | .clkr = { | |
1936 | .enable_reg = 0x296c, | |
1937 | .enable_mask = BIT(4), | |
1938 | .hw.init = &(struct clk_init_data){ | |
1939 | .parent_names = usb_fs1_xcvr_fs_src_p, | |
1940 | .num_parents = 1, | |
1941 | .name = "usb_fs1_system_clk", | |
1942 | .ops = &clk_branch_ops, | |
1943 | .flags = CLK_SET_RATE_PARENT, | |
1944 | }, | |
1945 | }, | |
1946 | }; | |
1947 | ||
1948 | static struct clk_rcg usb_fs2_xcvr_fs_src = { | |
1949 | .ns_reg = 0x2988, | |
1950 | .md_reg = 0x2984, | |
1951 | .mn = { | |
1952 | .mnctr_en_bit = 8, | |
1953 | .mnctr_reset_bit = 7, | |
1954 | .mnctr_mode_shift = 5, | |
1955 | .n_val_shift = 16, | |
1956 | .m_val_shift = 16, | |
1957 | .width = 8, | |
1958 | }, | |
1959 | .p = { | |
1960 | .pre_div_shift = 3, | |
1961 | .pre_div_width = 2, | |
1962 | }, | |
1963 | .s = { | |
1964 | .src_sel_shift = 0, | |
1965 | .parent_map = gcc_pxo_pll8_map, | |
1966 | }, | |
1967 | .freq_tbl = clk_tbl_usb, | |
1968 | .clkr = { | |
1969 | .enable_reg = 0x2988, | |
1970 | .enable_mask = BIT(11), | |
1971 | .hw.init = &(struct clk_init_data){ | |
1972 | .name = "usb_fs2_xcvr_fs_src", | |
1973 | .parent_names = gcc_pxo_pll8, | |
1974 | .num_parents = 2, | |
1975 | .ops = &clk_rcg_ops, | |
1976 | .flags = CLK_SET_RATE_GATE, | |
1977 | }, | |
1978 | } | |
1979 | }; | |
1980 | ||
adb11a40 | 1981 | static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; |
0eeff27b SB |
1982 | |
1983 | static struct clk_branch usb_fs2_xcvr_fs_clk = { | |
1984 | .halt_reg = 0x2fcc, | |
1985 | .halt_bit = 12, | |
1986 | .clkr = { | |
1987 | .enable_reg = 0x2988, | |
1988 | .enable_mask = BIT(9), | |
1989 | .hw.init = &(struct clk_init_data){ | |
1990 | .name = "usb_fs2_xcvr_fs_clk", | |
1991 | .parent_names = usb_fs2_xcvr_fs_src_p, | |
1992 | .num_parents = 1, | |
1993 | .ops = &clk_branch_ops, | |
1994 | .flags = CLK_SET_RATE_PARENT, | |
1995 | }, | |
1996 | }, | |
1997 | }; | |
1998 | ||
1999 | static struct clk_branch usb_fs2_system_clk = { | |
2000 | .halt_reg = 0x2fcc, | |
2001 | .halt_bit = 13, | |
2002 | .clkr = { | |
2003 | .enable_reg = 0x298c, | |
2004 | .enable_mask = BIT(4), | |
2005 | .hw.init = &(struct clk_init_data){ | |
2006 | .name = "usb_fs2_system_clk", | |
2007 | .parent_names = usb_fs2_xcvr_fs_src_p, | |
2008 | .num_parents = 1, | |
2009 | .ops = &clk_branch_ops, | |
2010 | .flags = CLK_SET_RATE_PARENT, | |
2011 | }, | |
2012 | }, | |
2013 | }; | |
2014 | ||
2015 | static struct clk_branch gsbi1_h_clk = { | |
2016 | .halt_reg = 0x2fcc, | |
2017 | .halt_bit = 11, | |
2018 | .clkr = { | |
2019 | .enable_reg = 0x29c0, | |
2020 | .enable_mask = BIT(4), | |
2021 | .hw.init = &(struct clk_init_data){ | |
2022 | .name = "gsbi1_h_clk", | |
2023 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2024 | }, |
2025 | }, | |
2026 | }; | |
2027 | ||
2028 | static struct clk_branch gsbi2_h_clk = { | |
2029 | .halt_reg = 0x2fcc, | |
2030 | .halt_bit = 7, | |
2031 | .clkr = { | |
2032 | .enable_reg = 0x29e0, | |
2033 | .enable_mask = BIT(4), | |
2034 | .hw.init = &(struct clk_init_data){ | |
2035 | .name = "gsbi2_h_clk", | |
2036 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2037 | }, |
2038 | }, | |
2039 | }; | |
2040 | ||
2041 | static struct clk_branch gsbi3_h_clk = { | |
2042 | .halt_reg = 0x2fcc, | |
2043 | .halt_bit = 3, | |
2044 | .clkr = { | |
2045 | .enable_reg = 0x2a00, | |
2046 | .enable_mask = BIT(4), | |
2047 | .hw.init = &(struct clk_init_data){ | |
2048 | .name = "gsbi3_h_clk", | |
2049 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2050 | }, |
2051 | }, | |
2052 | }; | |
2053 | ||
2054 | static struct clk_branch gsbi4_h_clk = { | |
2055 | .halt_reg = 0x2fd0, | |
2056 | .halt_bit = 27, | |
2057 | .clkr = { | |
2058 | .enable_reg = 0x2a20, | |
2059 | .enable_mask = BIT(4), | |
2060 | .hw.init = &(struct clk_init_data){ | |
2061 | .name = "gsbi4_h_clk", | |
2062 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2063 | }, |
2064 | }, | |
2065 | }; | |
2066 | ||
2067 | static struct clk_branch gsbi5_h_clk = { | |
2068 | .halt_reg = 0x2fd0, | |
2069 | .halt_bit = 23, | |
2070 | .clkr = { | |
2071 | .enable_reg = 0x2a40, | |
2072 | .enable_mask = BIT(4), | |
2073 | .hw.init = &(struct clk_init_data){ | |
2074 | .name = "gsbi5_h_clk", | |
2075 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2076 | }, |
2077 | }, | |
2078 | }; | |
2079 | ||
2080 | static struct clk_branch gsbi6_h_clk = { | |
2081 | .halt_reg = 0x2fd0, | |
2082 | .halt_bit = 19, | |
2083 | .clkr = { | |
2084 | .enable_reg = 0x2a60, | |
2085 | .enable_mask = BIT(4), | |
2086 | .hw.init = &(struct clk_init_data){ | |
2087 | .name = "gsbi6_h_clk", | |
2088 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2089 | }, |
2090 | }, | |
2091 | }; | |
2092 | ||
2093 | static struct clk_branch gsbi7_h_clk = { | |
2094 | .halt_reg = 0x2fd0, | |
2095 | .halt_bit = 15, | |
2096 | .clkr = { | |
2097 | .enable_reg = 0x2a80, | |
2098 | .enable_mask = BIT(4), | |
2099 | .hw.init = &(struct clk_init_data){ | |
2100 | .name = "gsbi7_h_clk", | |
2101 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2102 | }, |
2103 | }, | |
2104 | }; | |
2105 | ||
2106 | static struct clk_branch gsbi8_h_clk = { | |
2107 | .halt_reg = 0x2fd0, | |
2108 | .halt_bit = 11, | |
2109 | .clkr = { | |
2110 | .enable_reg = 0x2aa0, | |
2111 | .enable_mask = BIT(4), | |
2112 | .hw.init = &(struct clk_init_data){ | |
2113 | .name = "gsbi8_h_clk", | |
2114 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2115 | }, |
2116 | }, | |
2117 | }; | |
2118 | ||
2119 | static struct clk_branch gsbi9_h_clk = { | |
2120 | .halt_reg = 0x2fd0, | |
2121 | .halt_bit = 7, | |
2122 | .clkr = { | |
2123 | .enable_reg = 0x2ac0, | |
2124 | .enable_mask = BIT(4), | |
2125 | .hw.init = &(struct clk_init_data){ | |
2126 | .name = "gsbi9_h_clk", | |
2127 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2128 | }, |
2129 | }, | |
2130 | }; | |
2131 | ||
2132 | static struct clk_branch gsbi10_h_clk = { | |
2133 | .halt_reg = 0x2fd0, | |
2134 | .halt_bit = 3, | |
2135 | .clkr = { | |
2136 | .enable_reg = 0x2ae0, | |
2137 | .enable_mask = BIT(4), | |
2138 | .hw.init = &(struct clk_init_data){ | |
2139 | .name = "gsbi10_h_clk", | |
2140 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2141 | }, |
2142 | }, | |
2143 | }; | |
2144 | ||
2145 | static struct clk_branch gsbi11_h_clk = { | |
2146 | .halt_reg = 0x2fd4, | |
2147 | .halt_bit = 18, | |
2148 | .clkr = { | |
2149 | .enable_reg = 0x2b00, | |
2150 | .enable_mask = BIT(4), | |
2151 | .hw.init = &(struct clk_init_data){ | |
2152 | .name = "gsbi11_h_clk", | |
2153 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2154 | }, |
2155 | }, | |
2156 | }; | |
2157 | ||
2158 | static struct clk_branch gsbi12_h_clk = { | |
2159 | .halt_reg = 0x2fd4, | |
2160 | .halt_bit = 14, | |
2161 | .clkr = { | |
2162 | .enable_reg = 0x2b20, | |
2163 | .enable_mask = BIT(4), | |
2164 | .hw.init = &(struct clk_init_data){ | |
2165 | .name = "gsbi12_h_clk", | |
2166 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2167 | }, |
2168 | }, | |
2169 | }; | |
2170 | ||
2171 | static struct clk_branch tsif_h_clk = { | |
2172 | .halt_reg = 0x2fd4, | |
2173 | .halt_bit = 7, | |
2174 | .clkr = { | |
2175 | .enable_reg = 0x2700, | |
2176 | .enable_mask = BIT(4), | |
2177 | .hw.init = &(struct clk_init_data){ | |
2178 | .name = "tsif_h_clk", | |
2179 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2180 | }, |
2181 | }, | |
2182 | }; | |
2183 | ||
2184 | static struct clk_branch usb_fs1_h_clk = { | |
2185 | .halt_reg = 0x2fcc, | |
2186 | .halt_bit = 17, | |
2187 | .clkr = { | |
2188 | .enable_reg = 0x2960, | |
2189 | .enable_mask = BIT(4), | |
2190 | .hw.init = &(struct clk_init_data){ | |
2191 | .name = "usb_fs1_h_clk", | |
2192 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2193 | }, |
2194 | }, | |
2195 | }; | |
2196 | ||
2197 | static struct clk_branch usb_fs2_h_clk = { | |
2198 | .halt_reg = 0x2fcc, | |
2199 | .halt_bit = 14, | |
2200 | .clkr = { | |
2201 | .enable_reg = 0x2980, | |
2202 | .enable_mask = BIT(4), | |
2203 | .hw.init = &(struct clk_init_data){ | |
2204 | .name = "usb_fs2_h_clk", | |
2205 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2206 | }, |
2207 | }, | |
2208 | }; | |
2209 | ||
2210 | static struct clk_branch usb_hs1_h_clk = { | |
2211 | .halt_reg = 0x2fc8, | |
2212 | .halt_bit = 1, | |
2213 | .clkr = { | |
2214 | .enable_reg = 0x2900, | |
2215 | .enable_mask = BIT(4), | |
2216 | .hw.init = &(struct clk_init_data){ | |
2217 | .name = "usb_hs1_h_clk", | |
2218 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2219 | }, |
2220 | }, | |
2221 | }; | |
2222 | ||
2223 | static struct clk_branch sdc1_h_clk = { | |
2224 | .halt_reg = 0x2fc8, | |
2225 | .halt_bit = 11, | |
2226 | .clkr = { | |
2227 | .enable_reg = 0x2820, | |
2228 | .enable_mask = BIT(4), | |
2229 | .hw.init = &(struct clk_init_data){ | |
2230 | .name = "sdc1_h_clk", | |
2231 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2232 | }, |
2233 | }, | |
2234 | }; | |
2235 | ||
2236 | static struct clk_branch sdc2_h_clk = { | |
2237 | .halt_reg = 0x2fc8, | |
2238 | .halt_bit = 10, | |
2239 | .clkr = { | |
2240 | .enable_reg = 0x2840, | |
2241 | .enable_mask = BIT(4), | |
2242 | .hw.init = &(struct clk_init_data){ | |
2243 | .name = "sdc2_h_clk", | |
2244 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2245 | }, |
2246 | }, | |
2247 | }; | |
2248 | ||
2249 | static struct clk_branch sdc3_h_clk = { | |
2250 | .halt_reg = 0x2fc8, | |
2251 | .halt_bit = 9, | |
2252 | .clkr = { | |
2253 | .enable_reg = 0x2860, | |
2254 | .enable_mask = BIT(4), | |
2255 | .hw.init = &(struct clk_init_data){ | |
2256 | .name = "sdc3_h_clk", | |
2257 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2258 | }, |
2259 | }, | |
2260 | }; | |
2261 | ||
2262 | static struct clk_branch sdc4_h_clk = { | |
2263 | .halt_reg = 0x2fc8, | |
2264 | .halt_bit = 8, | |
2265 | .clkr = { | |
2266 | .enable_reg = 0x2880, | |
2267 | .enable_mask = BIT(4), | |
2268 | .hw.init = &(struct clk_init_data){ | |
2269 | .name = "sdc4_h_clk", | |
2270 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2271 | }, |
2272 | }, | |
2273 | }; | |
2274 | ||
2275 | static struct clk_branch sdc5_h_clk = { | |
2276 | .halt_reg = 0x2fc8, | |
2277 | .halt_bit = 7, | |
2278 | .clkr = { | |
2279 | .enable_reg = 0x28a0, | |
2280 | .enable_mask = BIT(4), | |
2281 | .hw.init = &(struct clk_init_data){ | |
2282 | .name = "sdc5_h_clk", | |
2283 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2284 | }, |
2285 | }, | |
2286 | }; | |
2287 | ||
cdbf85c1 LW |
2288 | static struct clk_branch ebi2_2x_clk = { |
2289 | .halt_reg = 0x2fcc, | |
2290 | .halt_bit = 18, | |
2291 | .clkr = { | |
2292 | .enable_reg = 0x2660, | |
2293 | .enable_mask = BIT(4), | |
2294 | .hw.init = &(struct clk_init_data){ | |
2295 | .name = "ebi2_2x_clk", | |
2296 | .ops = &clk_branch_ops, | |
2297 | }, | |
2298 | }, | |
2299 | }; | |
2300 | ||
2301 | static struct clk_branch ebi2_clk = { | |
2302 | .halt_reg = 0x2fcc, | |
2303 | .halt_bit = 19, | |
2304 | .clkr = { | |
2305 | .enable_reg = 0x2664, | |
2306 | .enable_mask = BIT(4), | |
2307 | .hw.init = &(struct clk_init_data){ | |
2308 | .name = "ebi2_clk", | |
2309 | .ops = &clk_branch_ops, | |
2310 | }, | |
2311 | }, | |
2312 | }; | |
2313 | ||
0eeff27b SB |
2314 | static struct clk_branch adm0_clk = { |
2315 | .halt_reg = 0x2fdc, | |
2316 | .halt_check = BRANCH_HALT_VOTED, | |
2317 | .halt_bit = 14, | |
2318 | .clkr = { | |
2319 | .enable_reg = 0x3080, | |
2320 | .enable_mask = BIT(2), | |
2321 | .hw.init = &(struct clk_init_data){ | |
2322 | .name = "adm0_clk", | |
2323 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2324 | }, |
2325 | }, | |
2326 | }; | |
2327 | ||
2328 | static struct clk_branch adm0_pbus_clk = { | |
2329 | .halt_reg = 0x2fdc, | |
2330 | .halt_check = BRANCH_HALT_VOTED, | |
2331 | .halt_bit = 13, | |
2332 | .clkr = { | |
2333 | .enable_reg = 0x3080, | |
2334 | .enable_mask = BIT(3), | |
2335 | .hw.init = &(struct clk_init_data){ | |
2336 | .name = "adm0_pbus_clk", | |
2337 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2338 | }, |
2339 | }, | |
2340 | }; | |
2341 | ||
2342 | static struct clk_branch adm1_clk = { | |
2343 | .halt_reg = 0x2fdc, | |
2344 | .halt_bit = 12, | |
2345 | .halt_check = BRANCH_HALT_VOTED, | |
2346 | .clkr = { | |
2347 | .enable_reg = 0x3080, | |
2348 | .enable_mask = BIT(4), | |
2349 | .hw.init = &(struct clk_init_data){ | |
2350 | .name = "adm1_clk", | |
2351 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2352 | }, |
2353 | }, | |
2354 | }; | |
2355 | ||
2356 | static struct clk_branch adm1_pbus_clk = { | |
2357 | .halt_reg = 0x2fdc, | |
2358 | .halt_bit = 11, | |
2359 | .halt_check = BRANCH_HALT_VOTED, | |
2360 | .clkr = { | |
2361 | .enable_reg = 0x3080, | |
2362 | .enable_mask = BIT(5), | |
2363 | .hw.init = &(struct clk_init_data){ | |
2364 | .name = "adm1_pbus_clk", | |
2365 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2366 | }, |
2367 | }, | |
2368 | }; | |
2369 | ||
2370 | static struct clk_branch modem_ahb1_h_clk = { | |
2371 | .halt_reg = 0x2fdc, | |
2372 | .halt_bit = 8, | |
2373 | .halt_check = BRANCH_HALT_VOTED, | |
2374 | .clkr = { | |
2375 | .enable_reg = 0x3080, | |
2376 | .enable_mask = BIT(0), | |
2377 | .hw.init = &(struct clk_init_data){ | |
2378 | .name = "modem_ahb1_h_clk", | |
2379 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2380 | }, |
2381 | }, | |
2382 | }; | |
2383 | ||
2384 | static struct clk_branch modem_ahb2_h_clk = { | |
2385 | .halt_reg = 0x2fdc, | |
2386 | .halt_bit = 7, | |
2387 | .halt_check = BRANCH_HALT_VOTED, | |
2388 | .clkr = { | |
2389 | .enable_reg = 0x3080, | |
2390 | .enable_mask = BIT(1), | |
2391 | .hw.init = &(struct clk_init_data){ | |
2392 | .name = "modem_ahb2_h_clk", | |
2393 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2394 | }, |
2395 | }, | |
2396 | }; | |
2397 | ||
2398 | static struct clk_branch pmic_arb0_h_clk = { | |
2399 | .halt_reg = 0x2fd8, | |
2400 | .halt_check = BRANCH_HALT_VOTED, | |
2401 | .halt_bit = 22, | |
2402 | .clkr = { | |
2403 | .enable_reg = 0x3080, | |
2404 | .enable_mask = BIT(8), | |
2405 | .hw.init = &(struct clk_init_data){ | |
2406 | .name = "pmic_arb0_h_clk", | |
2407 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2408 | }, |
2409 | }, | |
2410 | }; | |
2411 | ||
2412 | static struct clk_branch pmic_arb1_h_clk = { | |
2413 | .halt_reg = 0x2fd8, | |
2414 | .halt_check = BRANCH_HALT_VOTED, | |
2415 | .halt_bit = 21, | |
2416 | .clkr = { | |
2417 | .enable_reg = 0x3080, | |
2418 | .enable_mask = BIT(9), | |
2419 | .hw.init = &(struct clk_init_data){ | |
2420 | .name = "pmic_arb1_h_clk", | |
2421 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2422 | }, |
2423 | }, | |
2424 | }; | |
2425 | ||
2426 | static struct clk_branch pmic_ssbi2_clk = { | |
2427 | .halt_reg = 0x2fd8, | |
2428 | .halt_check = BRANCH_HALT_VOTED, | |
2429 | .halt_bit = 23, | |
2430 | .clkr = { | |
2431 | .enable_reg = 0x3080, | |
2432 | .enable_mask = BIT(7), | |
2433 | .hw.init = &(struct clk_init_data){ | |
2434 | .name = "pmic_ssbi2_clk", | |
2435 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2436 | }, |
2437 | }, | |
2438 | }; | |
2439 | ||
2440 | static struct clk_branch rpm_msg_ram_h_clk = { | |
2441 | .hwcg_reg = 0x27e0, | |
2442 | .hwcg_bit = 6, | |
2443 | .halt_reg = 0x2fd8, | |
2444 | .halt_check = BRANCH_HALT_VOTED, | |
2445 | .halt_bit = 12, | |
2446 | .clkr = { | |
2447 | .enable_reg = 0x3080, | |
2448 | .enable_mask = BIT(6), | |
2449 | .hw.init = &(struct clk_init_data){ | |
2450 | .name = "rpm_msg_ram_h_clk", | |
2451 | .ops = &clk_branch_ops, | |
0eeff27b SB |
2452 | }, |
2453 | }, | |
2454 | }; | |
2455 | ||
2456 | static struct clk_regmap *gcc_msm8660_clks[] = { | |
2457 | [PLL8] = &pll8.clkr, | |
2458 | [PLL8_VOTE] = &pll8_vote, | |
2459 | [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, | |
2460 | [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, | |
2461 | [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, | |
2462 | [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, | |
2463 | [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, | |
2464 | [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, | |
2465 | [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, | |
2466 | [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, | |
2467 | [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, | |
2468 | [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, | |
2469 | [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, | |
2470 | [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, | |
2471 | [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, | |
2472 | [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, | |
2473 | [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, | |
2474 | [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, | |
2475 | [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, | |
2476 | [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, | |
2477 | [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, | |
2478 | [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, | |
2479 | [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, | |
2480 | [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, | |
2481 | [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, | |
2482 | [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, | |
2483 | [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, | |
2484 | [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, | |
2485 | [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, | |
2486 | [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, | |
2487 | [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, | |
2488 | [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, | |
2489 | [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, | |
2490 | [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, | |
2491 | [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, | |
2492 | [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, | |
2493 | [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, | |
2494 | [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, | |
2495 | [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, | |
2496 | [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, | |
2497 | [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, | |
2498 | [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, | |
2499 | [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, | |
2500 | [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, | |
2501 | [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, | |
2502 | [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, | |
2503 | [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, | |
2504 | [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, | |
2505 | [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, | |
2506 | [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, | |
2507 | [GP0_SRC] = &gp0_src.clkr, | |
2508 | [GP0_CLK] = &gp0_clk.clkr, | |
2509 | [GP1_SRC] = &gp1_src.clkr, | |
2510 | [GP1_CLK] = &gp1_clk.clkr, | |
2511 | [GP2_SRC] = &gp2_src.clkr, | |
2512 | [GP2_CLK] = &gp2_clk.clkr, | |
2513 | [PMEM_CLK] = &pmem_clk.clkr, | |
2514 | [PRNG_SRC] = &prng_src.clkr, | |
2515 | [PRNG_CLK] = &prng_clk.clkr, | |
2516 | [SDC1_SRC] = &sdc1_src.clkr, | |
2517 | [SDC1_CLK] = &sdc1_clk.clkr, | |
2518 | [SDC2_SRC] = &sdc2_src.clkr, | |
2519 | [SDC2_CLK] = &sdc2_clk.clkr, | |
2520 | [SDC3_SRC] = &sdc3_src.clkr, | |
2521 | [SDC3_CLK] = &sdc3_clk.clkr, | |
2522 | [SDC4_SRC] = &sdc4_src.clkr, | |
2523 | [SDC4_CLK] = &sdc4_clk.clkr, | |
2524 | [SDC5_SRC] = &sdc5_src.clkr, | |
2525 | [SDC5_CLK] = &sdc5_clk.clkr, | |
2526 | [TSIF_REF_SRC] = &tsif_ref_src.clkr, | |
2527 | [TSIF_REF_CLK] = &tsif_ref_clk.clkr, | |
2528 | [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, | |
2529 | [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, | |
2530 | [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, | |
2531 | [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, | |
2532 | [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, | |
2533 | [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, | |
2534 | [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, | |
2535 | [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, | |
2536 | [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, | |
2537 | [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, | |
2538 | [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, | |
2539 | [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, | |
2540 | [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, | |
2541 | [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, | |
2542 | [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, | |
2543 | [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, | |
2544 | [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, | |
2545 | [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, | |
2546 | [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, | |
2547 | [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, | |
2548 | [TSIF_H_CLK] = &tsif_h_clk.clkr, | |
2549 | [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, | |
2550 | [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, | |
2551 | [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, | |
2552 | [SDC1_H_CLK] = &sdc1_h_clk.clkr, | |
2553 | [SDC2_H_CLK] = &sdc2_h_clk.clkr, | |
2554 | [SDC3_H_CLK] = &sdc3_h_clk.clkr, | |
2555 | [SDC4_H_CLK] = &sdc4_h_clk.clkr, | |
2556 | [SDC5_H_CLK] = &sdc5_h_clk.clkr, | |
cdbf85c1 LW |
2557 | [EBI2_2X_CLK] = &ebi2_2x_clk.clkr, |
2558 | [EBI2_CLK] = &ebi2_clk.clkr, | |
0eeff27b SB |
2559 | [ADM0_CLK] = &adm0_clk.clkr, |
2560 | [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, | |
2561 | [ADM1_CLK] = &adm1_clk.clkr, | |
2562 | [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr, | |
2563 | [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr, | |
2564 | [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr, | |
2565 | [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, | |
2566 | [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, | |
2567 | [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, | |
2568 | [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, | |
2569 | }; | |
2570 | ||
2571 | static const struct qcom_reset_map gcc_msm8660_resets[] = { | |
2572 | [AFAB_CORE_RESET] = { 0x2080, 7 }, | |
2573 | [SCSS_SYS_RESET] = { 0x20b4, 1 }, | |
2574 | [SCSS_SYS_POR_RESET] = { 0x20b4 }, | |
2575 | [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, | |
2576 | [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, | |
2577 | [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, | |
2578 | [AFAB_EBI1_S_RESET] = { 0x20c0, 7 }, | |
2579 | [SFAB_CORE_RESET] = { 0x2120, 7 }, | |
2580 | [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, | |
2581 | [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, | |
2582 | [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 }, | |
2583 | [ADM0_C2_RESET] = { 0x220c, 4 }, | |
2584 | [ADM0_C1_RESET] = { 0x220c, 3 }, | |
2585 | [ADM0_C0_RESET] = { 0x220c, 2 }, | |
2586 | [ADM0_PBUS_RESET] = { 0x220c, 1 }, | |
2587 | [ADM0_RESET] = { 0x220c }, | |
2588 | [SFAB_ADM1_M0_RESET] = { 0x2220, 7 }, | |
2589 | [SFAB_ADM1_M1_RESET] = { 0x2224, 7 }, | |
2590 | [SFAB_ADM1_M2_RESET] = { 0x2228, 7 }, | |
2591 | [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 }, | |
2592 | [ADM1_C3_RESET] = { 0x226c, 5 }, | |
2593 | [ADM1_C2_RESET] = { 0x226c, 4 }, | |
2594 | [ADM1_C1_RESET] = { 0x226c, 3 }, | |
2595 | [ADM1_C0_RESET] = { 0x226c, 2 }, | |
2596 | [ADM1_PBUS_RESET] = { 0x226c, 1 }, | |
2597 | [ADM1_RESET] = { 0x226c }, | |
2598 | [IMEM0_RESET] = { 0x2280, 7 }, | |
2599 | [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 }, | |
2600 | [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, | |
2601 | [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, | |
2602 | [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, | |
2603 | [DFAB_CORE_RESET] = { 0x24ac, 7 }, | |
2604 | [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, | |
2605 | [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, | |
2606 | [DFAB_SWAY0_RESET] = { 0x2540, 7 }, | |
2607 | [DFAB_SWAY1_RESET] = { 0x2544, 7 }, | |
2608 | [DFAB_ARB0_RESET] = { 0x2560, 7 }, | |
2609 | [DFAB_ARB1_RESET] = { 0x2564, 7 }, | |
2610 | [PPSS_PROC_RESET] = { 0x2594, 1 }, | |
2611 | [PPSS_RESET] = { 0x2594 }, | |
2612 | [PMEM_RESET] = { 0x25a0, 7 }, | |
2613 | [DMA_BAM_RESET] = { 0x25c0, 7 }, | |
2614 | [SIC_RESET] = { 0x25e0, 7 }, | |
2615 | [SPS_TIC_RESET] = { 0x2600, 7 }, | |
2616 | [CFBP0_RESET] = { 0x2650, 7 }, | |
2617 | [CFBP1_RESET] = { 0x2654, 7 }, | |
2618 | [CFBP2_RESET] = { 0x2658, 7 }, | |
2619 | [EBI2_RESET] = { 0x2664, 7 }, | |
2620 | [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, | |
2621 | [CFPB_MASTER_RESET] = { 0x26a0, 7 }, | |
2622 | [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, | |
2623 | [CFPB_SPLITTER_RESET] = { 0x26e0, 7 }, | |
2624 | [TSIF_RESET] = { 0x2700, 7 }, | |
2625 | [CE1_RESET] = { 0x2720, 7 }, | |
2626 | [CE2_RESET] = { 0x2740, 7 }, | |
2627 | [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, | |
2628 | [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, | |
2629 | [RPM_PROC_RESET] = { 0x27c0, 7 }, | |
2630 | [RPM_BUS_RESET] = { 0x27c4, 7 }, | |
2631 | [RPM_MSG_RAM_RESET] = { 0x27e0, 7 }, | |
2632 | [PMIC_ARB0_RESET] = { 0x2800, 7 }, | |
2633 | [PMIC_ARB1_RESET] = { 0x2804, 7 }, | |
2634 | [PMIC_SSBI2_RESET] = { 0x280c, 12 }, | |
2635 | [SDC1_RESET] = { 0x2830 }, | |
2636 | [SDC2_RESET] = { 0x2850 }, | |
2637 | [SDC3_RESET] = { 0x2870 }, | |
2638 | [SDC4_RESET] = { 0x2890 }, | |
2639 | [SDC5_RESET] = { 0x28b0 }, | |
2640 | [USB_HS1_RESET] = { 0x2910 }, | |
2641 | [USB_HS2_XCVR_RESET] = { 0x2934, 1 }, | |
2642 | [USB_HS2_RESET] = { 0x2934 }, | |
2643 | [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, | |
2644 | [USB_FS1_RESET] = { 0x2974 }, | |
2645 | [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, | |
2646 | [USB_FS2_RESET] = { 0x2994 }, | |
2647 | [GSBI1_RESET] = { 0x29dc }, | |
2648 | [GSBI2_RESET] = { 0x29fc }, | |
2649 | [GSBI3_RESET] = { 0x2a1c }, | |
2650 | [GSBI4_RESET] = { 0x2a3c }, | |
2651 | [GSBI5_RESET] = { 0x2a5c }, | |
2652 | [GSBI6_RESET] = { 0x2a7c }, | |
2653 | [GSBI7_RESET] = { 0x2a9c }, | |
2654 | [GSBI8_RESET] = { 0x2abc }, | |
2655 | [GSBI9_RESET] = { 0x2adc }, | |
2656 | [GSBI10_RESET] = { 0x2afc }, | |
2657 | [GSBI11_RESET] = { 0x2b1c }, | |
2658 | [GSBI12_RESET] = { 0x2b3c }, | |
2659 | [SPDM_RESET] = { 0x2b6c }, | |
2660 | [SEC_CTRL_RESET] = { 0x2b80, 7 }, | |
2661 | [TLMM_H_RESET] = { 0x2ba0, 7 }, | |
2662 | [TLMM_RESET] = { 0x2ba4, 7 }, | |
2663 | [MARRM_PWRON_RESET] = { 0x2bd4, 1 }, | |
2664 | [MARM_RESET] = { 0x2bd4 }, | |
2665 | [MAHB1_RESET] = { 0x2be4, 7 }, | |
2666 | [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, | |
2667 | [MAHB2_RESET] = { 0x2c20, 7 }, | |
2668 | [MODEM_SW_AHB_RESET] = { 0x2c48, 1 }, | |
2669 | [MODEM_RESET] = { 0x2c48 }, | |
2670 | [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 }, | |
2671 | [SFAB_MSS_MDM0_RESET] = { 0x2c4c }, | |
2672 | [MSS_SLP_RESET] = { 0x2c60, 7 }, | |
2673 | [MSS_MARM_SAW_RESET] = { 0x2c68, 1 }, | |
2674 | [MSS_WDOG_RESET] = { 0x2c68 }, | |
2675 | [TSSC_RESET] = { 0x2ca0, 7 }, | |
2676 | [PDM_RESET] = { 0x2cc0, 12 }, | |
2677 | [SCSS_CORE0_RESET] = { 0x2d60, 1 }, | |
2678 | [SCSS_CORE0_POR_RESET] = { 0x2d60 }, | |
2679 | [SCSS_CORE1_RESET] = { 0x2d80, 1 }, | |
2680 | [SCSS_CORE1_POR_RESET] = { 0x2d80 }, | |
2681 | [MPM_RESET] = { 0x2da4, 1 }, | |
2682 | [EBI1_1X_DIV_RESET] = { 0x2dec, 9 }, | |
2683 | [EBI1_RESET] = { 0x2dec, 7 }, | |
2684 | [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, | |
2685 | [USB_PHY0_RESET] = { 0x2e20 }, | |
2686 | [USB_PHY1_RESET] = { 0x2e40 }, | |
2687 | [PRNG_RESET] = { 0x2e80, 12 }, | |
2688 | }; | |
2689 | ||
2690 | static const struct regmap_config gcc_msm8660_regmap_config = { | |
2691 | .reg_bits = 32, | |
2692 | .reg_stride = 4, | |
2693 | .val_bits = 32, | |
2694 | .max_register = 0x363c, | |
2695 | .fast_io = true, | |
2696 | }; | |
2697 | ||
49fc825f SB |
2698 | static const struct qcom_cc_desc gcc_msm8660_desc = { |
2699 | .config = &gcc_msm8660_regmap_config, | |
2700 | .clks = gcc_msm8660_clks, | |
2701 | .num_clks = ARRAY_SIZE(gcc_msm8660_clks), | |
2702 | .resets = gcc_msm8660_resets, | |
2703 | .num_resets = ARRAY_SIZE(gcc_msm8660_resets), | |
2704 | }; | |
2705 | ||
0eeff27b SB |
2706 | static const struct of_device_id gcc_msm8660_match_table[] = { |
2707 | { .compatible = "qcom,gcc-msm8660" }, | |
2708 | { } | |
2709 | }; | |
2710 | MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); | |
2711 | ||
0eeff27b SB |
2712 | static int gcc_msm8660_probe(struct platform_device *pdev) |
2713 | { | |
a085f877 | 2714 | int ret; |
d15998e0 SB |
2715 | struct device *dev = &pdev->dev; |
2716 | ||
a085f877 SB |
2717 | ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000); |
2718 | if (ret) | |
2719 | return ret; | |
d15998e0 | 2720 | |
a085f877 SB |
2721 | ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000); |
2722 | if (ret) | |
2723 | return ret; | |
d15998e0 | 2724 | |
49fc825f | 2725 | return qcom_cc_probe(pdev, &gcc_msm8660_desc); |
0eeff27b SB |
2726 | } |
2727 | ||
0eeff27b SB |
2728 | static struct platform_driver gcc_msm8660_driver = { |
2729 | .probe = gcc_msm8660_probe, | |
0eeff27b SB |
2730 | .driver = { |
2731 | .name = "gcc-msm8660", | |
0eeff27b SB |
2732 | .of_match_table = gcc_msm8660_match_table, |
2733 | }, | |
2734 | }; | |
2735 | ||
2736 | static int __init gcc_msm8660_init(void) | |
2737 | { | |
2738 | return platform_driver_register(&gcc_msm8660_driver); | |
2739 | } | |
2740 | core_initcall(gcc_msm8660_init); | |
2741 | ||
2742 | static void __exit gcc_msm8660_exit(void) | |
2743 | { | |
2744 | platform_driver_unregister(&gcc_msm8660_driver); | |
2745 | } | |
2746 | module_exit(gcc_msm8660_exit); | |
2747 | ||
2748 | MODULE_DESCRIPTION("GCC MSM 8660 Driver"); | |
2749 | MODULE_LICENSE("GPL v2"); | |
2750 | MODULE_ALIAS("platform:gcc-msm8660"); |