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90114ca1 NA |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2023, Linaro Ltd. | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_device.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/regmap.h> | |
15 | #include <linux/pm_runtime.h> | |
16 | ||
17 | #include <dt-bindings/clock/qcom,sm8550-dispcc.h> | |
18 | ||
19 | #include "common.h" | |
20 | #include "clk-alpha-pll.h" | |
21 | #include "clk-branch.h" | |
22 | #include "clk-pll.h" | |
23 | #include "clk-rcg.h" | |
24 | #include "clk-regmap.h" | |
25 | #include "clk-regmap-divider.h" | |
26 | #include "clk-regmap-mux.h" | |
27 | #include "reset.h" | |
28 | #include "gdsc.h" | |
29 | ||
30 | /* Need to match the order of clocks in DT binding */ | |
31 | enum { | |
32 | DT_BI_TCXO, | |
33 | DT_BI_TCXO_AO, | |
34 | DT_AHB_CLK, | |
35 | DT_SLEEP_CLK, | |
36 | ||
37 | DT_DSI0_PHY_PLL_OUT_BYTECLK, | |
38 | DT_DSI0_PHY_PLL_OUT_DSICLK, | |
39 | DT_DSI1_PHY_PLL_OUT_BYTECLK, | |
40 | DT_DSI1_PHY_PLL_OUT_DSICLK, | |
41 | ||
42 | DT_DP0_PHY_PLL_LINK_CLK, | |
43 | DT_DP0_PHY_PLL_VCO_DIV_CLK, | |
44 | DT_DP1_PHY_PLL_LINK_CLK, | |
45 | DT_DP1_PHY_PLL_VCO_DIV_CLK, | |
46 | DT_DP2_PHY_PLL_LINK_CLK, | |
47 | DT_DP2_PHY_PLL_VCO_DIV_CLK, | |
48 | DT_DP3_PHY_PLL_LINK_CLK, | |
49 | DT_DP3_PHY_PLL_VCO_DIV_CLK, | |
50 | }; | |
51 | ||
52 | #define DISP_CC_MISC_CMD 0xF000 | |
53 | ||
54 | enum { | |
55 | P_BI_TCXO, | |
56 | P_DISP_CC_PLL0_OUT_MAIN, | |
57 | P_DISP_CC_PLL1_OUT_EVEN, | |
58 | P_DISP_CC_PLL1_OUT_MAIN, | |
59 | P_DP0_PHY_PLL_LINK_CLK, | |
60 | P_DP0_PHY_PLL_VCO_DIV_CLK, | |
61 | P_DP1_PHY_PLL_LINK_CLK, | |
62 | P_DP1_PHY_PLL_VCO_DIV_CLK, | |
63 | P_DP2_PHY_PLL_LINK_CLK, | |
64 | P_DP2_PHY_PLL_VCO_DIV_CLK, | |
65 | P_DP3_PHY_PLL_LINK_CLK, | |
66 | P_DP3_PHY_PLL_VCO_DIV_CLK, | |
67 | P_DSI0_PHY_PLL_OUT_BYTECLK, | |
68 | P_DSI0_PHY_PLL_OUT_DSICLK, | |
69 | P_DSI1_PHY_PLL_OUT_BYTECLK, | |
70 | P_DSI1_PHY_PLL_OUT_DSICLK, | |
71 | P_SLEEP_CLK, | |
72 | }; | |
73 | ||
74 | static struct pll_vco lucid_ole_vco[] = { | |
75 | { 249600000, 2000000000, 0 }, | |
76 | }; | |
77 | ||
78 | static const struct alpha_pll_config disp_cc_pll0_config = { | |
79 | .l = 0xd, | |
80 | .alpha = 0x6492, | |
81 | .config_ctl_val = 0x20485699, | |
82 | .config_ctl_hi_val = 0x00182261, | |
83 | .config_ctl_hi1_val = 0x82aa299c, | |
84 | .user_ctl_val = 0x00000000, | |
85 | .user_ctl_hi_val = 0x00000005, | |
86 | }; | |
87 | ||
88 | static struct clk_alpha_pll disp_cc_pll0 = { | |
89 | .offset = 0x0, | |
90 | .vco_table = lucid_ole_vco, | |
91 | .num_vco = ARRAY_SIZE(lucid_ole_vco), | |
92 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], | |
93 | .clkr = { | |
94 | .hw.init = &(struct clk_init_data) { | |
95 | .name = "disp_cc_pll0", | |
96 | .parent_data = &(const struct clk_parent_data) { | |
97 | .index = DT_BI_TCXO, | |
98 | }, | |
99 | .num_parents = 1, | |
100 | .ops = &clk_alpha_pll_reset_lucid_ole_ops, | |
101 | }, | |
102 | }, | |
103 | }; | |
104 | ||
105 | static const struct alpha_pll_config disp_cc_pll1_config = { | |
106 | .l = 0x1f, | |
107 | .alpha = 0x4000, | |
108 | .config_ctl_val = 0x20485699, | |
109 | .config_ctl_hi_val = 0x00182261, | |
110 | .config_ctl_hi1_val = 0x82aa299c, | |
111 | .user_ctl_val = 0x00000000, | |
112 | .user_ctl_hi_val = 0x00000005, | |
113 | }; | |
114 | ||
115 | static struct clk_alpha_pll disp_cc_pll1 = { | |
116 | .offset = 0x1000, | |
117 | .vco_table = lucid_ole_vco, | |
118 | .num_vco = ARRAY_SIZE(lucid_ole_vco), | |
119 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], | |
120 | .clkr = { | |
121 | .hw.init = &(struct clk_init_data) { | |
122 | .name = "disp_cc_pll1", | |
123 | .parent_data = &(const struct clk_parent_data) { | |
124 | .index = DT_BI_TCXO, | |
125 | }, | |
126 | .num_parents = 1, | |
127 | .ops = &clk_alpha_pll_reset_lucid_ole_ops, | |
128 | }, | |
129 | }, | |
130 | }; | |
131 | ||
132 | static const struct parent_map disp_cc_parent_map_0[] = { | |
133 | { P_BI_TCXO, 0 }, | |
134 | }; | |
135 | ||
136 | static const struct clk_parent_data disp_cc_parent_data_0[] = { | |
137 | { .index = DT_BI_TCXO }, | |
138 | }; | |
139 | ||
140 | static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { | |
141 | { .index = DT_BI_TCXO_AO }, | |
142 | }; | |
143 | ||
144 | static const struct parent_map disp_cc_parent_map_1[] = { | |
145 | { P_BI_TCXO, 0 }, | |
146 | { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, | |
147 | { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, | |
148 | { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, | |
149 | }; | |
150 | ||
151 | static const struct clk_parent_data disp_cc_parent_data_1[] = { | |
152 | { .index = DT_BI_TCXO }, | |
153 | { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, | |
154 | { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, | |
155 | { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, | |
156 | }; | |
157 | ||
158 | static const struct parent_map disp_cc_parent_map_2[] = { | |
159 | { P_BI_TCXO, 0 }, | |
160 | { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, | |
161 | { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, | |
162 | { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, | |
163 | { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, | |
164 | }; | |
165 | ||
166 | static const struct clk_parent_data disp_cc_parent_data_2[] = { | |
167 | { .index = DT_BI_TCXO }, | |
168 | { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, | |
169 | { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, | |
170 | { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, | |
171 | { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, | |
172 | }; | |
173 | ||
174 | static const struct parent_map disp_cc_parent_map_3[] = { | |
175 | { P_BI_TCXO, 0 }, | |
176 | { P_DP1_PHY_PLL_LINK_CLK, 2 }, | |
177 | { P_DP2_PHY_PLL_LINK_CLK, 3 }, | |
178 | { P_DP3_PHY_PLL_LINK_CLK, 4 }, | |
179 | }; | |
180 | ||
181 | static const struct clk_parent_data disp_cc_parent_data_3[] = { | |
182 | { .index = DT_BI_TCXO }, | |
183 | { .index = DT_DP1_PHY_PLL_LINK_CLK }, | |
184 | { .index = DT_DP2_PHY_PLL_LINK_CLK }, | |
185 | { .index = DT_DP3_PHY_PLL_LINK_CLK }, | |
186 | }; | |
187 | ||
188 | static const struct parent_map disp_cc_parent_map_4[] = { | |
189 | { P_BI_TCXO, 0 }, | |
190 | { P_DP0_PHY_PLL_LINK_CLK, 1 }, | |
191 | { P_DP1_PHY_PLL_VCO_DIV_CLK, 2 }, | |
192 | { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, | |
193 | { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, | |
194 | { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, | |
195 | }; | |
196 | ||
197 | static const struct clk_parent_data disp_cc_parent_data_4[] = { | |
198 | { .index = DT_BI_TCXO }, | |
199 | { .index = DT_DP0_PHY_PLL_LINK_CLK }, | |
200 | { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, | |
201 | { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, | |
202 | { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, | |
203 | { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, | |
204 | }; | |
205 | ||
206 | static const struct parent_map disp_cc_parent_map_5[] = { | |
207 | { P_BI_TCXO, 0 }, | |
208 | { P_DSI0_PHY_PLL_OUT_BYTECLK, 4 }, | |
209 | { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, | |
210 | }; | |
211 | ||
212 | static const struct clk_parent_data disp_cc_parent_data_5[] = { | |
213 | { .index = DT_BI_TCXO }, | |
214 | { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, | |
215 | { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, | |
216 | }; | |
217 | ||
218 | static const struct parent_map disp_cc_parent_map_6[] = { | |
219 | { P_BI_TCXO, 0 }, | |
220 | { P_DISP_CC_PLL1_OUT_MAIN, 4 }, | |
221 | { P_DISP_CC_PLL1_OUT_EVEN, 6 }, | |
222 | }; | |
223 | ||
224 | static const struct clk_parent_data disp_cc_parent_data_6[] = { | |
225 | { .index = DT_BI_TCXO }, | |
226 | { .hw = &disp_cc_pll1.clkr.hw }, | |
227 | { .hw = &disp_cc_pll1.clkr.hw }, | |
228 | }; | |
229 | ||
230 | static const struct parent_map disp_cc_parent_map_7[] = { | |
231 | { P_BI_TCXO, 0 }, | |
232 | { P_DP0_PHY_PLL_LINK_CLK, 1 }, | |
233 | { P_DP1_PHY_PLL_LINK_CLK, 2 }, | |
234 | { P_DP2_PHY_PLL_LINK_CLK, 3 }, | |
235 | { P_DP3_PHY_PLL_LINK_CLK, 4 }, | |
236 | }; | |
237 | ||
238 | static const struct clk_parent_data disp_cc_parent_data_7[] = { | |
239 | { .index = DT_BI_TCXO }, | |
240 | { .index = DT_DP0_PHY_PLL_LINK_CLK }, | |
241 | { .index = DT_DP1_PHY_PLL_LINK_CLK }, | |
242 | { .index = DT_DP2_PHY_PLL_LINK_CLK }, | |
243 | { .index = DT_DP3_PHY_PLL_LINK_CLK }, | |
244 | }; | |
245 | ||
246 | static const struct parent_map disp_cc_parent_map_8[] = { | |
247 | { P_BI_TCXO, 0 }, | |
248 | { P_DISP_CC_PLL0_OUT_MAIN, 1 }, | |
249 | { P_DISP_CC_PLL1_OUT_MAIN, 4 }, | |
250 | { P_DISP_CC_PLL1_OUT_EVEN, 6 }, | |
251 | }; | |
252 | ||
253 | static const struct clk_parent_data disp_cc_parent_data_8[] = { | |
254 | { .index = DT_BI_TCXO }, | |
255 | { .hw = &disp_cc_pll0.clkr.hw }, | |
256 | { .hw = &disp_cc_pll1.clkr.hw }, | |
257 | { .hw = &disp_cc_pll1.clkr.hw }, | |
258 | }; | |
259 | ||
260 | static const struct parent_map disp_cc_parent_map_9[] = { | |
261 | { P_SLEEP_CLK, 0 }, | |
262 | }; | |
263 | ||
264 | static const struct clk_parent_data disp_cc_parent_data_9[] = { | |
265 | { .index = DT_SLEEP_CLK }, | |
266 | }; | |
267 | ||
268 | static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { | |
269 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
270 | F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), | |
271 | F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), | |
272 | { } | |
273 | }; | |
274 | ||
275 | static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { | |
276 | .cmd_rcgr = 0x82e8, | |
277 | .mnd_width = 0, | |
278 | .hid_width = 5, | |
279 | .parent_map = disp_cc_parent_map_6, | |
280 | .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, | |
281 | .clkr.hw.init = &(struct clk_init_data) { | |
282 | .name = "disp_cc_mdss_ahb_clk_src", | |
283 | .parent_data = disp_cc_parent_data_6, | |
284 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), | |
285 | .flags = CLK_SET_RATE_PARENT, | |
286 | .ops = &clk_rcg2_shared_ops, | |
287 | }, | |
288 | }; | |
289 | ||
290 | static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { | |
291 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
292 | { } | |
293 | }; | |
294 | ||
295 | static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { | |
296 | .cmd_rcgr = 0x8108, | |
297 | .mnd_width = 0, | |
298 | .hid_width = 5, | |
299 | .parent_map = disp_cc_parent_map_2, | |
300 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
301 | .clkr.hw.init = &(struct clk_init_data) { | |
302 | .name = "disp_cc_mdss_byte0_clk_src", | |
303 | .parent_data = disp_cc_parent_data_2, | |
304 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), | |
305 | .flags = CLK_SET_RATE_PARENT, | |
306 | .ops = &clk_byte2_ops, | |
307 | }, | |
308 | }; | |
309 | ||
310 | static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { | |
311 | .cmd_rcgr = 0x8124, | |
312 | .mnd_width = 0, | |
313 | .hid_width = 5, | |
314 | .parent_map = disp_cc_parent_map_2, | |
315 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
316 | .clkr.hw.init = &(struct clk_init_data) { | |
317 | .name = "disp_cc_mdss_byte1_clk_src", | |
318 | .parent_data = disp_cc_parent_data_2, | |
319 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), | |
320 | .flags = CLK_SET_RATE_PARENT, | |
321 | .ops = &clk_byte2_ops, | |
322 | }, | |
323 | }; | |
324 | ||
325 | static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { | |
326 | .cmd_rcgr = 0x81bc, | |
327 | .mnd_width = 0, | |
328 | .hid_width = 5, | |
329 | .parent_map = disp_cc_parent_map_0, | |
330 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
331 | .clkr.hw.init = &(struct clk_init_data) { | |
332 | .name = "disp_cc_mdss_dptx0_aux_clk_src", | |
333 | .parent_data = disp_cc_parent_data_0, | |
334 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), | |
335 | .flags = CLK_SET_RATE_PARENT, | |
336 | .ops = &clk_rcg2_ops, | |
337 | }, | |
338 | }; | |
339 | ||
340 | static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { | |
341 | F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), | |
342 | F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), | |
343 | F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), | |
344 | F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), | |
345 | { } | |
346 | }; | |
347 | ||
348 | static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { | |
349 | .cmd_rcgr = 0x8170, | |
350 | .mnd_width = 0, | |
351 | .hid_width = 5, | |
352 | .parent_map = disp_cc_parent_map_7, | |
353 | .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, | |
354 | .clkr.hw.init = &(struct clk_init_data) { | |
355 | .name = "disp_cc_mdss_dptx0_link_clk_src", | |
356 | .parent_data = disp_cc_parent_data_7, | |
357 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), | |
358 | .flags = CLK_SET_RATE_PARENT, | |
359 | .ops = &clk_rcg2_ops, | |
360 | }, | |
361 | }; | |
362 | ||
363 | static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { | |
364 | .cmd_rcgr = 0x818c, | |
365 | .mnd_width = 16, | |
366 | .hid_width = 5, | |
367 | .parent_map = disp_cc_parent_map_4, | |
368 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
369 | .clkr.hw.init = &(struct clk_init_data) { | |
370 | .name = "disp_cc_mdss_dptx0_pixel0_clk_src", | |
371 | .parent_data = disp_cc_parent_data_4, | |
372 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), | |
373 | .flags = CLK_SET_RATE_PARENT, | |
374 | .ops = &clk_dp_ops, | |
375 | }, | |
376 | }; | |
377 | ||
378 | static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { | |
379 | .cmd_rcgr = 0x81a4, | |
380 | .mnd_width = 16, | |
381 | .hid_width = 5, | |
382 | .parent_map = disp_cc_parent_map_4, | |
383 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
384 | .clkr.hw.init = &(struct clk_init_data) { | |
385 | .name = "disp_cc_mdss_dptx0_pixel1_clk_src", | |
386 | .parent_data = disp_cc_parent_data_4, | |
387 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), | |
388 | .flags = CLK_SET_RATE_PARENT, | |
389 | .ops = &clk_dp_ops, | |
390 | }, | |
391 | }; | |
392 | ||
393 | static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { | |
394 | .cmd_rcgr = 0x8220, | |
395 | .mnd_width = 0, | |
396 | .hid_width = 5, | |
397 | .parent_map = disp_cc_parent_map_0, | |
398 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
399 | .clkr.hw.init = &(struct clk_init_data) { | |
400 | .name = "disp_cc_mdss_dptx1_aux_clk_src", | |
401 | .parent_data = disp_cc_parent_data_0, | |
402 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), | |
403 | .flags = CLK_SET_RATE_PARENT, | |
404 | .ops = &clk_dp_ops, | |
405 | }, | |
406 | }; | |
407 | ||
408 | static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { | |
409 | .cmd_rcgr = 0x8204, | |
410 | .mnd_width = 0, | |
411 | .hid_width = 5, | |
412 | .parent_map = disp_cc_parent_map_3, | |
413 | .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, | |
414 | .clkr.hw.init = &(struct clk_init_data) { | |
415 | .name = "disp_cc_mdss_dptx1_link_clk_src", | |
416 | .parent_data = disp_cc_parent_data_3, | |
417 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), | |
418 | .flags = CLK_SET_RATE_PARENT, | |
419 | .ops = &clk_rcg2_ops, | |
420 | }, | |
421 | }; | |
422 | ||
423 | static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { | |
424 | .cmd_rcgr = 0x81d4, | |
425 | .mnd_width = 16, | |
426 | .hid_width = 5, | |
427 | .parent_map = disp_cc_parent_map_1, | |
428 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
429 | .clkr.hw.init = &(struct clk_init_data) { | |
430 | .name = "disp_cc_mdss_dptx1_pixel0_clk_src", | |
431 | .parent_data = disp_cc_parent_data_1, | |
432 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), | |
433 | .flags = CLK_SET_RATE_PARENT, | |
434 | .ops = &clk_dp_ops, | |
435 | }, | |
436 | }; | |
437 | ||
438 | static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { | |
439 | .cmd_rcgr = 0x81ec, | |
440 | .mnd_width = 16, | |
441 | .hid_width = 5, | |
442 | .parent_map = disp_cc_parent_map_1, | |
443 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
444 | .clkr.hw.init = &(struct clk_init_data) { | |
445 | .name = "disp_cc_mdss_dptx1_pixel1_clk_src", | |
446 | .parent_data = disp_cc_parent_data_1, | |
447 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), | |
448 | .flags = CLK_SET_RATE_PARENT, | |
449 | .ops = &clk_dp_ops, | |
450 | }, | |
451 | }; | |
452 | ||
453 | static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { | |
454 | .cmd_rcgr = 0x8284, | |
455 | .mnd_width = 0, | |
456 | .hid_width = 5, | |
457 | .parent_map = disp_cc_parent_map_0, | |
458 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
459 | .clkr.hw.init = &(struct clk_init_data) { | |
460 | .name = "disp_cc_mdss_dptx2_aux_clk_src", | |
461 | .parent_data = disp_cc_parent_data_0, | |
462 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), | |
463 | .flags = CLK_SET_RATE_PARENT, | |
464 | .ops = &clk_rcg2_ops, | |
465 | }, | |
466 | }; | |
467 | ||
468 | static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { | |
469 | .cmd_rcgr = 0x8238, | |
470 | .mnd_width = 0, | |
471 | .hid_width = 5, | |
472 | .parent_map = disp_cc_parent_map_3, | |
473 | .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, | |
474 | .clkr.hw.init = &(struct clk_init_data) { | |
475 | .name = "disp_cc_mdss_dptx2_link_clk_src", | |
476 | .parent_data = disp_cc_parent_data_3, | |
477 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), | |
478 | .flags = CLK_SET_RATE_PARENT, | |
479 | .ops = &clk_rcg2_ops, | |
480 | }, | |
481 | }; | |
482 | ||
483 | static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { | |
484 | .cmd_rcgr = 0x8254, | |
485 | .mnd_width = 16, | |
486 | .hid_width = 5, | |
487 | .parent_map = disp_cc_parent_map_1, | |
488 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
489 | .clkr.hw.init = &(struct clk_init_data) { | |
490 | .name = "disp_cc_mdss_dptx2_pixel0_clk_src", | |
491 | .parent_data = disp_cc_parent_data_1, | |
492 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), | |
493 | .flags = CLK_SET_RATE_PARENT, | |
494 | .ops = &clk_dp_ops, | |
495 | }, | |
496 | }; | |
497 | ||
498 | static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { | |
499 | .cmd_rcgr = 0x826c, | |
500 | .mnd_width = 16, | |
501 | .hid_width = 5, | |
502 | .parent_map = disp_cc_parent_map_1, | |
503 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
504 | .clkr.hw.init = &(struct clk_init_data) { | |
505 | .name = "disp_cc_mdss_dptx2_pixel1_clk_src", | |
506 | .parent_data = disp_cc_parent_data_1, | |
507 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), | |
508 | .flags = CLK_SET_RATE_PARENT, | |
509 | .ops = &clk_dp_ops, | |
510 | }, | |
511 | }; | |
512 | ||
513 | static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { | |
514 | .cmd_rcgr = 0x82d0, | |
515 | .mnd_width = 0, | |
516 | .hid_width = 5, | |
517 | .parent_map = disp_cc_parent_map_0, | |
518 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
519 | .clkr.hw.init = &(struct clk_init_data) { | |
520 | .name = "disp_cc_mdss_dptx3_aux_clk_src", | |
521 | .parent_data = disp_cc_parent_data_0, | |
522 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), | |
523 | .flags = CLK_SET_RATE_PARENT, | |
524 | .ops = &clk_rcg2_ops, | |
525 | }, | |
526 | }; | |
527 | ||
528 | static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { | |
529 | .cmd_rcgr = 0x82b4, | |
530 | .mnd_width = 0, | |
531 | .hid_width = 5, | |
532 | .parent_map = disp_cc_parent_map_3, | |
533 | .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, | |
534 | .clkr.hw.init = &(struct clk_init_data) { | |
535 | .name = "disp_cc_mdss_dptx3_link_clk_src", | |
536 | .parent_data = disp_cc_parent_data_3, | |
537 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), | |
538 | .flags = CLK_SET_RATE_PARENT, | |
539 | .ops = &clk_rcg2_ops, | |
540 | }, | |
541 | }; | |
542 | ||
543 | static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { | |
544 | .cmd_rcgr = 0x829c, | |
545 | .mnd_width = 16, | |
546 | .hid_width = 5, | |
547 | .parent_map = disp_cc_parent_map_1, | |
548 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
549 | .clkr.hw.init = &(struct clk_init_data) { | |
550 | .name = "disp_cc_mdss_dptx3_pixel0_clk_src", | |
551 | .parent_data = disp_cc_parent_data_1, | |
552 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), | |
553 | .flags = CLK_SET_RATE_PARENT, | |
554 | .ops = &clk_dp_ops, | |
555 | }, | |
556 | }; | |
557 | ||
558 | static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { | |
559 | .cmd_rcgr = 0x8140, | |
560 | .mnd_width = 0, | |
561 | .hid_width = 5, | |
562 | .parent_map = disp_cc_parent_map_5, | |
563 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
564 | .clkr.hw.init = &(struct clk_init_data) { | |
565 | .name = "disp_cc_mdss_esc0_clk_src", | |
566 | .parent_data = disp_cc_parent_data_5, | |
567 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), | |
568 | .flags = CLK_SET_RATE_PARENT, | |
569 | .ops = &clk_rcg2_ops, | |
570 | }, | |
571 | }; | |
572 | ||
573 | static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { | |
574 | .cmd_rcgr = 0x8158, | |
575 | .mnd_width = 0, | |
576 | .hid_width = 5, | |
577 | .parent_map = disp_cc_parent_map_5, | |
578 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
579 | .clkr.hw.init = &(struct clk_init_data) { | |
580 | .name = "disp_cc_mdss_esc1_clk_src", | |
581 | .parent_data = disp_cc_parent_data_5, | |
582 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), | |
583 | .flags = CLK_SET_RATE_PARENT, | |
584 | .ops = &clk_rcg2_ops, | |
585 | }, | |
586 | }; | |
587 | ||
588 | static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { | |
589 | F(19200000, P_BI_TCXO, 1, 0, 0), | |
590 | F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
591 | F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
592 | F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
593 | F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
594 | F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
595 | F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
596 | F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
597 | F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), | |
598 | { } | |
599 | }; | |
600 | ||
601 | static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { | |
602 | .cmd_rcgr = 0x80d8, | |
603 | .mnd_width = 0, | |
604 | .hid_width = 5, | |
605 | .parent_map = disp_cc_parent_map_8, | |
606 | .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, | |
607 | .clkr.hw.init = &(struct clk_init_data) { | |
608 | .name = "disp_cc_mdss_mdp_clk_src", | |
609 | .parent_data = disp_cc_parent_data_8, | |
610 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), | |
611 | .flags = CLK_SET_RATE_PARENT, | |
612 | .ops = &clk_rcg2_shared_ops, | |
613 | }, | |
614 | }; | |
615 | ||
616 | static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { | |
617 | .cmd_rcgr = 0x80a8, | |
618 | .mnd_width = 8, | |
619 | .hid_width = 5, | |
620 | .parent_map = disp_cc_parent_map_2, | |
621 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
622 | .clkr.hw.init = &(struct clk_init_data) { | |
623 | .name = "disp_cc_mdss_pclk0_clk_src", | |
624 | .parent_data = disp_cc_parent_data_2, | |
625 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), | |
626 | .flags = CLK_SET_RATE_PARENT, | |
627 | .ops = &clk_pixel_ops, | |
628 | }, | |
629 | }; | |
630 | ||
631 | static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { | |
632 | .cmd_rcgr = 0x80c0, | |
633 | .mnd_width = 8, | |
634 | .hid_width = 5, | |
635 | .parent_map = disp_cc_parent_map_2, | |
636 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
637 | .clkr.hw.init = &(struct clk_init_data) { | |
638 | .name = "disp_cc_mdss_pclk1_clk_src", | |
639 | .parent_data = disp_cc_parent_data_2, | |
640 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), | |
641 | .flags = CLK_SET_RATE_PARENT, | |
642 | .ops = &clk_pixel_ops, | |
643 | }, | |
644 | }; | |
645 | ||
646 | static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { | |
647 | .cmd_rcgr = 0x80f0, | |
648 | .mnd_width = 0, | |
649 | .hid_width = 5, | |
650 | .parent_map = disp_cc_parent_map_0, | |
651 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
652 | .clkr.hw.init = &(struct clk_init_data) { | |
653 | .name = "disp_cc_mdss_vsync_clk_src", | |
654 | .parent_data = disp_cc_parent_data_0, | |
655 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), | |
656 | .flags = CLK_SET_RATE_PARENT, | |
657 | .ops = &clk_rcg2_ops, | |
658 | }, | |
659 | }; | |
660 | ||
661 | static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { | |
662 | F(32000, P_SLEEP_CLK, 1, 0, 0), | |
663 | { } | |
664 | }; | |
665 | ||
666 | static struct clk_rcg2 disp_cc_sleep_clk_src = { | |
667 | .cmd_rcgr = 0xe05c, | |
668 | .mnd_width = 0, | |
669 | .hid_width = 5, | |
670 | .parent_map = disp_cc_parent_map_9, | |
671 | .freq_tbl = ftbl_disp_cc_sleep_clk_src, | |
672 | .clkr.hw.init = &(struct clk_init_data) { | |
673 | .name = "disp_cc_sleep_clk_src", | |
674 | .parent_data = disp_cc_parent_data_9, | |
675 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), | |
676 | .flags = CLK_SET_RATE_PARENT, | |
677 | .ops = &clk_rcg2_ops, | |
678 | }, | |
679 | }; | |
680 | ||
681 | static struct clk_rcg2 disp_cc_xo_clk_src = { | |
682 | .cmd_rcgr = 0xe03c, | |
683 | .mnd_width = 0, | |
684 | .hid_width = 5, | |
685 | .parent_map = disp_cc_parent_map_0, | |
686 | .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, | |
687 | .clkr.hw.init = &(struct clk_init_data) { | |
688 | .name = "disp_cc_xo_clk_src", | |
689 | .parent_data = disp_cc_parent_data_0_ao, | |
690 | .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), | |
691 | .flags = CLK_SET_RATE_PARENT, | |
692 | .ops = &clk_rcg2_ops, | |
693 | }, | |
694 | }; | |
695 | ||
696 | static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { | |
697 | .reg = 0x8120, | |
698 | .shift = 0, | |
699 | .width = 4, | |
700 | .clkr.hw.init = &(struct clk_init_data) { | |
701 | .name = "disp_cc_mdss_byte0_div_clk_src", | |
702 | .parent_hws = (const struct clk_hw*[]) { | |
703 | &disp_cc_mdss_byte0_clk_src.clkr.hw, | |
704 | }, | |
705 | .num_parents = 1, | |
706 | .ops = &clk_regmap_div_ops, | |
707 | }, | |
708 | }; | |
709 | ||
710 | static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { | |
711 | .reg = 0x813c, | |
712 | .shift = 0, | |
713 | .width = 4, | |
714 | .clkr.hw.init = &(struct clk_init_data) { | |
715 | .name = "disp_cc_mdss_byte1_div_clk_src", | |
716 | .parent_hws = (const struct clk_hw*[]) { | |
717 | &disp_cc_mdss_byte1_clk_src.clkr.hw, | |
718 | }, | |
719 | .num_parents = 1, | |
720 | .ops = &clk_regmap_div_ops, | |
721 | }, | |
722 | }; | |
723 | ||
724 | static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { | |
725 | .reg = 0x8188, | |
726 | .shift = 0, | |
727 | .width = 4, | |
728 | .clkr.hw.init = &(struct clk_init_data) { | |
729 | .name = "disp_cc_mdss_dptx0_link_div_clk_src", | |
730 | .parent_hws = (const struct clk_hw*[]) { | |
731 | &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, | |
732 | }, | |
733 | .num_parents = 1, | |
734 | .flags = CLK_SET_RATE_PARENT, | |
735 | .ops = &clk_regmap_div_ro_ops, | |
736 | }, | |
737 | }; | |
738 | ||
739 | static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { | |
740 | .reg = 0x821c, | |
741 | .shift = 0, | |
742 | .width = 4, | |
743 | .clkr.hw.init = &(struct clk_init_data) { | |
744 | .name = "disp_cc_mdss_dptx1_link_div_clk_src", | |
745 | .parent_hws = (const struct clk_hw*[]) { | |
746 | &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, | |
747 | }, | |
748 | .num_parents = 1, | |
749 | .flags = CLK_SET_RATE_PARENT, | |
750 | .ops = &clk_regmap_div_ro_ops, | |
751 | }, | |
752 | }; | |
753 | ||
754 | static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { | |
755 | .reg = 0x8250, | |
756 | .shift = 0, | |
757 | .width = 4, | |
758 | .clkr.hw.init = &(struct clk_init_data) { | |
759 | .name = "disp_cc_mdss_dptx2_link_div_clk_src", | |
760 | .parent_hws = (const struct clk_hw*[]) { | |
761 | &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, | |
762 | }, | |
763 | .num_parents = 1, | |
764 | .flags = CLK_SET_RATE_PARENT, | |
765 | .ops = &clk_regmap_div_ro_ops, | |
766 | }, | |
767 | }; | |
768 | ||
769 | static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { | |
770 | .reg = 0x82cc, | |
771 | .shift = 0, | |
772 | .width = 4, | |
773 | .clkr.hw.init = &(struct clk_init_data) { | |
774 | .name = "disp_cc_mdss_dptx3_link_div_clk_src", | |
775 | .parent_hws = (const struct clk_hw*[]) { | |
776 | &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, | |
777 | }, | |
778 | .num_parents = 1, | |
779 | .flags = CLK_SET_RATE_PARENT, | |
780 | .ops = &clk_regmap_div_ro_ops, | |
781 | }, | |
782 | }; | |
783 | ||
784 | static struct clk_branch disp_cc_mdss_accu_clk = { | |
785 | .halt_reg = 0xe058, | |
786 | .halt_check = BRANCH_HALT_VOTED, | |
787 | .clkr = { | |
788 | .enable_reg = 0xe058, | |
789 | .enable_mask = BIT(0), | |
790 | .hw.init = &(struct clk_init_data){ | |
791 | .name = "disp_cc_mdss_accu_clk", | |
792 | .parent_hws = (const struct clk_hw*[]) { | |
793 | &disp_cc_xo_clk_src.clkr.hw, | |
794 | }, | |
795 | .num_parents = 1, | |
796 | .flags = CLK_SET_RATE_PARENT, | |
797 | .ops = &clk_branch2_ops, | |
798 | }, | |
799 | }, | |
800 | }; | |
801 | ||
802 | static struct clk_branch disp_cc_mdss_ahb1_clk = { | |
803 | .halt_reg = 0xa020, | |
804 | .halt_check = BRANCH_HALT, | |
805 | .clkr = { | |
806 | .enable_reg = 0xa020, | |
807 | .enable_mask = BIT(0), | |
808 | .hw.init = &(struct clk_init_data) { | |
809 | .name = "disp_cc_mdss_ahb1_clk", | |
810 | .parent_hws = (const struct clk_hw*[]) { | |
811 | &disp_cc_mdss_ahb_clk_src.clkr.hw, | |
812 | }, | |
813 | .num_parents = 1, | |
814 | .flags = CLK_SET_RATE_PARENT, | |
815 | .ops = &clk_branch2_ops, | |
816 | }, | |
817 | }, | |
818 | }; | |
819 | ||
820 | static struct clk_branch disp_cc_mdss_ahb_clk = { | |
821 | .halt_reg = 0x80a4, | |
822 | .halt_check = BRANCH_HALT, | |
823 | .clkr = { | |
824 | .enable_reg = 0x80a4, | |
825 | .enable_mask = BIT(0), | |
826 | .hw.init = &(struct clk_init_data) { | |
827 | .name = "disp_cc_mdss_ahb_clk", | |
828 | .parent_hws = (const struct clk_hw*[]) { | |
829 | &disp_cc_mdss_ahb_clk_src.clkr.hw, | |
830 | }, | |
831 | .num_parents = 1, | |
832 | .flags = CLK_SET_RATE_PARENT, | |
833 | .ops = &clk_branch2_ops, | |
834 | }, | |
835 | }, | |
836 | }; | |
837 | ||
838 | static struct clk_branch disp_cc_mdss_byte0_clk = { | |
839 | .halt_reg = 0x8028, | |
840 | .halt_check = BRANCH_HALT, | |
841 | .clkr = { | |
842 | .enable_reg = 0x8028, | |
843 | .enable_mask = BIT(0), | |
844 | .hw.init = &(struct clk_init_data) { | |
845 | .name = "disp_cc_mdss_byte0_clk", | |
846 | .parent_hws = (const struct clk_hw*[]) { | |
847 | &disp_cc_mdss_byte0_clk_src.clkr.hw, | |
848 | }, | |
849 | .num_parents = 1, | |
850 | .flags = CLK_SET_RATE_PARENT, | |
851 | .ops = &clk_branch2_ops, | |
852 | }, | |
853 | }, | |
854 | }; | |
855 | ||
856 | static struct clk_branch disp_cc_mdss_byte0_intf_clk = { | |
857 | .halt_reg = 0x802c, | |
858 | .halt_check = BRANCH_HALT, | |
859 | .clkr = { | |
860 | .enable_reg = 0x802c, | |
861 | .enable_mask = BIT(0), | |
862 | .hw.init = &(struct clk_init_data) { | |
863 | .name = "disp_cc_mdss_byte0_intf_clk", | |
864 | .parent_hws = (const struct clk_hw*[]) { | |
865 | &disp_cc_mdss_byte0_div_clk_src.clkr.hw, | |
866 | }, | |
867 | .num_parents = 1, | |
868 | .flags = CLK_SET_RATE_PARENT, | |
869 | .ops = &clk_branch2_ops, | |
870 | }, | |
871 | }, | |
872 | }; | |
873 | ||
874 | static struct clk_branch disp_cc_mdss_byte1_clk = { | |
875 | .halt_reg = 0x8030, | |
876 | .halt_check = BRANCH_HALT, | |
877 | .clkr = { | |
878 | .enable_reg = 0x8030, | |
879 | .enable_mask = BIT(0), | |
880 | .hw.init = &(struct clk_init_data) { | |
881 | .name = "disp_cc_mdss_byte1_clk", | |
882 | .parent_hws = (const struct clk_hw*[]) { | |
883 | &disp_cc_mdss_byte1_clk_src.clkr.hw, | |
884 | }, | |
885 | .num_parents = 1, | |
886 | .flags = CLK_SET_RATE_PARENT, | |
887 | .ops = &clk_branch2_ops, | |
888 | }, | |
889 | }, | |
890 | }; | |
891 | ||
892 | static struct clk_branch disp_cc_mdss_byte1_intf_clk = { | |
893 | .halt_reg = 0x8034, | |
894 | .halt_check = BRANCH_HALT, | |
895 | .clkr = { | |
896 | .enable_reg = 0x8034, | |
897 | .enable_mask = BIT(0), | |
898 | .hw.init = &(struct clk_init_data) { | |
899 | .name = "disp_cc_mdss_byte1_intf_clk", | |
900 | .parent_hws = (const struct clk_hw*[]) { | |
901 | &disp_cc_mdss_byte1_div_clk_src.clkr.hw, | |
902 | }, | |
903 | .num_parents = 1, | |
904 | .flags = CLK_SET_RATE_PARENT, | |
905 | .ops = &clk_branch2_ops, | |
906 | }, | |
907 | }, | |
908 | }; | |
909 | ||
910 | static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { | |
911 | .halt_reg = 0x8058, | |
912 | .halt_check = BRANCH_HALT, | |
913 | .clkr = { | |
914 | .enable_reg = 0x8058, | |
915 | .enable_mask = BIT(0), | |
916 | .hw.init = &(struct clk_init_data) { | |
917 | .name = "disp_cc_mdss_dptx0_aux_clk", | |
918 | .parent_hws = (const struct clk_hw*[]) { | |
919 | &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, | |
920 | }, | |
921 | .num_parents = 1, | |
922 | .flags = CLK_SET_RATE_PARENT, | |
923 | .ops = &clk_branch2_ops, | |
924 | }, | |
925 | }, | |
926 | }; | |
927 | ||
928 | static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { | |
929 | .halt_reg = 0x804c, | |
930 | .halt_check = BRANCH_HALT, | |
931 | .clkr = { | |
932 | .enable_reg = 0x804c, | |
933 | .enable_mask = BIT(0), | |
934 | .hw.init = &(struct clk_init_data) { | |
935 | .name = "disp_cc_mdss_dptx0_crypto_clk", | |
936 | .parent_hws = (const struct clk_hw*[]) { | |
937 | &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, | |
938 | }, | |
939 | .num_parents = 1, | |
940 | .flags = CLK_SET_RATE_PARENT, | |
941 | .ops = &clk_branch2_ops, | |
942 | }, | |
943 | }, | |
944 | }; | |
945 | ||
946 | static struct clk_branch disp_cc_mdss_dptx0_link_clk = { | |
947 | .halt_reg = 0x8040, | |
948 | .halt_check = BRANCH_HALT, | |
949 | .clkr = { | |
950 | .enable_reg = 0x8040, | |
951 | .enable_mask = BIT(0), | |
952 | .hw.init = &(struct clk_init_data) { | |
953 | .name = "disp_cc_mdss_dptx0_link_clk", | |
954 | .parent_hws = (const struct clk_hw*[]) { | |
955 | &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, | |
956 | }, | |
957 | .num_parents = 1, | |
958 | .flags = CLK_SET_RATE_PARENT, | |
959 | .ops = &clk_branch2_ops, | |
960 | }, | |
961 | }, | |
962 | }; | |
963 | ||
964 | static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { | |
965 | .halt_reg = 0x8048, | |
966 | .halt_check = BRANCH_HALT, | |
967 | .clkr = { | |
968 | .enable_reg = 0x8048, | |
969 | .enable_mask = BIT(0), | |
970 | .hw.init = &(struct clk_init_data) { | |
971 | .name = "disp_cc_mdss_dptx0_link_intf_clk", | |
972 | .parent_hws = (const struct clk_hw*[]) { | |
973 | &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, | |
974 | }, | |
975 | .num_parents = 1, | |
976 | .flags = CLK_SET_RATE_PARENT, | |
977 | .ops = &clk_branch2_ops, | |
978 | }, | |
979 | }, | |
980 | }; | |
981 | ||
982 | static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { | |
983 | .halt_reg = 0x8050, | |
984 | .halt_check = BRANCH_HALT, | |
985 | .clkr = { | |
986 | .enable_reg = 0x8050, | |
987 | .enable_mask = BIT(0), | |
988 | .hw.init = &(struct clk_init_data) { | |
989 | .name = "disp_cc_mdss_dptx0_pixel0_clk", | |
990 | .parent_hws = (const struct clk_hw*[]) { | |
991 | &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, | |
992 | }, | |
993 | .num_parents = 1, | |
994 | .flags = CLK_SET_RATE_PARENT, | |
995 | .ops = &clk_branch2_ops, | |
996 | }, | |
997 | }, | |
998 | }; | |
999 | ||
1000 | static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { | |
1001 | .halt_reg = 0x8054, | |
1002 | .halt_check = BRANCH_HALT, | |
1003 | .clkr = { | |
1004 | .enable_reg = 0x8054, | |
1005 | .enable_mask = BIT(0), | |
1006 | .hw.init = &(struct clk_init_data) { | |
1007 | .name = "disp_cc_mdss_dptx0_pixel1_clk", | |
1008 | .parent_hws = (const struct clk_hw*[]) { | |
1009 | &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, | |
1010 | }, | |
1011 | .num_parents = 1, | |
1012 | .flags = CLK_SET_RATE_PARENT, | |
1013 | .ops = &clk_branch2_ops, | |
1014 | }, | |
1015 | }, | |
1016 | }; | |
1017 | ||
1018 | static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { | |
1019 | .halt_reg = 0x8044, | |
1020 | .halt_check = BRANCH_HALT, | |
1021 | .clkr = { | |
1022 | .enable_reg = 0x8044, | |
1023 | .enable_mask = BIT(0), | |
1024 | .hw.init = &(struct clk_init_data) { | |
1025 | .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", | |
1026 | .parent_hws = (const struct clk_hw*[]) { | |
1027 | &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, | |
1028 | }, | |
1029 | .num_parents = 1, | |
1030 | .flags = CLK_SET_RATE_PARENT, | |
1031 | .ops = &clk_branch2_ops, | |
1032 | }, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { | |
1037 | .halt_reg = 0x8074, | |
1038 | .halt_check = BRANCH_HALT, | |
1039 | .clkr = { | |
1040 | .enable_reg = 0x8074, | |
1041 | .enable_mask = BIT(0), | |
1042 | .hw.init = &(struct clk_init_data) { | |
1043 | .name = "disp_cc_mdss_dptx1_aux_clk", | |
1044 | .parent_hws = (const struct clk_hw*[]) { | |
1045 | &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, | |
1046 | }, | |
1047 | .num_parents = 1, | |
1048 | .flags = CLK_SET_RATE_PARENT, | |
1049 | .ops = &clk_branch2_ops, | |
1050 | }, | |
1051 | }, | |
1052 | }; | |
1053 | ||
1054 | static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { | |
1055 | .halt_reg = 0x8070, | |
1056 | .halt_check = BRANCH_HALT, | |
1057 | .clkr = { | |
1058 | .enable_reg = 0x8070, | |
1059 | .enable_mask = BIT(0), | |
1060 | .hw.init = &(struct clk_init_data) { | |
1061 | .name = "disp_cc_mdss_dptx1_crypto_clk", | |
1062 | .parent_hws = (const struct clk_hw*[]) { | |
1063 | &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, | |
1064 | }, | |
1065 | .num_parents = 1, | |
1066 | .flags = CLK_SET_RATE_PARENT, | |
1067 | .ops = &clk_branch2_ops, | |
1068 | }, | |
1069 | }, | |
1070 | }; | |
1071 | ||
1072 | static struct clk_branch disp_cc_mdss_dptx1_link_clk = { | |
1073 | .halt_reg = 0x8064, | |
1074 | .halt_check = BRANCH_HALT, | |
1075 | .clkr = { | |
1076 | .enable_reg = 0x8064, | |
1077 | .enable_mask = BIT(0), | |
1078 | .hw.init = &(struct clk_init_data) { | |
1079 | .name = "disp_cc_mdss_dptx1_link_clk", | |
1080 | .parent_hws = (const struct clk_hw*[]) { | |
1081 | &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, | |
1082 | }, | |
1083 | .num_parents = 1, | |
1084 | .flags = CLK_SET_RATE_PARENT, | |
1085 | .ops = &clk_branch2_ops, | |
1086 | }, | |
1087 | }, | |
1088 | }; | |
1089 | ||
1090 | static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { | |
1091 | .halt_reg = 0x806c, | |
1092 | .halt_check = BRANCH_HALT, | |
1093 | .clkr = { | |
1094 | .enable_reg = 0x806c, | |
1095 | .enable_mask = BIT(0), | |
1096 | .hw.init = &(struct clk_init_data) { | |
1097 | .name = "disp_cc_mdss_dptx1_link_intf_clk", | |
1098 | .parent_hws = (const struct clk_hw*[]) { | |
1099 | &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, | |
1100 | }, | |
1101 | .num_parents = 1, | |
1102 | .flags = CLK_SET_RATE_PARENT, | |
1103 | .ops = &clk_branch2_ops, | |
1104 | }, | |
1105 | }, | |
1106 | }; | |
1107 | ||
1108 | static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { | |
1109 | .halt_reg = 0x805c, | |
1110 | .halt_check = BRANCH_HALT, | |
1111 | .clkr = { | |
1112 | .enable_reg = 0x805c, | |
1113 | .enable_mask = BIT(0), | |
1114 | .hw.init = &(struct clk_init_data) { | |
1115 | .name = "disp_cc_mdss_dptx1_pixel0_clk", | |
1116 | .parent_hws = (const struct clk_hw*[]) { | |
1117 | &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, | |
1118 | }, | |
1119 | .num_parents = 1, | |
1120 | .flags = CLK_SET_RATE_PARENT, | |
1121 | .ops = &clk_branch2_ops, | |
1122 | }, | |
1123 | }, | |
1124 | }; | |
1125 | ||
1126 | static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { | |
1127 | .halt_reg = 0x8060, | |
1128 | .halt_check = BRANCH_HALT, | |
1129 | .clkr = { | |
1130 | .enable_reg = 0x8060, | |
1131 | .enable_mask = BIT(0), | |
1132 | .hw.init = &(struct clk_init_data) { | |
1133 | .name = "disp_cc_mdss_dptx1_pixel1_clk", | |
1134 | .parent_hws = (const struct clk_hw*[]) { | |
1135 | &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, | |
1136 | }, | |
1137 | .num_parents = 1, | |
1138 | .flags = CLK_SET_RATE_PARENT, | |
1139 | .ops = &clk_branch2_ops, | |
1140 | }, | |
1141 | }, | |
1142 | }; | |
1143 | ||
1144 | static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { | |
1145 | .halt_reg = 0x8068, | |
1146 | .halt_check = BRANCH_HALT, | |
1147 | .clkr = { | |
1148 | .enable_reg = 0x8068, | |
1149 | .enable_mask = BIT(0), | |
1150 | .hw.init = &(struct clk_init_data) { | |
1151 | .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", | |
1152 | .parent_hws = (const struct clk_hw*[]) { | |
1153 | &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, | |
1154 | }, | |
1155 | .num_parents = 1, | |
1156 | .flags = CLK_SET_RATE_PARENT, | |
1157 | .ops = &clk_branch2_ops, | |
1158 | }, | |
1159 | }, | |
1160 | }; | |
1161 | ||
1162 | static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { | |
1163 | .halt_reg = 0x808c, | |
1164 | .halt_check = BRANCH_HALT, | |
1165 | .clkr = { | |
1166 | .enable_reg = 0x808c, | |
1167 | .enable_mask = BIT(0), | |
1168 | .hw.init = &(struct clk_init_data) { | |
1169 | .name = "disp_cc_mdss_dptx2_aux_clk", | |
1170 | .parent_hws = (const struct clk_hw*[]) { | |
1171 | &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, | |
1172 | }, | |
1173 | .num_parents = 1, | |
1174 | .flags = CLK_SET_RATE_PARENT, | |
1175 | .ops = &clk_branch2_ops, | |
1176 | }, | |
1177 | }, | |
1178 | }; | |
1179 | ||
1180 | static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { | |
1181 | .halt_reg = 0x8088, | |
1182 | .halt_check = BRANCH_HALT, | |
1183 | .clkr = { | |
1184 | .enable_reg = 0x8088, | |
1185 | .enable_mask = BIT(0), | |
1186 | .hw.init = &(struct clk_init_data) { | |
1187 | .name = "disp_cc_mdss_dptx2_crypto_clk", | |
1188 | .parent_hws = (const struct clk_hw*[]) { | |
1189 | &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, | |
1190 | }, | |
1191 | .num_parents = 1, | |
1192 | .flags = CLK_SET_RATE_PARENT, | |
1193 | .ops = &clk_branch2_ops, | |
1194 | }, | |
1195 | }, | |
1196 | }; | |
1197 | ||
1198 | static struct clk_branch disp_cc_mdss_dptx2_link_clk = { | |
1199 | .halt_reg = 0x8080, | |
1200 | .halt_check = BRANCH_HALT, | |
1201 | .clkr = { | |
1202 | .enable_reg = 0x8080, | |
1203 | .enable_mask = BIT(0), | |
1204 | .hw.init = &(struct clk_init_data) { | |
1205 | .name = "disp_cc_mdss_dptx2_link_clk", | |
1206 | .parent_hws = (const struct clk_hw*[]) { | |
1207 | &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, | |
1208 | }, | |
1209 | .num_parents = 1, | |
1210 | .flags = CLK_SET_RATE_PARENT, | |
1211 | .ops = &clk_branch2_ops, | |
1212 | }, | |
1213 | }, | |
1214 | }; | |
1215 | ||
1216 | static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { | |
1217 | .halt_reg = 0x8084, | |
1218 | .halt_check = BRANCH_HALT, | |
1219 | .clkr = { | |
1220 | .enable_reg = 0x8084, | |
1221 | .enable_mask = BIT(0), | |
1222 | .hw.init = &(struct clk_init_data) { | |
1223 | .name = "disp_cc_mdss_dptx2_link_intf_clk", | |
1224 | .parent_hws = (const struct clk_hw*[]) { | |
1225 | &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, | |
1226 | }, | |
1227 | .num_parents = 1, | |
1228 | .flags = CLK_SET_RATE_PARENT, | |
1229 | .ops = &clk_branch2_ops, | |
1230 | }, | |
1231 | }, | |
1232 | }; | |
1233 | ||
1234 | static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { | |
1235 | .halt_reg = 0x8078, | |
1236 | .halt_check = BRANCH_HALT, | |
1237 | .clkr = { | |
1238 | .enable_reg = 0x8078, | |
1239 | .enable_mask = BIT(0), | |
1240 | .hw.init = &(struct clk_init_data) { | |
1241 | .name = "disp_cc_mdss_dptx2_pixel0_clk", | |
1242 | .parent_hws = (const struct clk_hw*[]) { | |
1243 | &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, | |
1244 | }, | |
1245 | .num_parents = 1, | |
1246 | .flags = CLK_SET_RATE_PARENT, | |
1247 | .ops = &clk_branch2_ops, | |
1248 | }, | |
1249 | }, | |
1250 | }; | |
1251 | ||
1252 | static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { | |
1253 | .halt_reg = 0x807c, | |
1254 | .halt_check = BRANCH_HALT, | |
1255 | .clkr = { | |
1256 | .enable_reg = 0x807c, | |
1257 | .enable_mask = BIT(0), | |
1258 | .hw.init = &(struct clk_init_data) { | |
1259 | .name = "disp_cc_mdss_dptx2_pixel1_clk", | |
1260 | .parent_hws = (const struct clk_hw*[]) { | |
1261 | &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, | |
1262 | }, | |
1263 | .num_parents = 1, | |
1264 | .flags = CLK_SET_RATE_PARENT, | |
1265 | .ops = &clk_branch2_ops, | |
1266 | }, | |
1267 | }, | |
1268 | }; | |
1269 | ||
1270 | static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { | |
1271 | .halt_reg = 0x809c, | |
1272 | .halt_check = BRANCH_HALT, | |
1273 | .clkr = { | |
1274 | .enable_reg = 0x809c, | |
1275 | .enable_mask = BIT(0), | |
1276 | .hw.init = &(struct clk_init_data) { | |
1277 | .name = "disp_cc_mdss_dptx3_aux_clk", | |
1278 | .parent_hws = (const struct clk_hw*[]) { | |
1279 | &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, | |
1280 | }, | |
1281 | .num_parents = 1, | |
1282 | .flags = CLK_SET_RATE_PARENT, | |
1283 | .ops = &clk_branch2_ops, | |
1284 | }, | |
1285 | }, | |
1286 | }; | |
1287 | ||
1288 | static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { | |
1289 | .halt_reg = 0x80a0, | |
1290 | .halt_check = BRANCH_HALT, | |
1291 | .clkr = { | |
1292 | .enable_reg = 0x80a0, | |
1293 | .enable_mask = BIT(0), | |
1294 | .hw.init = &(struct clk_init_data) { | |
1295 | .name = "disp_cc_mdss_dptx3_crypto_clk", | |
1296 | .parent_hws = (const struct clk_hw*[]) { | |
1297 | &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, | |
1298 | }, | |
1299 | .num_parents = 1, | |
1300 | .flags = CLK_SET_RATE_PARENT, | |
1301 | .ops = &clk_branch2_ops, | |
1302 | }, | |
1303 | }, | |
1304 | }; | |
1305 | ||
1306 | static struct clk_branch disp_cc_mdss_dptx3_link_clk = { | |
1307 | .halt_reg = 0x8094, | |
1308 | .halt_check = BRANCH_HALT, | |
1309 | .clkr = { | |
1310 | .enable_reg = 0x8094, | |
1311 | .enable_mask = BIT(0), | |
1312 | .hw.init = &(struct clk_init_data) { | |
1313 | .name = "disp_cc_mdss_dptx3_link_clk", | |
1314 | .parent_hws = (const struct clk_hw*[]) { | |
1315 | &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, | |
1316 | }, | |
1317 | .num_parents = 1, | |
1318 | .flags = CLK_SET_RATE_PARENT, | |
1319 | .ops = &clk_branch2_ops, | |
1320 | }, | |
1321 | }, | |
1322 | }; | |
1323 | ||
1324 | static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { | |
1325 | .halt_reg = 0x8098, | |
1326 | .halt_check = BRANCH_HALT, | |
1327 | .clkr = { | |
1328 | .enable_reg = 0x8098, | |
1329 | .enable_mask = BIT(0), | |
1330 | .hw.init = &(struct clk_init_data) { | |
1331 | .name = "disp_cc_mdss_dptx3_link_intf_clk", | |
1332 | .parent_hws = (const struct clk_hw*[]) { | |
1333 | &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, | |
1334 | }, | |
1335 | .num_parents = 1, | |
1336 | .flags = CLK_SET_RATE_PARENT, | |
1337 | .ops = &clk_branch2_ops, | |
1338 | }, | |
1339 | }, | |
1340 | }; | |
1341 | ||
1342 | static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { | |
1343 | .halt_reg = 0x8090, | |
1344 | .halt_check = BRANCH_HALT, | |
1345 | .clkr = { | |
1346 | .enable_reg = 0x8090, | |
1347 | .enable_mask = BIT(0), | |
1348 | .hw.init = &(struct clk_init_data) { | |
1349 | .name = "disp_cc_mdss_dptx3_pixel0_clk", | |
1350 | .parent_hws = (const struct clk_hw*[]) { | |
1351 | &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, | |
1352 | }, | |
1353 | .num_parents = 1, | |
1354 | .flags = CLK_SET_RATE_PARENT, | |
1355 | .ops = &clk_branch2_ops, | |
1356 | }, | |
1357 | }, | |
1358 | }; | |
1359 | ||
1360 | static struct clk_branch disp_cc_mdss_esc0_clk = { | |
1361 | .halt_reg = 0x8038, | |
1362 | .halt_check = BRANCH_HALT, | |
1363 | .clkr = { | |
1364 | .enable_reg = 0x8038, | |
1365 | .enable_mask = BIT(0), | |
1366 | .hw.init = &(struct clk_init_data) { | |
1367 | .name = "disp_cc_mdss_esc0_clk", | |
1368 | .parent_hws = (const struct clk_hw*[]) { | |
1369 | &disp_cc_mdss_esc0_clk_src.clkr.hw, | |
1370 | }, | |
1371 | .num_parents = 1, | |
1372 | .flags = CLK_SET_RATE_PARENT, | |
1373 | .ops = &clk_branch2_ops, | |
1374 | }, | |
1375 | }, | |
1376 | }; | |
1377 | ||
1378 | static struct clk_branch disp_cc_mdss_esc1_clk = { | |
1379 | .halt_reg = 0x803c, | |
1380 | .halt_check = BRANCH_HALT, | |
1381 | .clkr = { | |
1382 | .enable_reg = 0x803c, | |
1383 | .enable_mask = BIT(0), | |
1384 | .hw.init = &(struct clk_init_data) { | |
1385 | .name = "disp_cc_mdss_esc1_clk", | |
1386 | .parent_hws = (const struct clk_hw*[]) { | |
1387 | &disp_cc_mdss_esc1_clk_src.clkr.hw, | |
1388 | }, | |
1389 | .num_parents = 1, | |
1390 | .flags = CLK_SET_RATE_PARENT, | |
1391 | .ops = &clk_branch2_ops, | |
1392 | }, | |
1393 | }, | |
1394 | }; | |
1395 | ||
1396 | static struct clk_branch disp_cc_mdss_mdp1_clk = { | |
1397 | .halt_reg = 0xa004, | |
1398 | .halt_check = BRANCH_HALT, | |
1399 | .clkr = { | |
1400 | .enable_reg = 0xa004, | |
1401 | .enable_mask = BIT(0), | |
1402 | .hw.init = &(struct clk_init_data) { | |
1403 | .name = "disp_cc_mdss_mdp1_clk", | |
1404 | .parent_hws = (const struct clk_hw*[]) { | |
1405 | &disp_cc_mdss_mdp_clk_src.clkr.hw, | |
1406 | }, | |
1407 | .num_parents = 1, | |
1408 | .flags = CLK_SET_RATE_PARENT, | |
1409 | .ops = &clk_branch2_ops, | |
1410 | }, | |
1411 | }, | |
1412 | }; | |
1413 | ||
1414 | static struct clk_branch disp_cc_mdss_mdp_clk = { | |
1415 | .halt_reg = 0x800c, | |
1416 | .halt_check = BRANCH_HALT, | |
1417 | .clkr = { | |
1418 | .enable_reg = 0x800c, | |
1419 | .enable_mask = BIT(0), | |
1420 | .hw.init = &(struct clk_init_data) { | |
1421 | .name = "disp_cc_mdss_mdp_clk", | |
1422 | .parent_hws = (const struct clk_hw*[]) { | |
1423 | &disp_cc_mdss_mdp_clk_src.clkr.hw, | |
1424 | }, | |
1425 | .num_parents = 1, | |
1426 | .flags = CLK_SET_RATE_PARENT, | |
1427 | .ops = &clk_branch2_ops, | |
1428 | }, | |
1429 | }, | |
1430 | }; | |
1431 | ||
1432 | static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { | |
1433 | .halt_reg = 0xa010, | |
1434 | .halt_check = BRANCH_HALT, | |
1435 | .clkr = { | |
1436 | .enable_reg = 0xa010, | |
1437 | .enable_mask = BIT(0), | |
1438 | .hw.init = &(struct clk_init_data) { | |
1439 | .name = "disp_cc_mdss_mdp_lut1_clk", | |
1440 | .parent_hws = (const struct clk_hw*[]) { | |
1441 | &disp_cc_mdss_mdp_clk_src.clkr.hw, | |
1442 | }, | |
1443 | .num_parents = 1, | |
1444 | .flags = CLK_SET_RATE_PARENT, | |
1445 | .ops = &clk_branch2_ops, | |
1446 | }, | |
1447 | }, | |
1448 | }; | |
1449 | ||
1450 | static struct clk_branch disp_cc_mdss_mdp_lut_clk = { | |
1451 | .halt_reg = 0x8018, | |
1452 | .halt_check = BRANCH_HALT_VOTED, | |
1453 | .clkr = { | |
1454 | .enable_reg = 0x8018, | |
1455 | .enable_mask = BIT(0), | |
1456 | .hw.init = &(struct clk_init_data) { | |
1457 | .name = "disp_cc_mdss_mdp_lut_clk", | |
1458 | .parent_hws = (const struct clk_hw*[]) { | |
1459 | &disp_cc_mdss_mdp_clk_src.clkr.hw, | |
1460 | }, | |
1461 | .num_parents = 1, | |
1462 | .flags = CLK_SET_RATE_PARENT, | |
1463 | .ops = &clk_branch2_ops, | |
1464 | }, | |
1465 | }, | |
1466 | }; | |
1467 | ||
1468 | static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { | |
1469 | .halt_reg = 0xc004, | |
1470 | .halt_check = BRANCH_HALT_VOTED, | |
1471 | .clkr = { | |
1472 | .enable_reg = 0xc004, | |
1473 | .enable_mask = BIT(0), | |
1474 | .hw.init = &(struct clk_init_data) { | |
1475 | .name = "disp_cc_mdss_non_gdsc_ahb_clk", | |
1476 | .parent_hws = (const struct clk_hw*[]) { | |
1477 | &disp_cc_mdss_ahb_clk_src.clkr.hw, | |
1478 | }, | |
1479 | .num_parents = 1, | |
1480 | .flags = CLK_SET_RATE_PARENT, | |
1481 | .ops = &clk_branch2_ops, | |
1482 | }, | |
1483 | }, | |
1484 | }; | |
1485 | ||
1486 | static struct clk_branch disp_cc_mdss_pclk0_clk = { | |
1487 | .halt_reg = 0x8004, | |
1488 | .halt_check = BRANCH_HALT, | |
1489 | .clkr = { | |
1490 | .enable_reg = 0x8004, | |
1491 | .enable_mask = BIT(0), | |
1492 | .hw.init = &(struct clk_init_data) { | |
1493 | .name = "disp_cc_mdss_pclk0_clk", | |
1494 | .parent_hws = (const struct clk_hw*[]) { | |
1495 | &disp_cc_mdss_pclk0_clk_src.clkr.hw, | |
1496 | }, | |
1497 | .num_parents = 1, | |
1498 | .flags = CLK_SET_RATE_PARENT, | |
1499 | .ops = &clk_branch2_ops, | |
1500 | }, | |
1501 | }, | |
1502 | }; | |
1503 | ||
1504 | static struct clk_branch disp_cc_mdss_pclk1_clk = { | |
1505 | .halt_reg = 0x8008, | |
1506 | .halt_check = BRANCH_HALT, | |
1507 | .clkr = { | |
1508 | .enable_reg = 0x8008, | |
1509 | .enable_mask = BIT(0), | |
1510 | .hw.init = &(struct clk_init_data) { | |
1511 | .name = "disp_cc_mdss_pclk1_clk", | |
1512 | .parent_hws = (const struct clk_hw*[]) { | |
1513 | &disp_cc_mdss_pclk1_clk_src.clkr.hw, | |
1514 | }, | |
1515 | .num_parents = 1, | |
1516 | .flags = CLK_SET_RATE_PARENT, | |
1517 | .ops = &clk_branch2_ops, | |
1518 | }, | |
1519 | }, | |
1520 | }; | |
1521 | ||
1522 | static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { | |
1523 | .halt_reg = 0xc00c, | |
1524 | .halt_check = BRANCH_HALT, | |
1525 | .clkr = { | |
1526 | .enable_reg = 0xc00c, | |
1527 | .enable_mask = BIT(0), | |
1528 | .hw.init = &(struct clk_init_data) { | |
1529 | .name = "disp_cc_mdss_rscc_ahb_clk", | |
1530 | .parent_hws = (const struct clk_hw*[]) { | |
1531 | &disp_cc_mdss_ahb_clk_src.clkr.hw, | |
1532 | }, | |
1533 | .num_parents = 1, | |
1534 | .flags = CLK_SET_RATE_PARENT, | |
1535 | .ops = &clk_branch2_ops, | |
1536 | }, | |
1537 | }, | |
1538 | }; | |
1539 | ||
1540 | static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { | |
1541 | .halt_reg = 0xc008, | |
1542 | .halt_check = BRANCH_HALT, | |
1543 | .clkr = { | |
1544 | .enable_reg = 0xc008, | |
1545 | .enable_mask = BIT(0), | |
1546 | .hw.init = &(struct clk_init_data) { | |
1547 | .name = "disp_cc_mdss_rscc_vsync_clk", | |
1548 | .parent_hws = (const struct clk_hw*[]) { | |
1549 | &disp_cc_mdss_vsync_clk_src.clkr.hw, | |
1550 | }, | |
1551 | .num_parents = 1, | |
1552 | .flags = CLK_SET_RATE_PARENT, | |
1553 | .ops = &clk_branch2_ops, | |
1554 | }, | |
1555 | }, | |
1556 | }; | |
1557 | ||
1558 | static struct clk_branch disp_cc_mdss_vsync1_clk = { | |
1559 | .halt_reg = 0xa01c, | |
1560 | .halt_check = BRANCH_HALT, | |
1561 | .clkr = { | |
1562 | .enable_reg = 0xa01c, | |
1563 | .enable_mask = BIT(0), | |
1564 | .hw.init = &(struct clk_init_data) { | |
1565 | .name = "disp_cc_mdss_vsync1_clk", | |
1566 | .parent_hws = (const struct clk_hw*[]) { | |
1567 | &disp_cc_mdss_vsync_clk_src.clkr.hw, | |
1568 | }, | |
1569 | .num_parents = 1, | |
1570 | .flags = CLK_SET_RATE_PARENT, | |
1571 | .ops = &clk_branch2_ops, | |
1572 | }, | |
1573 | }, | |
1574 | }; | |
1575 | ||
1576 | static struct clk_branch disp_cc_mdss_vsync_clk = { | |
1577 | .halt_reg = 0x8024, | |
1578 | .halt_check = BRANCH_HALT, | |
1579 | .clkr = { | |
1580 | .enable_reg = 0x8024, | |
1581 | .enable_mask = BIT(0), | |
1582 | .hw.init = &(struct clk_init_data) { | |
1583 | .name = "disp_cc_mdss_vsync_clk", | |
1584 | .parent_hws = (const struct clk_hw*[]) { | |
1585 | &disp_cc_mdss_vsync_clk_src.clkr.hw, | |
1586 | }, | |
1587 | .num_parents = 1, | |
1588 | .flags = CLK_SET_RATE_PARENT, | |
1589 | .ops = &clk_branch2_ops, | |
1590 | }, | |
1591 | }, | |
1592 | }; | |
1593 | ||
1594 | static struct clk_branch disp_cc_sleep_clk = { | |
1595 | .halt_reg = 0xe074, | |
1596 | .halt_check = BRANCH_HALT, | |
1597 | .clkr = { | |
1598 | .enable_reg = 0xe074, | |
1599 | .enable_mask = BIT(0), | |
1600 | .hw.init = &(struct clk_init_data) { | |
1601 | .name = "disp_cc_sleep_clk", | |
1602 | .parent_hws = (const struct clk_hw*[]) { | |
1603 | &disp_cc_sleep_clk_src.clkr.hw, | |
1604 | }, | |
1605 | .num_parents = 1, | |
1606 | .flags = CLK_SET_RATE_PARENT, | |
1607 | .ops = &clk_branch2_ops, | |
1608 | }, | |
1609 | }, | |
1610 | }; | |
1611 | ||
1612 | static struct gdsc mdss_gdsc = { | |
1613 | .gdscr = 0x9000, | |
1614 | .pd = { | |
1615 | .name = "mdss_gdsc", | |
1616 | }, | |
1617 | .pwrsts = PWRSTS_OFF_ON, | |
1618 | .flags = HW_CTRL | RETAIN_FF_ENABLE, | |
1619 | }; | |
1620 | ||
1621 | static struct gdsc mdss_int2_gdsc = { | |
1622 | .gdscr = 0xb000, | |
1623 | .pd = { | |
1624 | .name = "mdss_int2_gdsc", | |
1625 | }, | |
1626 | .pwrsts = PWRSTS_OFF_ON, | |
1627 | .flags = HW_CTRL | RETAIN_FF_ENABLE, | |
1628 | }; | |
1629 | ||
1630 | static struct clk_regmap *disp_cc_sm8550_clocks[] = { | |
1631 | [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, | |
1632 | [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, | |
1633 | [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, | |
1634 | [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, | |
1635 | [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, | |
1636 | [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, | |
1637 | [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, | |
1638 | [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, | |
1639 | [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, | |
1640 | [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, | |
1641 | [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, | |
1642 | [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, | |
1643 | [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, | |
1644 | [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, | |
1645 | [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, | |
1646 | [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, | |
1647 | [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, | |
1648 | [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, | |
1649 | [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, | |
1650 | [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, | |
1651 | [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, | |
1652 | [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, | |
1653 | [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, | |
1654 | [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = | |
1655 | &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, | |
1656 | [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, | |
1657 | [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, | |
1658 | [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, | |
1659 | [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, | |
1660 | [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, | |
1661 | [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, | |
1662 | [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, | |
1663 | [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, | |
1664 | [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, | |
1665 | [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, | |
1666 | [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, | |
1667 | [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = | |
1668 | &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, | |
1669 | [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, | |
1670 | [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, | |
1671 | [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, | |
1672 | [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, | |
1673 | [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, | |
1674 | [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, | |
1675 | [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, | |
1676 | [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, | |
1677 | [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, | |
1678 | [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, | |
1679 | [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, | |
1680 | [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, | |
1681 | [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, | |
1682 | [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, | |
1683 | [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, | |
1684 | [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, | |
1685 | [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, | |
1686 | [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, | |
1687 | [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, | |
1688 | [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, | |
1689 | [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, | |
1690 | [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, | |
1691 | [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, | |
1692 | [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, | |
1693 | [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, | |
1694 | [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, | |
1695 | [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, | |
1696 | [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, | |
1697 | [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, | |
1698 | [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, | |
1699 | [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, | |
1700 | [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, | |
1701 | [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, | |
1702 | [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, | |
1703 | [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, | |
1704 | [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, | |
1705 | [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, | |
1706 | [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, | |
1707 | [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, | |
1708 | [DISP_CC_PLL0] = &disp_cc_pll0.clkr, | |
1709 | [DISP_CC_PLL1] = &disp_cc_pll1.clkr, | |
1710 | [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, | |
1711 | [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, | |
1712 | [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, | |
1713 | }; | |
1714 | ||
1715 | static const struct qcom_reset_map disp_cc_sm8550_resets[] = { | |
1716 | [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, | |
1717 | [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, | |
1718 | [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, | |
1719 | }; | |
1720 | ||
1721 | static struct gdsc *disp_cc_sm8550_gdscs[] = { | |
1722 | [MDSS_GDSC] = &mdss_gdsc, | |
1723 | [MDSS_INT2_GDSC] = &mdss_int2_gdsc, | |
1724 | }; | |
1725 | ||
1726 | static const struct regmap_config disp_cc_sm8550_regmap_config = { | |
1727 | .reg_bits = 32, | |
1728 | .reg_stride = 4, | |
1729 | .val_bits = 32, | |
1730 | .max_register = 0x11008, | |
1731 | .fast_io = true, | |
1732 | }; | |
1733 | ||
1734 | static struct qcom_cc_desc disp_cc_sm8550_desc = { | |
1735 | .config = &disp_cc_sm8550_regmap_config, | |
1736 | .clks = disp_cc_sm8550_clocks, | |
1737 | .num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks), | |
1738 | .resets = disp_cc_sm8550_resets, | |
1739 | .num_resets = ARRAY_SIZE(disp_cc_sm8550_resets), | |
1740 | .gdscs = disp_cc_sm8550_gdscs, | |
1741 | .num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs), | |
1742 | }; | |
1743 | ||
1744 | static const struct of_device_id disp_cc_sm8550_match_table[] = { | |
1745 | { .compatible = "qcom,sm8550-dispcc" }, | |
1746 | { } | |
1747 | }; | |
1748 | MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table); | |
1749 | ||
1750 | static int disp_cc_sm8550_probe(struct platform_device *pdev) | |
1751 | { | |
1752 | struct regmap *regmap; | |
1753 | int ret; | |
1754 | ||
1755 | ret = devm_pm_runtime_enable(&pdev->dev); | |
1756 | if (ret) | |
1757 | return ret; | |
1758 | ||
1759 | ret = pm_runtime_resume_and_get(&pdev->dev); | |
1760 | if (ret) | |
1761 | return ret; | |
1762 | ||
1763 | regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc); | |
1764 | if (IS_ERR(regmap)) | |
1765 | return PTR_ERR(regmap); | |
1766 | ||
1767 | clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); | |
1768 | clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); | |
1769 | ||
1770 | /* Enable clock gating for MDP clocks */ | |
1771 | regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); | |
1772 | ||
1773 | /* | |
1774 | * Keep clocks always enabled: | |
1775 | * disp_cc_xo_clk | |
1776 | */ | |
1777 | regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); | |
1778 | ||
1779 | ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); | |
1780 | ||
1781 | pm_runtime_put(&pdev->dev); | |
1782 | ||
1783 | return ret; | |
1784 | } | |
1785 | ||
1786 | static struct platform_driver disp_cc_sm8550_driver = { | |
1787 | .probe = disp_cc_sm8550_probe, | |
1788 | .driver = { | |
1789 | .name = "disp_cc-sm8550", | |
1790 | .of_match_table = disp_cc_sm8550_match_table, | |
1791 | }, | |
1792 | }; | |
1793 | ||
1794 | static int __init disp_cc_sm8550_init(void) | |
1795 | { | |
1796 | return platform_driver_register(&disp_cc_sm8550_driver); | |
1797 | } | |
1798 | subsys_initcall(disp_cc_sm8550_init); | |
1799 | ||
1800 | static void __exit disp_cc_sm8550_exit(void) | |
1801 | { | |
1802 | platform_driver_unregister(&disp_cc_sm8550_driver); | |
1803 | } | |
1804 | module_exit(disp_cc_sm8550_exit); | |
1805 | ||
1806 | MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver"); | |
1807 | MODULE_LICENSE("GPL"); |