[linux-2.6-block.git] / drivers / clk / qcom / common.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>

#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"

struct qcom_cc {
	struct qcom_reset_controller reset;
	struct clk_regmap **rclks;
	size_t num_rclks;
};

const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
	if (!f)
		return NULL;

	for (; f->freq; f++)
		if (rate <= f->freq)
			return f;

	/* Default to our fastest rate */
	return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);

const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
					    unsigned long rate)
{
	const struct freq_tbl *best = NULL;

	for ( ; f->freq; f++) {
		if (rate >= f->freq)
			best = f;
		else
			break;
	}

	return best;
}
EXPORT_SYMBOL_GPL(qcom_find_freq_floor);

int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (src == map[i].src)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);

struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	void __iomem *base;
	struct resource *res;
	struct device *dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return ERR_CAST(base);

	return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);

void
qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
{
	u32 val;
	u32 mask;

	/* De-assert reset to FSM */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);

	/* Program bias count and lock count */
	val = bias_count << PLL_BIAS_COUNT_SHIFT |
		lock_count << PLL_LOCK_COUNT_SHIFT;
	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	regmap_update_bits(map, reg, mask, val);

	/* Enable PLL FSM voting */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
}
EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);

static void qcom_cc_gdsc_unregister(void *data)
{
	gdsc_unregister(data);
}

/*
 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
 * clock to translate 'path' clk into 'name' clk and register the 'path'
 * clk as a fixed rate clock if it isn't present.
 */
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
				       const char *name, unsigned long rate,
				       bool add_factor)
{
	struct device_node *node = NULL;
	struct device_node *clocks_node;
	struct clk_fixed_factor *factor;
	struct clk_fixed_rate *fixed;
	struct clk_init_data init_data = { };
	int ret;

	clocks_node = of_find_node_by_path("/clocks");
	if (clocks_node) {
		node = of_get_child_by_name(clocks_node, path);
		of_node_put(clocks_node);
	}

	if (!node) {
		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
		if (!fixed)
			return -EINVAL;

		fixed->fixed_rate = rate;
		fixed->hw.init = &init_data;

		init_data.name = path;
		init_data.ops = &clk_fixed_rate_ops;

		ret = devm_clk_hw_register(dev, &fixed->hw);
		if (ret)
			return ret;
	}
	of_node_put(node);

	if (add_factor) {
		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
		if (!factor)
			return -EINVAL;

		factor->mult = factor->div = 1;
		factor->hw.init = &init_data;

		init_data.name = name;
		init_data.parent_names = &path;
		init_data.num_parents = 1;
		init_data.flags = 0;
		init_data.ops = &clk_fixed_factor_ops;

		ret = devm_clk_hw_register(dev, &factor->hw);
		if (ret)
			return ret;
	}

	return 0;
}

int qcom_cc_register_board_clk(struct device *dev, const char *path,
			       const char *name, unsigned long rate)
{
	bool add_factor = true;

	/*
	 * TODO: The RPM clock driver currently does not support the xo clock.
	 * When xo is added to the RPM clock driver, we should change this
	 * function to skip registration of xo factor clocks.
	 */

	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);

int qcom_cc_register_sleep_clk(struct device *dev)
{
	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
					   32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);

/* Drop 'protected-clocks' from the list of clocks to register */
static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
{
	struct device_node *np = dev->of_node;
	struct property *prop;
	const __be32 *p;
	u32 i;

	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
		if (i >= cc->num_rclks)
			continue;

		cc->rclks[i] = NULL;
	}
}

static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
					 void *data)
{
	struct qcom_cc *cc = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= cc->num_rclks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
}

int qcom_cc_really_probe(struct platform_device *pdev,
			 const struct qcom_cc_desc *desc, struct regmap *regmap)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct qcom_reset_controller *reset;
	struct qcom_cc *cc;
	struct gdsc_desc *scd;
	size_t num_clks = desc->num_clks;
	struct clk_regmap **rclks = desc->clks;

	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
	if (!cc)
		return -ENOMEM;

	reset = &cc->reset;
	reset->rcdev.of_node = dev->of_node;
	reset->rcdev.ops = &qcom_reset_ops;
	reset->rcdev.owner = dev->driver->owner;
	reset->rcdev.nr_resets = desc->num_resets;
	reset->regmap = regmap;
	reset->reset_map = desc->resets;

	ret = devm_reset_controller_register(dev, &reset->rcdev);
	if (ret)
		return ret;

	if (desc->gdscs && desc->num_gdscs) {
		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
		if (!scd)
			return -ENOMEM;
		scd->dev = dev;
		scd->scs = desc->gdscs;
		scd->num = desc->num_gdscs;
		ret = gdsc_register(scd, &reset->rcdev, regmap);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
					       scd);
		if (ret)
			return ret;
	}

	cc->rclks = rclks;
	cc->num_rclks = num_clks;

	qcom_cc_drop_protected(dev, cc);

	for (i = 0; i < num_clks; i++) {
		if (!rclks[i])
			continue;

		ret = devm_clk_register_regmap(dev, rclks[i]);
		if (ret)
			return ret;
	}

	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
	if (ret)
		return ret;

	return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;

	regmap = qcom_cc_map(pdev, desc);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
f9419783	1	// SPDX-License-Identifier: GPL-2.0
49fc825f SB	2	/*
49fc825f SB	3	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
49fc825f SB	4	*/
	5
	6	#include <linux/export.h>
169f05e8	7	#include <linux/module.h>
49fc825f SB	8	#include <linux/regmap.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/clk-provider.h>
	11	#include <linux/reset-controller.h>
ee15faff	12	#include <linux/of.h>
49fc825f SB	13
49fc825f SB	14	#include "common.h"
50c6a503	15	#include "clk-rcg.h"
49fc825f SB	16	#include "clk-regmap.h"
49fc825f SB	17	#include "reset.h"
5e5cc241	18	#include "gdsc.h"
49fc825f SB	19
	20	struct qcom_cc {
	21	struct qcom_reset_controller reset;
120c1552 SB	22	struct clk_regmap **rclks;
120c1552 SB	23	size_t num_rclks;
49fc825f SB	24	};
49fc825f SB	25
50c6a503 SB	26	const
	27	struct freq_tbl qcom_find_freq(const struct freq_tbl f, unsigned long rate)
	28	{
	29	if (!f)
	30	return NULL;
	31
	32	for (; f->freq; f++)
	33	if (rate <= f->freq)
	34	return f;
	35
	36	/* Default to our fastest rate */
	37	return f - 1;
	38	}
	39	EXPORT_SYMBOL_GPL(qcom_find_freq);
	40
081ba802 RN	41	const struct freq_tbl qcom_find_freq_floor(const struct freq_tbl f,
	42	unsigned long rate)
	43	{
	44	const struct freq_tbl *best = NULL;
	45
	46	for ( ; f->freq; f++) {
	47	if (rate >= f->freq)
	48	best = f;
	49	else
	50	break;
	51	}
	52
	53	return best;
	54	}
	55	EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
	56
293d2e97 GD	57	int qcom_find_src_index(struct clk_hw hw, const struct parent_map map, u8 src)
293d2e97 GD	58	{
497295af	59	int i, num_parents = clk_hw_get_num_parents(hw);
293d2e97 GD	60
	61	for (i = 0; i < num_parents; i++)
	62	if (src == map[i].src)
	63	return i;
	64
	65	return -ENOENT;
	66	}
	67	EXPORT_SYMBOL_GPL(qcom_find_src_index);
	68
5b6b7490 SB	69	struct regmap *
5b6b7490 SB	70	qcom_cc_map(struct platform_device pdev, const struct qcom_cc_desc desc)
49fc825f SB	71	{
	72	void __iomem *base;
	73	struct resource *res;
5b6b7490 SB	74	struct device *dev = &pdev->dev;
	75
	76	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	77	base = devm_ioremap_resource(dev, res);
	78	if (IS_ERR(base))
	79	return ERR_CAST(base);
	80
	81	return devm_regmap_init_mmio(dev, base, desc->config);
	82	}
	83	EXPORT_SYMBOL_GPL(qcom_cc_map);
	84
400d9fda RN	85	void
	86	qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
	87	{
	88	u32 val;
	89	u32 mask;
	90
	91	/* De-assert reset to FSM */
	92	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
	93
	94	/* Program bias count and lock count */
	95	val = bias_count << PLL_BIAS_COUNT_SHIFT \|
	96	lock_count << PLL_LOCK_COUNT_SHIFT;
	97	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	98	mask \|= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	99	regmap_update_bits(map, reg, mask, val);
	100
	101	/* Enable PLL FSM voting */
	102	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
	103	}
	104	EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
	105
94c51f40 SB	106	static void qcom_cc_gdsc_unregister(void *data)
	107	{
	108	gdsc_unregister(data);
	109	}
	110
ee15faff SB	111	/*
ee15faff SB	112	* Backwards compatibility with old DTs. Register a pass-through factor 1/1
ad61dd30	113	* clock to translate 'path' clk into 'name' clk and register the 'path'
ee15faff SB	114	* clk as a fixed rate clock if it isn't present.
	115	*/
	116	static int _qcom_cc_register_board_clk(struct device dev, const char path,
	117	const char *name, unsigned long rate,
	118	bool add_factor)
	119	{
	120	struct device_node *node = NULL;
	121	struct device_node *clocks_node;
	122	struct clk_fixed_factor *factor;
	123	struct clk_fixed_rate *fixed;
ee15faff	124	struct clk_init_data init_data = { };
120c1552	125	int ret;
ee15faff SB	126
ee15faff SB	127	clocks_node = of_find_node_by_path("/clocks");
43a51019 JH	128	if (clocks_node) {
	129	node = of_get_child_by_name(clocks_node, path);
	130	of_node_put(clocks_node);
	131	}
ee15faff SB	132
	133	if (!node) {
	134	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
	135	if (!fixed)
	136	return -EINVAL;
	137
	138	fixed->fixed_rate = rate;
	139	fixed->hw.init = &init_data;
	140
	141	init_data.name = path;
ee15faff SB	142	init_data.ops = &clk_fixed_rate_ops;
ee15faff SB	143
120c1552 SB	144	ret = devm_clk_hw_register(dev, &fixed->hw);
	145	if (ret)
	146	return ret;
ee15faff SB	147	}
	148	of_node_put(node);
	149
	150	if (add_factor) {
	151	factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
	152	if (!factor)
	153	return -EINVAL;
	154
	155	factor->mult = factor->div = 1;
	156	factor->hw.init = &init_data;
	157
	158	init_data.name = name;
	159	init_data.parent_names = &path;
	160	init_data.num_parents = 1;
	161	init_data.flags = 0;
	162	init_data.ops = &clk_fixed_factor_ops;
	163
120c1552 SB	164	ret = devm_clk_hw_register(dev, &factor->hw);
	165	if (ret)
	166	return ret;
ee15faff SB	167	}
	168
	169	return 0;
	170	}
	171
	172	int qcom_cc_register_board_clk(struct device dev, const char path,
	173	const char *name, unsigned long rate)
	174	{
	175	bool add_factor = true;
54823af9 GD	176
	177	/*
	178	* TODO: The RPM clock driver currently does not support the xo clock.
	179	* When xo is added to the RPM clock driver, we should change this
	180	* function to skip registration of xo factor clocks.
	181	*/
ee15faff SB	182
	183	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
	184	}
	185	EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
	186
	187	int qcom_cc_register_sleep_clk(struct device *dev)
	188	{
	189	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
	190	32768, true);
	191	}
	192	EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
	193
b181b3b8 SB	194	/* Drop 'protected-clocks' from the list of clocks to register */
	195	static void qcom_cc_drop_protected(struct device dev, struct qcom_cc cc)
	196	{
	197	struct device_node *np = dev->of_node;
	198	struct property *prop;
	199	const __be32 *p;
	200	u32 i;
	201
	202	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
	203	if (i >= cc->num_rclks)
	204	continue;
	205
	206	cc->rclks[i] = NULL;
	207	}
	208	}
	209
120c1552 SB	210	static struct clk_hw qcom_cc_clk_hw_get(struct of_phandle_args clkspec,
	211	void *data)
	212	{
	213	struct qcom_cc *cc = data;
	214	unsigned int idx = clkspec->args[0];
	215
	216	if (idx >= cc->num_rclks) {
	217	pr_err("%s: invalid index %u\n", __func__, idx);
	218	return ERR_PTR(-EINVAL);
	219	}
	220
	221	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
	222	}
	223
5b6b7490 SB	224	int qcom_cc_really_probe(struct platform_device *pdev,
	225	const struct qcom_cc_desc desc, struct regmap regmap)
	226	{
49fc825f SB	227	int i, ret;
49fc825f SB	228	struct device *dev = &pdev->dev;
49fc825f SB	229	struct qcom_reset_controller *reset;
49fc825f SB	230	struct qcom_cc *cc;
c2c7f0a4	231	struct gdsc_desc *scd;
49fc825f SB	232	size_t num_clks = desc->num_clks;
	233	struct clk_regmap **rclks = desc->clks;
	234
120c1552	235	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
49fc825f SB	236	if (!cc)
	237	return -ENOMEM;
	238
49fc825f SB	239	reset = &cc->reset;
	240	reset->rcdev.of_node = dev->of_node;
	241	reset->rcdev.ops = &qcom_reset_ops;
	242	reset->rcdev.owner = dev->driver->owner;
	243	reset->rcdev.nr_resets = desc->num_resets;
	244	reset->regmap = regmap;
	245	reset->reset_map = desc->resets;
49fc825f	246
b87206f8	247	ret = devm_reset_controller_register(dev, &reset->rcdev);
66f5ce25 SM	248	if (ret)
66f5ce25 SM	249	return ret;
49fc825f	250
5e5cc241	251	if (desc->gdscs && desc->num_gdscs) {
c2c7f0a4 RN	252	scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
	253	if (!scd)
	254	return -ENOMEM;
	255	scd->dev = dev;
	256	scd->scs = desc->gdscs;
	257	scd->num = desc->num_gdscs;
	258	ret = gdsc_register(scd, &reset->rcdev, regmap);
	259	if (ret)
	260	return ret;
	261	ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
	262	scd);
5e5cc241	263	if (ret)
94c51f40	264	return ret;
5e5cc241 RN	265	}
5e5cc241 RN	266
31543ebb RN	267	cc->rclks = rclks;
	268	cc->num_rclks = num_clks;
	269
b181b3b8 SB	270	qcom_cc_drop_protected(dev, cc);
b181b3b8 SB	271
31543ebb RN	272	for (i = 0; i < num_clks; i++) {
	273	if (!rclks[i])
	274	continue;
	275
	276	ret = devm_clk_register_regmap(dev, rclks[i]);
	277	if (ret)
	278	return ret;
	279	}
	280
	281	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
	282	if (ret)
	283	return ret;
	284
c2c7f0a4	285	return 0;
49fc825f	286	}
5b6b7490 SB	287	EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
	288
	289	int qcom_cc_probe(struct platform_device pdev, const struct qcom_cc_desc desc)
	290	{
	291	struct regmap *regmap;
	292
	293	regmap = qcom_cc_map(pdev, desc);
	294	if (IS_ERR(regmap))
	295	return PTR_ERR(regmap);
	296
	297	return qcom_cc_really_probe(pdev, desc, regmap);
	298	}
49fc825f SB	299	EXPORT_SYMBOL_GPL(qcom_cc_probe);
49fc825f SB	300
169f05e8	301	MODULE_LICENSE("GPL v2");