[linux-2.6-block.git] / drivers / clk / qcom / common.c

/*
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>

#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"

struct qcom_cc {
	struct qcom_reset_controller reset;
	struct clk_regmap **rclks;
	size_t num_rclks;
};

const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
	if (!f)
		return NULL;

	for (; f->freq; f++)
		if (rate <= f->freq)
			return f;

	/* Default to our fastest rate */
	return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);

int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (src == map[i].src)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);

struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	void __iomem *base;
	struct resource *res;
	struct device *dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return ERR_CAST(base);

	return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);

void
qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
{
	u32 val;
	u32 mask;

	/* De-assert reset to FSM */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);

	/* Program bias count and lock count */
	val = bias_count << PLL_BIAS_COUNT_SHIFT |
		lock_count << PLL_LOCK_COUNT_SHIFT;
	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	regmap_update_bits(map, reg, mask, val);

	/* Enable PLL FSM voting */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
}
EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);

static void qcom_cc_del_clk_provider(void *data)
{
	of_clk_del_provider(data);
}

static void qcom_cc_reset_unregister(void *data)
{
	reset_controller_unregister(data);
}

static void qcom_cc_gdsc_unregister(void *data)
{
	gdsc_unregister(data);
}

/*
 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
 * clock to translate 'path' clk into 'name' clk and regsiter the 'path'
 * clk as a fixed rate clock if it isn't present.
 */
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
				       const char *name, unsigned long rate,
				       bool add_factor)
{
	struct device_node *node = NULL;
	struct device_node *clocks_node;
	struct clk_fixed_factor *factor;
	struct clk_fixed_rate *fixed;
	struct clk_init_data init_data = { };
	int ret;

	clocks_node = of_find_node_by_path("/clocks");
	if (clocks_node)
		node = of_find_node_by_name(clocks_node, path);
	of_node_put(clocks_node);

	if (!node) {
		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
		if (!fixed)
			return -EINVAL;

		fixed->fixed_rate = rate;
		fixed->hw.init = &init_data;

		init_data.name = path;
		init_data.ops = &clk_fixed_rate_ops;

		ret = devm_clk_hw_register(dev, &fixed->hw);
		if (ret)
			return ret;
	}
	of_node_put(node);

	if (add_factor) {
		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
		if (!factor)
			return -EINVAL;

		factor->mult = factor->div = 1;
		factor->hw.init = &init_data;

		init_data.name = name;
		init_data.parent_names = &path;
		init_data.num_parents = 1;
		init_data.flags = 0;
		init_data.ops = &clk_fixed_factor_ops;

		ret = devm_clk_hw_register(dev, &factor->hw);
		if (ret)
			return ret;
	}

	return 0;
}

int qcom_cc_register_board_clk(struct device *dev, const char *path,
			       const char *name, unsigned long rate)
{
	bool add_factor = true;

	/*
	 * TODO: The RPM clock driver currently does not support the xo clock.
	 * When xo is added to the RPM clock driver, we should change this
	 * function to skip registration of xo factor clocks.
	 */

	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);

int qcom_cc_register_sleep_clk(struct device *dev)
{
	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
					   32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);

static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
					 void *data)
{
	struct qcom_cc *cc = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= cc->num_rclks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
}

int qcom_cc_really_probe(struct platform_device *pdev,
			 const struct qcom_cc_desc *desc, struct regmap *regmap)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct qcom_reset_controller *reset;
	struct qcom_cc *cc;
	struct gdsc_desc *scd;
	size_t num_clks = desc->num_clks;
	struct clk_regmap **rclks = desc->clks;

	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
	if (!cc)
		return -ENOMEM;

	cc->rclks = rclks;
	cc->num_rclks = num_clks;

	for (i = 0; i < num_clks; i++) {
		if (!rclks[i])
			continue;

		ret = devm_clk_register_regmap(dev, rclks[i]);
		if (ret)
			return ret;
	}

	ret = of_clk_add_hw_provider(dev->of_node, qcom_cc_clk_hw_get, cc);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, qcom_cc_del_clk_provider,
				       pdev->dev.of_node);

	if (ret)
		return ret;

	reset = &cc->reset;
	reset->rcdev.of_node = dev->of_node;
	reset->rcdev.ops = &qcom_reset_ops;
	reset->rcdev.owner = dev->driver->owner;
	reset->rcdev.nr_resets = desc->num_resets;
	reset->regmap = regmap;
	reset->reset_map = desc->resets;

	ret = reset_controller_register(&reset->rcdev);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, qcom_cc_reset_unregister,
				       &reset->rcdev);

	if (ret)
		return ret;

	if (desc->gdscs && desc->num_gdscs) {
		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
		if (!scd)
			return -ENOMEM;
		scd->dev = dev;
		scd->scs = desc->gdscs;
		scd->num = desc->num_gdscs;
		ret = gdsc_register(scd, &reset->rcdev, regmap);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
					       scd);
		if (ret)
			return ret;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;

	regmap = qcom_cc_map(pdev, desc);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
49fc825f SB	1	/*
	2	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/export.h>
169f05e8	15	#include <linux/module.h>
49fc825f SB	16	#include <linux/regmap.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/reset-controller.h>
ee15faff	20	#include <linux/of.h>
49fc825f SB	21
49fc825f SB	22	#include "common.h"
50c6a503	23	#include "clk-rcg.h"
49fc825f SB	24	#include "clk-regmap.h"
49fc825f SB	25	#include "reset.h"
5e5cc241	26	#include "gdsc.h"
49fc825f SB	27
	28	struct qcom_cc {
	29	struct qcom_reset_controller reset;
120c1552 SB	30	struct clk_regmap **rclks;
120c1552 SB	31	size_t num_rclks;
49fc825f SB	32	};
49fc825f SB	33
50c6a503 SB	34	const
	35	struct freq_tbl qcom_find_freq(const struct freq_tbl f, unsigned long rate)
	36	{
	37	if (!f)
	38	return NULL;
	39
	40	for (; f->freq; f++)
	41	if (rate <= f->freq)
	42	return f;
	43
	44	/* Default to our fastest rate */
	45	return f - 1;
	46	}
	47	EXPORT_SYMBOL_GPL(qcom_find_freq);
	48
293d2e97 GD	49	int qcom_find_src_index(struct clk_hw hw, const struct parent_map map, u8 src)
293d2e97 GD	50	{
497295af	51	int i, num_parents = clk_hw_get_num_parents(hw);
293d2e97 GD	52
	53	for (i = 0; i < num_parents; i++)
	54	if (src == map[i].src)
	55	return i;
	56
	57	return -ENOENT;
	58	}
	59	EXPORT_SYMBOL_GPL(qcom_find_src_index);
	60
5b6b7490 SB	61	struct regmap *
5b6b7490 SB	62	qcom_cc_map(struct platform_device pdev, const struct qcom_cc_desc desc)
49fc825f SB	63	{
	64	void __iomem *base;
	65	struct resource *res;
5b6b7490 SB	66	struct device *dev = &pdev->dev;
	67
	68	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	69	base = devm_ioremap_resource(dev, res);
	70	if (IS_ERR(base))
	71	return ERR_CAST(base);
	72
	73	return devm_regmap_init_mmio(dev, base, desc->config);
	74	}
	75	EXPORT_SYMBOL_GPL(qcom_cc_map);
	76
400d9fda RN	77	void
	78	qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
	79	{
	80	u32 val;
	81	u32 mask;
	82
	83	/* De-assert reset to FSM */
	84	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
	85
	86	/* Program bias count and lock count */
	87	val = bias_count << PLL_BIAS_COUNT_SHIFT \|
	88	lock_count << PLL_LOCK_COUNT_SHIFT;
	89	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	90	mask \|= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	91	regmap_update_bits(map, reg, mask, val);
	92
	93	/* Enable PLL FSM voting */
	94	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
	95	}
	96	EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
	97
94c51f40 SB	98	static void qcom_cc_del_clk_provider(void *data)
	99	{
	100	of_clk_del_provider(data);
	101	}
	102
	103	static void qcom_cc_reset_unregister(void *data)
	104	{
	105	reset_controller_unregister(data);
	106	}
	107
	108	static void qcom_cc_gdsc_unregister(void *data)
	109	{
	110	gdsc_unregister(data);
	111	}
	112
ee15faff SB	113	/*
	114	* Backwards compatibility with old DTs. Register a pass-through factor 1/1
	115	* clock to translate 'path' clk into 'name' clk and regsiter the 'path'
	116	* clk as a fixed rate clock if it isn't present.
	117	*/
	118	static int _qcom_cc_register_board_clk(struct device dev, const char path,
	119	const char *name, unsigned long rate,
	120	bool add_factor)
	121	{
	122	struct device_node *node = NULL;
	123	struct device_node *clocks_node;
	124	struct clk_fixed_factor *factor;
	125	struct clk_fixed_rate *fixed;
ee15faff	126	struct clk_init_data init_data = { };
120c1552	127	int ret;
ee15faff SB	128
	129	clocks_node = of_find_node_by_path("/clocks");
	130	if (clocks_node)
	131	node = of_find_node_by_name(clocks_node, path);
	132	of_node_put(clocks_node);
	133
	134	if (!node) {
	135	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
	136	if (!fixed)
	137	return -EINVAL;
	138
	139	fixed->fixed_rate = rate;
	140	fixed->hw.init = &init_data;
	141
	142	init_data.name = path;
ee15faff SB	143	init_data.ops = &clk_fixed_rate_ops;
ee15faff SB	144
120c1552 SB	145	ret = devm_clk_hw_register(dev, &fixed->hw);
	146	if (ret)
	147	return ret;
ee15faff SB	148	}
	149	of_node_put(node);
	150
	151	if (add_factor) {
	152	factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
	153	if (!factor)
	154	return -EINVAL;
	155
	156	factor->mult = factor->div = 1;
	157	factor->hw.init = &init_data;
	158
	159	init_data.name = name;
	160	init_data.parent_names = &path;
	161	init_data.num_parents = 1;
	162	init_data.flags = 0;
	163	init_data.ops = &clk_fixed_factor_ops;
	164
120c1552 SB	165	ret = devm_clk_hw_register(dev, &factor->hw);
	166	if (ret)
	167	return ret;
ee15faff SB	168	}
	169
	170	return 0;
	171	}
	172
	173	int qcom_cc_register_board_clk(struct device dev, const char path,
	174	const char *name, unsigned long rate)
	175	{
	176	bool add_factor = true;
54823af9 GD	177
	178	/*
	179	* TODO: The RPM clock driver currently does not support the xo clock.
	180	* When xo is added to the RPM clock driver, we should change this
	181	* function to skip registration of xo factor clocks.
	182	*/
ee15faff SB	183
	184	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
	185	}
	186	EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
	187
	188	int qcom_cc_register_sleep_clk(struct device *dev)
	189	{
	190	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
	191	32768, true);
	192	}
	193	EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
	194
120c1552 SB	195	static struct clk_hw qcom_cc_clk_hw_get(struct of_phandle_args clkspec,
	196	void *data)
	197	{
	198	struct qcom_cc *cc = data;
	199	unsigned int idx = clkspec->args[0];
	200
	201	if (idx >= cc->num_rclks) {
	202	pr_err("%s: invalid index %u\n", __func__, idx);
	203	return ERR_PTR(-EINVAL);
	204	}
	205
	206	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
	207	}
	208
5b6b7490 SB	209	int qcom_cc_really_probe(struct platform_device *pdev,
	210	const struct qcom_cc_desc desc, struct regmap regmap)
	211	{
49fc825f SB	212	int i, ret;
49fc825f SB	213	struct device *dev = &pdev->dev;
49fc825f SB	214	struct qcom_reset_controller *reset;
49fc825f SB	215	struct qcom_cc *cc;
c2c7f0a4	216	struct gdsc_desc *scd;
49fc825f SB	217	size_t num_clks = desc->num_clks;
	218	struct clk_regmap **rclks = desc->clks;
	219
120c1552	220	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
49fc825f SB	221	if (!cc)
	222	return -ENOMEM;
	223
120c1552 SB	224	cc->rclks = rclks;
120c1552 SB	225	cc->num_rclks = num_clks;
49fc825f SB	226
49fc825f SB	227	for (i = 0; i < num_clks; i++) {
120c1552	228	if (!rclks[i])
49fc825f	229	continue;
120c1552 SB	230
	231	ret = devm_clk_register_regmap(dev, rclks[i]);
	232	if (ret)
	233	return ret;
49fc825f SB	234	}
49fc825f SB	235
120c1552	236	ret = of_clk_add_hw_provider(dev->of_node, qcom_cc_clk_hw_get, cc);
49fc825f SB	237	if (ret)
	238	return ret;
	239
66f5ce25 SM	240	ret = devm_add_action_or_reset(dev, qcom_cc_del_clk_provider,
	241	pdev->dev.of_node);
	242
	243	if (ret)
	244	return ret;
94c51f40	245
49fc825f SB	246	reset = &cc->reset;
	247	reset->rcdev.of_node = dev->of_node;
	248	reset->rcdev.ops = &qcom_reset_ops;
	249	reset->rcdev.owner = dev->driver->owner;
	250	reset->rcdev.nr_resets = desc->num_resets;
	251	reset->regmap = regmap;
	252	reset->reset_map = desc->resets;
49fc825f SB	253
	254	ret = reset_controller_register(&reset->rcdev);
	255	if (ret)
94c51f40 SB	256	return ret;
94c51f40 SB	257
66f5ce25 SM	258	ret = devm_add_action_or_reset(dev, qcom_cc_reset_unregister,
	259	&reset->rcdev);
	260
	261	if (ret)
	262	return ret;
49fc825f	263
5e5cc241	264	if (desc->gdscs && desc->num_gdscs) {
c2c7f0a4 RN	265	scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
	266	if (!scd)
	267	return -ENOMEM;
	268	scd->dev = dev;
	269	scd->scs = desc->gdscs;
	270	scd->num = desc->num_gdscs;
	271	ret = gdsc_register(scd, &reset->rcdev, regmap);
	272	if (ret)
	273	return ret;
	274	ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
	275	scd);
5e5cc241	276	if (ret)
94c51f40	277	return ret;
5e5cc241 RN	278	}
5e5cc241 RN	279
c2c7f0a4	280	return 0;
49fc825f	281	}
5b6b7490 SB	282	EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
	283
	284	int qcom_cc_probe(struct platform_device pdev, const struct qcom_cc_desc desc)
	285	{
	286	struct regmap *regmap;
	287
	288	regmap = qcom_cc_map(pdev, desc);
	289	if (IS_ERR(regmap))
	290	return PTR_ERR(regmap);
	291
	292	return qcom_cc_really_probe(pdev, desc, regmap);
	293	}
49fc825f SB	294	EXPORT_SYMBOL_GPL(qcom_cc_probe);
49fc825f SB	295
169f05e8	296	MODULE_LICENSE("GPL v2");