[linux-2.6-block.git] / drivers / clk / qcom / common.c

/*
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>

#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"

struct qcom_cc {
	struct qcom_reset_controller reset;
	struct clk_regmap **rclks;
	size_t num_rclks;
};

const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
	if (!f)
		return NULL;

	for (; f->freq; f++)
		if (rate <= f->freq)
			return f;

	/* Default to our fastest rate */
	return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);

const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
					    unsigned long rate)
{
	const struct freq_tbl *best = NULL;

	for ( ; f->freq; f++) {
		if (rate >= f->freq)
			best = f;
		else
			break;
	}

	return best;
}
EXPORT_SYMBOL_GPL(qcom_find_freq_floor);

int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (src == map[i].src)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);

struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	void __iomem *base;
	struct resource *res;
	struct device *dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return ERR_CAST(base);

	return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);

void
qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
{
	u32 val;
	u32 mask;

	/* De-assert reset to FSM */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);

	/* Program bias count and lock count */
	val = bias_count << PLL_BIAS_COUNT_SHIFT |
		lock_count << PLL_LOCK_COUNT_SHIFT;
	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	regmap_update_bits(map, reg, mask, val);

	/* Enable PLL FSM voting */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
}
EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);

static void qcom_cc_gdsc_unregister(void *data)
{
	gdsc_unregister(data);
}

/*
 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
 * clock to translate 'path' clk into 'name' clk and register the 'path'
 * clk as a fixed rate clock if it isn't present.
 */
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
				       const char *name, unsigned long rate,
				       bool add_factor)
{
	struct device_node *node = NULL;
	struct device_node *clocks_node;
	struct clk_fixed_factor *factor;
	struct clk_fixed_rate *fixed;
	struct clk_init_data init_data = { };
	int ret;

	clocks_node = of_find_node_by_path("/clocks");
	if (clocks_node) {
		node = of_get_child_by_name(clocks_node, path);
		of_node_put(clocks_node);
	}

	if (!node) {
		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
		if (!fixed)
			return -EINVAL;

		fixed->fixed_rate = rate;
		fixed->hw.init = &init_data;

		init_data.name = path;
		init_data.ops = &clk_fixed_rate_ops;

		ret = devm_clk_hw_register(dev, &fixed->hw);
		if (ret)
			return ret;
	}
	of_node_put(node);

	if (add_factor) {
		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
		if (!factor)
			return -EINVAL;

		factor->mult = factor->div = 1;
		factor->hw.init = &init_data;

		init_data.name = name;
		init_data.parent_names = &path;
		init_data.num_parents = 1;
		init_data.flags = 0;
		init_data.ops = &clk_fixed_factor_ops;

		ret = devm_clk_hw_register(dev, &factor->hw);
		if (ret)
			return ret;
	}

	return 0;
}

int qcom_cc_register_board_clk(struct device *dev, const char *path,
			       const char *name, unsigned long rate)
{
	bool add_factor = true;

	/*
	 * TODO: The RPM clock driver currently does not support the xo clock.
	 * When xo is added to the RPM clock driver, we should change this
	 * function to skip registration of xo factor clocks.
	 */

	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);

int qcom_cc_register_sleep_clk(struct device *dev)
{
	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
					   32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);

static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
					 void *data)
{
	struct qcom_cc *cc = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= cc->num_rclks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
}

int qcom_cc_really_probe(struct platform_device *pdev,
			 const struct qcom_cc_desc *desc, struct regmap *regmap)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct qcom_reset_controller *reset;
	struct qcom_cc *cc;
	struct gdsc_desc *scd;
	size_t num_clks = desc->num_clks;
	struct clk_regmap **rclks = desc->clks;

	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
	if (!cc)
		return -ENOMEM;

	cc->rclks = rclks;
	cc->num_rclks = num_clks;

	for (i = 0; i < num_clks; i++) {
		if (!rclks[i])
			continue;

		ret = devm_clk_register_regmap(dev, rclks[i]);
		if (ret)
			return ret;
	}

	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
	if (ret)
		return ret;

	reset = &cc->reset;
	reset->rcdev.of_node = dev->of_node;
	reset->rcdev.ops = &qcom_reset_ops;
	reset->rcdev.owner = dev->driver->owner;
	reset->rcdev.nr_resets = desc->num_resets;
	reset->regmap = regmap;
	reset->reset_map = desc->resets;

	ret = devm_reset_controller_register(dev, &reset->rcdev);
	if (ret)
		return ret;

	if (desc->gdscs && desc->num_gdscs) {
		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
		if (!scd)
			return -ENOMEM;
		scd->dev = dev;
		scd->scs = desc->gdscs;
		scd->num = desc->num_gdscs;
		ret = gdsc_register(scd, &reset->rcdev, regmap);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
					       scd);
		if (ret)
			return ret;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;

	regmap = qcom_cc_map(pdev, desc);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
49fc825f SB	1	/*
	2	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/export.h>
169f05e8	15	#include <linux/module.h>
49fc825f SB	16	#include <linux/regmap.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/reset-controller.h>
ee15faff	20	#include <linux/of.h>
49fc825f SB	21
49fc825f SB	22	#include "common.h"
50c6a503	23	#include "clk-rcg.h"
49fc825f SB	24	#include "clk-regmap.h"
49fc825f SB	25	#include "reset.h"
5e5cc241	26	#include "gdsc.h"
49fc825f SB	27
	28	struct qcom_cc {
	29	struct qcom_reset_controller reset;
120c1552 SB	30	struct clk_regmap **rclks;
120c1552 SB	31	size_t num_rclks;
49fc825f SB	32	};
49fc825f SB	33
50c6a503 SB	34	const
	35	struct freq_tbl qcom_find_freq(const struct freq_tbl f, unsigned long rate)
	36	{
	37	if (!f)
	38	return NULL;
	39
	40	for (; f->freq; f++)
	41	if (rate <= f->freq)
	42	return f;
	43
	44	/* Default to our fastest rate */
	45	return f - 1;
	46	}
	47	EXPORT_SYMBOL_GPL(qcom_find_freq);
	48
081ba802 RN	49	const struct freq_tbl qcom_find_freq_floor(const struct freq_tbl f,
	50	unsigned long rate)
	51	{
	52	const struct freq_tbl *best = NULL;
	53
	54	for ( ; f->freq; f++) {
	55	if (rate >= f->freq)
	56	best = f;
	57	else
	58	break;
	59	}
	60
	61	return best;
	62	}
	63	EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
	64
293d2e97 GD	65	int qcom_find_src_index(struct clk_hw hw, const struct parent_map map, u8 src)
293d2e97 GD	66	{
497295af	67	int i, num_parents = clk_hw_get_num_parents(hw);
293d2e97 GD	68
	69	for (i = 0; i < num_parents; i++)
	70	if (src == map[i].src)
	71	return i;
	72
	73	return -ENOENT;
	74	}
	75	EXPORT_SYMBOL_GPL(qcom_find_src_index);
	76
5b6b7490 SB	77	struct regmap *
5b6b7490 SB	78	qcom_cc_map(struct platform_device pdev, const struct qcom_cc_desc desc)
49fc825f SB	79	{
	80	void __iomem *base;
	81	struct resource *res;
5b6b7490 SB	82	struct device *dev = &pdev->dev;
	83
	84	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	85	base = devm_ioremap_resource(dev, res);
	86	if (IS_ERR(base))
	87	return ERR_CAST(base);
	88
	89	return devm_regmap_init_mmio(dev, base, desc->config);
	90	}
	91	EXPORT_SYMBOL_GPL(qcom_cc_map);
	92
400d9fda RN	93	void
	94	qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
	95	{
	96	u32 val;
	97	u32 mask;
	98
	99	/* De-assert reset to FSM */
	100	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
	101
	102	/* Program bias count and lock count */
	103	val = bias_count << PLL_BIAS_COUNT_SHIFT \|
	104	lock_count << PLL_LOCK_COUNT_SHIFT;
	105	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	106	mask \|= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	107	regmap_update_bits(map, reg, mask, val);
	108
	109	/* Enable PLL FSM voting */
	110	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
	111	}
	112	EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
	113
94c51f40 SB	114	static void qcom_cc_gdsc_unregister(void *data)
	115	{
	116	gdsc_unregister(data);
	117	}
	118
ee15faff SB	119	/*
ee15faff SB	120	* Backwards compatibility with old DTs. Register a pass-through factor 1/1
ad61dd30	121	* clock to translate 'path' clk into 'name' clk and register the 'path'
ee15faff SB	122	* clk as a fixed rate clock if it isn't present.
	123	*/
	124	static int _qcom_cc_register_board_clk(struct device dev, const char path,
	125	const char *name, unsigned long rate,
	126	bool add_factor)
	127	{
	128	struct device_node *node = NULL;
	129	struct device_node *clocks_node;
	130	struct clk_fixed_factor *factor;
	131	struct clk_fixed_rate *fixed;
ee15faff	132	struct clk_init_data init_data = { };
120c1552	133	int ret;
ee15faff SB	134
ee15faff SB	135	clocks_node = of_find_node_by_path("/clocks");
43a51019 JH	136	if (clocks_node) {
	137	node = of_get_child_by_name(clocks_node, path);
	138	of_node_put(clocks_node);
	139	}
ee15faff SB	140
	141	if (!node) {
	142	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
	143	if (!fixed)
	144	return -EINVAL;
	145
	146	fixed->fixed_rate = rate;
	147	fixed->hw.init = &init_data;
	148
	149	init_data.name = path;
ee15faff SB	150	init_data.ops = &clk_fixed_rate_ops;
ee15faff SB	151
120c1552 SB	152	ret = devm_clk_hw_register(dev, &fixed->hw);
	153	if (ret)
	154	return ret;
ee15faff SB	155	}
	156	of_node_put(node);
	157
	158	if (add_factor) {
	159	factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
	160	if (!factor)
	161	return -EINVAL;
	162
	163	factor->mult = factor->div = 1;
	164	factor->hw.init = &init_data;
	165
	166	init_data.name = name;
	167	init_data.parent_names = &path;
	168	init_data.num_parents = 1;
	169	init_data.flags = 0;
	170	init_data.ops = &clk_fixed_factor_ops;
	171
120c1552 SB	172	ret = devm_clk_hw_register(dev, &factor->hw);
	173	if (ret)
	174	return ret;
ee15faff SB	175	}
	176
	177	return 0;
	178	}
	179
	180	int qcom_cc_register_board_clk(struct device dev, const char path,
	181	const char *name, unsigned long rate)
	182	{
	183	bool add_factor = true;
54823af9 GD	184
	185	/*
	186	* TODO: The RPM clock driver currently does not support the xo clock.
	187	* When xo is added to the RPM clock driver, we should change this
	188	* function to skip registration of xo factor clocks.
	189	*/
ee15faff SB	190
	191	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
	192	}
	193	EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
	194
	195	int qcom_cc_register_sleep_clk(struct device *dev)
	196	{
	197	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
	198	32768, true);
	199	}
	200	EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
	201
120c1552 SB	202	static struct clk_hw qcom_cc_clk_hw_get(struct of_phandle_args clkspec,
	203	void *data)
	204	{
	205	struct qcom_cc *cc = data;
	206	unsigned int idx = clkspec->args[0];
	207
	208	if (idx >= cc->num_rclks) {
	209	pr_err("%s: invalid index %u\n", __func__, idx);
	210	return ERR_PTR(-EINVAL);
	211	}
	212
	213	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
	214	}
	215
5b6b7490 SB	216	int qcom_cc_really_probe(struct platform_device *pdev,
	217	const struct qcom_cc_desc desc, struct regmap regmap)
	218	{
49fc825f SB	219	int i, ret;
49fc825f SB	220	struct device *dev = &pdev->dev;
49fc825f SB	221	struct qcom_reset_controller *reset;
49fc825f SB	222	struct qcom_cc *cc;
c2c7f0a4	223	struct gdsc_desc *scd;
49fc825f SB	224	size_t num_clks = desc->num_clks;
	225	struct clk_regmap **rclks = desc->clks;
	226
120c1552	227	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
49fc825f SB	228	if (!cc)
	229	return -ENOMEM;
	230
120c1552 SB	231	cc->rclks = rclks;
120c1552 SB	232	cc->num_rclks = num_clks;
49fc825f SB	233
49fc825f SB	234	for (i = 0; i < num_clks; i++) {
120c1552	235	if (!rclks[i])
49fc825f	236	continue;
120c1552 SB	237
	238	ret = devm_clk_register_regmap(dev, rclks[i]);
	239	if (ret)
	240	return ret;
49fc825f SB	241	}
49fc825f SB	242
b87206f8	243	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
66f5ce25 SM	244	if (ret)
66f5ce25 SM	245	return ret;
94c51f40	246
49fc825f SB	247	reset = &cc->reset;
	248	reset->rcdev.of_node = dev->of_node;
	249	reset->rcdev.ops = &qcom_reset_ops;
	250	reset->rcdev.owner = dev->driver->owner;
	251	reset->rcdev.nr_resets = desc->num_resets;
	252	reset->regmap = regmap;
	253	reset->reset_map = desc->resets;
49fc825f	254
b87206f8	255	ret = devm_reset_controller_register(dev, &reset->rcdev);
66f5ce25 SM	256	if (ret)
66f5ce25 SM	257	return ret;
49fc825f	258
5e5cc241	259	if (desc->gdscs && desc->num_gdscs) {
c2c7f0a4 RN	260	scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
	261	if (!scd)
	262	return -ENOMEM;
	263	scd->dev = dev;
	264	scd->scs = desc->gdscs;
	265	scd->num = desc->num_gdscs;
	266	ret = gdsc_register(scd, &reset->rcdev, regmap);
	267	if (ret)
	268	return ret;
	269	ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
	270	scd);
5e5cc241	271	if (ret)
94c51f40	272	return ret;
5e5cc241 RN	273	}
5e5cc241 RN	274
c2c7f0a4	275	return 0;
49fc825f	276	}
5b6b7490 SB	277	EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
	278
	279	int qcom_cc_probe(struct platform_device pdev, const struct qcom_cc_desc desc)
	280	{
	281	struct regmap *regmap;
	282
	283	regmap = qcom_cc_map(pdev, desc);
	284	if (IS_ERR(regmap))
	285	return PTR_ERR(regmap);
	286
	287	return qcom_cc_really_probe(pdev, desc, regmap);
	288	}
49fc825f SB	289	EXPORT_SYMBOL_GPL(qcom_cc_probe);
49fc825f SB	290
169f05e8	291	MODULE_LICENSE("GPL v2");