[linux-block.git] / drivers / clk / qcom / common.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>

#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"

struct qcom_cc {
	struct qcom_reset_controller reset;
	struct clk_regmap **rclks;
	size_t num_rclks;
};

const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
	if (!f)
		return NULL;

	if (!f->freq)
		return f;

	for (; f->freq; f++)
		if (rate <= f->freq)
			return f;

	/* Default to our fastest rate */
	return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);

const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
					    unsigned long rate)
{
	const struct freq_tbl *best = NULL;

	for ( ; f->freq; f++) {
		if (rate >= f->freq)
			best = f;
		else
			break;
	}

	return best;
}
EXPORT_SYMBOL_GPL(qcom_find_freq_floor);

int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (src == map[i].src)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);

int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (cfg == map[i].cfg)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_cfg_index);

struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	void __iomem *base;
	struct device *dev = &pdev->dev;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return ERR_CAST(base);

	return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);

void
qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
{
	u32 val;
	u32 mask;

	/* De-assert reset to FSM */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);

	/* Program bias count and lock count */
	val = bias_count << PLL_BIAS_COUNT_SHIFT |
		lock_count << PLL_LOCK_COUNT_SHIFT;
	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	regmap_update_bits(map, reg, mask, val);

	/* Enable PLL FSM voting */
	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
}
EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);

static void qcom_cc_gdsc_unregister(void *data)
{
	gdsc_unregister(data);
}

/*
 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
 * clock to translate 'path' clk into 'name' clk and register the 'path'
 * clk as a fixed rate clock if it isn't present.
 */
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
				       const char *name, unsigned long rate,
				       bool add_factor)
{
	struct device_node *node = NULL;
	struct device_node *clocks_node;
	struct clk_fixed_factor *factor;
	struct clk_fixed_rate *fixed;
	struct clk_init_data init_data = { };
	int ret;

	clocks_node = of_find_node_by_path("/clocks");
	if (clocks_node) {
		node = of_get_child_by_name(clocks_node, path);
		of_node_put(clocks_node);
	}

	if (!node) {
		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
		if (!fixed)
			return -EINVAL;

		fixed->fixed_rate = rate;
		fixed->hw.init = &init_data;

		init_data.name = path;
		init_data.ops = &clk_fixed_rate_ops;

		ret = devm_clk_hw_register(dev, &fixed->hw);
		if (ret)
			return ret;
	}
	of_node_put(node);

	if (add_factor) {
		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
		if (!factor)
			return -EINVAL;

		factor->mult = factor->div = 1;
		factor->hw.init = &init_data;

		init_data.name = name;
		init_data.parent_names = &path;
		init_data.num_parents = 1;
		init_data.flags = 0;
		init_data.ops = &clk_fixed_factor_ops;

		ret = devm_clk_hw_register(dev, &factor->hw);
		if (ret)
			return ret;
	}

	return 0;
}

int qcom_cc_register_board_clk(struct device *dev, const char *path,
			       const char *name, unsigned long rate)
{
	bool add_factor = true;

	/*
	 * TODO: The RPM clock driver currently does not support the xo clock.
	 * When xo is added to the RPM clock driver, we should change this
	 * function to skip registration of xo factor clocks.
	 */

	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);

int qcom_cc_register_sleep_clk(struct device *dev)
{
	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
					   32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);

/* Drop 'protected-clocks' from the list of clocks to register */
static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
{
	struct device_node *np = dev->of_node;
	struct property *prop;
	const __be32 *p;
	u32 i;

	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
		if (i >= cc->num_rclks)
			continue;

		cc->rclks[i] = NULL;
	}
}

static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
					 void *data)
{
	struct qcom_cc *cc = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= cc->num_rclks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}

int qcom_cc_really_probe(struct platform_device *pdev,
			 const struct qcom_cc_desc *desc, struct regmap *regmap)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct qcom_reset_controller *reset;
	struct qcom_cc *cc;
	struct gdsc_desc *scd;
	size_t num_clks = desc->num_clks;
	struct clk_regmap **rclks = desc->clks;
	size_t num_clk_hws = desc->num_clk_hws;
	struct clk_hw **clk_hws = desc->clk_hws;

	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
	if (!cc)
		return -ENOMEM;

	reset = &cc->reset;
	reset->rcdev.of_node = dev->of_node;
	reset->rcdev.ops = &qcom_reset_ops;
	reset->rcdev.owner = dev->driver->owner;
	reset->rcdev.nr_resets = desc->num_resets;
	reset->regmap = regmap;
	reset->reset_map = desc->resets;

	ret = devm_reset_controller_register(dev, &reset->rcdev);
	if (ret)
		return ret;

	if (desc->gdscs && desc->num_gdscs) {
		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
		if (!scd)
			return -ENOMEM;
		scd->dev = dev;
		scd->scs = desc->gdscs;
		scd->num = desc->num_gdscs;
		ret = gdsc_register(scd, &reset->rcdev, regmap);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
					       scd);
		if (ret)
			return ret;
	}

	cc->rclks = rclks;
	cc->num_rclks = num_clks;

	qcom_cc_drop_protected(dev, cc);

	for (i = 0; i < num_clk_hws; i++) {
		ret = devm_clk_hw_register(dev, clk_hws[i]);
		if (ret)
			return ret;
	}

	for (i = 0; i < num_clks; i++) {
		if (!rclks[i])
			continue;

		ret = devm_clk_register_regmap(dev, rclks[i]);
		if (ret)
			return ret;
	}

	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
	if (ret)
		return ret;

	return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;

	regmap = qcom_cc_map(pdev, desc);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);

int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
			   const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;
	void __iomem *base;

	base = devm_platform_ioremap_resource(pdev, index);
	if (IS_ERR(base))
		return -ENOMEM;

	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
f9419783	1	// SPDX-License-Identifier: GPL-2.0
49fc825f SB	2	/*
49fc825f SB	3	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
49fc825f SB	4	*/
	5
	6	#include <linux/export.h>
169f05e8	7	#include <linux/module.h>
49fc825f SB	8	#include <linux/regmap.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/clk-provider.h>
	11	#include <linux/reset-controller.h>
ee15faff	12	#include <linux/of.h>
49fc825f SB	13
49fc825f SB	14	#include "common.h"
50c6a503	15	#include "clk-rcg.h"
49fc825f SB	16	#include "clk-regmap.h"
49fc825f SB	17	#include "reset.h"
5e5cc241	18	#include "gdsc.h"
49fc825f SB	19
	20	struct qcom_cc {
	21	struct qcom_reset_controller reset;
120c1552 SB	22	struct clk_regmap **rclks;
120c1552 SB	23	size_t num_rclks;
49fc825f SB	24	};
49fc825f SB	25
50c6a503 SB	26	const
	27	struct freq_tbl qcom_find_freq(const struct freq_tbl f, unsigned long rate)
	28	{
	29	if (!f)
	30	return NULL;
	31
efd164b5 JH	32	if (!f->freq)
	33	return f;
	34
50c6a503 SB	35	for (; f->freq; f++)
	36	if (rate <= f->freq)
	37	return f;
	38
	39	/* Default to our fastest rate */
	40	return f - 1;
	41	}
	42	EXPORT_SYMBOL_GPL(qcom_find_freq);
	43
081ba802 RN	44	const struct freq_tbl qcom_find_freq_floor(const struct freq_tbl f,
	45	unsigned long rate)
	46	{
	47	const struct freq_tbl *best = NULL;
	48
	49	for ( ; f->freq; f++) {
	50	if (rate >= f->freq)
	51	best = f;
	52	else
	53	break;
	54	}
	55
	56	return best;
	57	}
	58	EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
	59
293d2e97 GD	60	int qcom_find_src_index(struct clk_hw hw, const struct parent_map map, u8 src)
293d2e97 GD	61	{
497295af	62	int i, num_parents = clk_hw_get_num_parents(hw);
293d2e97 GD	63
	64	for (i = 0; i < num_parents; i++)
	65	if (src == map[i].src)
	66	return i;
	67
	68	return -ENOENT;
	69	}
	70	EXPORT_SYMBOL_GPL(qcom_find_src_index);
	71
9a61f813 DB	72	int qcom_find_cfg_index(struct clk_hw hw, const struct parent_map map, u8 cfg)
	73	{
	74	int i, num_parents = clk_hw_get_num_parents(hw);
	75
	76	for (i = 0; i < num_parents; i++)
	77	if (cfg == map[i].cfg)
	78	return i;
	79
	80	return -ENOENT;
	81	}
	82	EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
	83
5b6b7490 SB	84	struct regmap *
5b6b7490 SB	85	qcom_cc_map(struct platform_device pdev, const struct qcom_cc_desc desc)
49fc825f SB	86	{
49fc825f SB	87	void __iomem *base;
5b6b7490 SB	88	struct device *dev = &pdev->dev;
5b6b7490 SB	89
437cbbb0	90	base = devm_platform_ioremap_resource(pdev, 0);
5b6b7490 SB	91	if (IS_ERR(base))
	92	return ERR_CAST(base);
	93
	94	return devm_regmap_init_mmio(dev, base, desc->config);
	95	}
	96	EXPORT_SYMBOL_GPL(qcom_cc_map);
	97
400d9fda RN	98	void
	99	qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
	100	{
	101	u32 val;
	102	u32 mask;
	103
	104	/* De-assert reset to FSM */
	105	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
	106
	107	/* Program bias count and lock count */
	108	val = bias_count << PLL_BIAS_COUNT_SHIFT \|
	109	lock_count << PLL_LOCK_COUNT_SHIFT;
	110	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
	111	mask \|= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
	112	regmap_update_bits(map, reg, mask, val);
	113
	114	/* Enable PLL FSM voting */
	115	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
	116	}
	117	EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
	118
94c51f40 SB	119	static void qcom_cc_gdsc_unregister(void *data)
	120	{
	121	gdsc_unregister(data);
	122	}
	123
ee15faff SB	124	/*
ee15faff SB	125	* Backwards compatibility with old DTs. Register a pass-through factor 1/1
ad61dd30	126	* clock to translate 'path' clk into 'name' clk and register the 'path'
ee15faff SB	127	* clk as a fixed rate clock if it isn't present.
	128	*/
	129	static int _qcom_cc_register_board_clk(struct device dev, const char path,
	130	const char *name, unsigned long rate,
	131	bool add_factor)
	132	{
	133	struct device_node *node = NULL;
	134	struct device_node *clocks_node;
	135	struct clk_fixed_factor *factor;
	136	struct clk_fixed_rate *fixed;
ee15faff	137	struct clk_init_data init_data = { };
120c1552	138	int ret;
ee15faff SB	139
ee15faff SB	140	clocks_node = of_find_node_by_path("/clocks");
43a51019 JH	141	if (clocks_node) {
	142	node = of_get_child_by_name(clocks_node, path);
	143	of_node_put(clocks_node);
	144	}
ee15faff SB	145
	146	if (!node) {
	147	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
	148	if (!fixed)
	149	return -EINVAL;
	150
	151	fixed->fixed_rate = rate;
	152	fixed->hw.init = &init_data;
	153
	154	init_data.name = path;
ee15faff SB	155	init_data.ops = &clk_fixed_rate_ops;
ee15faff SB	156
120c1552 SB	157	ret = devm_clk_hw_register(dev, &fixed->hw);
	158	if (ret)
	159	return ret;
ee15faff SB	160	}
	161	of_node_put(node);
	162
	163	if (add_factor) {
	164	factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
	165	if (!factor)
	166	return -EINVAL;
	167
	168	factor->mult = factor->div = 1;
	169	factor->hw.init = &init_data;
	170
	171	init_data.name = name;
	172	init_data.parent_names = &path;
	173	init_data.num_parents = 1;
	174	init_data.flags = 0;
	175	init_data.ops = &clk_fixed_factor_ops;
	176
120c1552 SB	177	ret = devm_clk_hw_register(dev, &factor->hw);
	178	if (ret)
	179	return ret;
ee15faff SB	180	}
	181
	182	return 0;
	183	}
	184
	185	int qcom_cc_register_board_clk(struct device dev, const char path,
	186	const char *name, unsigned long rate)
	187	{
	188	bool add_factor = true;
54823af9 GD	189
	190	/*
	191	* TODO: The RPM clock driver currently does not support the xo clock.
	192	* When xo is added to the RPM clock driver, we should change this
	193	* function to skip registration of xo factor clocks.
	194	*/
ee15faff SB	195
	196	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
	197	}
	198	EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
	199
	200	int qcom_cc_register_sleep_clk(struct device *dev)
	201	{
	202	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
	203	32768, true);
	204	}
	205	EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
	206
b181b3b8 SB	207	/* Drop 'protected-clocks' from the list of clocks to register */
	208	static void qcom_cc_drop_protected(struct device dev, struct qcom_cc cc)
	209	{
	210	struct device_node *np = dev->of_node;
	211	struct property *prop;
	212	const __be32 *p;
	213	u32 i;
	214
	215	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
	216	if (i >= cc->num_rclks)
	217	continue;
	218
	219	cc->rclks[i] = NULL;
	220	}
	221	}
	222
120c1552 SB	223	static struct clk_hw qcom_cc_clk_hw_get(struct of_phandle_args clkspec,
	224	void *data)
	225	{
	226	struct qcom_cc *cc = data;
	227	unsigned int idx = clkspec->args[0];
	228
	229	if (idx >= cc->num_rclks) {
	230	pr_err("%s: invalid index %u\n", __func__, idx);
	231	return ERR_PTR(-EINVAL);
	232	}
	233
ffe37ede	234	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
120c1552 SB	235	}
120c1552 SB	236
5b6b7490 SB	237	int qcom_cc_really_probe(struct platform_device *pdev,
	238	const struct qcom_cc_desc desc, struct regmap regmap)
	239	{
49fc825f SB	240	int i, ret;
49fc825f SB	241	struct device *dev = &pdev->dev;
49fc825f SB	242	struct qcom_reset_controller *reset;
49fc825f SB	243	struct qcom_cc *cc;
c2c7f0a4	244	struct gdsc_desc *scd;
49fc825f SB	245	size_t num_clks = desc->num_clks;
49fc825f SB	246	struct clk_regmap **rclks = desc->clks;
760be658 JH	247	size_t num_clk_hws = desc->num_clk_hws;
760be658 JH	248	struct clk_hw **clk_hws = desc->clk_hws;
49fc825f	249
120c1552	250	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
49fc825f SB	251	if (!cc)
	252	return -ENOMEM;
	253
49fc825f SB	254	reset = &cc->reset;
	255	reset->rcdev.of_node = dev->of_node;
	256	reset->rcdev.ops = &qcom_reset_ops;
	257	reset->rcdev.owner = dev->driver->owner;
	258	reset->rcdev.nr_resets = desc->num_resets;
	259	reset->regmap = regmap;
	260	reset->reset_map = desc->resets;
49fc825f	261
b87206f8	262	ret = devm_reset_controller_register(dev, &reset->rcdev);
66f5ce25 SM	263	if (ret)
66f5ce25 SM	264	return ret;
49fc825f	265
5e5cc241	266	if (desc->gdscs && desc->num_gdscs) {
c2c7f0a4 RN	267	scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
	268	if (!scd)
	269	return -ENOMEM;
	270	scd->dev = dev;
	271	scd->scs = desc->gdscs;
	272	scd->num = desc->num_gdscs;
	273	ret = gdsc_register(scd, &reset->rcdev, regmap);
	274	if (ret)
	275	return ret;
	276	ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
	277	scd);
5e5cc241	278	if (ret)
94c51f40	279	return ret;
5e5cc241 RN	280	}
5e5cc241 RN	281
31543ebb RN	282	cc->rclks = rclks;
	283	cc->num_rclks = num_clks;
	284
b181b3b8 SB	285	qcom_cc_drop_protected(dev, cc);
b181b3b8 SB	286
760be658 JH	287	for (i = 0; i < num_clk_hws; i++) {
	288	ret = devm_clk_hw_register(dev, clk_hws[i]);
	289	if (ret)
	290	return ret;
	291	}
	292
31543ebb RN	293	for (i = 0; i < num_clks; i++) {
	294	if (!rclks[i])
	295	continue;
	296
	297	ret = devm_clk_register_regmap(dev, rclks[i]);
	298	if (ret)
	299	return ret;
	300	}
	301
	302	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
	303	if (ret)
	304	return ret;
	305
c2c7f0a4	306	return 0;
49fc825f	307	}
5b6b7490 SB	308	EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
	309
	310	int qcom_cc_probe(struct platform_device pdev, const struct qcom_cc_desc desc)
	311	{
	312	struct regmap *regmap;
	313
	314	regmap = qcom_cc_map(pdev, desc);
	315	if (IS_ERR(regmap))
	316	return PTR_ERR(regmap);
	317
	318	return qcom_cc_really_probe(pdev, desc, regmap);
	319	}
49fc825f SB	320	EXPORT_SYMBOL_GPL(qcom_cc_probe);
49fc825f SB	321
75e0a1e3 GS	322	int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
	323	const struct qcom_cc_desc *desc)
	324	{
	325	struct regmap *regmap;
75e0a1e3 GS	326	void __iomem *base;
75e0a1e3 GS	327
437cbbb0	328	base = devm_platform_ioremap_resource(pdev, index);
75e0a1e3 GS	329	if (IS_ERR(base))
	330	return -ENOMEM;
	331
	332	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
	333	if (IS_ERR(regmap))
	334	return PTR_ERR(regmap);
	335
	336	return qcom_cc_really_probe(pdev, desc, regmap);
	337	}
	338	EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
	339
169f05e8	340	MODULE_LICENSE("GPL v2");