[linux-block.git] / drivers / clk / qcom / clk-rpm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, Linaro Limited
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/mfd/qcom_rpm.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>

#define QCOM_RPM_MISC_CLK_TYPE				0x306b6c63
#define QCOM_RPM_SCALING_ENABLE_ID			0x2
#define QCOM_RPM_XO_MODE_ON				0x2

static const struct clk_parent_data gcc_pxo[] = {
	{ .fw_name = "pxo", .name = "pxo_board" },
};

static const struct clk_parent_data gcc_cxo[] = {
	{ .fw_name = "cxo", .name = "cxo_board" },
};

#define DEFINE_CLK_RPM(_name, r_id)					      \
	static struct clk_rpm clk_rpm_##_name##_a_clk;			      \
	static struct clk_rpm clk_rpm_##_name##_clk = {			      \
		.rpm_clk_id = (r_id),					      \
		.peer = &clk_rpm_##_name##_a_clk,			      \
		.rate = INT_MAX,					      \
		.hw.init = &(struct clk_init_data){			      \
			.ops = &clk_rpm_ops,				      \
			.name = #_name "_clk",				      \
			.parent_data = gcc_pxo,				      \
			.num_parents = ARRAY_SIZE(gcc_pxo),		      \
		},							      \
	};								      \
	static struct clk_rpm clk_rpm_##_name##_a_clk = {		      \
		.rpm_clk_id = (r_id),					      \
		.peer = &clk_rpm_##_name##_clk,				      \
		.active_only = true,					      \
		.rate = INT_MAX,					      \
		.hw.init = &(struct clk_init_data){			      \
			.ops = &clk_rpm_ops,				      \
			.name = #_name "_a_clk",			      \
			.parent_data = gcc_pxo,				      \
			.num_parents = ARRAY_SIZE(gcc_pxo),		      \
		},							      \
	}

#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset)				      \
	static struct clk_rpm clk_rpm_##_name##_clk = {			      \
		.rpm_clk_id = QCOM_RPM_CXO_BUFFERS,			      \
		.xo_offset = (offset),					      \
		.hw.init = &(struct clk_init_data){			      \
			.ops = &clk_rpm_xo_ops,				      \
			.name = #_name "_clk",				      \
			.parent_data = gcc_cxo,				      \
			.num_parents = ARRAY_SIZE(gcc_cxo),		      \
		},							      \
	}

#define DEFINE_CLK_RPM_FIXED(_name, r_id, r)				      \
	static struct clk_rpm clk_rpm_##_name##_clk = {			      \
		.rpm_clk_id = (r_id),					      \
		.rate = (r),						      \
		.hw.init = &(struct clk_init_data){			      \
			.ops = &clk_rpm_fixed_ops,			      \
			.name = #_name "_clk",				      \
			.parent_data = gcc_pxo,				      \
			.num_parents = ARRAY_SIZE(gcc_pxo),		      \
		},							      \
	}

#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)

struct rpm_cc;

struct clk_rpm {
	const int rpm_clk_id;
	const int xo_offset;
	const bool active_only;
	unsigned long rate;
	bool enabled;
	bool branch;
	struct clk_rpm *peer;
	struct clk_hw hw;
	struct qcom_rpm *rpm;
	struct rpm_cc *rpm_cc;
};

struct rpm_cc {
	struct qcom_rpm *rpm;
	struct clk_rpm **clks;
	size_t num_clks;
	u32 xo_buffer_value;
	struct mutex xo_lock;
};

struct rpm_clk_desc {
	struct clk_rpm **clks;
	size_t num_clks;
};

static DEFINE_MUTEX(rpm_clk_lock);

static int clk_rpm_handoff(struct clk_rpm *r)
{
	int ret;
	u32 value = INT_MAX;

	/*
	 * The vendor tree simply reads the status for this
	 * RPM clock.
	 */
	if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
		r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
		return 0;

	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
			     r->rpm_clk_id, &value, 1);
	if (ret)
		return ret;
	ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
			     r->rpm_clk_id, &value, 1);
	if (ret)
		return ret;

	return 0;
}

static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
{
	u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */

	return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
			      r->rpm_clk_id, &value, 1);
}

static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
{
	u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */

	return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
			      r->rpm_clk_id, &value, 1);
}

static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
			    unsigned long *active, unsigned long *sleep)
{
	*active = rate;

	/*
	 * Active-only clocks don't care what the rate is during sleep. So,
	 * they vote for zero.
	 */
	if (r->active_only)
		*sleep = 0;
	else
		*sleep = *active;
}

static int clk_rpm_prepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	struct clk_rpm *peer = r->peer;
	unsigned long this_rate = 0, this_sleep_rate = 0;
	unsigned long peer_rate = 0, peer_sleep_rate = 0;
	unsigned long active_rate, sleep_rate;
	int ret = 0;

	mutex_lock(&rpm_clk_lock);

	/* Don't send requests to the RPM if the rate has not been set. */
	if (!r->rate)
		goto out;

	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);

	/* Take peer clock's rate into account only if it's enabled. */
	if (peer->enabled)
		to_active_sleep(peer, peer->rate,
				&peer_rate, &peer_sleep_rate);

	active_rate = max(this_rate, peer_rate);

	if (r->branch)
		active_rate = !!active_rate;

	ret = clk_rpm_set_rate_active(r, active_rate);
	if (ret)
		goto out;

	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
	if (r->branch)
		sleep_rate = !!sleep_rate;

	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
	if (ret)
		/* Undo the active set vote and restore it */
		ret = clk_rpm_set_rate_active(r, peer_rate);

out:
	if (!ret)
		r->enabled = true;

	mutex_unlock(&rpm_clk_lock);

	return ret;
}

static void clk_rpm_unprepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	struct clk_rpm *peer = r->peer;
	unsigned long peer_rate = 0, peer_sleep_rate = 0;
	unsigned long active_rate, sleep_rate;
	int ret;

	mutex_lock(&rpm_clk_lock);

	if (!r->rate)
		goto out;

	/* Take peer clock's rate into account only if it's enabled. */
	if (peer->enabled)
		to_active_sleep(peer, peer->rate, &peer_rate,
				&peer_sleep_rate);

	active_rate = r->branch ? !!peer_rate : peer_rate;
	ret = clk_rpm_set_rate_active(r, active_rate);
	if (ret)
		goto out;

	sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
	if (ret)
		goto out;

	r->enabled = false;

out:
	mutex_unlock(&rpm_clk_lock);
}

static int clk_rpm_xo_prepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	struct rpm_cc *rcc = r->rpm_cc;
	int ret, clk_id = r->rpm_clk_id;
	u32 value;

	mutex_lock(&rcc->xo_lock);

	value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
	if (!ret) {
		r->enabled = true;
		rcc->xo_buffer_value = value;
	}

	mutex_unlock(&rcc->xo_lock);

	return ret;
}

static void clk_rpm_xo_unprepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	struct rpm_cc *rcc = r->rpm_cc;
	int ret, clk_id = r->rpm_clk_id;
	u32 value;

	mutex_lock(&rcc->xo_lock);

	value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
	if (!ret) {
		r->enabled = false;
		rcc->xo_buffer_value = value;
	}

	mutex_unlock(&rcc->xo_lock);
}

static int clk_rpm_fixed_prepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	u32 value = 1;
	int ret;

	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
			     r->rpm_clk_id, &value, 1);
	if (!ret)
		r->enabled = true;

	return ret;
}

static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	u32 value = 0;
	int ret;

	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
			     r->rpm_clk_id, &value, 1);
	if (!ret)
		r->enabled = false;
}

static int clk_rpm_set_rate(struct clk_hw *hw,
			    unsigned long rate, unsigned long parent_rate)
{
	struct clk_rpm *r = to_clk_rpm(hw);
	struct clk_rpm *peer = r->peer;
	unsigned long active_rate, sleep_rate;
	unsigned long this_rate = 0, this_sleep_rate = 0;
	unsigned long peer_rate = 0, peer_sleep_rate = 0;
	int ret = 0;

	mutex_lock(&rpm_clk_lock);

	if (!r->enabled)
		goto out;

	to_active_sleep(r, rate, &this_rate, &this_sleep_rate);

	/* Take peer clock's rate into account only if it's enabled. */
	if (peer->enabled)
		to_active_sleep(peer, peer->rate,
				&peer_rate, &peer_sleep_rate);

	active_rate = max(this_rate, peer_rate);
	ret = clk_rpm_set_rate_active(r, active_rate);
	if (ret)
		goto out;

	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
	if (ret)
		goto out;

	r->rate = rate;

out:
	mutex_unlock(&rpm_clk_lock);

	return ret;
}

static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long *parent_rate)
{
	/*
	 * RPM handles rate rounding and we don't have a way to
	 * know what the rate will be, so just return whatever
	 * rate is requested.
	 */
	return rate;
}

static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
					 unsigned long parent_rate)
{
	struct clk_rpm *r = to_clk_rpm(hw);

	/*
	 * RPM handles rate rounding and we don't have a way to
	 * know what the rate will be, so just return whatever
	 * rate was set.
	 */
	return r->rate;
}

static const struct clk_ops clk_rpm_xo_ops = {
	.prepare	= clk_rpm_xo_prepare,
	.unprepare	= clk_rpm_xo_unprepare,
};

static const struct clk_ops clk_rpm_fixed_ops = {
	.prepare	= clk_rpm_fixed_prepare,
	.unprepare	= clk_rpm_fixed_unprepare,
	.round_rate	= clk_rpm_round_rate,
	.recalc_rate	= clk_rpm_recalc_rate,
};

static const struct clk_ops clk_rpm_ops = {
	.prepare	= clk_rpm_prepare,
	.unprepare	= clk_rpm_unprepare,
	.set_rate	= clk_rpm_set_rate,
	.round_rate	= clk_rpm_round_rate,
	.recalc_rate	= clk_rpm_recalc_rate,
};

DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);

DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);

DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);

DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);

static struct clk_rpm *msm8660_clks[] = {
	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
	[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
	[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
	[RPM_SMI_CLK] = &clk_rpm_smi_clk,
	[RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	[RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
};

static const struct rpm_clk_desc rpm_clk_msm8660 = {
	.clks = msm8660_clks,
	.num_clks = ARRAY_SIZE(msm8660_clks),
};

static struct clk_rpm *apq8064_clks[] = {
	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
	[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
	[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
	[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	[RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
	[RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
	[RPM_XO_D0] = &clk_rpm_xo_d0_clk,
	[RPM_XO_D1] = &clk_rpm_xo_d1_clk,
	[RPM_XO_A0] = &clk_rpm_xo_a0_clk,
	[RPM_XO_A1] = &clk_rpm_xo_a1_clk,
	[RPM_XO_A2] = &clk_rpm_xo_a2_clk,
};

static const struct rpm_clk_desc rpm_clk_apq8064 = {
	.clks = apq8064_clks,
	.num_clks = ARRAY_SIZE(apq8064_clks),
};

static struct clk_rpm *ipq806x_clks[] = {
	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	[RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
	[RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
	[RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
	[RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
};

static const struct rpm_clk_desc rpm_clk_ipq806x = {
	.clks = ipq806x_clks,
	.num_clks = ARRAY_SIZE(ipq806x_clks),
};

static const struct of_device_id rpm_clk_match_table[] = {
	{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
	{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
	{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
	{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
	{ }
};
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);

static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
					  void *data)
{
	struct rpm_cc *rcc = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= rcc->num_clks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
}

static int rpm_clk_probe(struct platform_device *pdev)
{
	struct rpm_cc *rcc;
	int ret;
	size_t num_clks, i;
	struct qcom_rpm *rpm;
	struct clk_rpm **rpm_clks;
	const struct rpm_clk_desc *desc;

	rpm = dev_get_drvdata(pdev->dev.parent);
	if (!rpm) {
		dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
		return -ENODEV;
	}

	desc = of_device_get_match_data(&pdev->dev);
	if (!desc)
		return -EINVAL;

	rpm_clks = desc->clks;
	num_clks = desc->num_clks;

	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
	if (!rcc)
		return -ENOMEM;

	rcc->clks = rpm_clks;
	rcc->num_clks = num_clks;
	mutex_init(&rcc->xo_lock);

	for (i = 0; i < num_clks; i++) {
		if (!rpm_clks[i])
			continue;

		rpm_clks[i]->rpm = rpm;
		rpm_clks[i]->rpm_cc = rcc;

		ret = clk_rpm_handoff(rpm_clks[i]);
		if (ret)
			goto err;
	}

	for (i = 0; i < num_clks; i++) {
		if (!rpm_clks[i])
			continue;

		ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
		if (ret)
			goto err;
	}

	ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,
					  rcc);
	if (ret)
		goto err;

	return 0;
err:
	dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
	return ret;
}

static struct platform_driver rpm_clk_driver = {
	.driver = {
		.name = "qcom-clk-rpm",
		.of_match_table = rpm_clk_match_table,
	},
	.probe = rpm_clk_probe,
};

static int __init rpm_clk_init(void)
{
	return platform_driver_register(&rpm_clk_driver);
}
core_initcall(rpm_clk_init);

static void __exit rpm_clk_exit(void)
{
	platform_driver_unregister(&rpm_clk_driver);
}
module_exit(rpm_clk_exit);

MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:qcom-clk-rpm");
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
872f91b5 GD	2	/*
	3	* Copyright (c) 2016, Linaro Limited
	4	* Copyright (c) 2014, The Linux Foundation. All rights reserved.
872f91b5 GD	5	*/
	6
	7	#include <linux/clk-provider.h>
	8	#include <linux/err.h>
	9	#include <linux/export.h>
	10	#include <linux/init.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/mutex.h>
	14	#include <linux/mfd/qcom_rpm.h>
	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18
	19	#include <dt-bindings/mfd/qcom-rpm.h>
	20	#include <dt-bindings/clock/qcom,rpmcc.h>
	21
	22	#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
	23	#define QCOM_RPM_SCALING_ENABLE_ID 0x2
8bcde658	24	#define QCOM_RPM_XO_MODE_ON 0x2
872f91b5	25
129d9cd9 CM	26	static const struct clk_parent_data gcc_pxo[] = {
	27	{ .fw_name = "pxo", .name = "pxo_board" },
	28	};
	29
	30	static const struct clk_parent_data gcc_cxo[] = {
	31	{ .fw_name = "cxo", .name = "cxo_board" },
	32	};
	33
3de1c1fd DB	34	#define DEFINE_CLK_RPM(_name, r_id) \
	35	static struct clk_rpm clk_rpm_##_name##_a_clk; \
	36	static struct clk_rpm clk_rpm_##_name##_clk = { \
872f91b5	37	.rpm_clk_id = (r_id), \
3de1c1fd	38	.peer = &clk_rpm_##_name##_a_clk, \
872f91b5 GD	39	.rate = INT_MAX, \
	40	.hw.init = &(struct clk_init_data){ \
	41	.ops = &clk_rpm_ops, \
35a57cda	42	.name = #_name "_clk", \
129d9cd9 CM	43	.parent_data = gcc_pxo, \
129d9cd9 CM	44	.num_parents = ARRAY_SIZE(gcc_pxo), \
872f91b5 GD	45	}, \
872f91b5 GD	46	}; \
3de1c1fd	47	static struct clk_rpm clk_rpm_##_name##_a_clk = { \
872f91b5	48	.rpm_clk_id = (r_id), \
3de1c1fd	49	.peer = &clk_rpm_##_name##_clk, \
872f91b5 GD	50	.active_only = true, \
	51	.rate = INT_MAX, \
	52	.hw.init = &(struct clk_init_data){ \
	53	.ops = &clk_rpm_ops, \
35a57cda	54	.name = #_name "_a_clk", \
129d9cd9 CM	55	.parent_data = gcc_pxo, \
129d9cd9 CM	56	.num_parents = ARRAY_SIZE(gcc_pxo), \
872f91b5 GD	57	}, \
	58	}
	59
3de1c1fd DB	60	#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \
3de1c1fd DB	61	static struct clk_rpm clk_rpm_##_name##_clk = { \
8bcde658 SK	62	.rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
	63	.xo_offset = (offset), \
	64	.hw.init = &(struct clk_init_data){ \
fbd5a2cb	65	.ops = &clk_rpm_xo_ops, \
e9bf411a	66	.name = #_name "_clk", \
129d9cd9 CM	67	.parent_data = gcc_cxo, \
129d9cd9 CM	68	.num_parents = ARRAY_SIZE(gcc_cxo), \
8bcde658 SK	69	}, \
	70	}
	71
3de1c1fd DB	72	#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \
3de1c1fd DB	73	static struct clk_rpm clk_rpm_##_name##_clk = { \
d4a69583 LW	74	.rpm_clk_id = (r_id), \
	75	.rate = (r), \
	76	.hw.init = &(struct clk_init_data){ \
	77	.ops = &clk_rpm_fixed_ops, \
e9bf411a	78	.name = #_name "_clk", \
129d9cd9 CM	79	.parent_data = gcc_pxo, \
129d9cd9 CM	80	.num_parents = ARRAY_SIZE(gcc_pxo), \
d4a69583 LW	81	}, \
	82	}
	83
872f91b5 GD	84	#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
872f91b5 GD	85
8bcde658 SK	86	struct rpm_cc;
8bcde658 SK	87
872f91b5 GD	88	struct clk_rpm {
872f91b5 GD	89	const int rpm_clk_id;
8bcde658	90	const int xo_offset;
872f91b5 GD	91	const bool active_only;
	92	unsigned long rate;
	93	bool enabled;
	94	bool branch;
	95	struct clk_rpm *peer;
	96	struct clk_hw hw;
	97	struct qcom_rpm *rpm;
8bcde658	98	struct rpm_cc *rpm_cc;
872f91b5 GD	99	};
	100
	101	struct rpm_cc {
	102	struct qcom_rpm *rpm;
c260524a GD	103	struct clk_rpm **clks;
c260524a GD	104	size_t num_clks;
8bcde658 SK	105	u32 xo_buffer_value;
8bcde658 SK	106	struct mutex xo_lock;
872f91b5 GD	107	};
	108
	109	struct rpm_clk_desc {
	110	struct clk_rpm **clks;
	111	size_t num_clks;
	112	};
	113
	114	static DEFINE_MUTEX(rpm_clk_lock);
	115
	116	static int clk_rpm_handoff(struct clk_rpm *r)
	117	{
	118	int ret;
	119	u32 value = INT_MAX;
	120
d4a69583 LW	121	/*
	122	* The vendor tree simply reads the status for this
	123	* RPM clock.
	124	*/
8bcde658 SK	125	if (r->rpm_clk_id == QCOM_RPM_PLL_4 \|\|
8bcde658 SK	126	r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
d4a69583 LW	127	return 0;
d4a69583 LW	128
872f91b5 GD	129	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
	130	r->rpm_clk_id, &value, 1);
	131	if (ret)
	132	return ret;
	133	ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
	134	r->rpm_clk_id, &value, 1);
	135	if (ret)
	136	return ret;
	137
	138	return 0;
	139	}
	140
	141	static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
	142	{
	143	u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
	144
	145	return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
	146	r->rpm_clk_id, &value, 1);
	147	}
	148
	149	static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
	150	{
	151	u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
	152
	153	return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
	154	r->rpm_clk_id, &value, 1);
	155	}
	156
	157	static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
	158	unsigned long active, unsigned long sleep)
	159	{
	160	*active = rate;
	161
	162	/*
	163	* Active-only clocks don't care what the rate is during sleep. So,
	164	* they vote for zero.
	165	*/
	166	if (r->active_only)
	167	*sleep = 0;
	168	else
	169	sleep = active;
	170	}
	171
	172	static int clk_rpm_prepare(struct clk_hw *hw)
	173	{
	174	struct clk_rpm *r = to_clk_rpm(hw);
	175	struct clk_rpm *peer = r->peer;
	176	unsigned long this_rate = 0, this_sleep_rate = 0;
	177	unsigned long peer_rate = 0, peer_sleep_rate = 0;
	178	unsigned long active_rate, sleep_rate;
	179	int ret = 0;
	180
	181	mutex_lock(&rpm_clk_lock);
	182
	183	/* Don't send requests to the RPM if the rate has not been set. */
	184	if (!r->rate)
	185	goto out;
	186
	187	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
	188
	189	/* Take peer clock's rate into account only if it's enabled. */
	190	if (peer->enabled)
	191	to_active_sleep(peer, peer->rate,
	192	&peer_rate, &peer_sleep_rate);
193
194	active_rate = max(this_rate, peer_rate);
195
196	if (r->branch)
197	active_rate = !!active_rate;
198
199	ret = clk_rpm_set_rate_active(r, active_rate);
200	if (ret)
201	goto out;
202
203	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
204	if (r->branch)
205	sleep_rate = !!sleep_rate;
206
207	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
208	if (ret)
209	/* Undo the active set vote and restore it */
210	ret = clk_rpm_set_rate_active(r, peer_rate);
211
212	out:
213	if (!ret)
214	r->enabled = true;
215
216	mutex_unlock(&rpm_clk_lock);
217
218	return ret;
219	}
220
221	static void clk_rpm_unprepare(struct clk_hw *hw)
222	{
223	struct clk_rpm *r = to_clk_rpm(hw);
224	struct clk_rpm *peer = r->peer;
225	unsigned long peer_rate = 0, peer_sleep_rate = 0;
226	unsigned long active_rate, sleep_rate;
227	int ret;
228
229	mutex_lock(&rpm_clk_lock);
230
231	if (!r->rate)
232	goto out;
233
234	/* Take peer clock's rate into account only if it's enabled. */
235	if (peer->enabled)
236	to_active_sleep(peer, peer->rate, &peer_rate,
237	&peer_sleep_rate);
238
239	active_rate = r->branch ? !!peer_rate : peer_rate;
240	ret = clk_rpm_set_rate_active(r, active_rate);
241	if (ret)
242	goto out;
243
244	sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
245	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
246	if (ret)
247	goto out;
248
249	r->enabled = false;
250
251	out:
252	mutex_unlock(&rpm_clk_lock);
253	}
254
8bcde658 SK	255	static int clk_rpm_xo_prepare(struct clk_hw *hw)
	256	{
	257	struct clk_rpm *r = to_clk_rpm(hw);
	258	struct rpm_cc *rcc = r->rpm_cc;
	259	int ret, clk_id = r->rpm_clk_id;
	260	u32 value;
	261
	262	mutex_lock(&rcc->xo_lock);
	263
	264	value = rcc->xo_buffer_value \| (QCOM_RPM_XO_MODE_ON << r->xo_offset);
	265	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
	266	if (!ret) {
	267	r->enabled = true;
	268	rcc->xo_buffer_value = value;
	269	}
	270
	271	mutex_unlock(&rcc->xo_lock);
	272
	273	return ret;
	274	}
	275
	276	static void clk_rpm_xo_unprepare(struct clk_hw *hw)
	277	{
	278	struct clk_rpm *r = to_clk_rpm(hw);
	279	struct rpm_cc *rcc = r->rpm_cc;
	280	int ret, clk_id = r->rpm_clk_id;
	281	u32 value;
	282
	283	mutex_lock(&rcc->xo_lock);
	284
	285	value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
	286	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
	287	if (!ret) {
	288	r->enabled = false;
	289	rcc->xo_buffer_value = value;
	290	}
	291
	292	mutex_unlock(&rcc->xo_lock);
	293	}
	294
d4a69583 LW	295	static int clk_rpm_fixed_prepare(struct clk_hw *hw)
	296	{
	297	struct clk_rpm *r = to_clk_rpm(hw);
	298	u32 value = 1;
	299	int ret;
	300
	301	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
	302	r->rpm_clk_id, &value, 1);
	303	if (!ret)
	304	r->enabled = true;
	305
	306	return ret;
	307	}
	308
	309	static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
	310	{
	311	struct clk_rpm *r = to_clk_rpm(hw);
	312	u32 value = 0;
	313	int ret;
	314
	315	ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
	316	r->rpm_clk_id, &value, 1);
	317	if (!ret)
	318	r->enabled = false;
	319	}
	320
872f91b5 GD	321	static int clk_rpm_set_rate(struct clk_hw *hw,
	322	unsigned long rate, unsigned long parent_rate)
	323	{
	324	struct clk_rpm *r = to_clk_rpm(hw);
	325	struct clk_rpm *peer = r->peer;
	326	unsigned long active_rate, sleep_rate;
	327	unsigned long this_rate = 0, this_sleep_rate = 0;
	328	unsigned long peer_rate = 0, peer_sleep_rate = 0;
	329	int ret = 0;
	330
	331	mutex_lock(&rpm_clk_lock);
	332
	333	if (!r->enabled)
	334	goto out;
	335
	336	to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
	337
	338	/* Take peer clock's rate into account only if it's enabled. */
	339	if (peer->enabled)
	340	to_active_sleep(peer, peer->rate,
	341	&peer_rate, &peer_sleep_rate);
	342
	343	active_rate = max(this_rate, peer_rate);
	344	ret = clk_rpm_set_rate_active(r, active_rate);
	345	if (ret)
	346	goto out;
	347
	348	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
	349	ret = clk_rpm_set_rate_sleep(r, sleep_rate);
	350	if (ret)
	351	goto out;
	352
	353	r->rate = rate;
	354
	355	out:
	356	mutex_unlock(&rpm_clk_lock);
	357
	358	return ret;
	359	}
	360
	361	static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
	362	unsigned long *parent_rate)
	363	{
	364	/*
	365	* RPM handles rate rounding and we don't have a way to
	366	* know what the rate will be, so just return whatever
	367	* rate is requested.
	368	*/
	369	return rate;
	370	}
	371
	372	static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
	373	unsigned long parent_rate)
	374	{
	375	struct clk_rpm *r = to_clk_rpm(hw);
	376
	377	/*
	378	* RPM handles rate rounding and we don't have a way to
	379	* know what the rate will be, so just return whatever
	380	* rate was set.
	381	*/
	382	return r->rate;
	383	}
	384
8bcde658 SK	385	static const struct clk_ops clk_rpm_xo_ops = {
	386	.prepare = clk_rpm_xo_prepare,
	387	.unprepare = clk_rpm_xo_unprepare,
	388	};
	389
d4a69583 LW	390	static const struct clk_ops clk_rpm_fixed_ops = {
	391	.prepare = clk_rpm_fixed_prepare,
	392	.unprepare = clk_rpm_fixed_unprepare,
	393	.round_rate = clk_rpm_round_rate,
	394	.recalc_rate = clk_rpm_recalc_rate,
	395	};
	396
872f91b5 GD	397	static const struct clk_ops clk_rpm_ops = {
	398	.prepare = clk_rpm_prepare,
	399	.unprepare = clk_rpm_unprepare,
	400	.set_rate = clk_rpm_set_rate,
	401	.round_rate = clk_rpm_round_rate,
	402	.recalc_rate = clk_rpm_recalc_rate,
	403	};
	404
3de1c1fd DB	405	DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
	406	DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
	407	DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
	408	DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
	409	DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
	410	DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
	411	DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
	412	DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
	413	DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
	414
	415	DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
	416	DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
	417	DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
	418
	419	DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
	420
	421	DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
	422	DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
	423	DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
	424	DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
	425	DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
d4a69583 LW	426
d4a69583 LW	427	static struct clk_rpm *msm8660_clks[] = {
3de1c1fd DB	428	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	429	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	430	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	431	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	432	[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
	433	[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
	434	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	435	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	436	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	437	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	438	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	439	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	440	[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
	441	[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
	442	[RPM_SMI_CLK] = &clk_rpm_smi_clk,
	443	[RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
	444	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	445	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	446	[RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
d4a69583 LW	447	};
	448
	449	static const struct rpm_clk_desc rpm_clk_msm8660 = {
	450	.clks = msm8660_clks,
	451	.num_clks = ARRAY_SIZE(msm8660_clks),
	452	};
	453
872f91b5	454	static struct clk_rpm *apq8064_clks[] = {
3de1c1fd DB	455	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	456	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	457	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	458	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	459	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	460	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	461	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	462	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	463	[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
	464	[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
	465	[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
	466	[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
	467	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	468	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	469	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	470	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	471	[RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
	472	[RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
	473	[RPM_XO_D0] = &clk_rpm_xo_d0_clk,
	474	[RPM_XO_D1] = &clk_rpm_xo_d1_clk,
	475	[RPM_XO_A0] = &clk_rpm_xo_a0_clk,
	476	[RPM_XO_A1] = &clk_rpm_xo_a1_clk,
	477	[RPM_XO_A2] = &clk_rpm_xo_a2_clk,
872f91b5 GD	478	};
	479
	480	static const struct rpm_clk_desc rpm_clk_apq8064 = {
	481	.clks = apq8064_clks,
	482	.num_clks = ARRAY_SIZE(apq8064_clks),
	483	};
	484
eec15273	485	static struct clk_rpm *ipq806x_clks[] = {
3de1c1fd DB	486	[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
	487	[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
	488	[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
	489	[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
	490	[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
	491	[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
	492	[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
	493	[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
	494	[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
	495	[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
	496	[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
	497	[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
	498	[RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
	499	[RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
	500	[RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
	501	[RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
eec15273 AS	502	};
	503
	504	static const struct rpm_clk_desc rpm_clk_ipq806x = {
	505	.clks = ipq806x_clks,
	506	.num_clks = ARRAY_SIZE(ipq806x_clks),
	507	};
	508
872f91b5	509	static const struct of_device_id rpm_clk_match_table[] = {
d4a69583 LW	510	{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
d4a69583 LW	511	{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
872f91b5	512	{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
eec15273	513	{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
872f91b5 GD	514	{ }
	515	};
	516	MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
	517
c260524a GD	518	static struct clk_hw qcom_rpm_clk_hw_get(struct of_phandle_args clkspec,
	519	void *data)
	520	{
	521	struct rpm_cc *rcc = data;
	522	unsigned int idx = clkspec->args[0];
	523
	524	if (idx >= rcc->num_clks) {
	525	pr_err("%s: invalid index %u\n", __func__, idx);
	526	return ERR_PTR(-EINVAL);
	527	}
	528
	529	return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
	530	}
	531
872f91b5 GD	532	static int rpm_clk_probe(struct platform_device *pdev)
872f91b5 GD	533	{
872f91b5	534	struct rpm_cc *rcc;
872f91b5 GD	535	int ret;
	536	size_t num_clks, i;
	537	struct qcom_rpm *rpm;
	538	struct clk_rpm **rpm_clks;
	539	const struct rpm_clk_desc *desc;
	540
	541	rpm = dev_get_drvdata(pdev->dev.parent);
	542	if (!rpm) {
	543	dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
	544	return -ENODEV;
	545	}
	546
	547	desc = of_device_get_match_data(&pdev->dev);
	548	if (!desc)
	549	return -EINVAL;
	550
	551	rpm_clks = desc->clks;
	552	num_clks = desc->num_clks;
	553
c260524a	554	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
872f91b5 GD	555	if (!rcc)
	556	return -ENOMEM;
	557
c260524a GD	558	rcc->clks = rpm_clks;
c260524a GD	559	rcc->num_clks = num_clks;
8bcde658	560	mutex_init(&rcc->xo_lock);
872f91b5 GD	561
	562	for (i = 0; i < num_clks; i++) {
	563	if (!rpm_clks[i])
	564	continue;
	565
	566	rpm_clks[i]->rpm = rpm;
8bcde658	567	rpm_clks[i]->rpm_cc = rcc;
872f91b5 GD	568
	569	ret = clk_rpm_handoff(rpm_clks[i]);
	570	if (ret)
	571	goto err;
	572	}
	573
	574	for (i = 0; i < num_clks; i++) {
c260524a	575	if (!rpm_clks[i])
872f91b5	576	continue;
872f91b5 GD	577
	578	ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
	579	if (ret)
	580	goto err;
	581	}
	582
f1f67db9 LPC	583	ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,
f1f67db9 LPC	584	rcc);
872f91b5 GD	585	if (ret)
	586	goto err;
	587
	588	return 0;
	589	err:
	590	dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
	591	return ret;
	592	}
	593
872f91b5 GD	594	static struct platform_driver rpm_clk_driver = {
	595	.driver = {
	596	.name = "qcom-clk-rpm",
	597	.of_match_table = rpm_clk_match_table,
	598	},
	599	.probe = rpm_clk_probe,
872f91b5 GD	600	};
	601
	602	static int __init rpm_clk_init(void)
	603	{
	604	return platform_driver_register(&rpm_clk_driver);
	605	}
	606	core_initcall(rpm_clk_init);
	607
	608	static void __exit rpm_clk_exit(void)
	609	{
	610	platform_driver_unregister(&rpm_clk_driver);
	611	}
	612	module_exit(rpm_clk_exit);
	613
	614	MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
	615	MODULE_LICENSE("GPL v2");
	616	MODULE_ALIAS("platform:qcom-clk-rpm");