Commit | Line | Data |
---|---|---|
7ef6f118 AN |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */ | |
bcd61c0f SB |
3 | |
4 | #ifndef __QCOM_CLK_RCG_H__ | |
5 | #define __QCOM_CLK_RCG_H__ | |
6 | ||
7 | #include <linux/clk-provider.h> | |
8 | #include "clk-regmap.h" | |
9 | ||
da172d2b TD |
10 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
11 | ||
bcd61c0f SB |
12 | struct freq_tbl { |
13 | unsigned long freq; | |
14 | u8 src; | |
15 | u8 pre_div; | |
16 | u16 m; | |
17 | u16 n; | |
18 | }; | |
19 | ||
20 | /** | |
21 | * struct mn - M/N:D counter | |
22 | * @mnctr_en_bit: bit to enable mn counter | |
23 | * @mnctr_reset_bit: bit to assert mn counter reset | |
24 | * @mnctr_mode_shift: lowest bit of mn counter mode field | |
25 | * @n_val_shift: lowest bit of n value field | |
26 | * @m_val_shift: lowest bit of m value field | |
27 | * @width: number of bits in m/n/d values | |
28 | * @reset_in_cc: true if the mnctr_reset_bit is in the CC register | |
29 | */ | |
30 | struct mn { | |
31 | u8 mnctr_en_bit; | |
32 | u8 mnctr_reset_bit; | |
33 | u8 mnctr_mode_shift; | |
34 | #define MNCTR_MODE_DUAL 0x2 | |
35 | #define MNCTR_MODE_MASK 0x3 | |
36 | u8 n_val_shift; | |
37 | u8 m_val_shift; | |
38 | u8 width; | |
39 | bool reset_in_cc; | |
40 | }; | |
41 | ||
42 | /** | |
43 | * struct pre_div - pre-divider | |
44 | * @pre_div_shift: lowest bit of pre divider field | |
45 | * @pre_div_width: number of bits in predivider | |
46 | */ | |
47 | struct pre_div { | |
48 | u8 pre_div_shift; | |
49 | u8 pre_div_width; | |
50 | }; | |
51 | ||
52 | /** | |
53 | * struct src_sel - source selector | |
54 | * @src_sel_shift: lowest bit of source selection field | |
55 | * @parent_map: map from software's parent index to hardware's src_sel field | |
56 | */ | |
57 | struct src_sel { | |
58 | u8 src_sel_shift; | |
59 | #define SRC_SEL_MASK 0x7 | |
293d2e97 | 60 | const struct parent_map *parent_map; |
bcd61c0f SB |
61 | }; |
62 | ||
63 | /** | |
64 | * struct clk_rcg - root clock generator | |
65 | * | |
66 | * @ns_reg: NS register | |
67 | * @md_reg: MD register | |
68 | * @mn: mn counter | |
69 | * @p: pre divider | |
70 | * @s: source selector | |
71 | * @freq_tbl: frequency table | |
72 | * @clkr: regmap clock handle | |
73 | * @lock: register lock | |
74 | * | |
75 | */ | |
76 | struct clk_rcg { | |
77 | u32 ns_reg; | |
78 | u32 md_reg; | |
79 | ||
80 | struct mn mn; | |
81 | struct pre_div p; | |
82 | struct src_sel s; | |
83 | ||
84 | const struct freq_tbl *freq_tbl; | |
85 | ||
86 | struct clk_regmap clkr; | |
87 | }; | |
88 | ||
89 | extern const struct clk_ops clk_rcg_ops; | |
404c1ff6 | 90 | extern const struct clk_ops clk_rcg_bypass_ops; |
d8aa2bee AT |
91 | extern const struct clk_ops clk_rcg_bypass2_ops; |
92 | extern const struct clk_ops clk_rcg_pixel_ops; | |
93 | extern const struct clk_ops clk_rcg_esc_ops; | |
9d3745d4 | 94 | extern const struct clk_ops clk_rcg_lcc_ops; |
bcd61c0f SB |
95 | |
96 | #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) | |
97 | ||
98 | /** | |
99 | * struct clk_dyn_rcg - root clock generator with glitch free mux | |
100 | * | |
101 | * @mux_sel_bit: bit to switch glitch free mux | |
229fd4a5 | 102 | * @ns_reg: NS0 and NS1 register |
bcd61c0f | 103 | * @md_reg: MD0 and MD1 register |
229fd4a5 | 104 | * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux |
bcd61c0f SB |
105 | * @mn: mn counter (banked) |
106 | * @s: source selector (banked) | |
107 | * @freq_tbl: frequency table | |
108 | * @clkr: regmap clock handle | |
109 | * @lock: register lock | |
110 | * | |
111 | */ | |
112 | struct clk_dyn_rcg { | |
229fd4a5 | 113 | u32 ns_reg[2]; |
bcd61c0f | 114 | u32 md_reg[2]; |
229fd4a5 | 115 | u32 bank_reg; |
bcd61c0f SB |
116 | |
117 | u8 mux_sel_bit; | |
118 | ||
119 | struct mn mn[2]; | |
120 | struct pre_div p[2]; | |
121 | struct src_sel s[2]; | |
122 | ||
123 | const struct freq_tbl *freq_tbl; | |
124 | ||
125 | struct clk_regmap clkr; | |
126 | }; | |
127 | ||
128 | extern const struct clk_ops clk_dyn_rcg_ops; | |
129 | ||
130 | #define to_clk_dyn_rcg(_hw) \ | |
131 | container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr) | |
132 | ||
133 | /** | |
134 | * struct clk_rcg2 - root clock generator | |
135 | * | |
136 | * @cmd_rcgr: corresponds to *_CMD_RCGR | |
137 | * @mnd_width: number of bits in m/n/d values | |
138 | * @hid_width: number of bits in half integer divider | |
7ef6f118 | 139 | * @safe_src_index: safe src index value |
bcd61c0f SB |
140 | * @parent_map: map from software's parent index to hardware's src_sel field |
141 | * @freq_tbl: frequency table | |
142 | * @clkr: regmap clock handle | |
bcd61c0f SB |
143 | * |
144 | */ | |
145 | struct clk_rcg2 { | |
146 | u32 cmd_rcgr; | |
147 | u8 mnd_width; | |
148 | u8 hid_width; | |
7ef6f118 | 149 | u8 safe_src_index; |
293d2e97 | 150 | const struct parent_map *parent_map; |
bcd61c0f SB |
151 | const struct freq_tbl *freq_tbl; |
152 | struct clk_regmap clkr; | |
153 | }; | |
154 | ||
155 | #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) | |
156 | ||
157 | extern const struct clk_ops clk_rcg2_ops; | |
081ba802 | 158 | extern const struct clk_ops clk_rcg2_floor_ops; |
99cbd064 SB |
159 | extern const struct clk_ops clk_edp_pixel_ops; |
160 | extern const struct clk_ops clk_byte_ops; | |
8ee9c7de | 161 | extern const struct clk_ops clk_byte2_ops; |
99cbd064 | 162 | extern const struct clk_ops clk_pixel_ops; |
55213e1a | 163 | extern const struct clk_ops clk_gfx3d_ops; |
7ef6f118 | 164 | extern const struct clk_ops clk_rcg2_shared_ops; |
bcd61c0f SB |
165 | |
166 | #endif |