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9e263131 SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/export.h> | |
20 | #include <linux/clk-provider.h> | |
21 | #include <linux/regmap.h> | |
22 | ||
23 | #include <asm/div64.h> | |
24 | ||
25 | #include "clk-pll.h" | |
26 | ||
27 | #define PLL_OUTCTRL BIT(0) | |
28 | #define PLL_BYPASSNL BIT(1) | |
29 | #define PLL_RESET_N BIT(2) | |
30 | #define PLL_LOCK_COUNT_SHIFT 8 | |
31 | #define PLL_LOCK_COUNT_MASK 0x3f | |
32 | #define PLL_BIAS_COUNT_SHIFT 14 | |
33 | #define PLL_BIAS_COUNT_MASK 0x3f | |
34 | #define PLL_VOTE_FSM_ENA BIT(20) | |
35 | #define PLL_VOTE_FSM_RESET BIT(21) | |
36 | ||
37 | static int clk_pll_enable(struct clk_hw *hw) | |
38 | { | |
39 | struct clk_pll *pll = to_clk_pll(hw); | |
40 | int ret; | |
41 | u32 mask, val; | |
42 | ||
43 | mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; | |
44 | ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); | |
45 | if (ret) | |
46 | return ret; | |
47 | ||
48 | /* Skip if already enabled or in FSM mode */ | |
49 | if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA) | |
50 | return 0; | |
51 | ||
52 | /* Disable PLL bypass mode. */ | |
53 | ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, | |
54 | PLL_BYPASSNL); | |
55 | if (ret) | |
56 | return ret; | |
57 | ||
58 | /* | |
59 | * H/W requires a 5us delay between disabling the bypass and | |
60 | * de-asserting the reset. Delay 10us just to be safe. | |
61 | */ | |
62 | udelay(10); | |
63 | ||
64 | /* De-assert active-low PLL reset. */ | |
65 | ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, | |
66 | PLL_RESET_N); | |
67 | if (ret) | |
68 | return ret; | |
69 | ||
70 | /* Wait until PLL is locked. */ | |
71 | udelay(50); | |
72 | ||
73 | /* Enable PLL output. */ | |
74 | ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, | |
75 | PLL_OUTCTRL); | |
76 | if (ret) | |
77 | return ret; | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | static void clk_pll_disable(struct clk_hw *hw) | |
83 | { | |
84 | struct clk_pll *pll = to_clk_pll(hw); | |
85 | u32 mask; | |
86 | u32 val; | |
87 | ||
88 | regmap_read(pll->clkr.regmap, pll->mode_reg, &val); | |
89 | /* Skip if in FSM mode */ | |
90 | if (val & PLL_VOTE_FSM_ENA) | |
91 | return; | |
92 | mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; | |
93 | regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); | |
94 | } | |
95 | ||
96 | static unsigned long | |
97 | clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | |
98 | { | |
99 | struct clk_pll *pll = to_clk_pll(hw); | |
100 | u32 l, m, n; | |
101 | unsigned long rate; | |
102 | u64 tmp; | |
103 | ||
104 | regmap_read(pll->clkr.regmap, pll->l_reg, &l); | |
105 | regmap_read(pll->clkr.regmap, pll->m_reg, &m); | |
106 | regmap_read(pll->clkr.regmap, pll->n_reg, &n); | |
107 | ||
108 | l &= 0x3ff; | |
109 | m &= 0x7ffff; | |
110 | n &= 0x7ffff; | |
111 | ||
112 | rate = parent_rate * l; | |
113 | if (n) { | |
114 | tmp = parent_rate; | |
115 | tmp *= m; | |
116 | do_div(tmp, n); | |
117 | rate += tmp; | |
118 | } | |
119 | return rate; | |
120 | } | |
121 | ||
122 | const struct clk_ops clk_pll_ops = { | |
123 | .enable = clk_pll_enable, | |
124 | .disable = clk_pll_disable, | |
125 | .recalc_rate = clk_pll_recalc_rate, | |
126 | }; | |
127 | EXPORT_SYMBOL_GPL(clk_pll_ops); | |
128 | ||
129 | static int wait_for_pll(struct clk_pll *pll) | |
130 | { | |
131 | u32 val; | |
132 | int count; | |
133 | int ret; | |
134 | const char *name = __clk_get_name(pll->clkr.hw.clk); | |
135 | ||
136 | /* Wait for pll to enable. */ | |
137 | for (count = 200; count > 0; count--) { | |
138 | ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val); | |
139 | if (ret) | |
140 | return ret; | |
141 | if (val & BIT(pll->status_bit)) | |
142 | return 0; | |
143 | udelay(1); | |
144 | } | |
145 | ||
146 | WARN(1, "%s didn't enable after voting for it!\n", name); | |
147 | return -ETIMEDOUT; | |
148 | } | |
149 | ||
150 | static int clk_pll_vote_enable(struct clk_hw *hw) | |
151 | { | |
152 | int ret; | |
153 | struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk))); | |
154 | ||
155 | ret = clk_enable_regmap(hw); | |
156 | if (ret) | |
157 | return ret; | |
158 | ||
159 | return wait_for_pll(p); | |
160 | } | |
161 | ||
162 | const struct clk_ops clk_pll_vote_ops = { | |
163 | .enable = clk_pll_vote_enable, | |
164 | .disable = clk_disable_regmap, | |
165 | }; | |
166 | EXPORT_SYMBOL_GPL(clk_pll_vote_ops); | |
167 | ||
168 | static void | |
169 | clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) | |
170 | { | |
171 | u32 val; | |
172 | u32 mask; | |
173 | ||
174 | /* De-assert reset to FSM */ | |
175 | regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); | |
176 | ||
177 | /* Program bias count and lock count */ | |
178 | val = 1 << PLL_BIAS_COUNT_SHIFT; | |
179 | mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; | |
180 | mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; | |
181 | regmap_update_bits(regmap, pll->mode_reg, mask, val); | |
182 | ||
183 | /* Enable PLL FSM voting */ | |
184 | regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA, | |
185 | PLL_VOTE_FSM_ENA); | |
186 | } | |
187 | ||
188 | static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, | |
189 | const struct pll_config *config) | |
190 | { | |
191 | u32 val; | |
192 | u32 mask; | |
193 | ||
194 | regmap_write(regmap, pll->l_reg, config->l); | |
195 | regmap_write(regmap, pll->m_reg, config->m); | |
196 | regmap_write(regmap, pll->n_reg, config->n); | |
197 | ||
198 | val = config->vco_val; | |
199 | val |= config->pre_div_val; | |
200 | val |= config->post_div_val; | |
201 | val |= config->mn_ena_mask; | |
202 | val |= config->main_output_mask; | |
203 | val |= config->aux_output_mask; | |
204 | ||
205 | mask = config->vco_mask; | |
206 | mask |= config->pre_div_mask; | |
207 | mask |= config->post_div_mask; | |
208 | mask |= config->mn_ena_mask; | |
209 | mask |= config->main_output_mask; | |
210 | mask |= config->aux_output_mask; | |
211 | ||
212 | regmap_update_bits(regmap, pll->config_reg, mask, val); | |
213 | } | |
214 | ||
215 | void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, | |
216 | const struct pll_config *config, bool fsm_mode) | |
217 | { | |
218 | clk_pll_configure(pll, regmap, config); | |
219 | if (fsm_mode) | |
220 | clk_pll_set_fsm_mode(pll, regmap); | |
221 | } | |
222 | EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); |