[linux-block.git] / drivers / clk / pxa / clk-pxa27x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Marvell PXA27x family clocks
 *
 * Copyright (C) 2014 Robert Jarzmik
 *
 * Heavily inspired from former arch/arm/mach-pxa/clock.c.
 */
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/soc/pxa/smemc.h>

#include <dt-bindings/clock/pxa-clock.h>
#include "clk-pxa.h"
#include "clk-pxa2xx.h"

#define KHz 1000
#define MHz (1000 * 1000)

enum {
	PXA_CORE_13Mhz = 0,
	PXA_CORE_RUN,
	PXA_CORE_TURBO,
};

enum {
	PXA_BUS_13Mhz = 0,
	PXA_BUS_RUN,
};

enum {
	PXA_LCD_13Mhz = 0,
	PXA_LCD_RUN,
};

enum {
	PXA_MEM_13Mhz = 0,
	PXA_MEM_SYSTEM_BUS,
	PXA_MEM_RUN,
};

#define PXA27x_CLKCFG(B, HT, T)			\
	(CLKCFG_FCS |				\
	 ((B)  ? CLKCFG_FASTBUS : 0) |		\
	 ((HT) ? CLKCFG_HALFTURBO : 0) |	\
	 ((T)  ? CLKCFG_TURBO : 0))
#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)

/* Define the refresh period in mSec for the SDRAM and the number of rows */
#define SDRAM_TREF	64	/* standard 64ms SDRAM */

static void __iomem *clk_regs;

static const char * const get_freq_khz[] = {
	"core", "run", "cpll", "memory",
	"system_bus"
};

static u32 mdrefr_dri(unsigned int freq_khz)
{
	u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();

	return (interval - 31) / 32;
}

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	struct clk *clk;
	unsigned long clks[5];
	int i;

	for (i = 0; i < 5; i++) {
		clk = clk_get(NULL, get_freq_khz[i]);
		if (IS_ERR(clk)) {
			clks[i] = 0;
		} else {
			clks[i] = clk_get_rate(clk);
			clk_put(clk);
		}
	}
	if (info) {
		pr_info("Run Mode clock: %ld.%02ldMHz\n",
			clks[1] / 1000000, (clks[1] % 1000000) / 10000);
		pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
			clks[2] / 1000000, (clks[2] % 1000000) / 10000);
		pr_info("Memory clock: %ld.%02ldMHz\n",
			clks[3] / 1000000, (clks[3] % 1000000) / 10000);
		pr_info("System bus clock: %ld.%02ldMHz\n",
			clks[4] / 1000000, (clks[4] % 1000000) / 10000);
	}
	return (unsigned int)clks[0] / KHz;
}

bool pxa27x_is_ppll_disabled(void)
{
	unsigned long ccsr = readl(clk_regs + CCSR);

	return ccsr & (1 << CCCR_PPDIS_BIT);
}

#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp,		\
		    bit, is_lp, flags)					\
	PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp,	\
		 is_lp,  CKEN, CKEN_ ## bit, flags)
#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)	\
	PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp,	\
		    div_hp, bit, pxa27x_is_ppll_disabled, 0)

PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };

#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)		\
	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\
		       CKEN, CKEN_ ## bit, 0)
#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)	\
	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\
		       CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)

static struct desc_clk_cken pxa27x_clocks[] __initdata = {
	PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
	PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
	PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
	PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
	PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
	PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
	PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
	PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
	PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
	PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
	PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
	PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
	PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
	PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
	PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
	PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
	PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
	PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
	PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
	PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
	PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),

	PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
			  pxa27x_32Mhz_bus_parents, 0),
	PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
	PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
	PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
			  pxa27x_lcd_bus_parents, 0),
	PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
			     pxa27x_membus_parents, 0),

};

/*
 * PXA270 definitions
 *
 * For the PXA27x:
 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
 *
 * A = 0 => memory controller clock from table 3-7,
 * A = 1 => memory controller clock = system bus clock
 * Run mode frequency	= 13 MHz * L
 * Turbo mode frequency = 13 MHz * L * N
 * System bus frequency = 13 MHz * L / (B + 1)
 *
 * In CCCR:
 * A = 1
 * L = 16	  oscillator to run mode ratio
 * 2N = 6	  2 * (turbo mode to run mode ratio)
 *
 * In CCLKCFG:
 * B = 1	  Fast bus mode
 * HT = 0	  Half-Turbo mode
 * T = 1	  Turbo mode
 *
 * For now, just support some of the combinations in table 3-7 of
 * PXA27x Processor Family Developer's Manual to simplify frequency
 * change sequences.
 */
static struct pxa2xx_freq pxa27x_freqs[] = {
	{104000000, 104000, PXA27x_CCCR(1,  8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
	{156000000, 104000, PXA27x_CCCR(1,  8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
	{208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
	{312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
	{416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
	{520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
	{624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
};

static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
	unsigned long parent_rate)
{
	unsigned long clkcfg;
	unsigned int t, ht;
	unsigned int l, L, n2, N;
	unsigned long ccsr = readl(clk_regs + CCSR);

	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);

	l  = ccsr & CCSR_L_MASK;
	n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
	L  = l * parent_rate;
	N  = (L * n2) / 2;

	return N;
}

static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
					  struct clk_rate_request *req)
{
	return pxa2xx_determine_rate(req, pxa27x_freqs,
				     ARRAY_SIZE(pxa27x_freqs));
}

static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{
	int i;

	pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
	for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
		if (pxa27x_freqs[i].cpll == rate)
			break;

	if (i >= ARRAY_SIZE(pxa27x_freqs))
		return -EINVAL;

	pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR);
	return 0;
}

PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
RATE_OPS(clk_pxa27x_cpll, "cpll");

static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
						  unsigned long parent_rate)
{
	unsigned int l, osc_forced;
	unsigned long ccsr = readl(clk_regs + CCSR);
	unsigned long cccr = readl(clk_regs + CCCR);

	l  = ccsr & CCSR_L_MASK;
	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	if (osc_forced) {
		if (cccr & (1 << CCCR_LCD_26_BIT))
			return parent_rate * 2;
		else
			return parent_rate;
	}

	if (l <= 7)
		return parent_rate;
	if (l <= 16)
		return parent_rate / 2;
	return parent_rate / 4;
}

static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
{
	unsigned int osc_forced;
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	if (osc_forced)
		return PXA_LCD_13Mhz;
	else
		return PXA_LCD_RUN;
}

PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");

static void __init pxa27x_register_plls(void)
{
	clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
				CLK_GET_RATE_NOCACHE,
				13 * MHz);
	clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
			    clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
						    CLK_GET_RATE_NOCACHE,
						    32768 * KHz));
	clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
	clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
}

static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
{
	unsigned long clkcfg;
	unsigned int t, ht, osc_forced;
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	if (osc_forced)
		return PXA_CORE_13Mhz;

	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);

	if (ht || t)
		return PXA_CORE_TURBO;
	return PXA_CORE_RUN;
}

static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
{
	if (index > PXA_CORE_TURBO)
		return -EINVAL;

	pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);

	return 0;
}

static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
					  struct clk_rate_request *req)
{
	return __clk_mux_determine_rate(hw, req);
}

PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);

static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{
	unsigned long ccsr = readl(clk_regs + CCSR);
	unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;

	return (parent_rate / n2) * 2;
}
PARENTS(clk_pxa27x_run) = { "cpll" };
RATE_RO_OPS(clk_pxa27x_run, "run");

static void __init pxa27x_register_core(void)
{
	clkdev_pxa_register(CLK_NONE, "cpll", NULL,
			    clk_register_clk_pxa27x_cpll());
	clkdev_pxa_register(CLK_NONE, "run", NULL,
			    clk_register_clk_pxa27x_run());
	clkdev_pxa_register(CLK_CORE, "core", NULL,
			    clk_register_clk_pxa27x_core());
}

static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
						    unsigned long parent_rate)
{
	unsigned long clkcfg;
	unsigned int b, osc_forced;
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	b  = clkcfg & (1 << 3);

	if (osc_forced)
		return parent_rate;
	if (b)
		return parent_rate;
	else
		return parent_rate / 2;
}

static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
{
	unsigned int osc_forced;
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	if (osc_forced)
		return PXA_BUS_13Mhz;
	else
		return PXA_BUS_RUN;
}

PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");

static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	unsigned int a, l, osc_forced;
	unsigned long cccr = readl(clk_regs + CCCR);
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	a = cccr & (1 << CCCR_A_BIT);
	l  = ccsr & CCSR_L_MASK;

	if (osc_forced || a)
		return parent_rate;
	if (l <= 10)
		return parent_rate;
	if (l <= 20)
		return parent_rate / 2;
	return parent_rate / 4;
}

static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
{
	unsigned int osc_forced, a;
	unsigned long cccr = readl(clk_regs + CCCR);
	unsigned long ccsr = readl(clk_regs + CCSR);

	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	a = cccr & (1 << CCCR_A_BIT);
	if (osc_forced)
		return PXA_MEM_13Mhz;
	if (a)
		return PXA_MEM_SYSTEM_BUS;
	else
		return PXA_MEM_RUN;
}

PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");

#define DUMMY_CLK(_con_id, _dev_id, _parent) \
	{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
struct dummy_clk {
	const char *con_id;
	const char *dev_id;
	const char *parent;
};
static struct dummy_clk dummy_clks[] __initdata = {
	DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
	DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
};

static void __init pxa27x_dummy_clocks_init(void)
{
	struct clk *clk;
	struct dummy_clk *d;
	const char *name;
	int i;

	for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
		d = &dummy_clks[i];
		name = d->dev_id ? d->dev_id : d->con_id;
		clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
		clk_register_clkdev(clk, d->con_id, d->dev_id);
	}
}

static void __init pxa27x_base_clocks_init(void)
{
	pxa27x_register_plls();
	pxa27x_register_core();
	clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
			    clk_register_clk_pxa27x_system_bus());
	clkdev_pxa_register(CLK_NONE, "memory", NULL,
			    clk_register_clk_pxa27x_memory());
	clk_register_clk_pxa27x_lcd_base();
}

int __init pxa27x_clocks_init(void __iomem *regs)
{
	clk_regs = regs;
	pxa27x_base_clocks_init();
	pxa27x_dummy_clocks_init();
	return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs);
}

static void __init pxa27x_dt_clocks_init(struct device_node *np)
{
	pxa27x_clocks_init(ioremap(0x41300000ul, 0x10));
	clk_pxa_dt_common_init(np);
}
CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
Commit	Line	Data
b886d83c	1	// SPDX-License-Identifier: GPL-2.0-only
d40670dc RJ	2	/*
	3	* Marvell PXA27x family clocks
	4	*
	5	* Copyright (C) 2014 Robert Jarzmik
	6	*
	7	* Heavily inspired from former arch/arm/mach-pxa/clock.c.
d40670dc RJ	8	*/
d40670dc RJ	9	#include <linux/clk-provider.h>
d40670dc RJ	10	#include <linux/io.h>
	11	#include <linux/clk.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/of.h>
fd13f811	14	#include <linux/soc/pxa/smemc.h>
9fe69429	15
d40670dc RJ	16	#include <dt-bindings/clock/pxa-clock.h>
d40670dc RJ	17	#include "clk-pxa.h"
3c816d95	18	#include "clk-pxa2xx.h"
d40670dc RJ	19
	20	#define KHz 1000
	21	#define MHz (1000 * 1000)
	22
	23	enum {
	24	PXA_CORE_13Mhz = 0,
	25	PXA_CORE_RUN,
	26	PXA_CORE_TURBO,
	27	};
	28
	29	enum {
	30	PXA_BUS_13Mhz = 0,
	31	PXA_BUS_RUN,
	32	};
	33
	34	enum {
	35	PXA_LCD_13Mhz = 0,
	36	PXA_LCD_RUN,
	37	};
	38
	39	enum {
	40	PXA_MEM_13Mhz = 0,
	41	PXA_MEM_SYSTEM_BUS,
	42	PXA_MEM_RUN,
	43	};
	44
9fe69429 RJ	45	#define PXA27x_CLKCFG(B, HT, T) \
	46	(CLKCFG_FCS \| \
	47	((B) ? CLKCFG_FASTBUS : 0) \| \
	48	((HT) ? CLKCFG_HALFTURBO : 0) \| \
	49	((T) ? CLKCFG_TURBO : 0))
	50	#define PXA27x_CCCR(A, L, N2) (A << 25 \| N2 << 7 \| L)
	51
9fe69429 RJ	52	/* Define the refresh period in mSec for the SDRAM and the number of rows */
	53	#define SDRAM_TREF 64 /* standard 64ms SDRAM */
	54
3c816d95 AB	55	static void __iomem *clk_regs;
3c816d95 AB	56
d40670dc RJ	57	static const char * const get_freq_khz[] = {
	58	"core", "run", "cpll", "memory",
	59	"system_bus"
	60	};
	61
9fe69429 RJ	62	static u32 mdrefr_dri(unsigned int freq_khz)
9fe69429 RJ	63	{
fd13f811	64	u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
9fe69429 RJ	65
	66	return (interval - 31) / 32;
	67	}
	68
d40670dc RJ	69	/*
	70	* Get the clock frequency as reflected by CCSR and the turbo flag.
	71	* We assume these values have been applied via a fcs.
	72	* If info is not 0 we also display the current settings.
	73	*/
	74	unsigned int pxa27x_get_clk_frequency_khz(int info)
	75	{
	76	struct clk *clk;
	77	unsigned long clks[5];
	78	int i;
	79
	80	for (i = 0; i < 5; i++) {
	81	clk = clk_get(NULL, get_freq_khz[i]);
	82	if (IS_ERR(clk)) {
	83	clks[i] = 0;
	84	} else {
	85	clks[i] = clk_get_rate(clk);
	86	clk_put(clk);
	87	}
	88	}
	89	if (info) {
	90	pr_info("Run Mode clock: %ld.%02ldMHz\n",
	91	clks[1] / 1000000, (clks[1] % 1000000) / 10000);
	92	pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
	93	clks[2] / 1000000, (clks[2] % 1000000) / 10000);
	94	pr_info("Memory clock: %ld.%02ldMHz\n",
	95	clks[3] / 1000000, (clks[3] % 1000000) / 10000);
	96	pr_info("System bus clock: %ld.%02ldMHz\n",
	97	clks[4] / 1000000, (clks[4] % 1000000) / 10000);
	98	}
4b5fb7dc	99	return (unsigned int)clks[0] / KHz;
d40670dc RJ	100	}
	101
	102	bool pxa27x_is_ppll_disabled(void)
	103	{
3c816d95	104	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	105
	106	return ccsr & (1 << CCCR_PPDIS_BIT);
	107	}
	108
	109	#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
	110	bit, is_lp, flags) \
	111	PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
ea7743e2	112	is_lp, CKEN, CKEN_ ## bit, flags)
d40670dc RJ	113	#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
	114	PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
	115	div_hp, bit, pxa27x_is_ppll_disabled, 0)
	116
	117	PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
	118	PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
	119	PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
	120	PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
	121	PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
	122
	123	#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
	124	PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
ea7743e2	125	CKEN, CKEN_ ## bit, 0)
d40670dc RJ	126	#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
d40670dc RJ	127	PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
ea7743e2	128	CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
d40670dc	129
14dd5b01	130	static struct desc_clk_cken pxa27x_clocks[] __initdata = {
d40670dc RJ	131	PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
	132	PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
	133	PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
	134	PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
	135	PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
	136	PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
	137	PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
	138	PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
	139	PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
	140	PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
	141	PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
	142	PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
	143	PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
	144	PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
	145	PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
	146	PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
	147	PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
	148	PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
	149	PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
	150	PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
	151	PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
	152
	153	PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
	154	pxa27x_32Mhz_bus_parents, 0),
	155	PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
	156	PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
	157	PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
	158	pxa27x_lcd_bus_parents, 0),
	159	PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
	160	pxa27x_membus_parents, 0),
	161
	162	};
	163
9fe69429 RJ	164	/*
	165	* PXA270 definitions
	166	*
	167	* For the PXA27x:
	168	* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
	169	*
	170	* A = 0 => memory controller clock from table 3-7,
	171	* A = 1 => memory controller clock = system bus clock
	172	* Run mode frequency = 13 MHz * L
	173	* Turbo mode frequency = 13 MHz * L * N
	174	* System bus frequency = 13 MHz * L / (B + 1)
	175	*
	176	* In CCCR:
	177	* A = 1
	178	* L = 16 oscillator to run mode ratio
	179	* 2N = 6 2 * (turbo mode to run mode ratio)
	180	*
	181	* In CCLKCFG:
	182	* B = 1 Fast bus mode
	183	* HT = 0 Half-Turbo mode
	184	* T = 1 Turbo mode
	185	*
	186	* For now, just support some of the combinations in table 3-7 of
	187	* PXA27x Processor Family Developer's Manual to simplify frequency
	188	* change sequences.
	189	*/
	190	static struct pxa2xx_freq pxa27x_freqs[] = {
	191	{104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
	192	{156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
	193	{208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
	194	{312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
	195	{416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
	196	{520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
	197	{624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
	198	};
	199
d40670dc RJ	200	static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
	201	unsigned long parent_rate)
	202	{
	203	unsigned long clkcfg;
	204	unsigned int t, ht;
	205	unsigned int l, L, n2, N;
3c816d95	206	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	207
	208	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	209	t = clkcfg & (1 << 0);
	210	ht = clkcfg & (1 << 2);
	211
	212	l = ccsr & CCSR_L_MASK;
	213	n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
	214	L = l * parent_rate;
	215	N = (L * n2) / 2;
	216
26bd423b	217	return N;
d40670dc	218	}
9fe69429 RJ	219
	220	static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
	221	struct clk_rate_request *req)
	222	{
	223	return pxa2xx_determine_rate(req, pxa27x_freqs,
	224	ARRAY_SIZE(pxa27x_freqs));
	225	}
	226
	227	static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
	228	unsigned long parent_rate)
	229	{
	230	int i;
	231
	232	pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
	233	for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
	234	if (pxa27x_freqs[i].cpll == rate)
	235	break;
	236
	237	if (i >= ARRAY_SIZE(pxa27x_freqs))
	238	return -EINVAL;
	239
3c816d95	240	pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR);
9fe69429 RJ	241	return 0;
	242	}
	243
d40670dc	244	PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
9fe69429	245	RATE_OPS(clk_pxa27x_cpll, "cpll");
d40670dc RJ	246
	247	static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
	248	unsigned long parent_rate)
	249	{
	250	unsigned int l, osc_forced;
3c816d95 AB	251	unsigned long ccsr = readl(clk_regs + CCSR);
3c816d95 AB	252	unsigned long cccr = readl(clk_regs + CCCR);
d40670dc RJ	253
	254	l = ccsr & CCSR_L_MASK;
	255	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	256	if (osc_forced) {
	257	if (cccr & (1 << CCCR_LCD_26_BIT))
	258	return parent_rate * 2;
	259	else
	260	return parent_rate;
	261	}
	262
	263	if (l <= 7)
	264	return parent_rate;
	265	if (l <= 16)
	266	return parent_rate / 2;
	267	return parent_rate / 4;
	268	}
	269
	270	static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
	271	{
	272	unsigned int osc_forced;
3c816d95	273	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	274
	275	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	276	if (osc_forced)
	277	return PXA_LCD_13Mhz;
	278	else
	279	return PXA_LCD_RUN;
	280	}
	281
	282	PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
	283	MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
	284
	285	static void __init pxa27x_register_plls(void)
	286	{
	287	clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
2c63935d	288	CLK_GET_RATE_NOCACHE,
d40670dc	289	13 * MHz);
fc206543 RJ	290	clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
	291	clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
	292	CLK_GET_RATE_NOCACHE,
	293	32768 * KHz));
2c63935d	294	clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
d40670dc RJ	295	clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
	296	}
	297
d40670dc RJ	298	static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
	299	{
	300	unsigned long clkcfg;
06b8ec4e	301	unsigned int t, ht, osc_forced;
3c816d95	302	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	303
	304	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	305	if (osc_forced)
	306	return PXA_CORE_13Mhz;
	307
	308	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	309	t = clkcfg & (1 << 0);
	310	ht = clkcfg & (1 << 2);
d40670dc RJ	311
	312	if (ht \|\| t)
	313	return PXA_CORE_TURBO;
	314	return PXA_CORE_RUN;
	315	}
9fe69429 RJ	316
	317	static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
	318	{
	319	if (index > PXA_CORE_TURBO)
	320	return -EINVAL;
	321
	322	pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
	323
	324	return 0;
	325	}
	326
	327	static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
	328	struct clk_rate_request *req)
	329	{
	330	return __clk_mux_determine_rate(hw, req);
	331	}
	332
d40670dc	333	PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
9fe69429	334	MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
d40670dc RJ	335
	336	static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
	337	unsigned long parent_rate)
	338	{
3c816d95	339	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	340	unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
	341
	342	return (parent_rate / n2) * 2;
	343	}
	344	PARENTS(clk_pxa27x_run) = { "cpll" };
	345	RATE_RO_OPS(clk_pxa27x_run, "run");
	346
	347	static void __init pxa27x_register_core(void)
	348	{
fb16d9e5 RJ	349	clkdev_pxa_register(CLK_NONE, "cpll", NULL,
	350	clk_register_clk_pxa27x_cpll());
	351	clkdev_pxa_register(CLK_NONE, "run", NULL,
	352	clk_register_clk_pxa27x_run());
d40670dc RJ	353	clkdev_pxa_register(CLK_CORE, "core", NULL,
	354	clk_register_clk_pxa27x_core());
	355	}
	356
	357	static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
	358	unsigned long parent_rate)
	359	{
	360	unsigned long clkcfg;
	361	unsigned int b, osc_forced;
3c816d95	362	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	363
	364	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	365	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	366	b = clkcfg & (1 << 3);
	367
	368	if (osc_forced)
	369	return parent_rate;
	370	if (b)
d40670dc	371	return parent_rate;
7c514519 RJ	372	else
7c514519 RJ	373	return parent_rate / 2;
d40670dc RJ	374	}
	375
	376	static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
	377	{
	378	unsigned int osc_forced;
3c816d95	379	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	380
	381	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
	382	if (osc_forced)
	383	return PXA_BUS_13Mhz;
	384	else
	385	return PXA_BUS_RUN;
	386	}
	387
	388	PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
	389	MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
	390
	391	static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
	392	unsigned long parent_rate)
	393	{
	394	unsigned int a, l, osc_forced;
3c816d95 AB	395	unsigned long cccr = readl(clk_regs + CCCR);
3c816d95 AB	396	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	397
d40670dc RJ	398	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
dcf3d458	399	a = cccr & (1 << CCCR_A_BIT);
d40670dc RJ	400	l = ccsr & CCSR_L_MASK;
	401
	402	if (osc_forced \|\| a)
	403	return parent_rate;
	404	if (l <= 10)
	405	return parent_rate;
	406	if (l <= 20)
	407	return parent_rate / 2;
	408	return parent_rate / 4;
	409	}
	410
	411	static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
	412	{
	413	unsigned int osc_forced, a;
3c816d95 AB	414	unsigned long cccr = readl(clk_regs + CCCR);
3c816d95 AB	415	unsigned long ccsr = readl(clk_regs + CCSR);
d40670dc RJ	416
d40670dc RJ	417	osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
dcf3d458	418	a = cccr & (1 << CCCR_A_BIT);
d40670dc RJ	419	if (osc_forced)
	420	return PXA_MEM_13Mhz;
	421	if (a)
	422	return PXA_MEM_SYSTEM_BUS;
	423	else
	424	return PXA_MEM_RUN;
	425	}
	426
	427	PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
	428	MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
	429
8b6d1034 RJ	430	#define DUMMY_CLK(_con_id, _dev_id, _parent) \
	431	{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
	432	struct dummy_clk {
	433	const char *con_id;
	434	const char *dev_id;
	435	const char *parent;
	436	};
	437	static struct dummy_clk dummy_clks[] __initdata = {
	438	DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
46acbcb4	439	DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
8b6d1034 RJ	440	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
	441	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
	442	};
	443
	444	static void __init pxa27x_dummy_clocks_init(void)
	445	{
	446	struct clk *clk;
	447	struct dummy_clk *d;
	448	const char *name;
	449	int i;
	450
	451	for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
	452	d = &dummy_clks[i];
	453	name = d->dev_id ? d->dev_id : d->con_id;
	454	clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
	455	clk_register_clkdev(clk, d->con_id, d->dev_id);
	456	}
	457	}
	458
d40670dc RJ	459	static void __init pxa27x_base_clocks_init(void)
	460	{
	461	pxa27x_register_plls();
	462	pxa27x_register_core();
fb16d9e5 RJ	463	clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
	464	clk_register_clk_pxa27x_system_bus());
	465	clkdev_pxa_register(CLK_NONE, "memory", NULL,
	466	clk_register_clk_pxa27x_memory());
d40670dc RJ	467	clk_register_clk_pxa27x_lcd_base();
	468	}
	469
3c816d95	470	int __init pxa27x_clocks_init(void __iomem *regs)
d40670dc	471	{
3c816d95	472	clk_regs = regs;
d40670dc	473	pxa27x_base_clocks_init();
8b6d1034	474	pxa27x_dummy_clocks_init();
3c816d95	475	return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs);
d40670dc	476	}
6f8a444a RJ	477
	478	static void __init pxa27x_dt_clocks_init(struct device_node *np)
	479	{
3c816d95	480	pxa27x_clocks_init(ioremap(0x41300000ul, 0x10));
6f8a444a RJ	481	clk_pxa_dt_common_init(np);
	482	}
	483	CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);