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7d81397c SG |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
d68c3805 | 13 | #include <linux/clk/mxs.h> |
7d81397c | 14 | #include <linux/clkdev.h> |
dd03ee9a | 15 | #include <linux/clk-provider.h> |
7d81397c SG |
16 | #include <linux/err.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/io.h> | |
b598b9f3 | 19 | #include <linux/of.h> |
38d6590f | 20 | #include <linux/of_address.h> |
7d81397c SG |
21 | #include "clk.h" |
22 | ||
38d6590f SG |
23 | static void __iomem *clkctrl; |
24 | #define CLKCTRL clkctrl | |
25 | ||
7d81397c SG |
26 | #define PLL0CTRL0 (CLKCTRL + 0x0000) |
27 | #define PLL1CTRL0 (CLKCTRL + 0x0020) | |
28 | #define PLL2CTRL0 (CLKCTRL + 0x0040) | |
29 | #define CPU (CLKCTRL + 0x0050) | |
30 | #define HBUS (CLKCTRL + 0x0060) | |
31 | #define XBUS (CLKCTRL + 0x0070) | |
32 | #define XTAL (CLKCTRL + 0x0080) | |
33 | #define SSP0 (CLKCTRL + 0x0090) | |
34 | #define SSP1 (CLKCTRL + 0x00a0) | |
35 | #define SSP2 (CLKCTRL + 0x00b0) | |
36 | #define SSP3 (CLKCTRL + 0x00c0) | |
37 | #define GPMI (CLKCTRL + 0x00d0) | |
38 | #define SPDIF (CLKCTRL + 0x00e0) | |
39 | #define EMI (CLKCTRL + 0x00f0) | |
40 | #define SAIF0 (CLKCTRL + 0x0100) | |
41 | #define SAIF1 (CLKCTRL + 0x0110) | |
42 | #define LCDIF (CLKCTRL + 0x0120) | |
43 | #define ETM (CLKCTRL + 0x0130) | |
44 | #define ENET (CLKCTRL + 0x0140) | |
45 | #define FLEXCAN (CLKCTRL + 0x0160) | |
46 | #define FRAC0 (CLKCTRL + 0x01b0) | |
47 | #define FRAC1 (CLKCTRL + 0x01c0) | |
48 | #define CLKSEQ (CLKCTRL + 0x01d0) | |
49 | ||
50 | #define BP_CPU_INTERRUPT_WAIT 12 | |
51 | #define BP_SAIF_DIV_FRAC_EN 16 | |
52 | #define BP_ENET_DIV_TIME 21 | |
53 | #define BP_ENET_SLEEP 31 | |
54 | #define BP_CLKSEQ_BYPASS_SAIF0 0 | |
55 | #define BP_CLKSEQ_BYPASS_SSP0 3 | |
56 | #define BP_FRAC0_IO1FRAC 16 | |
57 | #define BP_FRAC0_IO0FRAC 24 | |
58 | ||
38d6590f SG |
59 | static void __iomem *digctrl; |
60 | #define DIGCTRL digctrl | |
7d81397c SG |
61 | #define BP_SAIF_CLKMUX 10 |
62 | ||
63 | /* | |
64 | * HW_SAIF_CLKMUX_SEL: | |
65 | * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 | |
66 | * clock pins selected for SAIF1 input clocks. | |
67 | * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and | |
68 | * SAIF0 clock inputs selected for SAIF1 input clocks. | |
69 | * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input | |
70 | * clocks. | |
71 | * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input | |
72 | * clocks. | |
73 | */ | |
74 | int mxs_saif_clkmux_select(unsigned int clkmux) | |
75 | { | |
76 | if (clkmux > 0x3) | |
77 | return -EINVAL; | |
78 | ||
0c672aae SG |
79 | writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); |
80 | writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); | |
7d81397c SG |
81 | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static void __init clk_misc_init(void) | |
86 | { | |
87 | u32 val; | |
88 | ||
89 | /* Gate off cpu clock in WFI for power saving */ | |
0c672aae | 90 | writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); |
7d81397c SG |
91 | |
92 | /* 0 is a bad default value for a divider */ | |
0c672aae | 93 | writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); |
7d81397c SG |
94 | |
95 | /* Clear BYPASS for SAIF */ | |
0c672aae | 96 | writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); |
7d81397c SG |
97 | |
98 | /* SAIF has to use frac div for functional operation */ | |
99 | val = readl_relaxed(SAIF0); | |
100 | val |= 1 << BP_SAIF_DIV_FRAC_EN; | |
101 | writel_relaxed(val, SAIF0); | |
102 | ||
103 | val = readl_relaxed(SAIF1); | |
104 | val |= 1 << BP_SAIF_DIV_FRAC_EN; | |
105 | writel_relaxed(val, SAIF1); | |
106 | ||
107 | /* Extra fec clock setting */ | |
108 | val = readl_relaxed(ENET); | |
109 | val &= ~(1 << BP_ENET_SLEEP); | |
110 | writel_relaxed(val, ENET); | |
111 | ||
112 | /* | |
113 | * Source ssp clock from ref_io than ref_xtal, | |
114 | * as ref_xtal only provides 24 MHz as maximum. | |
115 | */ | |
0c672aae | 116 | writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); |
7d81397c SG |
117 | |
118 | /* | |
119 | * 480 MHz seems too high to be ssp clock source directly, | |
64e2bc41 | 120 | * so set frac0 to get a 288 MHz ref_io0 and ref_io1. |
7d81397c SG |
121 | */ |
122 | val = readl_relaxed(FRAC0); | |
64e2bc41 LH |
123 | val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC)); |
124 | val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC); | |
7d81397c SG |
125 | writel_relaxed(val, FRAC0); |
126 | } | |
127 | ||
7d81397c SG |
128 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; |
129 | static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; | |
130 | static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; | |
131 | static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; | |
132 | static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", }; | |
133 | static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", }; | |
134 | static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; | |
135 | static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; | |
136 | static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", }; | |
137 | ||
138 | enum imx28_clk { | |
139 | ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, | |
140 | ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel, | |
141 | ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel, | |
142 | lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus, | |
143 | ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll, | |
144 | emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div, | |
145 | clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, | |
146 | ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, | |
f5894539 | 147 | fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out, |
7d81397c SG |
148 | clk_max |
149 | }; | |
150 | ||
151 | static struct clk *clks[clk_max]; | |
b598b9f3 | 152 | static struct clk_onecell_data clk_data; |
7d81397c SG |
153 | |
154 | static enum imx28_clk clks_init_on[] __initdata = { | |
155 | cpu, hbus, xbus, emi, uart, | |
156 | }; | |
157 | ||
dd03ee9a | 158 | static void __init mx28_clocks_init(struct device_node *np) |
7d81397c | 159 | { |
dd03ee9a | 160 | struct device_node *dcnp; |
38a8b096 | 161 | u32 i; |
7d81397c | 162 | |
dd03ee9a SH |
163 | dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); |
164 | digctrl = of_iomap(dcnp, 0); | |
38d6590f | 165 | WARN_ON(!digctrl); |
dd03ee9a | 166 | of_node_put(dcnp); |
38d6590f | 167 | |
38d6590f SG |
168 | clkctrl = of_iomap(np, 0); |
169 | WARN_ON(!clkctrl); | |
170 | ||
7d81397c SG |
171 | clk_misc_init(); |
172 | ||
173 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); | |
174 | clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); | |
175 | clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); | |
176 | clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); | |
177 | clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); | |
178 | clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); | |
d6dc55c1 SG |
179 | clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); |
180 | clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); | |
7d81397c SG |
181 | clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); |
182 | clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); | |
183 | clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); | |
184 | clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); | |
185 | clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); | |
186 | clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); | |
187 | clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); | |
188 | clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); | |
189 | clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); | |
190 | clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); | |
191 | clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); | |
192 | clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); | |
193 | clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); | |
194 | clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); | |
195 | clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); | |
196 | clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); | |
197 | clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); | |
198 | clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); | |
199 | clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); | |
200 | clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); | |
201 | clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); | |
202 | clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); | |
203 | clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); | |
204 | clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); | |
205 | clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); | |
206 | clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); | |
207 | clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); | |
208 | clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); | |
209 | clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); | |
210 | clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); | |
211 | clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); | |
212 | clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); | |
213 | clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); | |
214 | clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); | |
215 | clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); | |
216 | clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); | |
217 | clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); | |
218 | clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); | |
219 | clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); | |
220 | clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); | |
221 | clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31); | |
222 | clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31); | |
223 | clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); | |
224 | clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); | |
225 | clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); | |
226 | clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31); | |
227 | clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31); | |
228 | clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); | |
229 | clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); | |
230 | clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); | |
231 | clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); | |
232 | clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); | |
f5894539 FE |
233 | clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2); |
234 | clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16); | |
235 | clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); | |
236 | clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); | |
7d81397c SG |
237 | clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); |
238 | ||
239 | for (i = 0; i < ARRAY_SIZE(clks); i++) | |
240 | if (IS_ERR(clks[i])) { | |
241 | pr_err("i.MX28 clk %d: register failed with %ld\n", | |
242 | i, PTR_ERR(clks[i])); | |
dd03ee9a | 243 | return; |
7d81397c SG |
244 | } |
245 | ||
38d6590f SG |
246 | clk_data.clks = clks; |
247 | clk_data.clk_num = ARRAY_SIZE(clks); | |
248 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
b598b9f3 | 249 | |
7d81397c | 250 | clk_register_clkdev(clks[enet_out], NULL, "enet_out"); |
7d81397c SG |
251 | |
252 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | |
253 | clk_prepare_enable(clks[clks_init_on[i]]); | |
7d81397c | 254 | } |
dd03ee9a | 255 | CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); |