[linux-2.6-block.git] / drivers / clk / mvebu / clk-cpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell MVEBU CPU clock handling.
 *
 * Copyright (C) 2012 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/mvebu-pmsu.h>
#include <asm/smp_plat.h>

#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET               0x0
#define   SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL          0xff
#define   SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT        8
#define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET              0x8
#define   SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16
#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET              0xC
#define SYS_CTRL_CLK_DIVIDER_MASK                      0x3F

#define PMU_DFS_RATIO_SHIFT 16
#define PMU_DFS_RATIO_MASK  0x3F

#define MAX_CPU	    4
struct cpu_clk {
	struct clk_hw hw;
	int cpu;
	const char *clk_name;
	const char *parent_name;
	void __iomem *reg_base;
	void __iomem *pmu_dfs;
};

static struct clk **clks;

static struct clk_onecell_data clk_data;

#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)

static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{
	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
	u32 reg, div;

	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
	div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
	return parent_rate / div;
}

static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
			       unsigned long *parent_rate)
{
	/* Valid ratio are 1:1, 1:2 and 1:3 */
	u32 div;

	div = *parent_rate / rate;
	if (div == 0)
		div = 1;
	else if (div > 3)
		div = 3;

	return *parent_rate / div;
}

static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate,
				unsigned long parent_rate)

{
	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
	u32 reg, div;
	u32 reload_mask;

	div = parent_rate / rate;
	reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
		& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
		| (div << (cpuclk->cpu * 8));
	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
	/* Set clock divider reload smooth bit mask */
	reload_mask = 1 << (20 + cpuclk->cpu);

	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
	    | reload_mask;
	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);

	/* Now trigger the clock update */
	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
	    | 1 << 24;
	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);

	/* Wait for clocks to settle down then clear reload request */
	udelay(1000);
	reg &= ~(reload_mask | 1 << 24);
	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	udelay(1000);

	return 0;
}

static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,
			       unsigned long parent_rate)
{
	u32 reg;
	unsigned long fabric_div, target_div, cur_rate;
	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);

	/*
	 * PMU DFS registers are not mapped, Device Tree does not
	 * describes them. We cannot change the frequency dynamically.
	 */
	if (!cpuclk->pmu_dfs)
		return -ENODEV;

	cur_rate = clk_hw_get_rate(hwclk);

	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);
	fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
		SYS_CTRL_CLK_DIVIDER_MASK;

	/* Frequency is going up */
	if (rate == 2 * cur_rate)
		target_div = fabric_div / 2;
	/* Frequency is going down */
	else
		target_div = fabric_div;

	if (target_div == 0)
		target_div = 1;

	reg = readl(cpuclk->pmu_dfs);
	reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);
	reg |= (target_div << PMU_DFS_RATIO_SHIFT);
	writel(reg, cpuclk->pmu_dfs);

	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<
		SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT);
	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);

	return mvebu_pmsu_dfs_request(cpuclk->cpu);
}

static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
			    unsigned long parent_rate)
{
	if (__clk_is_enabled(hwclk->clk))
		return clk_cpu_on_set_rate(hwclk, rate, parent_rate);
	else
		return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
}

static const struct clk_ops cpu_ops = {
	.recalc_rate = clk_cpu_recalc_rate,
	.round_rate = clk_cpu_round_rate,
	.set_rate = clk_cpu_set_rate,
};

static void __init of_cpu_clk_setup(struct device_node *node)
{
	struct cpu_clk *cpuclk;
	void __iomem *clock_complex_base = of_iomap(node, 0);
	void __iomem *pmu_dfs_base = of_iomap(node, 1);
	int ncpus = 0;
	struct device_node *dn;

	if (clock_complex_base == NULL) {
		pr_err("%s: clock-complex base register not set\n",
			__func__);
		return;
	}

	if (pmu_dfs_base == NULL)
		pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",
			__func__);

	for_each_of_cpu_node(dn)
		ncpus++;

	cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL);
	if (WARN_ON(!cpuclk))
		goto cpuclk_out;

	clks = kcalloc(ncpus, sizeof(*clks), GFP_KERNEL);
	if (WARN_ON(!clks))
		goto clks_out;

	for_each_of_cpu_node(dn) {
		struct clk_init_data init;
		struct clk *clk;
		char *clk_name = kzalloc(5, GFP_KERNEL);
		int cpu, err;

		if (WARN_ON(!clk_name))
			goto bail_out;

		err = of_property_read_u32(dn, "reg", &cpu);
		if (WARN_ON(err))
			goto bail_out;

		sprintf(clk_name, "cpu%d", cpu);

		cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0);
		cpuclk[cpu].clk_name = clk_name;
		cpuclk[cpu].cpu = cpu;
		cpuclk[cpu].reg_base = clock_complex_base;
		if (pmu_dfs_base)
			cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;
		cpuclk[cpu].hw.init = &init;

		init.name = cpuclk[cpu].clk_name;
		init.ops = &cpu_ops;
		init.flags = 0;
		init.parent_names = &cpuclk[cpu].parent_name;
		init.num_parents = 1;

		clk = clk_register(NULL, &cpuclk[cpu].hw);
		if (WARN_ON(IS_ERR(clk)))
			goto bail_out;
		clks[cpu] = clk;
	}
	clk_data.clk_num = MAX_CPU;
	clk_data.clks = clks;
	of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);

	return;
bail_out:
	kfree(clks);
	while(ncpus--)
		kfree(cpuclk[ncpus].clk_name);
clks_out:
	kfree(cpuclk);
cpuclk_out:
	iounmap(clock_complex_base);
}

CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
					 of_cpu_clk_setup);

static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
{
	of_clk_add_provider(node, of_clk_src_simple_get, NULL);
}

CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
					 of_mv98dx3236_cpu_clk_setup);
Commit	Line	Data
c3828949	1	// SPDX-License-Identifier: GPL-2.0
ab8ba01b GC	2	/*
	3	* Marvell MVEBU CPU clock handling.
	4	*
	5	* Copyright (C) 2012 Marvell
	6	*
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	*
ab8ba01b GC	9	*/
ab8ba01b GC	10	#include <linux/kernel.h>
db00c3e5 SB	11	#include <linux/slab.h>
db00c3e5 SB	12	#include <linux/clk.h>
ab8ba01b GC	13	#include <linux/clk-provider.h>
	14	#include <linux/of_address.h>
	15	#include <linux/io.h>
	16	#include <linux/of.h>
	17	#include <linux/delay.h>
ee2d8ea1 TP	18	#include <linux/mvebu-pmsu.h>
ee2d8ea1 TP	19	#include <asm/smp_plat.h>
ab8ba01b	20
ee2d8ea1 TP	21	#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
	22	#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff
	23	#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8
	24	#define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8
	25	#define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16
	26	#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
	27	#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
	28
	29	#define PMU_DFS_RATIO_SHIFT 16
	30	#define PMU_DFS_RATIO_MASK 0x3F
ab8ba01b GC	31
	32	#define MAX_CPU 4
	33	struct cpu_clk {
	34	struct clk_hw hw;
	35	int cpu;
	36	const char *clk_name;
	37	const char *parent_name;
	38	void __iomem *reg_base;
ee2d8ea1	39	void __iomem *pmu_dfs;
ab8ba01b GC	40	};
	41
	42	static struct clk **clks;
	43
	44	static struct clk_onecell_data clk_data;
	45
	46	#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
	47
	48	static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
	49	unsigned long parent_rate)
	50	{
	51	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
	52	u32 reg, div;
	53
	54	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
	55	div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
	56	return parent_rate / div;
	57	}
	58
	59	static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
	60	unsigned long *parent_rate)
	61	{
	62	/* Valid ratio are 1:1, 1:2 and 1:3 */
	63	u32 div;
	64
	65	div = *parent_rate / rate;
	66	if (div == 0)
	67	div = 1;
	68	else if (div > 3)
	69	div = 3;
	70
	71	return *parent_rate / div;
	72	}
	73
ee2d8ea1 TP	74	static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate,
	75	unsigned long parent_rate)
	76
ab8ba01b GC	77	{
	78	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
	79	u32 reg, div;
	80	u32 reload_mask;
	81
	82	div = parent_rate / rate;
	83	reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
	84	& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
	85	\| (div << (cpuclk->cpu * 8));
	86	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
	87	/* Set clock divider reload smooth bit mask */
	88	reload_mask = 1 << (20 + cpuclk->cpu);
	89
	90	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
	91	\| reload_mask;
	92	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	93
	94	/* Now trigger the clock update */
	95	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
	96	\| 1 << 24;
	97	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	98
	99	/* Wait for clocks to settle down then clear reload request */
	100	udelay(1000);
	101	reg &= ~(reload_mask \| 1 << 24);
	102	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	103	udelay(1000);
	104
	105	return 0;
	106	}
	107
ee2d8ea1 TP	108	static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,
	109	unsigned long parent_rate)
	110	{
	111	u32 reg;
	112	unsigned long fabric_div, target_div, cur_rate;
	113	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
	114
	115	/*
	116	* PMU DFS registers are not mapped, Device Tree does not
	117	* describes them. We cannot change the frequency dynamically.
	118	*/
	119	if (!cpuclk->pmu_dfs)
	120	return -ENODEV;
	121
eca61c9f	122	cur_rate = clk_hw_get_rate(hwclk);
ee2d8ea1 TP	123
	124	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);
	125	fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
	126	SYS_CTRL_CLK_DIVIDER_MASK;
	127
	128	/* Frequency is going up */
	129	if (rate == 2 * cur_rate)
	130	target_div = fabric_div / 2;
	131	/* Frequency is going down */
	132	else
	133	target_div = fabric_div;
	134
	135	if (target_div == 0)
	136	target_div = 1;
	137
	138	reg = readl(cpuclk->pmu_dfs);
	139	reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);
	140	reg \|= (target_div << PMU_DFS_RATIO_SHIFT);
	141	writel(reg, cpuclk->pmu_dfs);
	142
	143	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	144	reg \|= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<
	145	SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT);
	146	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
	147
	148	return mvebu_pmsu_dfs_request(cpuclk->cpu);
	149	}
	150
	151	static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
	152	unsigned long parent_rate)
	153	{
	154	if (__clk_is_enabled(hwclk->clk))
	155	return clk_cpu_on_set_rate(hwclk, rate, parent_rate);
	156	else
	157	return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
	158	}
	159
ab8ba01b GC	160	static const struct clk_ops cpu_ops = {
	161	.recalc_rate = clk_cpu_recalc_rate,
	162	.round_rate = clk_cpu_round_rate,
	163	.set_rate = clk_cpu_set_rate,
	164	};
	165
9ac81751	166	static void __init of_cpu_clk_setup(struct device_node *node)
ab8ba01b GC	167	{
	168	struct cpu_clk *cpuclk;
	169	void __iomem *clock_complex_base = of_iomap(node, 0);
ee2d8ea1	170	void __iomem *pmu_dfs_base = of_iomap(node, 1);
ab8ba01b GC	171	int ncpus = 0;
	172	struct device_node *dn;
	173
	174	if (clock_complex_base == NULL) {
	175	pr_err("%s: clock-complex base register not set\n",
	176	__func__);
	177	return;
	178	}
	179
ee2d8ea1 TP	180	if (pmu_dfs_base == NULL)
	181	pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",
	182	__func__);
	183
76ec23b1	184	for_each_of_cpu_node(dn)
ab8ba01b GC	185	ncpus++;
ab8ba01b GC	186
23826e24	187	cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL);
ab8ba01b	188	if (WARN_ON(!cpuclk))
f98d007d	189	goto cpuclk_out;
ab8ba01b	190
23826e24	191	clks = kcalloc(ncpus, sizeof(*clks), GFP_KERNEL);
ab8ba01b	192	if (WARN_ON(!clks))
d6f620a4	193	goto clks_out;
ab8ba01b	194
76ec23b1	195	for_each_of_cpu_node(dn) {
ab8ba01b GC	196	struct clk_init_data init;
ab8ba01b GC	197	struct clk *clk;
ab8ba01b GC	198	char *clk_name = kzalloc(5, GFP_KERNEL);
	199	int cpu, err;
	200
	201	if (WARN_ON(!clk_name))
d6f620a4	202	goto bail_out;
ab8ba01b GC	203
	204	err = of_property_read_u32(dn, "reg", &cpu);
	205	if (WARN_ON(err))
d6f620a4	206	goto bail_out;
ab8ba01b GC	207
ab8ba01b GC	208	sprintf(clk_name, "cpu%d", cpu);
ab8ba01b	209
61e22fff	210	cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0);
ab8ba01b GC	211	cpuclk[cpu].clk_name = clk_name;
	212	cpuclk[cpu].cpu = cpu;
	213	cpuclk[cpu].reg_base = clock_complex_base;
ee2d8ea1 TP	214	if (pmu_dfs_base)
ee2d8ea1 TP	215	cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;
ab8ba01b GC	216	cpuclk[cpu].hw.init = &init;
	217
	218	init.name = cpuclk[cpu].clk_name;
	219	init.ops = &cpu_ops;
	220	init.flags = 0;
	221	init.parent_names = &cpuclk[cpu].parent_name;
	222	init.num_parents = 1;
	223
	224	clk = clk_register(NULL, &cpuclk[cpu].hw);
	225	if (WARN_ON(IS_ERR(clk)))
	226	goto bail_out;
	227	clks[cpu] = clk;
	228	}
	229	clk_data.clk_num = MAX_CPU;
	230	clk_data.clks = clks;
	231	of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
	232
	233	return;
	234	bail_out:
	235	kfree(clks);
d6f620a4 CD	236	while(ncpus--)
	237	kfree(cpuclk[ncpus].clk_name);
	238	clks_out:
ab8ba01b	239	kfree(cpuclk);
f98d007d JZ	240	cpuclk_out:
f98d007d JZ	241	iounmap(clock_complex_base);
ab8ba01b GC	242	}
ab8ba01b GC	243
f640c0fa JFM	244	CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
f640c0fa JFM	245	of_cpu_clk_setup);
e120c17a CP	246
	247	static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
	248	{
	249	of_clk_add_provider(node, of_clk_src_simple_get, NULL);
	250	}
	251
	252	CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
	253	of_mv98dx3236_cpu_clk_setup);