[linux-2.6-block.git] / drivers / clk / mmp / clk-pxa910.c

/*
 * pxa910 clock framework source file
 *
 * Copyright (C) 2012 Marvell
 * Chao Xie <xiechao.mail@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>

#include "clk.h"

#define APBC_RTC	0x28
#define APBC_TWSI0	0x2c
#define APBC_KPC	0x18
#define APBC_UART0	0x0
#define APBC_UART1	0x4
#define APBC_GPIO	0x8
#define APBC_PWM0	0xc
#define APBC_PWM1	0x10
#define APBC_PWM2	0x14
#define APBC_PWM3	0x18
#define APBC_SSP0	0x1c
#define APBC_SSP1	0x20
#define APBC_SSP2	0x4c
#define APBCP_TWSI1	0x28
#define APBCP_UART2	0x1c
#define APMU_SDH0	0x54
#define APMU_SDH1	0x58
#define APMU_USB	0x5c
#define APMU_DISP0	0x4c
#define APMU_CCIC0	0x50
#define APMU_DFC	0x60
#define MPMU_UART_PLL	0x14

static DEFINE_SPINLOCK(clk_lock);

static struct mmp_clk_factor_masks uart_factor_masks = {
	.factor = 2,
	.num_mask = 0x1fff,
	.den_mask = 0x1fff,
	.num_shift = 16,
	.den_shift = 0,
};

static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
	{.num = 8125, .den = 1536},	/*14.745MHZ */
};

static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
static const char *disp_parent[] = {"pll1_2", "pll1_12"};
static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};

void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
			    phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
{
	struct clk *clk;
	struct clk *uart_pll;
	void __iomem *mpmu_base;
	void __iomem *apmu_base;
	void __iomem *apbcp_base;
	void __iomem *apbc_base;

	mpmu_base = ioremap(mpmu_phys, SZ_4K);
	if (mpmu_base == NULL) {
		pr_err("error to ioremap MPMU base\n");
		return;
	}

	apmu_base = ioremap(apmu_phys, SZ_4K);
	if (apmu_base == NULL) {
		pr_err("error to ioremap APMU base\n");
		return;
	}

	apbcp_base = ioremap(apbcp_phys, SZ_4K);
	if (apbcp_base == NULL) {
		pr_err("error to ioremap APBC extension base\n");
		return;
	}

	apbc_base = ioremap(apbc_phys, SZ_4K);
	if (apbc_base == NULL) {
		pr_err("error to ioremap APBC base\n");
		return;
	}

	clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
	clk_register_clkdev(clk, "clk32", NULL);

	clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
	clk_register_clkdev(clk, "vctcxo", NULL);

	clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
	clk_register_clkdev(clk, "pll1", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_2", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_4", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_8", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_16", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
				CLK_SET_RATE_PARENT, 1, 3);
	clk_register_clkdev(clk, "pll1_6", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_12", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_24", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_48", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_96", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
				CLK_SET_RATE_PARENT, 1, 13);
	clk_register_clkdev(clk, "pll1_13", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
				CLK_SET_RATE_PARENT, 2, 3);
	clk_register_clkdev(clk, "pll1_13_1_5", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
				CLK_SET_RATE_PARENT, 2, 3);
	clk_register_clkdev(clk, "pll1_2_1_5", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
				CLK_SET_RATE_PARENT, 3, 16);
	clk_register_clkdev(clk, "pll1_3_16", NULL);

	uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
				mpmu_base + MPMU_UART_PLL,
				&uart_factor_masks, uart_factor_tbl,
				ARRAY_SIZE(uart_factor_tbl), &clk_lock);
	clk_set_rate(uart_pll, 14745600);
	clk_register_clkdev(uart_pll, "uart_pll", NULL);

	clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");

	clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
				apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");

	clk = mmp_clk_register_apbc("gpio", "vctcxo",
				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-gpio");

	clk = mmp_clk_register_apbc("kpc", "clk32",
				apbc_base + APBC_KPC, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa27x-keypad");

	clk = mmp_clk_register_apbc("rtc", "clk32",
				apbc_base + APBC_RTC, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "sa1100-rtc");

	clk = mmp_clk_register_apbc("pwm0", "pll1_48",
				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa910-pwm.0");

	clk = mmp_clk_register_apbc("pwm1", "pll1_48",
				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa910-pwm.1");

	clk = mmp_clk_register_apbc("pwm2", "pll1_48",
				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa910-pwm.2");

	clk = mmp_clk_register_apbc("pwm3", "pll1_48",
				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");

	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, uart_pll);
	clk_register_clkdev(clk, "uart_mux.0", NULL);

	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
				apbc_base + APBC_UART0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");

	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, uart_pll);
	clk_register_clkdev(clk, "uart_mux.1", NULL);

	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
				apbc_base + APBC_UART1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");

	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, uart_pll);
	clk_register_clkdev(clk, "uart_mux.2", NULL);

	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
				apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");

	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "uart_mux.0", NULL);

	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
				apbc_base + APBC_SSP0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.0");

	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "ssp_mux.1", NULL);

	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
				apbc_base + APBC_SSP1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.1");

	clk = mmp_clk_register_apmu("dfc", "pll1_4",
				apmu_base + APMU_DFC, 0x19b, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");

	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
				ARRAY_SIZE(sdh_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
	clk_register_clkdev(clk, "sdh0_mux", NULL);

	clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
				apmu_base + APMU_SDH0, 0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");

	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
				ARRAY_SIZE(sdh_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
	clk_register_clkdev(clk, "sdh1_mux", NULL);

	clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
				apmu_base + APMU_SDH1, 0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");

	clk = mmp_clk_register_apmu("usb", "usb_pll",
				apmu_base + APMU_USB, 0x9, &clk_lock);
	clk_register_clkdev(clk, "usb_clk", NULL);

	clk = mmp_clk_register_apmu("sph", "usb_pll",
				apmu_base + APMU_USB, 0x12, &clk_lock);
	clk_register_clkdev(clk, "sph_clk", NULL);

	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
				ARRAY_SIZE(disp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
	clk_register_clkdev(clk, "disp_mux.0", NULL);

	clk = mmp_clk_register_apmu("disp0", "disp0_mux",
				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-disp.0");

	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
				ARRAY_SIZE(ccic_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
	clk_register_clkdev(clk, "ccic_mux.0", NULL);

	clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");

	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
				ARRAY_SIZE(ccic_phy_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);

	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");

	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
				10, 5, 0, &clk_lock);
	clk_register_clkdev(clk, "sphyclk_div", NULL);

	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
}
Commit	Line	Data
84a62e6e CX	1	/*
	2	* pxa910 clock framework source file
	3	*
	4	* Copyright (C) 2012 Marvell
	5	* Chao Xie <xiechao.mail@gmail.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
990f2f22	12	#include <linux/clk.h>
84a62e6e CX	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/io.h>
	17	#include <linux/delay.h>
	18	#include <linux/err.h>
	19
84a62e6e CX	20	#include "clk.h"
	21
	22	#define APBC_RTC 0x28
	23	#define APBC_TWSI0 0x2c
	24	#define APBC_KPC 0x18
	25	#define APBC_UART0 0x0
	26	#define APBC_UART1 0x4
	27	#define APBC_GPIO 0x8
	28	#define APBC_PWM0 0xc
	29	#define APBC_PWM1 0x10
	30	#define APBC_PWM2 0x14
	31	#define APBC_PWM3 0x18
	32	#define APBC_SSP0 0x1c
	33	#define APBC_SSP1 0x20
	34	#define APBC_SSP2 0x4c
	35	#define APBCP_TWSI1 0x28
	36	#define APBCP_UART2 0x1c
	37	#define APMU_SDH0 0x54
	38	#define APMU_SDH1 0x58
	39	#define APMU_USB 0x5c
	40	#define APMU_DISP0 0x4c
	41	#define APMU_CCIC0 0x50
	42	#define APMU_DFC 0x60
	43	#define MPMU_UART_PLL 0x14
	44
	45	static DEFINE_SPINLOCK(clk_lock);
	46
2bd1e256	47	static struct mmp_clk_factor_masks uart_factor_masks = {
84a62e6e CX	48	.factor = 2,
	49	.num_mask = 0x1fff,
	50	.den_mask = 0x1fff,
	51	.num_shift = 16,
	52	.den_shift = 0,
	53	};
	54
2bd1e256	55	static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
84a62e6e CX	56	{.num = 8125, .den = 1536}, /14.745MHZ /
	57	};
	58
	59	static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
	60	static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
	61	static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
	62	static const char *disp_parent[] = {"pll1_2", "pll1_12"};
	63	static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
	64	static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
	65
990f2f22 AB	66	void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
990f2f22 AB	67	phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
84a62e6e CX	68	{
	69	struct clk *clk;
	70	struct clk *uart_pll;
	71	void __iomem *mpmu_base;
	72	void __iomem *apmu_base;
	73	void __iomem *apbcp_base;
	74	void __iomem *apbc_base;
	75
990f2f22	76	mpmu_base = ioremap(mpmu_phys, SZ_4K);
84a62e6e CX	77	if (mpmu_base == NULL) {
	78	pr_err("error to ioremap MPMU base\n");
	79	return;
	80	}
	81
990f2f22	82	apmu_base = ioremap(apmu_phys, SZ_4K);
84a62e6e CX	83	if (apmu_base == NULL) {
	84	pr_err("error to ioremap APMU base\n");
	85	return;
	86	}
	87
990f2f22	88	apbcp_base = ioremap(apbcp_phys, SZ_4K);
84a62e6e CX	89	if (apbcp_base == NULL) {
	90	pr_err("error to ioremap APBC extension base\n");
	91	return;
	92	}
	93
990f2f22	94	apbc_base = ioremap(apbc_phys, SZ_4K);
84a62e6e CX	95	if (apbc_base == NULL) {
	96	pr_err("error to ioremap APBC base\n");
	97	return;
	98	}
	99
536630dd	100	clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
84a62e6e CX	101	clk_register_clkdev(clk, "clk32", NULL);
84a62e6e CX	102
536630dd	103	clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
84a62e6e CX	104	clk_register_clkdev(clk, "vctcxo", NULL);
84a62e6e CX	105
536630dd	106	clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
84a62e6e CX	107	clk_register_clkdev(clk, "pll1", NULL);
	108
	109	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
	110	CLK_SET_RATE_PARENT, 1, 2);
	111	clk_register_clkdev(clk, "pll1_2", NULL);
	112
	113	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
	114	CLK_SET_RATE_PARENT, 1, 2);
	115	clk_register_clkdev(clk, "pll1_4", NULL);
	116
	117	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
	118	CLK_SET_RATE_PARENT, 1, 2);
	119	clk_register_clkdev(clk, "pll1_8", NULL);
	120
	121	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
	122	CLK_SET_RATE_PARENT, 1, 2);
	123	clk_register_clkdev(clk, "pll1_16", NULL);
	124
	125	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
	126	CLK_SET_RATE_PARENT, 1, 3);
	127	clk_register_clkdev(clk, "pll1_6", NULL);
	128
	129	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
	130	CLK_SET_RATE_PARENT, 1, 2);
	131	clk_register_clkdev(clk, "pll1_12", NULL);
	132
	133	clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
	134	CLK_SET_RATE_PARENT, 1, 2);
	135	clk_register_clkdev(clk, "pll1_24", NULL);
	136
	137	clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
	138	CLK_SET_RATE_PARENT, 1, 2);
	139	clk_register_clkdev(clk, "pll1_48", NULL);
	140
	141	clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
	142	CLK_SET_RATE_PARENT, 1, 2);
	143	clk_register_clkdev(clk, "pll1_96", NULL);
	144
	145	clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
	146	CLK_SET_RATE_PARENT, 1, 13);
	147	clk_register_clkdev(clk, "pll1_13", NULL);
	148
	149	clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
	150	CLK_SET_RATE_PARENT, 2, 3);
	151	clk_register_clkdev(clk, "pll1_13_1_5", NULL);
	152
	153	clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
	154	CLK_SET_RATE_PARENT, 2, 3);
	155	clk_register_clkdev(clk, "pll1_2_1_5", NULL);
	156
	157	clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
	158	CLK_SET_RATE_PARENT, 3, 16);
	159	clk_register_clkdev(clk, "pll1_3_16", NULL);
	160
	161	uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
	162	mpmu_base + MPMU_UART_PLL,
	163	&uart_factor_masks, uart_factor_tbl,
61256133	164	ARRAY_SIZE(uart_factor_tbl), &clk_lock);
84a62e6e CX	165	clk_set_rate(uart_pll, 14745600);
	166	clk_register_clkdev(uart_pll, "uart_pll", NULL);
	167
	168	clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
	169	apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
	170	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
	171
	172	clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
	173	apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
	174	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
	175
	176	clk = mmp_clk_register_apbc("gpio", "vctcxo",
	177	apbc_base + APBC_GPIO, 10, 0, &clk_lock);
2cab0292	178	clk_register_clkdev(clk, NULL, "mmp-gpio");
84a62e6e CX	179
	180	clk = mmp_clk_register_apbc("kpc", "clk32",
	181	apbc_base + APBC_KPC, 10, 0, &clk_lock);
	182	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
	183
	184	clk = mmp_clk_register_apbc("rtc", "clk32",
	185	apbc_base + APBC_RTC, 10, 0, &clk_lock);
	186	clk_register_clkdev(clk, NULL, "sa1100-rtc");
	187
	188	clk = mmp_clk_register_apbc("pwm0", "pll1_48",
	189	apbc_base + APBC_PWM0, 10, 0, &clk_lock);
	190	clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
	191
	192	clk = mmp_clk_register_apbc("pwm1", "pll1_48",
	193	apbc_base + APBC_PWM1, 10, 0, &clk_lock);
	194	clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
	195
	196	clk = mmp_clk_register_apbc("pwm2", "pll1_48",
	197	apbc_base + APBC_PWM2, 10, 0, &clk_lock);
	198	clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
	199
	200	clk = mmp_clk_register_apbc("pwm3", "pll1_48",
	201	apbc_base + APBC_PWM3, 10, 0, &clk_lock);
	202	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
	203
	204	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
819c1de3 JH	205	ARRAY_SIZE(uart_parent),
819c1de3 JH	206	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	207	apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
	208	clk_set_parent(clk, uart_pll);
	209	clk_register_clkdev(clk, "uart_mux.0", NULL);
	210
	211	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
	212	apbc_base + APBC_UART0, 10, 0, &clk_lock);
	213	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
	214
	215	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
819c1de3 JH	216	ARRAY_SIZE(uart_parent),
819c1de3 JH	217	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	218	apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
	219	clk_set_parent(clk, uart_pll);
	220	clk_register_clkdev(clk, "uart_mux.1", NULL);
	221
	222	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
	223	apbc_base + APBC_UART1, 10, 0, &clk_lock);
	224	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
	225
	226	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
819c1de3 JH	227	ARRAY_SIZE(uart_parent),
819c1de3 JH	228	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	229	apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
	230	clk_set_parent(clk, uart_pll);
	231	clk_register_clkdev(clk, "uart_mux.2", NULL);
	232
	233	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
	234	apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
	235	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
	236
	237	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
819c1de3 JH	238	ARRAY_SIZE(ssp_parent),
819c1de3 JH	239	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	240	apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
	241	clk_register_clkdev(clk, "uart_mux.0", NULL);
	242
	243	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
	244	apbc_base + APBC_SSP0, 10, 0, &clk_lock);
	245	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
	246
	247	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
819c1de3 JH	248	ARRAY_SIZE(ssp_parent),
819c1de3 JH	249	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	250	apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
	251	clk_register_clkdev(clk, "ssp_mux.1", NULL);
	252
	253	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
	254	apbc_base + APBC_SSP1, 10, 0, &clk_lock);
	255	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
	256
	257	clk = mmp_clk_register_apmu("dfc", "pll1_4",
	258	apmu_base + APMU_DFC, 0x19b, &clk_lock);
	259	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
	260
	261	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
819c1de3 JH	262	ARRAY_SIZE(sdh_parent),
819c1de3 JH	263	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	264	apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
	265	clk_register_clkdev(clk, "sdh0_mux", NULL);
	266
	267	clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
	268	apmu_base + APMU_SDH0, 0x1b, &clk_lock);
	269	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
	270
	271	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
819c1de3 JH	272	ARRAY_SIZE(sdh_parent),
819c1de3 JH	273	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	274	apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
	275	clk_register_clkdev(clk, "sdh1_mux", NULL);
	276
	277	clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
	278	apmu_base + APMU_SDH1, 0x1b, &clk_lock);
	279	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
	280
	281	clk = mmp_clk_register_apmu("usb", "usb_pll",
	282	apmu_base + APMU_USB, 0x9, &clk_lock);
	283	clk_register_clkdev(clk, "usb_clk", NULL);
	284
	285	clk = mmp_clk_register_apmu("sph", "usb_pll",
	286	apmu_base + APMU_USB, 0x12, &clk_lock);
	287	clk_register_clkdev(clk, "sph_clk", NULL);
	288
	289	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
819c1de3 JH	290	ARRAY_SIZE(disp_parent),
819c1de3 JH	291	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	292	apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
	293	clk_register_clkdev(clk, "disp_mux.0", NULL);
	294
	295	clk = mmp_clk_register_apmu("disp0", "disp0_mux",
	296	apmu_base + APMU_DISP0, 0x1b, &clk_lock);
	297	clk_register_clkdev(clk, NULL, "mmp-disp.0");
	298
	299	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
819c1de3 JH	300	ARRAY_SIZE(ccic_parent),
819c1de3 JH	301	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
84a62e6e CX	302	apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
	303	clk_register_clkdev(clk, "ccic_mux.0", NULL);
	304
	305	clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
	306	apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
	307	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
	308
	309	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
	310	ARRAY_SIZE(ccic_phy_parent),
819c1de3 JH	311	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	312	apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
84a62e6e CX	313	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
	314
	315	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
	316	apmu_base + APMU_CCIC0, 0x24, &clk_lock);
	317	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
	318
	319	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
	320	CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
	321	10, 5, 0, &clk_lock);
	322	clk_register_clkdev(clk, "sphyclk_div", NULL);
	323
	324	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
	325	apmu_base + APMU_CCIC0, 0x300, &clk_lock);
	326	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
	327	}