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Merge tag 'kvm-ppc-fixes-4.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / clk / meson / gxbb.c
CommitLineData
738f66d3 1/*
1f501d63
PG		 2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
738f66d3
MT		 4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/of_address.h>
0d48fc55 23#include <linux/of_device.h>
738f66d3 24#include <linux/platform_device.h>
1f501d63 25#include <linux/init.h>
738f66d3
MT		 26
27#include "clkc.h"
28#include "gxbb.h"
29
30static DEFINE_SPINLOCK(clk_lock);
31
32static const struct pll_rate_table sys_pll_rate_table[] = {
33 PLL_RATE(24000000, 56, 1, 2),
34 PLL_RATE(48000000, 64, 1, 2),
35 PLL_RATE(72000000, 72, 1, 2),
36 PLL_RATE(96000000, 64, 1, 2),
37 PLL_RATE(120000000, 80, 1, 2),
38 PLL_RATE(144000000, 96, 1, 2),
39 PLL_RATE(168000000, 56, 1, 1),
40 PLL_RATE(192000000, 64, 1, 1),
41 PLL_RATE(216000000, 72, 1, 1),
42 PLL_RATE(240000000, 80, 1, 1),
43 PLL_RATE(264000000, 88, 1, 1),
44 PLL_RATE(288000000, 96, 1, 1),
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 PLL_RATE(1560000000, 65, 1, 0),
98 PLL_RATE(1584000000, 66, 1, 0),
99 PLL_RATE(1608000000, 67, 1, 0),
100 PLL_RATE(1632000000, 68, 1, 0),
101 PLL_RATE(1656000000, 68, 1, 0),
102 PLL_RATE(1680000000, 68, 1, 0),
103 PLL_RATE(1704000000, 68, 1, 0),
104 PLL_RATE(1728000000, 69, 1, 0),
105 PLL_RATE(1752000000, 69, 1, 0),
106 PLL_RATE(1776000000, 69, 1, 0),
107 PLL_RATE(1800000000, 69, 1, 0),
108 PLL_RATE(1824000000, 70, 1, 0),
109 PLL_RATE(1848000000, 70, 1, 0),
110 PLL_RATE(1872000000, 70, 1, 0),
111 PLL_RATE(1896000000, 70, 1, 0),
112 PLL_RATE(1920000000, 71, 1, 0),
113 PLL_RATE(1944000000, 71, 1, 0),
114 PLL_RATE(1968000000, 71, 1, 0),
115 PLL_RATE(1992000000, 71, 1, 0),
116 PLL_RATE(2016000000, 72, 1, 0),
117 PLL_RATE(2040000000, 72, 1, 0),
118 PLL_RATE(2064000000, 72, 1, 0),
119 PLL_RATE(2088000000, 72, 1, 0),
120 PLL_RATE(2112000000, 73, 1, 0),
121 { /* sentinel */ },
122};
123
0d48fc55 124static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
738f66d3
MT		 125 PLL_RATE(96000000, 32, 1, 3),
126 PLL_RATE(99000000, 33, 1, 3),
127 PLL_RATE(102000000, 34, 1, 3),
128 PLL_RATE(105000000, 35, 1, 3),
129 PLL_RATE(108000000, 36, 1, 3),
130 PLL_RATE(111000000, 37, 1, 3),
131 PLL_RATE(114000000, 38, 1, 3),
132 PLL_RATE(117000000, 39, 1, 3),
133 PLL_RATE(120000000, 40, 1, 3),
134 PLL_RATE(123000000, 41, 1, 3),
135 PLL_RATE(126000000, 42, 1, 3),
136 PLL_RATE(129000000, 43, 1, 3),
137 PLL_RATE(132000000, 44, 1, 3),
138 PLL_RATE(135000000, 45, 1, 3),
139 PLL_RATE(138000000, 46, 1, 3),
140 PLL_RATE(141000000, 47, 1, 3),
141 PLL_RATE(144000000, 48, 1, 3),
142 PLL_RATE(147000000, 49, 1, 3),
143 PLL_RATE(150000000, 50, 1, 3),
144 PLL_RATE(153000000, 51, 1, 3),
145 PLL_RATE(156000000, 52, 1, 3),
146 PLL_RATE(159000000, 53, 1, 3),
147 PLL_RATE(162000000, 54, 1, 3),
148 PLL_RATE(165000000, 55, 1, 3),
149 PLL_RATE(168000000, 56, 1, 3),
150 PLL_RATE(171000000, 57, 1, 3),
151 PLL_RATE(174000000, 58, 1, 3),
152 PLL_RATE(177000000, 59, 1, 3),
153 PLL_RATE(180000000, 60, 1, 3),
154 PLL_RATE(183000000, 61, 1, 3),
155 PLL_RATE(186000000, 62, 1, 3),
156 PLL_RATE(192000000, 32, 1, 2),
157 PLL_RATE(198000000, 33, 1, 2),
158 PLL_RATE(204000000, 34, 1, 2),
159 PLL_RATE(210000000, 35, 1, 2),
160 PLL_RATE(216000000, 36, 1, 2),
161 PLL_RATE(222000000, 37, 1, 2),
162 PLL_RATE(228000000, 38, 1, 2),
163 PLL_RATE(234000000, 39, 1, 2),
164 PLL_RATE(240000000, 40, 1, 2),
165 PLL_RATE(246000000, 41, 1, 2),
166 PLL_RATE(252000000, 42, 1, 2),
167 PLL_RATE(258000000, 43, 1, 2),
168 PLL_RATE(264000000, 44, 1, 2),
169 PLL_RATE(270000000, 45, 1, 2),
170 PLL_RATE(276000000, 46, 1, 2),
171 PLL_RATE(282000000, 47, 1, 2),
172 PLL_RATE(288000000, 48, 1, 2),
173 PLL_RATE(294000000, 49, 1, 2),
174 PLL_RATE(300000000, 50, 1, 2),
175 PLL_RATE(306000000, 51, 1, 2),
176 PLL_RATE(312000000, 52, 1, 2),
177 PLL_RATE(318000000, 53, 1, 2),
178 PLL_RATE(324000000, 54, 1, 2),
179 PLL_RATE(330000000, 55, 1, 2),
180 PLL_RATE(336000000, 56, 1, 2),
181 PLL_RATE(342000000, 57, 1, 2),
182 PLL_RATE(348000000, 58, 1, 2),
183 PLL_RATE(354000000, 59, 1, 2),
184 PLL_RATE(360000000, 60, 1, 2),
185 PLL_RATE(366000000, 61, 1, 2),
186 PLL_RATE(372000000, 62, 1, 2),
187 PLL_RATE(384000000, 32, 1, 1),
188 PLL_RATE(396000000, 33, 1, 1),
189 PLL_RATE(408000000, 34, 1, 1),
190 PLL_RATE(420000000, 35, 1, 1),
191 PLL_RATE(432000000, 36, 1, 1),
192 PLL_RATE(444000000, 37, 1, 1),
193 PLL_RATE(456000000, 38, 1, 1),
194 PLL_RATE(468000000, 39, 1, 1),
195 PLL_RATE(480000000, 40, 1, 1),
196 PLL_RATE(492000000, 41, 1, 1),
197 PLL_RATE(504000000, 42, 1, 1),
198 PLL_RATE(516000000, 43, 1, 1),
199 PLL_RATE(528000000, 44, 1, 1),
200 PLL_RATE(540000000, 45, 1, 1),
201 PLL_RATE(552000000, 46, 1, 1),
202 PLL_RATE(564000000, 47, 1, 1),
203 PLL_RATE(576000000, 48, 1, 1),
204 PLL_RATE(588000000, 49, 1, 1),
205 PLL_RATE(600000000, 50, 1, 1),
206 PLL_RATE(612000000, 51, 1, 1),
207 PLL_RATE(624000000, 52, 1, 1),
208 PLL_RATE(636000000, 53, 1, 1),
209 PLL_RATE(648000000, 54, 1, 1),
210 PLL_RATE(660000000, 55, 1, 1),
211 PLL_RATE(672000000, 56, 1, 1),
212 PLL_RATE(684000000, 57, 1, 1),
213 PLL_RATE(696000000, 58, 1, 1),
214 PLL_RATE(708000000, 59, 1, 1),
215 PLL_RATE(720000000, 60, 1, 1),
216 PLL_RATE(732000000, 61, 1, 1),
217 PLL_RATE(744000000, 62, 1, 1),
218 PLL_RATE(768000000, 32, 1, 0),
219 PLL_RATE(792000000, 33, 1, 0),
220 PLL_RATE(816000000, 34, 1, 0),
221 PLL_RATE(840000000, 35, 1, 0),
222 PLL_RATE(864000000, 36, 1, 0),
223 PLL_RATE(888000000, 37, 1, 0),
224 PLL_RATE(912000000, 38, 1, 0),
225 PLL_RATE(936000000, 39, 1, 0),
226 PLL_RATE(960000000, 40, 1, 0),
227 PLL_RATE(984000000, 41, 1, 0),
228 PLL_RATE(1008000000, 42, 1, 0),
229 PLL_RATE(1032000000, 43, 1, 0),
230 PLL_RATE(1056000000, 44, 1, 0),
231 PLL_RATE(1080000000, 45, 1, 0),
232 PLL_RATE(1104000000, 46, 1, 0),
233 PLL_RATE(1128000000, 47, 1, 0),
234 PLL_RATE(1152000000, 48, 1, 0),
235 PLL_RATE(1176000000, 49, 1, 0),
236 PLL_RATE(1200000000, 50, 1, 0),
237 PLL_RATE(1224000000, 51, 1, 0),
238 PLL_RATE(1248000000, 52, 1, 0),
239 PLL_RATE(1272000000, 53, 1, 0),
240 PLL_RATE(1296000000, 54, 1, 0),
241 PLL_RATE(1320000000, 55, 1, 0),
242 PLL_RATE(1344000000, 56, 1, 0),
243 PLL_RATE(1368000000, 57, 1, 0),
244 PLL_RATE(1392000000, 58, 1, 0),
245 PLL_RATE(1416000000, 59, 1, 0),
246 PLL_RATE(1440000000, 60, 1, 0),
247 PLL_RATE(1464000000, 61, 1, 0),
248 PLL_RATE(1488000000, 62, 1, 0),
249 { /* sentinel */ },
250};
251
0d48fc55
NA		 252static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
253 PLL_RATE(504000000, 42, 1, 1),
254 PLL_RATE(516000000, 43, 1, 1),
255 PLL_RATE(528000000, 44, 1, 1),
256 PLL_RATE(540000000, 45, 1, 1),
257 PLL_RATE(552000000, 46, 1, 1),
258 PLL_RATE(564000000, 47, 1, 1),
259 PLL_RATE(576000000, 48, 1, 1),
260 PLL_RATE(588000000, 49, 1, 1),
261 PLL_RATE(600000000, 50, 1, 1),
262 PLL_RATE(612000000, 51, 1, 1),
263 PLL_RATE(624000000, 52, 1, 1),
264 PLL_RATE(636000000, 53, 1, 1),
265 PLL_RATE(648000000, 54, 1, 1),
266 PLL_RATE(660000000, 55, 1, 1),
267 PLL_RATE(672000000, 56, 1, 1),
268 PLL_RATE(684000000, 57, 1, 1),
269 PLL_RATE(696000000, 58, 1, 1),
270 PLL_RATE(708000000, 59, 1, 1),
271 PLL_RATE(720000000, 60, 1, 1),
272 PLL_RATE(732000000, 61, 1, 1),
273 PLL_RATE(744000000, 62, 1, 1),
274 PLL_RATE(756000000, 63, 1, 1),
275 PLL_RATE(768000000, 64, 1, 1),
276 PLL_RATE(780000000, 65, 1, 1),
277 PLL_RATE(792000000, 66, 1, 1),
278 { /* sentinel */ },
279};
280
738f66d3
MT		 281static struct meson_clk_pll gxbb_fixed_pll = {
282 .m = {
283 .reg_off = HHI_MPLL_CNTL,
284 .shift = 0,
285 .width = 9,
286 },
287 .n = {
288 .reg_off = HHI_MPLL_CNTL,
289 .shift = 9,
290 .width = 5,
291 },
292 .od = {
293 .reg_off = HHI_MPLL_CNTL,
294 .shift = 16,
295 .width = 2,
296 },
297 .lock = &clk_lock,
298 .hw.init = &(struct clk_init_data){
299 .name = "fixed_pll",
300 .ops = &meson_clk_pll_ro_ops,
301 .parent_names = (const char *[]){ "xtal" },
302 .num_parents = 1,
303 .flags = CLK_GET_RATE_NOCACHE,
304 },
305};
306
307static struct meson_clk_pll gxbb_hdmi_pll = {
308 .m = {
309 .reg_off = HHI_HDMI_PLL_CNTL,
310 .shift = 0,
311 .width = 9,
312 },
313 .n = {
314 .reg_off = HHI_HDMI_PLL_CNTL,
315 .shift = 9,
316 .width = 5,
317 },
318 .frac = {
319 .reg_off = HHI_HDMI_PLL_CNTL2,
320 .shift = 0,
321 .width = 12,
322 },
323 .od = {
324 .reg_off = HHI_HDMI_PLL_CNTL2,
325 .shift = 16,
326 .width = 2,
327 },
328 .od2 = {
329 .reg_off = HHI_HDMI_PLL_CNTL2,
330 .shift = 22,
331 .width = 2,
332 },
333 .lock = &clk_lock,
334 .hw.init = &(struct clk_init_data){
335 .name = "hdmi_pll",
336 .ops = &meson_clk_pll_ro_ops,
337 .parent_names = (const char *[]){ "xtal" },
338 .num_parents = 1,
339 .flags = CLK_GET_RATE_NOCACHE,
340 },
341};
342
343static struct meson_clk_pll gxbb_sys_pll = {
344 .m = {
345 .reg_off = HHI_SYS_PLL_CNTL,
346 .shift = 0,
347 .width = 9,
348 },
349 .n = {
350 .reg_off = HHI_SYS_PLL_CNTL,
351 .shift = 9,
352 .width = 5,
353 },
354 .od = {
355 .reg_off = HHI_SYS_PLL_CNTL,
356 .shift = 10,
357 .width = 2,
358 },
359 .rate_table = sys_pll_rate_table,
360 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
361 .lock = &clk_lock,
362 .hw.init = &(struct clk_init_data){
363 .name = "sys_pll",
364 .ops = &meson_clk_pll_ro_ops,
365 .parent_names = (const char *[]){ "xtal" },
366 .num_parents = 1,
367 .flags = CLK_GET_RATE_NOCACHE,
368 },
369};
370
e194401c
NA		 371struct pll_params_table gxbb_gp0_params_table[] = {
372 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
373 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
374 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
375 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
376};
377
738f66d3
MT		 378static struct meson_clk_pll gxbb_gp0_pll = {
379 .m = {
380 .reg_off = HHI_GP0_PLL_CNTL,
381 .shift = 0,
382 .width = 9,
383 },
384 .n = {
385 .reg_off = HHI_GP0_PLL_CNTL,
386 .shift = 9,
387 .width = 5,
388 },
389 .od = {
390 .reg_off = HHI_GP0_PLL_CNTL,
391 .shift = 16,
392 .width = 2,
393 },
e194401c
NA		 394 .params = {
395 .params_table = gxbb_gp0_params_table,
396 .params_count = ARRAY_SIZE(gxbb_gp0_params_table),
397 .no_init_reset = true,
398 .clear_reset_for_lock = true,
399 },
0d48fc55
NA		 400 .rate_table = gxbb_gp0_pll_rate_table,
401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
402 .lock = &clk_lock,
403 .hw.init = &(struct clk_init_data){
404 .name = "gp0_pll",
405 .ops = &meson_clk_pll_ops,
406 .parent_names = (const char *[]){ "xtal" },
407 .num_parents = 1,
408 .flags = CLK_GET_RATE_NOCACHE,
409 },
410};
411
412struct pll_params_table gxl_gp0_params_table[] = {
413 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
414 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
415 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
416 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
417 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
418 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
419};
420
421static struct meson_clk_pll gxl_gp0_pll = {
422 .m = {
423 .reg_off = HHI_GP0_PLL_CNTL,
424 .shift = 0,
425 .width = 9,
426 },
427 .n = {
428 .reg_off = HHI_GP0_PLL_CNTL,
429 .shift = 9,
430 .width = 5,
431 },
432 .od = {
433 .reg_off = HHI_GP0_PLL_CNTL,
434 .shift = 16,
435 .width = 2,
436 },
437 .params = {
438 .params_table = gxl_gp0_params_table,
439 .params_count = ARRAY_SIZE(gxl_gp0_params_table),
440 .no_init_reset = true,
441 .reset_lock_loop = true,
442 },
443 .rate_table = gxl_gp0_pll_rate_table,
444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
738f66d3
MT		 445 .lock = &clk_lock,
446 .hw.init = &(struct clk_init_data){
447 .name = "gp0_pll",
448 .ops = &meson_clk_pll_ops,
449 .parent_names = (const char *[]){ "xtal" },
450 .num_parents = 1,
451 .flags = CLK_GET_RATE_NOCACHE,
452 },
453};
454
455static struct clk_fixed_factor gxbb_fclk_div2 = {
456 .mult = 1,
457 .div = 2,
458 .hw.init = &(struct clk_init_data){
459 .name = "fclk_div2",
460 .ops = &clk_fixed_factor_ops,
461 .parent_names = (const char *[]){ "fixed_pll" },
462 .num_parents = 1,
463 },
464};
465
466static struct clk_fixed_factor gxbb_fclk_div3 = {
467 .mult = 1,
468 .div = 3,
469 .hw.init = &(struct clk_init_data){
470 .name = "fclk_div3",
471 .ops = &clk_fixed_factor_ops,
472 .parent_names = (const char *[]){ "fixed_pll" },
473 .num_parents = 1,
474 },
475};
476
477static struct clk_fixed_factor gxbb_fclk_div4 = {
478 .mult = 1,
479 .div = 4,
480 .hw.init = &(struct clk_init_data){
481 .name = "fclk_div4",
482 .ops = &clk_fixed_factor_ops,
483 .parent_names = (const char *[]){ "fixed_pll" },
484 .num_parents = 1,
485 },
486};
487
488static struct clk_fixed_factor gxbb_fclk_div5 = {
489 .mult = 1,
490 .div = 5,
491 .hw.init = &(struct clk_init_data){
492 .name = "fclk_div5",
493 .ops = &clk_fixed_factor_ops,
494 .parent_names = (const char *[]){ "fixed_pll" },
495 .num_parents = 1,
496 },
497};
498
499static struct clk_fixed_factor gxbb_fclk_div7 = {
500 .mult = 1,
501 .div = 7,
502 .hw.init = &(struct clk_init_data){
503 .name = "fclk_div7",
504 .ops = &clk_fixed_factor_ops,
505 .parent_names = (const char *[]){ "fixed_pll" },
506 .num_parents = 1,
507 },
508};
509
510static struct meson_clk_mpll gxbb_mpll0 = {
511 .sdm = {
512 .reg_off = HHI_MPLL_CNTL7,
513 .shift = 0,
514 .width = 14,
515 },
007e6e5c
JB		 516 .sdm_en = {
517 .reg_off = HHI_MPLL_CNTL7,
518 .shift = 15,
519 .width = 1,
520 },
738f66d3
MT		 521 .n2 = {
522 .reg_off = HHI_MPLL_CNTL7,
523 .shift = 16,
524 .width = 9,
525 },
007e6e5c
JB		 526 .en = {
527 .reg_off = HHI_MPLL_CNTL7,
528 .shift = 14,
529 .width = 1,
530 },
1f737ffa
JB		 531 .ssen = {
532 .reg_off = HHI_MPLL_CNTL,
533 .shift = 25,
534 .width = 1,
535 },
738f66d3
MT		 536 .lock = &clk_lock,
537 .hw.init = &(struct clk_init_data){
538 .name = "mpll0",
05b43aa2 539 .ops = &meson_clk_mpll_ops,
738f66d3
MT		 540 .parent_names = (const char *[]){ "fixed_pll" },
541 .num_parents = 1,
542 },
543};
544
545static struct meson_clk_mpll gxbb_mpll1 = {
546 .sdm = {
547 .reg_off = HHI_MPLL_CNTL8,
548 .shift = 0,
549 .width = 14,
550 },
007e6e5c
JB		 551 .sdm_en = {
552 .reg_off = HHI_MPLL_CNTL8,
553 .shift = 15,
554 .width = 1,
555 },
738f66d3
MT		 556 .n2 = {
557 .reg_off = HHI_MPLL_CNTL8,
558 .shift = 16,
559 .width = 9,
560 },
007e6e5c
JB		 561 .en = {
562 .reg_off = HHI_MPLL_CNTL8,
563 .shift = 14,
564 .width = 1,
565 },
738f66d3
MT		 566 .lock = &clk_lock,
567 .hw.init = &(struct clk_init_data){
568 .name = "mpll1",
05b43aa2 569 .ops = &meson_clk_mpll_ops,
738f66d3
MT		 570 .parent_names = (const char *[]){ "fixed_pll" },
571 .num_parents = 1,
572 },
573};
574
575static struct meson_clk_mpll gxbb_mpll2 = {
576 .sdm = {
577 .reg_off = HHI_MPLL_CNTL9,
578 .shift = 0,
579 .width = 14,
580 },
007e6e5c
JB		 581 .sdm_en = {
582 .reg_off = HHI_MPLL_CNTL9,
583 .shift = 15,
584 .width = 1,
585 },
738f66d3
MT		 586 .n2 = {
587 .reg_off = HHI_MPLL_CNTL9,
588 .shift = 16,
589 .width = 9,
590 },
007e6e5c
JB		 591 .en = {
592 .reg_off = HHI_MPLL_CNTL9,
593 .shift = 14,
594 .width = 1,
595 },
738f66d3
MT		 596 .lock = &clk_lock,
597 .hw.init = &(struct clk_init_data){
598 .name = "mpll2",
05b43aa2 599 .ops = &meson_clk_mpll_ops,
738f66d3
MT		 600 .parent_names = (const char *[]){ "fixed_pll" },
601 .num_parents = 1,
602 },
603};
604
605/*
96b61c8d
MB		 606 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
607 * and should be modeled with their respective PLLs via the forthcoming
608 * coordinated clock rates feature
738f66d3 609 */
738f66d3 610
215c80a7
JB		 611static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
612static const char * const clk81_parent_names[] = {
613 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
614 "fclk_div3", "fclk_div5"
615};
738f66d3
MT		 616
617static struct clk_mux gxbb_mpeg_clk_sel = {
618 .reg = (void *)HHI_MPEG_CLK_CNTL,
619 .mask = 0x7,
620 .shift = 12,
621 .flags = CLK_MUX_READ_ONLY,
622 .table = mux_table_clk81,
623 .lock = &clk_lock,
624 .hw.init = &(struct clk_init_data){
625 .name = "mpeg_clk_sel",
626 .ops = &clk_mux_ro_ops,
627 /*
215c80a7 628 * bits 14:12 selects from 8 possible parents:
738f66d3
MT		 629 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
630 * fclk_div4, fclk_div3, fclk_div5
631 */
215c80a7
JB		 632 .parent_names = clk81_parent_names,
633 .num_parents = ARRAY_SIZE(clk81_parent_names),
738f66d3
MT		 634 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
635 },
636};
637
638static struct clk_divider gxbb_mpeg_clk_div = {
639 .reg = (void *)HHI_MPEG_CLK_CNTL,
640 .shift = 0,
641 .width = 7,
642 .lock = &clk_lock,
643 .hw.init = &(struct clk_init_data){
644 .name = "mpeg_clk_div",
645 .ops = &clk_divider_ops,
646 .parent_names = (const char *[]){ "mpeg_clk_sel" },
647 .num_parents = 1,
648 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
649 },
650};
651
652/* the mother of dragons^W gates */
653static struct clk_gate gxbb_clk81 = {
654 .reg = (void *)HHI_MPEG_CLK_CNTL,
655 .bit_idx = 7,
656 .lock = &clk_lock,
657 .hw.init = &(struct clk_init_data){
658 .name = "clk81",
659 .ops = &clk_gate_ops,
660 .parent_names = (const char *[]){ "mpeg_clk_div" },
661 .num_parents = 1,
39c42ca9 662 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
738f66d3
MT		 663 },
664};
665
33d0fcdf
MB		 666static struct clk_mux gxbb_sar_adc_clk_sel = {
667 .reg = (void *)HHI_SAR_CLK_CNTL,
668 .mask = 0x3,
669 .shift = 9,
670 .lock = &clk_lock,
671 .hw.init = &(struct clk_init_data){
672 .name = "sar_adc_clk_sel",
673 .ops = &clk_mux_ops,
674 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675 .parent_names = (const char *[]){ "xtal", "clk81", },
676 .num_parents = 2,
677 },
678};
679
680static struct clk_divider gxbb_sar_adc_clk_div = {
681 .reg = (void *)HHI_SAR_CLK_CNTL,
682 .shift = 0,
683 .width = 8,
684 .lock = &clk_lock,
685 .hw.init = &(struct clk_init_data){
686 .name = "sar_adc_clk_div",
687 .ops = &clk_divider_ops,
688 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
689 .num_parents = 1,
690 },
691};
692
693static struct clk_gate gxbb_sar_adc_clk = {
694 .reg = (void *)HHI_SAR_CLK_CNTL,
695 .bit_idx = 8,
696 .lock = &clk_lock,
697 .hw.init = &(struct clk_init_data){
698 .name = "sar_adc_clk",
699 .ops = &clk_gate_ops,
700 .parent_names = (const char *[]){ "sar_adc_clk_div" },
701 .num_parents = 1,
702 .flags = CLK_SET_RATE_PARENT,
703 },
704};
705
fac9a55b
NA		 706/*
707 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
708 * muxed by a glitch-free switch.
709 */
710
711static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
c3c4cb8d 712static const char * const gxbb_mali_0_1_parent_names[] = {
fac9a55b
NA		 713 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
714 "fclk_div4", "fclk_div3", "fclk_div5"
715};
716
717static struct clk_mux gxbb_mali_0_sel = {
718 .reg = (void *)HHI_MALI_CLK_CNTL,
719 .mask = 0x7,
720 .shift = 9,
721 .table = mux_table_mali_0_1,
722 .lock = &clk_lock,
723 .hw.init = &(struct clk_init_data){
724 .name = "mali_0_sel",
725 .ops = &clk_mux_ops,
726 /*
727 * bits 10:9 selects from 8 possible parents:
728 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
729 * fclk_div4, fclk_div3, fclk_div5
730 */
731 .parent_names = gxbb_mali_0_1_parent_names,
732 .num_parents = 8,
733 .flags = CLK_SET_RATE_NO_REPARENT,
734 },
735};
736
737static struct clk_divider gxbb_mali_0_div = {
738 .reg = (void *)HHI_MALI_CLK_CNTL,
739 .shift = 0,
740 .width = 7,
741 .lock = &clk_lock,
742 .hw.init = &(struct clk_init_data){
743 .name = "mali_0_div",
744 .ops = &clk_divider_ops,
745 .parent_names = (const char *[]){ "mali_0_sel" },
746 .num_parents = 1,
747 .flags = CLK_SET_RATE_NO_REPARENT,
748 },
749};
750
751static struct clk_gate gxbb_mali_0 = {
752 .reg = (void *)HHI_MALI_CLK_CNTL,
753 .bit_idx = 8,
754 .lock = &clk_lock,
755 .hw.init = &(struct clk_init_data){
756 .name = "mali_0",
757 .ops = &clk_gate_ops,
758 .parent_names = (const char *[]){ "mali_0_div" },
759 .num_parents = 1,
760 .flags = CLK_SET_RATE_PARENT,
761 },
762};
763
764static struct clk_mux gxbb_mali_1_sel = {
765 .reg = (void *)HHI_MALI_CLK_CNTL,
766 .mask = 0x7,
767 .shift = 25,
768 .table = mux_table_mali_0_1,
769 .lock = &clk_lock,
770 .hw.init = &(struct clk_init_data){
771 .name = "mali_1_sel",
772 .ops = &clk_mux_ops,
773 /*
774 * bits 10:9 selects from 8 possible parents:
775 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
776 * fclk_div4, fclk_div3, fclk_div5
777 */
778 .parent_names = gxbb_mali_0_1_parent_names,
779 .num_parents = 8,
780 .flags = CLK_SET_RATE_NO_REPARENT,
781 },
782};
783
784static struct clk_divider gxbb_mali_1_div = {
785 .reg = (void *)HHI_MALI_CLK_CNTL,
786 .shift = 16,
787 .width = 7,
788 .lock = &clk_lock,
789 .hw.init = &(struct clk_init_data){
790 .name = "mali_1_div",
791 .ops = &clk_divider_ops,
792 .parent_names = (const char *[]){ "mali_1_sel" },
793 .num_parents = 1,
794 .flags = CLK_SET_RATE_NO_REPARENT,
795 },
796};
797
798static struct clk_gate gxbb_mali_1 = {
799 .reg = (void *)HHI_MALI_CLK_CNTL,
800 .bit_idx = 24,
801 .lock = &clk_lock,
802 .hw.init = &(struct clk_init_data){
803 .name = "mali_1",
804 .ops = &clk_gate_ops,
805 .parent_names = (const char *[]){ "mali_1_div" },
806 .num_parents = 1,
807 .flags = CLK_SET_RATE_PARENT,
808 },
809};
810
811static u32 mux_table_mali[] = {0, 1};
c3c4cb8d 812static const char * const gxbb_mali_parent_names[] = {
fac9a55b
NA		 813 "mali_0", "mali_1"
814};
815
816static struct clk_mux gxbb_mali = {
817 .reg = (void *)HHI_MALI_CLK_CNTL,
818 .mask = 1,
819 .shift = 31,
820 .table = mux_table_mali,
821 .lock = &clk_lock,
822 .hw.init = &(struct clk_init_data){
823 .name = "mali",
824 .ops = &clk_mux_ops,
825 .parent_names = gxbb_mali_parent_names,
826 .num_parents = 2,
827 .flags = CLK_SET_RATE_NO_REPARENT,
828 },
829};
830
4087bd4b
JB		 831static struct clk_mux gxbb_cts_amclk_sel = {
832 .reg = (void *) HHI_AUD_CLK_CNTL,
833 .mask = 0x3,
834 .shift = 9,
835 /* Default parent unknown (register reset value: 0) */
836 .table = (u32[]){ 1, 2, 3 },
837 .lock = &clk_lock,
838 .hw.init = &(struct clk_init_data){
839 .name = "cts_amclk_sel",
840 .ops = &clk_mux_ops,
841 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
842 .num_parents = 3,
843 .flags = CLK_SET_RATE_PARENT,
844 },
845};
846
847static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
848 .div = {
849 .reg_off = HHI_AUD_CLK_CNTL,
850 .shift = 0,
851 .width = 8,
852 },
004f6f46 853 .flags = CLK_DIVIDER_ROUND_CLOSEST,
4087bd4b
JB		 854 .lock = &clk_lock,
855 .hw.init = &(struct clk_init_data){
856 .name = "cts_amclk_div",
857 .ops = &meson_clk_audio_divider_ops,
858 .parent_names = (const char *[]){ "cts_amclk_sel" },
859 .num_parents = 1,
004f6f46 860 .flags = CLK_SET_RATE_PARENT,
4087bd4b
JB		 861 },
862};
863
864static struct clk_gate gxbb_cts_amclk = {
865 .reg = (void *) HHI_AUD_CLK_CNTL,
866 .bit_idx = 8,
867 .lock = &clk_lock,
868 .hw.init = &(struct clk_init_data){
869 .name = "cts_amclk",
870 .ops = &clk_gate_ops,
871 .parent_names = (const char *[]){ "cts_amclk_div" },
872 .num_parents = 1,
873 .flags = CLK_SET_RATE_PARENT,
874 },
875};
876
3c277c24
JB		 877static struct clk_mux gxbb_cts_mclk_i958_sel = {
878 .reg = (void *)HHI_AUD_CLK_CNTL2,
879 .mask = 0x3,
880 .shift = 25,
881 /* Default parent unknown (register reset value: 0) */
882 .table = (u32[]){ 1, 2, 3 },
883 .lock = &clk_lock,
7605aa5b 884 .hw.init = &(struct clk_init_data) {
3c277c24
JB		 885 .name = "cts_mclk_i958_sel",
886 .ops = &clk_mux_ops,
887 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
888 .num_parents = 3,
889 .flags = CLK_SET_RATE_PARENT,
890 },
891};
892
893static struct clk_divider gxbb_cts_mclk_i958_div = {
894 .reg = (void *)HHI_AUD_CLK_CNTL2,
895 .shift = 16,
896 .width = 8,
897 .lock = &clk_lock,
7605aa5b
JB		 898 .flags = CLK_DIVIDER_ROUND_CLOSEST,
899 .hw.init = &(struct clk_init_data) {
3c277c24
JB		 900 .name = "cts_mclk_i958_div",
901 .ops = &clk_divider_ops,
902 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
903 .num_parents = 1,
7605aa5b 904 .flags = CLK_SET_RATE_PARENT,
3c277c24
JB		 905 },
906};
907
908static struct clk_gate gxbb_cts_mclk_i958 = {
909 .reg = (void *)HHI_AUD_CLK_CNTL2,
910 .bit_idx = 24,
911 .lock = &clk_lock,
912 .hw.init = &(struct clk_init_data){
913 .name = "cts_mclk_i958",
914 .ops = &clk_gate_ops,
915 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
916 .num_parents = 1,
917 .flags = CLK_SET_RATE_PARENT,
918 },
919};
920
7eaa44f6
JB		 921static struct clk_mux gxbb_cts_i958 = {
922 .reg = (void *)HHI_AUD_CLK_CNTL2,
923 .mask = 0x1,
924 .shift = 27,
925 .lock = &clk_lock,
926 .hw.init = &(struct clk_init_data){
927 .name = "cts_i958",
928 .ops = &clk_mux_ops,
929 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
930 .num_parents = 2,
931 /*
932 *The parent is specific to origin of the audio data. Let the
933 * consumer choose the appropriate parent
934 */
935 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
936 },
937};
938
14c735c8
NA		 939static struct clk_divider gxbb_32k_clk_div = {
940 .reg = (void *)HHI_32K_CLK_CNTL,
941 .shift = 0,
942 .width = 14,
943 .lock = &clk_lock,
944 .hw.init = &(struct clk_init_data){
945 .name = "32k_clk_div",
946 .ops = &clk_divider_ops,
947 .parent_names = (const char *[]){ "32k_clk_sel" },
948 .num_parents = 1,
949 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
950 },
951};
952
953static struct clk_gate gxbb_32k_clk = {
954 .reg = (void *)HHI_32K_CLK_CNTL,
955 .bit_idx = 15,
956 .lock = &clk_lock,
957 .hw.init = &(struct clk_init_data){
958 .name = "32k_clk",
959 .ops = &clk_gate_ops,
960 .parent_names = (const char *[]){ "32k_clk_div" },
961 .num_parents = 1,
962 .flags = CLK_SET_RATE_PARENT,
963 },
964};
965
c3c4cb8d 966static const char * const gxbb_32k_clk_parent_names[] = {
14c735c8
NA		 967 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
968};
969
970static struct clk_mux gxbb_32k_clk_sel = {
971 .reg = (void *)HHI_32K_CLK_CNTL,
972 .mask = 0x3,
973 .shift = 16,
974 .lock = &clk_lock,
975 .hw.init = &(struct clk_init_data){
976 .name = "32k_clk_sel",
977 .ops = &clk_mux_ops,
978 .parent_names = gxbb_32k_clk_parent_names,
979 .num_parents = 4,
980 .flags = CLK_SET_RATE_PARENT,
981 },
982};
983
914e6e80
JB		 984static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
985 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
986
987 /*
988 * Following these parent clocks, we should also have had mpll2, mpll3
989 * and gp0_pll but these clocks are too precious to be used here. All
990 * the necessary rates for MMC and NAND operation can be acheived using
991 * xtal or fclk_div clocks
992 */
993};
994
995/* SDIO clock */
996static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
997 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
998 .mask = 0x7,
999 .shift = 9,
1000 .lock = &clk_lock,
1001 .hw.init = &(struct clk_init_data) {
1002 .name = "sd_emmc_a_clk0_sel",
1003 .ops = &clk_mux_ops,
1004 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1005 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1006 .flags = CLK_SET_RATE_PARENT,
1007 },
1008};
1009
1010static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
1011 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1012 .shift = 0,
1013 .width = 7,
1014 .lock = &clk_lock,
1015 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1016 .hw.init = &(struct clk_init_data) {
1017 .name = "sd_emmc_a_clk0_div",
1018 .ops = &clk_divider_ops,
1019 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1020 .num_parents = 1,
1021 .flags = CLK_SET_RATE_PARENT,
1022 },
1023};
1024
1025static struct clk_gate gxbb_sd_emmc_a_clk0 = {
1026 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1027 .bit_idx = 7,
1028 .lock = &clk_lock,
1029 .hw.init = &(struct clk_init_data){
1030 .name = "sd_emmc_a_clk0",
1031 .ops = &clk_gate_ops,
1032 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1033 .num_parents = 1,
1034
1035 /*
1036 * FIXME:
1037 * We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
1038 * instead of this clock. CCF would gate this on boot, killing
1039 * the mmc controller. Please remove this flag once DT properly
1040 * point to this clock instead of xtal
1041 *
1042 * Same goes for emmc B and C clocks
1043 */
1044 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1045 },
1046};
1047
1048/* SDcard clock */
1049static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
1050 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1051 .mask = 0x7,
1052 .shift = 25,
1053 .lock = &clk_lock,
1054 .hw.init = &(struct clk_init_data) {
1055 .name = "sd_emmc_b_clk0_sel",
1056 .ops = &clk_mux_ops,
1057 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1058 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1059 .flags = CLK_SET_RATE_PARENT,
1060 },
1061};
1062
1063static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
1064 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1065 .shift = 16,
1066 .width = 7,
1067 .lock = &clk_lock,
1068 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1069 .hw.init = &(struct clk_init_data) {
1070 .name = "sd_emmc_b_clk0_div",
1071 .ops = &clk_divider_ops,
1072 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1073 .num_parents = 1,
1074 .flags = CLK_SET_RATE_PARENT,
1075 },
1076};
1077
1078static struct clk_gate gxbb_sd_emmc_b_clk0 = {
1079 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1080 .bit_idx = 23,
1081 .lock = &clk_lock,
1082 .hw.init = &(struct clk_init_data){
1083 .name = "sd_emmc_b_clk0",
1084 .ops = &clk_gate_ops,
1085 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1086 .num_parents = 1,
1087 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1088 },
1089};
1090
1091/* EMMC/NAND clock */
1092static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
1093 .reg = (void *)HHI_NAND_CLK_CNTL,
1094 .mask = 0x7,
1095 .shift = 9,
1096 .lock = &clk_lock,
1097 .hw.init = &(struct clk_init_data) {
1098 .name = "sd_emmc_c_clk0_sel",
1099 .ops = &clk_mux_ops,
1100 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1101 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1102 .flags = CLK_SET_RATE_PARENT,
1103 },
1104};
1105
1106static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
1107 .reg = (void *)HHI_NAND_CLK_CNTL,
1108 .shift = 0,
1109 .width = 7,
1110 .lock = &clk_lock,
1111 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1112 .hw.init = &(struct clk_init_data) {
1113 .name = "sd_emmc_c_clk0_div",
1114 .ops = &clk_divider_ops,
1115 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1116 .num_parents = 1,
1117 .flags = CLK_SET_RATE_PARENT,
1118 },
1119};
1120
1121static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1122 .reg = (void *)HHI_NAND_CLK_CNTL,
1123 .bit_idx = 7,
1124 .lock = &clk_lock,
1125 .hw.init = &(struct clk_init_data){
1126 .name = "sd_emmc_c_clk0",
1127 .ops = &clk_gate_ops,
1128 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1131 },
1132};
1133
762a1f20
NA		 1134/* VPU Clock */
1135
1136static u32 mux_table_vpu[] = {0, 1, 2, 3};
1137static const char * const gxbb_vpu_parent_names[] = {
1138 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1139};
1140
1141static struct clk_mux gxbb_vpu_0_sel = {
1142 .reg = (void *)HHI_VPU_CLK_CNTL,
1143 .mask = 0x3,
1144 .shift = 9,
1145 .lock = &clk_lock,
1146 .table = mux_table_vpu,
1147 .hw.init = &(struct clk_init_data){
1148 .name = "vpu_0_sel",
1149 .ops = &clk_mux_ops,
1150 /*
1151 * bits 9:10 selects from 4 possible parents:
1152 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1153 */
1154 .parent_names = gxbb_vpu_parent_names,
1155 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1156 .flags = CLK_SET_RATE_NO_REPARENT,
1157 },
1158};
1159
1160static struct clk_divider gxbb_vpu_0_div = {
1161 .reg = (void *)HHI_VPU_CLK_CNTL,
1162 .shift = 0,
1163 .width = 7,
1164 .lock = &clk_lock,
1165 .hw.init = &(struct clk_init_data){
1166 .name = "vpu_0_div",
1167 .ops = &clk_divider_ops,
1168 .parent_names = (const char *[]){ "vpu_0_sel" },
1169 .num_parents = 1,
1170 .flags = CLK_SET_RATE_PARENT,
1171 },
1172};
1173
1174static struct clk_gate gxbb_vpu_0 = {
1175 .reg = (void *)HHI_VPU_CLK_CNTL,
1176 .bit_idx = 8,
1177 .lock = &clk_lock,
1178 .hw.init = &(struct clk_init_data) {
1179 .name = "vpu_0",
1180 .ops = &clk_gate_ops,
1181 .parent_names = (const char *[]){ "vpu_0_div" },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1184 },
1185};
1186
1187static struct clk_mux gxbb_vpu_1_sel = {
1188 .reg = (void *)HHI_VPU_CLK_CNTL,
1189 .mask = 0x3,
1190 .shift = 25,
1191 .lock = &clk_lock,
1192 .table = mux_table_vpu,
1193 .hw.init = &(struct clk_init_data){
1194 .name = "vpu_1_sel",
1195 .ops = &clk_mux_ops,
1196 /*
1197 * bits 25:26 selects from 4 possible parents:
1198 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1199 */
1200 .parent_names = gxbb_vpu_parent_names,
1201 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1202 .flags = CLK_SET_RATE_NO_REPARENT,
1203 },
1204};
1205
1206static struct clk_divider gxbb_vpu_1_div = {
1207 .reg = (void *)HHI_VPU_CLK_CNTL,
1208 .shift = 16,
1209 .width = 7,
1210 .lock = &clk_lock,
1211 .hw.init = &(struct clk_init_data){
1212 .name = "vpu_1_div",
1213 .ops = &clk_divider_ops,
1214 .parent_names = (const char *[]){ "vpu_1_sel" },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 },
1218};
1219
1220static struct clk_gate gxbb_vpu_1 = {
1221 .reg = (void *)HHI_VPU_CLK_CNTL,
1222 .bit_idx = 24,
1223 .lock = &clk_lock,
1224 .hw.init = &(struct clk_init_data) {
1225 .name = "vpu_1",
1226 .ops = &clk_gate_ops,
1227 .parent_names = (const char *[]){ "vpu_1_div" },
1228 .num_parents = 1,
1229 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1230 },
1231};
1232
1233static struct clk_mux gxbb_vpu = {
1234 .reg = (void *)HHI_VPU_CLK_CNTL,
1235 .mask = 1,
1236 .shift = 31,
1237 .lock = &clk_lock,
1238 .hw.init = &(struct clk_init_data){
1239 .name = "vpu",
1240 .ops = &clk_mux_ops,
1241 /*
1242 * bit 31 selects from 2 possible parents:
1243 * vpu_0 or vpu_1
1244 */
1245 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1246 .num_parents = 2,
1247 .flags = CLK_SET_RATE_NO_REPARENT,
1248 },
1249};
1250
1251/* VAPB Clock */
1252
1253static u32 mux_table_vapb[] = {0, 1, 2, 3};
1254static const char * const gxbb_vapb_parent_names[] = {
1255 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1256};
1257
1258static struct clk_mux gxbb_vapb_0_sel = {
1259 .reg = (void *)HHI_VAPBCLK_CNTL,
1260 .mask = 0x3,
1261 .shift = 9,
1262 .lock = &clk_lock,
1263 .table = mux_table_vapb,
1264 .hw.init = &(struct clk_init_data){
1265 .name = "vapb_0_sel",
1266 .ops = &clk_mux_ops,
1267 /*
1268 * bits 9:10 selects from 4 possible parents:
1269 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1270 */
1271 .parent_names = gxbb_vapb_parent_names,
1272 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1273 .flags = CLK_SET_RATE_NO_REPARENT,
1274 },
1275};
1276
1277static struct clk_divider gxbb_vapb_0_div = {
1278 .reg = (void *)HHI_VAPBCLK_CNTL,
1279 .shift = 0,
1280 .width = 7,
1281 .lock = &clk_lock,
1282 .hw.init = &(struct clk_init_data){
1283 .name = "vapb_0_div",
1284 .ops = &clk_divider_ops,
1285 .parent_names = (const char *[]){ "vapb_0_sel" },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 },
1289};
1290
1291static struct clk_gate gxbb_vapb_0 = {
1292 .reg = (void *)HHI_VAPBCLK_CNTL,
1293 .bit_idx = 8,
1294 .lock = &clk_lock,
1295 .hw.init = &(struct clk_init_data) {
1296 .name = "vapb_0",
1297 .ops = &clk_gate_ops,
1298 .parent_names = (const char *[]){ "vapb_0_div" },
1299 .num_parents = 1,
1300 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1301 },
1302};
1303
1304static struct clk_mux gxbb_vapb_1_sel = {
1305 .reg = (void *)HHI_VAPBCLK_CNTL,
1306 .mask = 0x3,
1307 .shift = 25,
1308 .lock = &clk_lock,
1309 .table = mux_table_vapb,
1310 .hw.init = &(struct clk_init_data){
1311 .name = "vapb_1_sel",
1312 .ops = &clk_mux_ops,
1313 /*
1314 * bits 25:26 selects from 4 possible parents:
1315 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1316 */
1317 .parent_names = gxbb_vapb_parent_names,
1318 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1319 .flags = CLK_SET_RATE_NO_REPARENT,
1320 },
1321};
1322
1323static struct clk_divider gxbb_vapb_1_div = {
1324 .reg = (void *)HHI_VAPBCLK_CNTL,
1325 .shift = 16,
1326 .width = 7,
1327 .lock = &clk_lock,
1328 .hw.init = &(struct clk_init_data){
1329 .name = "vapb_1_div",
1330 .ops = &clk_divider_ops,
1331 .parent_names = (const char *[]){ "vapb_1_sel" },
1332 .num_parents = 1,
1333 .flags = CLK_SET_RATE_PARENT,
1334 },
1335};
1336
1337static struct clk_gate gxbb_vapb_1 = {
1338 .reg = (void *)HHI_VAPBCLK_CNTL,
1339 .bit_idx = 24,
1340 .lock = &clk_lock,
1341 .hw.init = &(struct clk_init_data) {
1342 .name = "vapb_1",
1343 .ops = &clk_gate_ops,
1344 .parent_names = (const char *[]){ "vapb_1_div" },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1347 },
1348};
1349
1350static struct clk_mux gxbb_vapb_sel = {
1351 .reg = (void *)HHI_VAPBCLK_CNTL,
1352 .mask = 1,
1353 .shift = 31,
1354 .lock = &clk_lock,
1355 .hw.init = &(struct clk_init_data){
1356 .name = "vapb_sel",
1357 .ops = &clk_mux_ops,
1358 /*
1359 * bit 31 selects from 2 possible parents:
1360 * vapb_0 or vapb_1
1361 */
1362 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1363 .num_parents = 2,
1364 .flags = CLK_SET_RATE_NO_REPARENT,
1365 },
1366};
1367
1368static struct clk_gate gxbb_vapb = {
1369 .reg = (void *)HHI_VAPBCLK_CNTL,
1370 .bit_idx = 30,
1371 .lock = &clk_lock,
1372 .hw.init = &(struct clk_init_data) {
1373 .name = "vapb",
1374 .ops = &clk_gate_ops,
1375 .parent_names = (const char *[]){ "vapb_sel" },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1378 },
1379};
1380
738f66d3 1381/* Everything Else (EE) domain gates */
7ba64d82
AM		 1382static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1383static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1384static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1385static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1386static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1387static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1388static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1389static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
1390static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1391static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1392static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1393static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1394static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1395static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1396static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1397static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1398static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1399static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1400static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1401static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1402static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1403static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
738f66d3 1404
7ba64d82
AM		 1405static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1406static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1407static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1408static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1409static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1410static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1411static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1412static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1413static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1414static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1415static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1416static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1417static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1418static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1419static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1420static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1421static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1422static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1423static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1424static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1425static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1426static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1427static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1428static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1429static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
738f66d3 1430
7ba64d82
AM		 1431static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1432static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1433static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1434static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1435static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1436static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1437static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1438static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1439static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1440static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
1441static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1442static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1443static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
738f66d3 1444
7ba64d82
AM		 1445static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1446static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1447static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1448static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1449static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1450static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1451static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1452static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1453static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1454static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1455static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1456static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1457static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1458static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1459static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1460static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
738f66d3
MT		 1461
1462/* Always On (AO) domain gates */
1463
7ba64d82
AM		 1464static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1465static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1466static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1467static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1468static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
738f66d3
MT		 1469
1470/* Array of all clocks provided by this provider */
1471
1472static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1473 .hws = {
1474 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
738f66d3
MT		 1475 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1476 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1477 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1478 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1479 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1480 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1481 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1482 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1483 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1484 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1485 [CLKID_CLK81] = &gxbb_clk81.hw,
1486 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1487 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1488 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1489 [CLKID_DDR] = &gxbb_ddr.hw,
1490 [CLKID_DOS] = &gxbb_dos.hw,
1491 [CLKID_ISA] = &gxbb_isa.hw,
1492 [CLKID_PL301] = &gxbb_pl301.hw,
1493 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1494 [CLKID_SPICC] = &gxbb_spicc.hw,
1495 [CLKID_I2C] = &gxbb_i2c.hw,
1496 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1497 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1498 [CLKID_RNG0] = &gxbb_rng0.hw,
1499 [CLKID_UART0] = &gxbb_uart0.hw,
1500 [CLKID_SDHC] = &gxbb_sdhc.hw,
1501 [CLKID_STREAM] = &gxbb_stream.hw,
1502 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1503 [CLKID_SDIO] = &gxbb_sdio.hw,
1504 [CLKID_ABUF] = &gxbb_abuf.hw,
1505 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1506 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1507 [CLKID_SPI] = &gxbb_spi.hw,
1508 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1509 [CLKID_ETH] = &gxbb_eth.hw,
1510 [CLKID_DEMUX] = &gxbb_demux.hw,
1511 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1512 [CLKID_IEC958] = &gxbb_iec958.hw,
1513 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1514 [CLKID_AMCLK] = &gxbb_amclk.hw,
1515 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1516 [CLKID_MIXER] = &gxbb_mixer.hw,
1517 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1518 [CLKID_ADC] = &gxbb_adc.hw,
1519 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1520 [CLKID_AIU] = &gxbb_aiu.hw,
1521 [CLKID_UART1] = &gxbb_uart1.hw,
1522 [CLKID_G2D] = &gxbb_g2d.hw,
1523 [CLKID_USB0] = &gxbb_usb0.hw,
1524 [CLKID_USB1] = &gxbb_usb1.hw,
1525 [CLKID_RESET] = &gxbb_reset.hw,
1526 [CLKID_NAND] = &gxbb_nand.hw,
1527 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1528 [CLKID_USB] = &gxbb_usb.hw,
1529 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1530 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1531 [CLKID_EFUSE] = &gxbb_efuse.hw,
1532 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1533 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1534 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1535 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1536 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1537 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1538 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1539 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1540 [CLKID_DVIN] = &gxbb_dvin.hw,
1541 [CLKID_UART2] = &gxbb_uart2.hw,
1542 [CLKID_SANA] = &gxbb_sana.hw,
1543 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1544 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1545 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1546 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1547 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1548 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1549 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1550 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1551 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1552 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1553 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1554 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1555 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1556 [CLKID_RNG1] = &gxbb_rng1.hw,
1557 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1558 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1559 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1560 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1561 [CLKID_EDP] = &gxbb_edp.hw,
1562 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1563 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1564 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1565 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1566 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
33608dcd
KH		 1567 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1568 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1569 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
33d0fcdf
MB		 1570 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1571 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1572 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
fac9a55b
NA		 1573 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1574 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1575 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1576 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1577 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1578 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1579 [CLKID_MALI] = &gxbb_mali.hw,
4087bd4b
JB		 1580 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1581 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1582 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
3c277c24
JB		 1583 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1584 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1585 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
7eaa44f6 1586 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
14c735c8
NA		 1587 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1588 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1589 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
914e6e80
JB		 1590 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1591 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1592 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1593 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1594 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1595 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1596 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1597 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1598 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
762a1f20
NA		 1599 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1600 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1601 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1602 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1603 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1604 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1605 [CLKID_VPU] = &gxbb_vpu.hw,
1606 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1607 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1608 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1609 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1610 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1611 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1612 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1613 [CLKID_VAPB] = &gxbb_vapb.hw,
1f6f1dcb 1614 [NR_CLKS] = NULL,
738f66d3
MT		 1615 },
1616 .num = NR_CLKS,
1617};
1618
0d48fc55
NA		 1619static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1620 .hws = {
1621 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
0d48fc55
NA		 1622 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1623 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1624 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1625 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1626 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1627 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1628 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1629 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
1630 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1631 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1632 [CLKID_CLK81] = &gxbb_clk81.hw,
1633 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1634 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1635 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1636 [CLKID_DDR] = &gxbb_ddr.hw,
1637 [CLKID_DOS] = &gxbb_dos.hw,
1638 [CLKID_ISA] = &gxbb_isa.hw,
1639 [CLKID_PL301] = &gxbb_pl301.hw,
1640 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1641 [CLKID_SPICC] = &gxbb_spicc.hw,
1642 [CLKID_I2C] = &gxbb_i2c.hw,
1643 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1644 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1645 [CLKID_RNG0] = &gxbb_rng0.hw,
1646 [CLKID_UART0] = &gxbb_uart0.hw,
1647 [CLKID_SDHC] = &gxbb_sdhc.hw,
1648 [CLKID_STREAM] = &gxbb_stream.hw,
1649 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1650 [CLKID_SDIO] = &gxbb_sdio.hw,
1651 [CLKID_ABUF] = &gxbb_abuf.hw,
1652 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1653 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1654 [CLKID_SPI] = &gxbb_spi.hw,
1655 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1656 [CLKID_ETH] = &gxbb_eth.hw,
1657 [CLKID_DEMUX] = &gxbb_demux.hw,
1658 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1659 [CLKID_IEC958] = &gxbb_iec958.hw,
1660 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1661 [CLKID_AMCLK] = &gxbb_amclk.hw,
1662 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1663 [CLKID_MIXER] = &gxbb_mixer.hw,
1664 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1665 [CLKID_ADC] = &gxbb_adc.hw,
1666 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1667 [CLKID_AIU] = &gxbb_aiu.hw,
1668 [CLKID_UART1] = &gxbb_uart1.hw,
1669 [CLKID_G2D] = &gxbb_g2d.hw,
1670 [CLKID_USB0] = &gxbb_usb0.hw,
1671 [CLKID_USB1] = &gxbb_usb1.hw,
1672 [CLKID_RESET] = &gxbb_reset.hw,
1673 [CLKID_NAND] = &gxbb_nand.hw,
1674 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1675 [CLKID_USB] = &gxbb_usb.hw,
1676 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1677 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1678 [CLKID_EFUSE] = &gxbb_efuse.hw,
1679 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1680 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1681 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1682 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1683 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1684 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1685 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1686 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1687 [CLKID_DVIN] = &gxbb_dvin.hw,
1688 [CLKID_UART2] = &gxbb_uart2.hw,
1689 [CLKID_SANA] = &gxbb_sana.hw,
1690 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1691 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1692 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1693 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1694 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1695 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1696 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1697 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1698 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1699 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1700 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1701 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1702 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1703 [CLKID_RNG1] = &gxbb_rng1.hw,
1704 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1705 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1706 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1707 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1708 [CLKID_EDP] = &gxbb_edp.hw,
1709 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1710 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1711 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1712 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1713 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1714 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1715 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1716 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1717 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1718 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1719 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1720 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1721 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1722 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1723 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1724 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1725 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1726 [CLKID_MALI] = &gxbb_mali.hw,
4087bd4b
JB		 1727 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1728 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1729 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
3c277c24
JB		 1730 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1731 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1732 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
7eaa44f6 1733 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
14c735c8
NA		 1734 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1735 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1736 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
914e6e80
JB		 1737 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1738 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1739 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1740 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1741 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1742 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1743 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1744 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1745 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
762a1f20
NA		 1746 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1747 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1748 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1749 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1750 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1751 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1752 [CLKID_VPU] = &gxbb_vpu.hw,
1753 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1754 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1755 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1756 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1757 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1758 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1759 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1760 [CLKID_VAPB] = &gxbb_vapb.hw,
1f6f1dcb 1761 [NR_CLKS] = NULL,
0d48fc55
NA		 1762 },
1763 .num = NR_CLKS,
1764};
1765
738f66d3
MT		 1766/* Convenience tables to populate base addresses in .probe */
1767
1768static struct meson_clk_pll *const gxbb_clk_plls[] = {
1769 &gxbb_fixed_pll,
1770 &gxbb_hdmi_pll,
1771 &gxbb_sys_pll,
1772 &gxbb_gp0_pll,
1773};
1774
0d48fc55
NA		 1775static struct meson_clk_pll *const gxl_clk_plls[] = {
1776 &gxbb_fixed_pll,
1777 &gxbb_hdmi_pll,
1778 &gxbb_sys_pll,
1779 &gxl_gp0_pll,
1780};
1781
738f66d3
MT		 1782static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
1783 &gxbb_mpll0,
1784 &gxbb_mpll1,
1785 &gxbb_mpll2,
1786};
1787
f7e3a826 1788static struct clk_gate *const gxbb_clk_gates[] = {
738f66d3
MT		 1789 &gxbb_clk81,
1790 &gxbb_ddr,
1791 &gxbb_dos,
1792 &gxbb_isa,
1793 &gxbb_pl301,
1794 &gxbb_periphs,
1795 &gxbb_spicc,
1796 &gxbb_i2c,
1797 &gxbb_sar_adc,
1798 &gxbb_smart_card,
1799 &gxbb_rng0,
1800 &gxbb_uart0,
1801 &gxbb_sdhc,
1802 &gxbb_stream,
1803 &gxbb_async_fifo,
1804 &gxbb_sdio,
1805 &gxbb_abuf,
1806 &gxbb_hiu_iface,
1807 &gxbb_assist_misc,
1808 &gxbb_spi,
1809 &gxbb_i2s_spdif,
1810 &gxbb_eth,
1811 &gxbb_demux,
1812 &gxbb_aiu_glue,
1813 &gxbb_iec958,
1814 &gxbb_i2s_out,
1815 &gxbb_amclk,
1816 &gxbb_aififo2,
1817 &gxbb_mixer,
1818 &gxbb_mixer_iface,
1819 &gxbb_adc,
1820 &gxbb_blkmv,
1821 &gxbb_aiu,
1822 &gxbb_uart1,
1823 &gxbb_g2d,
1824 &gxbb_usb0,
1825 &gxbb_usb1,
1826 &gxbb_reset,
1827 &gxbb_nand,
1828 &gxbb_dos_parser,
1829 &gxbb_usb,
1830 &gxbb_vdin1,
1831 &gxbb_ahb_arb0,
1832 &gxbb_efuse,
1833 &gxbb_boot_rom,
1834 &gxbb_ahb_data_bus,
1835 &gxbb_ahb_ctrl_bus,
1836 &gxbb_hdmi_intr_sync,
1837 &gxbb_hdmi_pclk,
1838 &gxbb_usb1_ddr_bridge,
1839 &gxbb_usb0_ddr_bridge,
1840 &gxbb_mmc_pclk,
1841 &gxbb_dvin,
1842 &gxbb_uart2,
1843 &gxbb_sana,
1844 &gxbb_vpu_intr,
1845 &gxbb_sec_ahb_ahb3_bridge,
1846 &gxbb_clk81_a53,
1847 &gxbb_vclk2_venci0,
1848 &gxbb_vclk2_venci1,
1849 &gxbb_vclk2_vencp0,
1850 &gxbb_vclk2_vencp1,
1851 &gxbb_gclk_venci_int0,
1852 &gxbb_gclk_vencp_int,
1853 &gxbb_dac_clk,
1854 &gxbb_aoclk_gate,
1855 &gxbb_iec958_gate,
1856 &gxbb_enc480p,
1857 &gxbb_rng1,
1858 &gxbb_gclk_venci_int1,
1859 &gxbb_vclk2_venclmcc,
1860 &gxbb_vclk2_vencl,
1861 &gxbb_vclk_other,
1862 &gxbb_edp,
1863 &gxbb_ao_media_cpu,
1864 &gxbb_ao_ahb_sram,
1865 &gxbb_ao_ahb_bus,
1866 &gxbb_ao_iface,
1867 &gxbb_ao_i2c,
33608dcd
KH		 1868 &gxbb_emmc_a,
1869 &gxbb_emmc_b,
1870 &gxbb_emmc_c,
33d0fcdf 1871 &gxbb_sar_adc_clk,
fac9a55b
NA		 1872 &gxbb_mali_0,
1873 &gxbb_mali_1,
4087bd4b 1874 &gxbb_cts_amclk,
3c277c24 1875 &gxbb_cts_mclk_i958,
14c735c8 1876 &gxbb_32k_clk,
914e6e80
JB		 1877 &gxbb_sd_emmc_a_clk0,
1878 &gxbb_sd_emmc_b_clk0,
1879 &gxbb_sd_emmc_c_clk0,
762a1f20
NA		 1880 &gxbb_vpu_0,
1881 &gxbb_vpu_1,
1882 &gxbb_vapb_0,
1883 &gxbb_vapb_1,
1884 &gxbb_vapb,
738f66d3
MT		 1885};
1886
b92332ee
JB		 1887static struct clk_mux *const gxbb_clk_muxes[] = {
1888 &gxbb_mpeg_clk_sel,
1889 &gxbb_sar_adc_clk_sel,
fac9a55b
NA		 1890 &gxbb_mali_0_sel,
1891 &gxbb_mali_1_sel,
1892 &gxbb_mali,
4087bd4b 1893 &gxbb_cts_amclk_sel,
3c277c24 1894 &gxbb_cts_mclk_i958_sel,
7eaa44f6 1895 &gxbb_cts_i958,
14c735c8 1896 &gxbb_32k_clk_sel,
914e6e80
JB		 1897 &gxbb_sd_emmc_a_clk0_sel,
1898 &gxbb_sd_emmc_b_clk0_sel,
1899 &gxbb_sd_emmc_c_clk0_sel,
762a1f20
NA		 1900 &gxbb_vpu_0_sel,
1901 &gxbb_vpu_1_sel,
1902 &gxbb_vpu,
1903 &gxbb_vapb_0_sel,
1904 &gxbb_vapb_1_sel,
1905 &gxbb_vapb_sel,
b92332ee
JB		 1906};
1907
1908static struct clk_divider *const gxbb_clk_dividers[] = {
1909 &gxbb_mpeg_clk_div,
1910 &gxbb_sar_adc_clk_div,
fac9a55b
NA		 1911 &gxbb_mali_0_div,
1912 &gxbb_mali_1_div,
3c277c24 1913 &gxbb_cts_mclk_i958_div,
14c735c8 1914 &gxbb_32k_clk_div,
914e6e80
JB		 1915 &gxbb_sd_emmc_a_clk0_div,
1916 &gxbb_sd_emmc_b_clk0_div,
1917 &gxbb_sd_emmc_c_clk0_div,
762a1f20
NA		 1918 &gxbb_vpu_0_div,
1919 &gxbb_vpu_1_div,
1920 &gxbb_vapb_0_div,
1921 &gxbb_vapb_1_div,
b92332ee
JB		 1922};
1923
4087bd4b
JB		 1924static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
1925 &gxbb_cts_amclk_div,
1926};
1927
0d48fc55
NA		 1928struct clkc_data {
1929 struct clk_gate *const *clk_gates;
1930 unsigned int clk_gates_count;
1931 struct meson_clk_mpll *const *clk_mplls;
1932 unsigned int clk_mplls_count;
1933 struct meson_clk_pll *const *clk_plls;
1934 unsigned int clk_plls_count;
1935 struct clk_mux *const *clk_muxes;
1936 unsigned int clk_muxes_count;
1937 struct clk_divider *const *clk_dividers;
1938 unsigned int clk_dividers_count;
4087bd4b
JB		 1939 struct meson_clk_audio_divider *const *clk_audio_dividers;
1940 unsigned int clk_audio_dividers_count;
0d48fc55
NA		 1941 struct clk_hw_onecell_data *hw_onecell_data;
1942};
1943
1944static const struct clkc_data gxbb_clkc_data = {
1945 .clk_gates = gxbb_clk_gates,
1946 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1947 .clk_mplls = gxbb_clk_mplls,
1948 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1949 .clk_plls = gxbb_clk_plls,
1950 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
1951 .clk_muxes = gxbb_clk_muxes,
1952 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1953 .clk_dividers = gxbb_clk_dividers,
1954 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
4087bd4b
JB		 1955 .clk_audio_dividers = gxbb_audio_dividers,
1956 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
0d48fc55
NA		 1957 .hw_onecell_data = &gxbb_hw_onecell_data,
1958};
1959
1960static const struct clkc_data gxl_clkc_data = {
1961 .clk_gates = gxbb_clk_gates,
1962 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1963 .clk_mplls = gxbb_clk_mplls,
1964 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1965 .clk_plls = gxl_clk_plls,
1966 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
1967 .clk_muxes = gxbb_clk_muxes,
1968 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1969 .clk_dividers = gxbb_clk_dividers,
1970 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
4087bd4b
JB		 1971 .clk_audio_dividers = gxbb_audio_dividers,
1972 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
0d48fc55
NA		 1973 .hw_onecell_data = &gxl_hw_onecell_data,
1974};
1975
1976static const struct of_device_id clkc_match_table[] = {
1977 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
1978 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
1979 {},
1980};
1981
738f66d3
MT		 1982static int gxbb_clkc_probe(struct platform_device *pdev)
1983{
0d48fc55 1984 const struct clkc_data *clkc_data;
738f66d3
MT		 1985 void __iomem *clk_base;
1986 int ret, clkid, i;
738f66d3
MT		 1987 struct device *dev = &pdev->dev;
1988
0d48fc55
NA		 1989 clkc_data = of_device_get_match_data(&pdev->dev);
1990 if (!clkc_data)
1991 return -EINVAL;
1992
738f66d3
MT		 1993 /* Generic clocks and PLLs */
1994 clk_base = of_iomap(dev->of_node, 0);
1995 if (!clk_base) {
1996 pr_err("%s: Unable to map clk base\n", __func__);
1997 return -ENXIO;
1998 }
1999
2000 /* Populate base address for PLLs */
0d48fc55
NA		 2001 for (i = 0; i < clkc_data->clk_plls_count; i++)
2002 clkc_data->clk_plls[i]->base = clk_base;
738f66d3
MT		 2003
2004 /* Populate base address for MPLLs */
0d48fc55
NA		 2005 for (i = 0; i < clkc_data->clk_mplls_count; i++)
2006 clkc_data->clk_mplls[i]->base = clk_base;
738f66d3 2007
738f66d3 2008 /* Populate base address for gates */
0d48fc55
NA		 2009 for (i = 0; i < clkc_data->clk_gates_count; i++)
2010 clkc_data->clk_gates[i]->reg = clk_base +
2011 (u64)clkc_data->clk_gates[i]->reg;
738f66d3 2012
b92332ee 2013 /* Populate base address for muxes */
0d48fc55
NA		 2014 for (i = 0; i < clkc_data->clk_muxes_count; i++)
2015 clkc_data->clk_muxes[i]->reg = clk_base +
2016 (u64)clkc_data->clk_muxes[i]->reg;
b92332ee
JB		 2017
2018 /* Populate base address for dividers */
0d48fc55
NA		 2019 for (i = 0; i < clkc_data->clk_dividers_count; i++)
2020 clkc_data->clk_dividers[i]->reg = clk_base +
2021 (u64)clkc_data->clk_dividers[i]->reg;
b92332ee 2022
4087bd4b
JB		 2023 /* Populate base address for the audio dividers */
2024 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
2025 clkc_data->clk_audio_dividers[i]->base = clk_base;
2026
738f66d3
MT		 2027 /*
2028 * register all clks
2029 */
0d48fc55 2030 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
a70c6e06
JB		 2031 /* array might be sparse */
2032 if (!clkc_data->hw_onecell_data->hws[clkid])
2033 continue;
2034
0d48fc55
NA		 2035 ret = devm_clk_hw_register(dev,
2036 clkc_data->hw_onecell_data->hws[clkid]);
738f66d3
MT		 2037 if (ret)
2038 goto iounmap;
2039 }
2040
738f66d3 2041 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
0d48fc55 2042 clkc_data->hw_onecell_data);
738f66d3
MT		 2043
2044iounmap:
2045 iounmap(clk_base);
2046 return ret;
2047}
2048
738f66d3
MT		 2049static struct platform_driver gxbb_driver = {
2050 .probe = gxbb_clkc_probe,
2051 .driver = {
2052 .name = "gxbb-clkc",
0d48fc55 2053 .of_match_table = clkc_match_table,
738f66d3
MT		 2054 },
2055};
2056
00746f10 2057builtin_platform_driver(gxbb_driver);
Linux 6.x block layer and io_uring tree(s)