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085a4ea9 JH |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Amlogic Meson-G12A Clock Controller Driver | |
4 | * | |
5 | * Copyright (c) 2016 Baylibre SAS. | |
6 | * Author: Michael Turquette <mturquette@baylibre.com> | |
7 | * | |
8 | * Copyright (c) 2018 Amlogic, inc. | |
9 | * Author: Qiufang Dai <qiufang.dai@amlogic.com> | |
10 | * Author: Jian Hu <jian.hu@amlogic.com> | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/of_device.h> | |
085a4ea9 | 16 | #include <linux/platform_device.h> |
085a4ea9 JH |
17 | |
18 | #include "clk-input.h" | |
19 | #include "clk-mpll.h" | |
20 | #include "clk-pll.h" | |
21 | #include "clk-regmap.h" | |
22 | #include "vid-pll-div.h" | |
6682bd4d | 23 | #include "meson-eeclk.h" |
085a4ea9 JH |
24 | #include "g12a.h" |
25 | ||
085a4ea9 JH |
26 | static DEFINE_SPINLOCK(meson_clk_lock); |
27 | ||
28 | static struct clk_regmap g12a_fixed_pll_dco = { | |
29 | .data = &(struct meson_clk_pll_data){ | |
30 | .en = { | |
31 | .reg_off = HHI_FIX_PLL_CNTL0, | |
32 | .shift = 28, | |
33 | .width = 1, | |
34 | }, | |
35 | .m = { | |
36 | .reg_off = HHI_FIX_PLL_CNTL0, | |
37 | .shift = 0, | |
38 | .width = 8, | |
39 | }, | |
40 | .n = { | |
41 | .reg_off = HHI_FIX_PLL_CNTL0, | |
42 | .shift = 10, | |
43 | .width = 5, | |
44 | }, | |
45 | .frac = { | |
46 | .reg_off = HHI_FIX_PLL_CNTL1, | |
47 | .shift = 0, | |
48 | .width = 17, | |
49 | }, | |
50 | .l = { | |
51 | .reg_off = HHI_FIX_PLL_CNTL0, | |
52 | .shift = 31, | |
53 | .width = 1, | |
54 | }, | |
55 | .rst = { | |
56 | .reg_off = HHI_FIX_PLL_CNTL0, | |
57 | .shift = 29, | |
58 | .width = 1, | |
59 | }, | |
60 | }, | |
61 | .hw.init = &(struct clk_init_data){ | |
62 | .name = "fixed_pll_dco", | |
63 | .ops = &meson_clk_pll_ro_ops, | |
64 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
65 | .num_parents = 1, | |
66 | }, | |
67 | }; | |
68 | ||
69 | static struct clk_regmap g12a_fixed_pll = { | |
70 | .data = &(struct clk_regmap_div_data){ | |
71 | .offset = HHI_FIX_PLL_CNTL0, | |
72 | .shift = 16, | |
73 | .width = 2, | |
74 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
75 | }, | |
76 | .hw.init = &(struct clk_init_data){ | |
77 | .name = "fixed_pll", | |
78 | .ops = &clk_regmap_divider_ro_ops, | |
79 | .parent_names = (const char *[]){ "fixed_pll_dco" }, | |
80 | .num_parents = 1, | |
81 | /* | |
82 | * This clock won't ever change at runtime so | |
83 | * CLK_SET_RATE_PARENT is not required | |
84 | */ | |
85 | }, | |
86 | }; | |
87 | ||
88 | /* | |
89 | * Internal sys pll emulation configuration parameters | |
90 | */ | |
91 | static const struct reg_sequence g12a_sys_init_regs[] = { | |
92 | { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 }, | |
93 | { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 }, | |
94 | { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 }, | |
95 | { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 }, | |
96 | { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 }, | |
97 | { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 }, | |
98 | }; | |
99 | ||
100 | static struct clk_regmap g12a_sys_pll_dco = { | |
101 | .data = &(struct meson_clk_pll_data){ | |
102 | .en = { | |
103 | .reg_off = HHI_SYS_PLL_CNTL0, | |
104 | .shift = 28, | |
105 | .width = 1, | |
106 | }, | |
107 | .m = { | |
108 | .reg_off = HHI_SYS_PLL_CNTL0, | |
109 | .shift = 0, | |
110 | .width = 8, | |
111 | }, | |
112 | .n = { | |
113 | .reg_off = HHI_SYS_PLL_CNTL0, | |
114 | .shift = 10, | |
115 | .width = 5, | |
116 | }, | |
117 | .l = { | |
118 | .reg_off = HHI_SYS_PLL_CNTL0, | |
119 | .shift = 31, | |
120 | .width = 1, | |
121 | }, | |
122 | .rst = { | |
123 | .reg_off = HHI_SYS_PLL_CNTL0, | |
124 | .shift = 29, | |
125 | .width = 1, | |
126 | }, | |
127 | .init_regs = g12a_sys_init_regs, | |
128 | .init_count = ARRAY_SIZE(g12a_sys_init_regs), | |
129 | }, | |
130 | .hw.init = &(struct clk_init_data){ | |
131 | .name = "sys_pll_dco", | |
132 | .ops = &meson_clk_pll_ro_ops, | |
133 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
134 | .num_parents = 1, | |
135 | }, | |
136 | }; | |
137 | ||
138 | static struct clk_regmap g12a_sys_pll = { | |
139 | .data = &(struct clk_regmap_div_data){ | |
140 | .offset = HHI_SYS_PLL_CNTL0, | |
141 | .shift = 16, | |
142 | .width = 3, | |
143 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
144 | }, | |
145 | .hw.init = &(struct clk_init_data){ | |
146 | .name = "sys_pll", | |
147 | .ops = &clk_regmap_divider_ro_ops, | |
148 | .parent_names = (const char *[]){ "sys_pll_dco" }, | |
149 | .num_parents = 1, | |
150 | }, | |
151 | }; | |
152 | ||
370294e2 NA |
153 | static struct clk_regmap g12a_sys_pll_div16_en = { |
154 | .data = &(struct clk_regmap_gate_data){ | |
155 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
156 | .bit_idx = 24, | |
157 | }, | |
158 | .hw.init = &(struct clk_init_data) { | |
159 | .name = "sys_pll_div16_en", | |
160 | .ops = &clk_regmap_gate_ro_ops, | |
161 | .parent_names = (const char *[]){ "sys_pll" }, | |
162 | .num_parents = 1, | |
163 | /* | |
164 | * This clock is used to debug the sys_pll range | |
165 | * Linux should not change it at runtime | |
166 | */ | |
167 | }, | |
168 | }; | |
169 | ||
170 | static struct clk_fixed_factor g12a_sys_pll_div16 = { | |
171 | .mult = 1, | |
172 | .div = 16, | |
173 | .hw.init = &(struct clk_init_data){ | |
174 | .name = "sys_pll_div16", | |
175 | .ops = &clk_fixed_factor_ops, | |
176 | .parent_names = (const char *[]){ "sys_pll_div16_en" }, | |
177 | .num_parents = 1, | |
178 | }, | |
179 | }; | |
180 | ||
181 | /* Datasheet names this field as "premux0" */ | |
182 | static struct clk_regmap g12a_cpu_clk_premux0 = { | |
183 | .data = &(struct clk_regmap_mux_data){ | |
184 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
185 | .mask = 0x3, | |
186 | .shift = 0, | |
187 | }, | |
188 | .hw.init = &(struct clk_init_data){ | |
189 | .name = "cpu_clk_dyn0_sel", | |
190 | .ops = &clk_regmap_mux_ro_ops, | |
191 | .parent_names = (const char *[]){ IN_PREFIX "xtal", | |
192 | "fclk_div2", | |
193 | "fclk_div3" }, | |
194 | .num_parents = 3, | |
195 | }, | |
196 | }; | |
197 | ||
198 | /* Datasheet names this field as "mux0_divn_tcnt" */ | |
199 | static struct clk_regmap g12a_cpu_clk_mux0_div = { | |
200 | .data = &(struct clk_regmap_div_data){ | |
201 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
202 | .shift = 4, | |
203 | .width = 6, | |
204 | }, | |
205 | .hw.init = &(struct clk_init_data){ | |
206 | .name = "cpu_clk_dyn0_div", | |
207 | .ops = &clk_regmap_divider_ro_ops, | |
208 | .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" }, | |
209 | .num_parents = 1, | |
210 | }, | |
211 | }; | |
212 | ||
213 | /* Datasheet names this field as "postmux0" */ | |
214 | static struct clk_regmap g12a_cpu_clk_postmux0 = { | |
215 | .data = &(struct clk_regmap_mux_data){ | |
216 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
217 | .mask = 0x1, | |
218 | .shift = 2, | |
219 | }, | |
220 | .hw.init = &(struct clk_init_data){ | |
221 | .name = "cpu_clk_dyn0", | |
222 | .ops = &clk_regmap_mux_ro_ops, | |
223 | .parent_names = (const char *[]){ "cpu_clk_dyn0_sel", | |
224 | "cpu_clk_dyn0_div" }, | |
225 | .num_parents = 2, | |
226 | }, | |
227 | }; | |
228 | ||
229 | /* Datasheet names this field as "premux1" */ | |
230 | static struct clk_regmap g12a_cpu_clk_premux1 = { | |
231 | .data = &(struct clk_regmap_mux_data){ | |
232 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
233 | .mask = 0x3, | |
234 | .shift = 16, | |
235 | }, | |
236 | .hw.init = &(struct clk_init_data){ | |
237 | .name = "cpu_clk_dyn1_sel", | |
238 | .ops = &clk_regmap_mux_ro_ops, | |
239 | .parent_names = (const char *[]){ IN_PREFIX "xtal", | |
240 | "fclk_div2", | |
241 | "fclk_div3" }, | |
242 | .num_parents = 3, | |
243 | }, | |
244 | }; | |
245 | ||
246 | /* Datasheet names this field as "Mux1_divn_tcnt" */ | |
247 | static struct clk_regmap g12a_cpu_clk_mux1_div = { | |
248 | .data = &(struct clk_regmap_div_data){ | |
249 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
250 | .shift = 20, | |
251 | .width = 6, | |
252 | }, | |
253 | .hw.init = &(struct clk_init_data){ | |
254 | .name = "cpu_clk_dyn1_div", | |
255 | .ops = &clk_regmap_divider_ro_ops, | |
256 | .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" }, | |
257 | .num_parents = 1, | |
258 | }, | |
259 | }; | |
260 | ||
261 | /* Datasheet names this field as "postmux1" */ | |
262 | static struct clk_regmap g12a_cpu_clk_postmux1 = { | |
263 | .data = &(struct clk_regmap_mux_data){ | |
264 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
265 | .mask = 0x1, | |
266 | .shift = 18, | |
267 | }, | |
268 | .hw.init = &(struct clk_init_data){ | |
269 | .name = "cpu_clk_dyn1", | |
270 | .ops = &clk_regmap_mux_ro_ops, | |
271 | .parent_names = (const char *[]){ "cpu_clk_dyn1_sel", | |
272 | "cpu_clk_dyn1_div" }, | |
273 | .num_parents = 2, | |
274 | }, | |
275 | }; | |
276 | ||
277 | /* Datasheet names this field as "Final_dyn_mux_sel" */ | |
278 | static struct clk_regmap g12a_cpu_clk_dyn = { | |
279 | .data = &(struct clk_regmap_mux_data){ | |
280 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
281 | .mask = 0x1, | |
282 | .shift = 10, | |
283 | }, | |
284 | .hw.init = &(struct clk_init_data){ | |
285 | .name = "cpu_clk_dyn", | |
286 | .ops = &clk_regmap_mux_ro_ops, | |
287 | .parent_names = (const char *[]){ "cpu_clk_dyn0", | |
288 | "cpu_clk_dyn1" }, | |
289 | .num_parents = 2, | |
290 | }, | |
291 | }; | |
292 | ||
293 | /* Datasheet names this field as "Final_mux_sel" */ | |
294 | static struct clk_regmap g12a_cpu_clk = { | |
295 | .data = &(struct clk_regmap_mux_data){ | |
296 | .offset = HHI_SYS_CPU_CLK_CNTL0, | |
297 | .mask = 0x1, | |
298 | .shift = 11, | |
299 | }, | |
300 | .hw.init = &(struct clk_init_data){ | |
301 | .name = "cpu_clk", | |
302 | .ops = &clk_regmap_mux_ro_ops, | |
303 | .parent_names = (const char *[]){ "cpu_clk_dyn", | |
304 | "sys_pll" }, | |
305 | .num_parents = 2, | |
306 | }, | |
307 | }; | |
308 | ||
309 | static struct clk_regmap g12a_cpu_clk_div16_en = { | |
310 | .data = &(struct clk_regmap_gate_data){ | |
311 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
312 | .bit_idx = 1, | |
313 | }, | |
314 | .hw.init = &(struct clk_init_data) { | |
315 | .name = "cpu_clk_div16_en", | |
316 | .ops = &clk_regmap_gate_ro_ops, | |
317 | .parent_names = (const char *[]){ "cpu_clk" }, | |
318 | .num_parents = 1, | |
319 | /* | |
320 | * This clock is used to debug the cpu_clk range | |
321 | * Linux should not change it at runtime | |
322 | */ | |
323 | }, | |
324 | }; | |
325 | ||
326 | static struct clk_fixed_factor g12a_cpu_clk_div16 = { | |
327 | .mult = 1, | |
328 | .div = 16, | |
329 | .hw.init = &(struct clk_init_data){ | |
330 | .name = "cpu_clk_div16", | |
331 | .ops = &clk_fixed_factor_ops, | |
332 | .parent_names = (const char *[]){ "cpu_clk_div16_en" }, | |
333 | .num_parents = 1, | |
334 | }, | |
335 | }; | |
336 | ||
337 | static struct clk_regmap g12a_cpu_clk_apb_div = { | |
338 | .data = &(struct clk_regmap_div_data){ | |
339 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
340 | .shift = 3, | |
341 | .width = 3, | |
342 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
343 | }, | |
344 | .hw.init = &(struct clk_init_data){ | |
345 | .name = "cpu_clk_apb_div", | |
346 | .ops = &clk_regmap_divider_ro_ops, | |
347 | .parent_names = (const char *[]){ "cpu_clk" }, | |
348 | .num_parents = 1, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct clk_regmap g12a_cpu_clk_apb = { | |
353 | .data = &(struct clk_regmap_gate_data){ | |
354 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
355 | .bit_idx = 1, | |
356 | }, | |
357 | .hw.init = &(struct clk_init_data) { | |
358 | .name = "cpu_clk_apb", | |
359 | .ops = &clk_regmap_gate_ro_ops, | |
360 | .parent_names = (const char *[]){ "cpu_clk_apb_div" }, | |
361 | .num_parents = 1, | |
362 | /* | |
363 | * This clock is set by the ROM monitor code, | |
364 | * Linux should not change it at runtime | |
365 | */ | |
366 | }, | |
367 | }; | |
368 | ||
369 | static struct clk_regmap g12a_cpu_clk_atb_div = { | |
370 | .data = &(struct clk_regmap_div_data){ | |
371 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
372 | .shift = 6, | |
373 | .width = 3, | |
374 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
375 | }, | |
376 | .hw.init = &(struct clk_init_data){ | |
377 | .name = "cpu_clk_atb_div", | |
378 | .ops = &clk_regmap_divider_ro_ops, | |
379 | .parent_names = (const char *[]){ "cpu_clk" }, | |
380 | .num_parents = 1, | |
381 | }, | |
382 | }; | |
383 | ||
384 | static struct clk_regmap g12a_cpu_clk_atb = { | |
385 | .data = &(struct clk_regmap_gate_data){ | |
386 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
387 | .bit_idx = 17, | |
388 | }, | |
389 | .hw.init = &(struct clk_init_data) { | |
390 | .name = "cpu_clk_atb", | |
391 | .ops = &clk_regmap_gate_ro_ops, | |
392 | .parent_names = (const char *[]){ "cpu_clk_atb_div" }, | |
393 | .num_parents = 1, | |
394 | /* | |
395 | * This clock is set by the ROM monitor code, | |
396 | * Linux should not change it at runtime | |
397 | */ | |
398 | }, | |
399 | }; | |
400 | ||
401 | static struct clk_regmap g12a_cpu_clk_axi_div = { | |
402 | .data = &(struct clk_regmap_div_data){ | |
403 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
404 | .shift = 9, | |
405 | .width = 3, | |
406 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
407 | }, | |
408 | .hw.init = &(struct clk_init_data){ | |
409 | .name = "cpu_clk_axi_div", | |
410 | .ops = &clk_regmap_divider_ro_ops, | |
411 | .parent_names = (const char *[]){ "cpu_clk" }, | |
412 | .num_parents = 1, | |
413 | }, | |
414 | }; | |
415 | ||
416 | static struct clk_regmap g12a_cpu_clk_axi = { | |
417 | .data = &(struct clk_regmap_gate_data){ | |
418 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
419 | .bit_idx = 18, | |
420 | }, | |
421 | .hw.init = &(struct clk_init_data) { | |
422 | .name = "cpu_clk_axi", | |
423 | .ops = &clk_regmap_gate_ro_ops, | |
424 | .parent_names = (const char *[]){ "cpu_clk_axi_div" }, | |
425 | .num_parents = 1, | |
426 | /* | |
427 | * This clock is set by the ROM monitor code, | |
428 | * Linux should not change it at runtime | |
429 | */ | |
430 | }, | |
431 | }; | |
432 | ||
433 | static struct clk_regmap g12a_cpu_clk_trace_div = { | |
434 | .data = &(struct clk_regmap_div_data){ | |
435 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
436 | .shift = 20, | |
437 | .width = 3, | |
438 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
439 | }, | |
440 | .hw.init = &(struct clk_init_data){ | |
441 | .name = "cpu_clk_trace_div", | |
442 | .ops = &clk_regmap_divider_ro_ops, | |
443 | .parent_names = (const char *[]){ "cpu_clk" }, | |
444 | .num_parents = 1, | |
445 | }, | |
446 | }; | |
447 | ||
448 | static struct clk_regmap g12a_cpu_clk_trace = { | |
449 | .data = &(struct clk_regmap_gate_data){ | |
450 | .offset = HHI_SYS_CPU_CLK_CNTL1, | |
451 | .bit_idx = 23, | |
452 | }, | |
453 | .hw.init = &(struct clk_init_data) { | |
454 | .name = "cpu_clk_trace", | |
455 | .ops = &clk_regmap_gate_ro_ops, | |
456 | .parent_names = (const char *[]){ "cpu_clk_trace_div" }, | |
457 | .num_parents = 1, | |
458 | /* | |
459 | * This clock is set by the ROM monitor code, | |
460 | * Linux should not change it at runtime | |
461 | */ | |
462 | }, | |
463 | }; | |
464 | ||
085a4ea9 JH |
465 | static const struct pll_mult_range g12a_gp0_pll_mult_range = { |
466 | .min = 55, | |
467 | .max = 255, | |
468 | }; | |
469 | ||
470 | /* | |
471 | * Internal gp0 pll emulation configuration parameters | |
472 | */ | |
473 | static const struct reg_sequence g12a_gp0_init_regs[] = { | |
474 | { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, | |
475 | { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, | |
476 | { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, | |
477 | { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, | |
478 | { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, | |
479 | { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, | |
480 | }; | |
481 | ||
482 | static struct clk_regmap g12a_gp0_pll_dco = { | |
483 | .data = &(struct meson_clk_pll_data){ | |
484 | .en = { | |
485 | .reg_off = HHI_GP0_PLL_CNTL0, | |
486 | .shift = 28, | |
487 | .width = 1, | |
488 | }, | |
489 | .m = { | |
490 | .reg_off = HHI_GP0_PLL_CNTL0, | |
491 | .shift = 0, | |
492 | .width = 8, | |
493 | }, | |
494 | .n = { | |
495 | .reg_off = HHI_GP0_PLL_CNTL0, | |
496 | .shift = 10, | |
497 | .width = 5, | |
498 | }, | |
499 | .frac = { | |
500 | .reg_off = HHI_GP0_PLL_CNTL1, | |
501 | .shift = 0, | |
502 | .width = 17, | |
503 | }, | |
504 | .l = { | |
505 | .reg_off = HHI_GP0_PLL_CNTL0, | |
506 | .shift = 31, | |
507 | .width = 1, | |
508 | }, | |
509 | .rst = { | |
510 | .reg_off = HHI_GP0_PLL_CNTL0, | |
511 | .shift = 29, | |
512 | .width = 1, | |
513 | }, | |
514 | .range = &g12a_gp0_pll_mult_range, | |
515 | .init_regs = g12a_gp0_init_regs, | |
516 | .init_count = ARRAY_SIZE(g12a_gp0_init_regs), | |
517 | }, | |
518 | .hw.init = &(struct clk_init_data){ | |
519 | .name = "gp0_pll_dco", | |
520 | .ops = &meson_clk_pll_ops, | |
521 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
522 | .num_parents = 1, | |
523 | }, | |
524 | }; | |
525 | ||
526 | static struct clk_regmap g12a_gp0_pll = { | |
527 | .data = &(struct clk_regmap_div_data){ | |
528 | .offset = HHI_GP0_PLL_CNTL0, | |
529 | .shift = 16, | |
530 | .width = 3, | |
531 | .flags = (CLK_DIVIDER_POWER_OF_TWO | | |
532 | CLK_DIVIDER_ROUND_CLOSEST), | |
533 | }, | |
534 | .hw.init = &(struct clk_init_data){ | |
535 | .name = "gp0_pll", | |
536 | .ops = &clk_regmap_divider_ops, | |
537 | .parent_names = (const char *[]){ "gp0_pll_dco" }, | |
538 | .num_parents = 1, | |
539 | .flags = CLK_SET_RATE_PARENT, | |
540 | }, | |
541 | }; | |
542 | ||
543 | /* | |
544 | * Internal hifi pll emulation configuration parameters | |
545 | */ | |
546 | static const struct reg_sequence g12a_hifi_init_regs[] = { | |
547 | { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, | |
548 | { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, | |
549 | { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, | |
550 | { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, | |
551 | { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, | |
552 | { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, | |
553 | }; | |
554 | ||
555 | static struct clk_regmap g12a_hifi_pll_dco = { | |
556 | .data = &(struct meson_clk_pll_data){ | |
557 | .en = { | |
558 | .reg_off = HHI_HIFI_PLL_CNTL0, | |
559 | .shift = 28, | |
560 | .width = 1, | |
561 | }, | |
562 | .m = { | |
563 | .reg_off = HHI_HIFI_PLL_CNTL0, | |
564 | .shift = 0, | |
565 | .width = 8, | |
566 | }, | |
567 | .n = { | |
568 | .reg_off = HHI_HIFI_PLL_CNTL0, | |
569 | .shift = 10, | |
570 | .width = 5, | |
571 | }, | |
572 | .frac = { | |
573 | .reg_off = HHI_HIFI_PLL_CNTL1, | |
574 | .shift = 0, | |
575 | .width = 17, | |
576 | }, | |
577 | .l = { | |
578 | .reg_off = HHI_HIFI_PLL_CNTL0, | |
579 | .shift = 31, | |
580 | .width = 1, | |
581 | }, | |
582 | .rst = { | |
583 | .reg_off = HHI_HIFI_PLL_CNTL0, | |
584 | .shift = 29, | |
585 | .width = 1, | |
586 | }, | |
587 | .range = &g12a_gp0_pll_mult_range, | |
588 | .init_regs = g12a_hifi_init_regs, | |
589 | .init_count = ARRAY_SIZE(g12a_hifi_init_regs), | |
590 | .flags = CLK_MESON_PLL_ROUND_CLOSEST, | |
591 | }, | |
592 | .hw.init = &(struct clk_init_data){ | |
593 | .name = "hifi_pll_dco", | |
594 | .ops = &meson_clk_pll_ops, | |
595 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
596 | .num_parents = 1, | |
597 | }, | |
598 | }; | |
599 | ||
600 | static struct clk_regmap g12a_hifi_pll = { | |
601 | .data = &(struct clk_regmap_div_data){ | |
602 | .offset = HHI_HIFI_PLL_CNTL0, | |
603 | .shift = 16, | |
604 | .width = 2, | |
605 | .flags = (CLK_DIVIDER_POWER_OF_TWO | | |
606 | CLK_DIVIDER_ROUND_CLOSEST), | |
607 | }, | |
608 | .hw.init = &(struct clk_init_data){ | |
609 | .name = "hifi_pll", | |
610 | .ops = &clk_regmap_divider_ops, | |
611 | .parent_names = (const char *[]){ "hifi_pll_dco" }, | |
612 | .num_parents = 1, | |
613 | .flags = CLK_SET_RATE_PARENT, | |
614 | }, | |
615 | }; | |
616 | ||
34775209 NA |
617 | /* |
618 | * The Meson G12A PCIE PLL is fined tuned to deliver a very precise | |
619 | * 100MHz reference clock for the PCIe Analog PHY, and thus requires | |
620 | * a strict register sequence to enable the PLL. | |
621 | */ | |
622 | static const struct reg_sequence g12a_pcie_pll_init_regs[] = { | |
623 | { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 }, | |
624 | { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 }, | |
625 | { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 }, | |
626 | { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 }, | |
627 | { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 }, | |
628 | { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 }, | |
629 | { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 }, | |
630 | { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 }, | |
631 | { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 }, | |
632 | { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 }, | |
633 | { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 }, | |
634 | { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 }, | |
635 | }; | |
636 | ||
637 | /* Keep a single entry table for recalc/round_rate() ops */ | |
638 | static const struct pll_params_table g12a_pcie_pll_table[] = { | |
639 | PLL_PARAMS(150, 1), | |
640 | {0, 0}, | |
641 | }; | |
642 | ||
643 | static struct clk_regmap g12a_pcie_pll_dco = { | |
644 | .data = &(struct meson_clk_pll_data){ | |
645 | .en = { | |
646 | .reg_off = HHI_PCIE_PLL_CNTL0, | |
647 | .shift = 28, | |
648 | .width = 1, | |
649 | }, | |
650 | .m = { | |
651 | .reg_off = HHI_PCIE_PLL_CNTL0, | |
652 | .shift = 0, | |
653 | .width = 8, | |
654 | }, | |
655 | .n = { | |
656 | .reg_off = HHI_PCIE_PLL_CNTL0, | |
657 | .shift = 10, | |
658 | .width = 5, | |
659 | }, | |
660 | .frac = { | |
661 | .reg_off = HHI_PCIE_PLL_CNTL1, | |
662 | .shift = 0, | |
663 | .width = 12, | |
664 | }, | |
665 | .l = { | |
666 | .reg_off = HHI_PCIE_PLL_CNTL0, | |
667 | .shift = 31, | |
668 | .width = 1, | |
669 | }, | |
670 | .rst = { | |
671 | .reg_off = HHI_PCIE_PLL_CNTL0, | |
672 | .shift = 29, | |
673 | .width = 1, | |
674 | }, | |
675 | .table = g12a_pcie_pll_table, | |
676 | .init_regs = g12a_pcie_pll_init_regs, | |
677 | .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs), | |
678 | }, | |
679 | .hw.init = &(struct clk_init_data){ | |
680 | .name = "pcie_pll_dco", | |
681 | .ops = &meson_clk_pcie_pll_ops, | |
682 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
683 | .num_parents = 1, | |
684 | }, | |
685 | }; | |
686 | ||
687 | static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = { | |
688 | .mult = 1, | |
689 | .div = 2, | |
690 | .hw.init = &(struct clk_init_data){ | |
691 | .name = "pcie_pll_dco_div2", | |
692 | .ops = &clk_fixed_factor_ops, | |
693 | .parent_names = (const char *[]){ "pcie_pll_dco" }, | |
694 | .num_parents = 1, | |
695 | .flags = CLK_SET_RATE_PARENT, | |
696 | }, | |
697 | }; | |
698 | ||
699 | static struct clk_regmap g12a_pcie_pll_od = { | |
700 | .data = &(struct clk_regmap_div_data){ | |
701 | .offset = HHI_PCIE_PLL_CNTL0, | |
702 | .shift = 16, | |
703 | .width = 5, | |
704 | .flags = CLK_DIVIDER_ROUND_CLOSEST | | |
705 | CLK_DIVIDER_ONE_BASED | | |
706 | CLK_DIVIDER_ALLOW_ZERO, | |
707 | }, | |
708 | .hw.init = &(struct clk_init_data){ | |
709 | .name = "pcie_pll_od", | |
710 | .ops = &clk_regmap_divider_ops, | |
711 | .parent_names = (const char *[]){ "pcie_pll_dco_div2" }, | |
712 | .num_parents = 1, | |
713 | .flags = CLK_SET_RATE_PARENT, | |
714 | }, | |
715 | }; | |
716 | ||
717 | static struct clk_fixed_factor g12a_pcie_pll = { | |
718 | .mult = 1, | |
719 | .div = 2, | |
720 | .hw.init = &(struct clk_init_data){ | |
721 | .name = "pcie_pll_pll", | |
722 | .ops = &clk_fixed_factor_ops, | |
723 | .parent_names = (const char *[]){ "pcie_pll_od" }, | |
724 | .num_parents = 1, | |
725 | .flags = CLK_SET_RATE_PARENT, | |
726 | }, | |
727 | }; | |
728 | ||
085a4ea9 JH |
729 | static struct clk_regmap g12a_hdmi_pll_dco = { |
730 | .data = &(struct meson_clk_pll_data){ | |
731 | .en = { | |
732 | .reg_off = HHI_HDMI_PLL_CNTL0, | |
733 | .shift = 28, | |
734 | .width = 1, | |
735 | }, | |
736 | .m = { | |
737 | .reg_off = HHI_HDMI_PLL_CNTL0, | |
738 | .shift = 0, | |
739 | .width = 8, | |
740 | }, | |
741 | .n = { | |
742 | .reg_off = HHI_HDMI_PLL_CNTL0, | |
743 | .shift = 10, | |
744 | .width = 5, | |
745 | }, | |
746 | .frac = { | |
747 | .reg_off = HHI_HDMI_PLL_CNTL1, | |
748 | .shift = 0, | |
749 | .width = 16, | |
750 | }, | |
751 | .l = { | |
752 | .reg_off = HHI_HDMI_PLL_CNTL0, | |
753 | .shift = 30, | |
754 | .width = 1, | |
755 | }, | |
756 | .rst = { | |
757 | .reg_off = HHI_HDMI_PLL_CNTL0, | |
758 | .shift = 29, | |
759 | .width = 1, | |
760 | }, | |
761 | }, | |
762 | .hw.init = &(struct clk_init_data){ | |
763 | .name = "hdmi_pll_dco", | |
764 | .ops = &meson_clk_pll_ro_ops, | |
765 | .parent_names = (const char *[]){ IN_PREFIX "xtal" }, | |
766 | .num_parents = 1, | |
767 | /* | |
768 | * Display directly handle hdmi pll registers ATM, we need | |
769 | * NOCACHE to keep our view of the clock as accurate as possible | |
770 | */ | |
771 | .flags = CLK_GET_RATE_NOCACHE, | |
772 | }, | |
773 | }; | |
774 | ||
775 | static struct clk_regmap g12a_hdmi_pll_od = { | |
776 | .data = &(struct clk_regmap_div_data){ | |
777 | .offset = HHI_HDMI_PLL_CNTL0, | |
778 | .shift = 16, | |
779 | .width = 2, | |
780 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
781 | }, | |
782 | .hw.init = &(struct clk_init_data){ | |
783 | .name = "hdmi_pll_od", | |
784 | .ops = &clk_regmap_divider_ro_ops, | |
785 | .parent_names = (const char *[]){ "hdmi_pll_dco" }, | |
786 | .num_parents = 1, | |
787 | .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, | |
788 | }, | |
789 | }; | |
790 | ||
791 | static struct clk_regmap g12a_hdmi_pll_od2 = { | |
792 | .data = &(struct clk_regmap_div_data){ | |
793 | .offset = HHI_HDMI_PLL_CNTL0, | |
794 | .shift = 18, | |
795 | .width = 2, | |
796 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
797 | }, | |
798 | .hw.init = &(struct clk_init_data){ | |
799 | .name = "hdmi_pll_od2", | |
800 | .ops = &clk_regmap_divider_ro_ops, | |
801 | .parent_names = (const char *[]){ "hdmi_pll_od" }, | |
802 | .num_parents = 1, | |
803 | .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, | |
804 | }, | |
805 | }; | |
806 | ||
807 | static struct clk_regmap g12a_hdmi_pll = { | |
808 | .data = &(struct clk_regmap_div_data){ | |
809 | .offset = HHI_HDMI_PLL_CNTL0, | |
810 | .shift = 20, | |
811 | .width = 2, | |
812 | .flags = CLK_DIVIDER_POWER_OF_TWO, | |
813 | }, | |
814 | .hw.init = &(struct clk_init_data){ | |
815 | .name = "hdmi_pll", | |
816 | .ops = &clk_regmap_divider_ro_ops, | |
817 | .parent_names = (const char *[]){ "hdmi_pll_od2" }, | |
818 | .num_parents = 1, | |
819 | .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, | |
820 | }, | |
821 | }; | |
822 | ||
823 | static struct clk_fixed_factor g12a_fclk_div2_div = { | |
824 | .mult = 1, | |
825 | .div = 2, | |
826 | .hw.init = &(struct clk_init_data){ | |
827 | .name = "fclk_div2_div", | |
828 | .ops = &clk_fixed_factor_ops, | |
829 | .parent_names = (const char *[]){ "fixed_pll" }, | |
830 | .num_parents = 1, | |
831 | }, | |
832 | }; | |
833 | ||
834 | static struct clk_regmap g12a_fclk_div2 = { | |
835 | .data = &(struct clk_regmap_gate_data){ | |
836 | .offset = HHI_FIX_PLL_CNTL1, | |
837 | .bit_idx = 24, | |
838 | }, | |
839 | .hw.init = &(struct clk_init_data){ | |
840 | .name = "fclk_div2", | |
841 | .ops = &clk_regmap_gate_ops, | |
842 | .parent_names = (const char *[]){ "fclk_div2_div" }, | |
843 | .num_parents = 1, | |
844 | }, | |
845 | }; | |
846 | ||
847 | static struct clk_fixed_factor g12a_fclk_div3_div = { | |
848 | .mult = 1, | |
849 | .div = 3, | |
850 | .hw.init = &(struct clk_init_data){ | |
851 | .name = "fclk_div3_div", | |
852 | .ops = &clk_fixed_factor_ops, | |
853 | .parent_names = (const char *[]){ "fixed_pll" }, | |
854 | .num_parents = 1, | |
855 | }, | |
856 | }; | |
857 | ||
858 | static struct clk_regmap g12a_fclk_div3 = { | |
859 | .data = &(struct clk_regmap_gate_data){ | |
860 | .offset = HHI_FIX_PLL_CNTL1, | |
861 | .bit_idx = 20, | |
862 | }, | |
863 | .hw.init = &(struct clk_init_data){ | |
864 | .name = "fclk_div3", | |
865 | .ops = &clk_regmap_gate_ops, | |
866 | .parent_names = (const char *[]){ "fclk_div3_div" }, | |
867 | .num_parents = 1, | |
868 | }, | |
869 | }; | |
870 | ||
871 | static struct clk_fixed_factor g12a_fclk_div4_div = { | |
872 | .mult = 1, | |
873 | .div = 4, | |
874 | .hw.init = &(struct clk_init_data){ | |
875 | .name = "fclk_div4_div", | |
876 | .ops = &clk_fixed_factor_ops, | |
877 | .parent_names = (const char *[]){ "fixed_pll" }, | |
878 | .num_parents = 1, | |
879 | }, | |
880 | }; | |
881 | ||
882 | static struct clk_regmap g12a_fclk_div4 = { | |
883 | .data = &(struct clk_regmap_gate_data){ | |
884 | .offset = HHI_FIX_PLL_CNTL1, | |
885 | .bit_idx = 21, | |
886 | }, | |
887 | .hw.init = &(struct clk_init_data){ | |
888 | .name = "fclk_div4", | |
889 | .ops = &clk_regmap_gate_ops, | |
890 | .parent_names = (const char *[]){ "fclk_div4_div" }, | |
891 | .num_parents = 1, | |
892 | }, | |
893 | }; | |
894 | ||
895 | static struct clk_fixed_factor g12a_fclk_div5_div = { | |
896 | .mult = 1, | |
897 | .div = 5, | |
898 | .hw.init = &(struct clk_init_data){ | |
899 | .name = "fclk_div5_div", | |
900 | .ops = &clk_fixed_factor_ops, | |
901 | .parent_names = (const char *[]){ "fixed_pll" }, | |
902 | .num_parents = 1, | |
903 | }, | |
904 | }; | |
905 | ||
906 | static struct clk_regmap g12a_fclk_div5 = { | |
907 | .data = &(struct clk_regmap_gate_data){ | |
908 | .offset = HHI_FIX_PLL_CNTL1, | |
909 | .bit_idx = 22, | |
910 | }, | |
911 | .hw.init = &(struct clk_init_data){ | |
912 | .name = "fclk_div5", | |
913 | .ops = &clk_regmap_gate_ops, | |
914 | .parent_names = (const char *[]){ "fclk_div5_div" }, | |
915 | .num_parents = 1, | |
916 | }, | |
917 | }; | |
918 | ||
919 | static struct clk_fixed_factor g12a_fclk_div7_div = { | |
920 | .mult = 1, | |
921 | .div = 7, | |
922 | .hw.init = &(struct clk_init_data){ | |
923 | .name = "fclk_div7_div", | |
924 | .ops = &clk_fixed_factor_ops, | |
925 | .parent_names = (const char *[]){ "fixed_pll" }, | |
926 | .num_parents = 1, | |
927 | }, | |
928 | }; | |
929 | ||
930 | static struct clk_regmap g12a_fclk_div7 = { | |
931 | .data = &(struct clk_regmap_gate_data){ | |
932 | .offset = HHI_FIX_PLL_CNTL1, | |
933 | .bit_idx = 23, | |
934 | }, | |
935 | .hw.init = &(struct clk_init_data){ | |
936 | .name = "fclk_div7", | |
937 | .ops = &clk_regmap_gate_ops, | |
938 | .parent_names = (const char *[]){ "fclk_div7_div" }, | |
939 | .num_parents = 1, | |
940 | }, | |
941 | }; | |
942 | ||
943 | static struct clk_fixed_factor g12a_fclk_div2p5_div = { | |
944 | .mult = 1, | |
945 | .div = 5, | |
946 | .hw.init = &(struct clk_init_data){ | |
947 | .name = "fclk_div2p5_div", | |
948 | .ops = &clk_fixed_factor_ops, | |
949 | .parent_names = (const char *[]){ "fixed_pll_dco" }, | |
950 | .num_parents = 1, | |
951 | }, | |
952 | }; | |
953 | ||
954 | static struct clk_regmap g12a_fclk_div2p5 = { | |
955 | .data = &(struct clk_regmap_gate_data){ | |
956 | .offset = HHI_FIX_PLL_CNTL1, | |
957 | .bit_idx = 25, | |
958 | }, | |
959 | .hw.init = &(struct clk_init_data){ | |
960 | .name = "fclk_div2p5", | |
961 | .ops = &clk_regmap_gate_ops, | |
962 | .parent_names = (const char *[]){ "fclk_div2p5_div" }, | |
963 | .num_parents = 1, | |
964 | }, | |
965 | }; | |
966 | ||
967 | static struct clk_fixed_factor g12a_mpll_50m_div = { | |
968 | .mult = 1, | |
969 | .div = 80, | |
970 | .hw.init = &(struct clk_init_data){ | |
971 | .name = "mpll_50m_div", | |
972 | .ops = &clk_fixed_factor_ops, | |
973 | .parent_names = (const char *[]){ "fixed_pll_dco" }, | |
974 | .num_parents = 1, | |
975 | }, | |
976 | }; | |
977 | ||
978 | static struct clk_regmap g12a_mpll_50m = { | |
979 | .data = &(struct clk_regmap_mux_data){ | |
980 | .offset = HHI_FIX_PLL_CNTL3, | |
981 | .mask = 0x1, | |
982 | .shift = 5, | |
983 | }, | |
984 | .hw.init = &(struct clk_init_data){ | |
985 | .name = "mpll_50m", | |
986 | .ops = &clk_regmap_mux_ro_ops, | |
987 | .parent_names = (const char *[]){ IN_PREFIX "xtal", | |
988 | "mpll_50m_div" }, | |
989 | .num_parents = 2, | |
990 | }, | |
991 | }; | |
992 | ||
993 | static struct clk_fixed_factor g12a_mpll_prediv = { | |
994 | .mult = 1, | |
995 | .div = 2, | |
996 | .hw.init = &(struct clk_init_data){ | |
997 | .name = "mpll_prediv", | |
998 | .ops = &clk_fixed_factor_ops, | |
999 | .parent_names = (const char *[]){ "fixed_pll_dco" }, | |
1000 | .num_parents = 1, | |
1001 | }, | |
1002 | }; | |
1003 | ||
76d3fc38 JB |
1004 | static const struct reg_sequence g12a_mpll0_init_regs[] = { |
1005 | { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 }, | |
1006 | }; | |
1007 | ||
085a4ea9 JH |
1008 | static struct clk_regmap g12a_mpll0_div = { |
1009 | .data = &(struct meson_clk_mpll_data){ | |
1010 | .sdm = { | |
1011 | .reg_off = HHI_MPLL_CNTL1, | |
1012 | .shift = 0, | |
1013 | .width = 14, | |
1014 | }, | |
1015 | .sdm_en = { | |
1016 | .reg_off = HHI_MPLL_CNTL1, | |
1017 | .shift = 30, | |
1018 | .width = 1, | |
1019 | }, | |
1020 | .n2 = { | |
1021 | .reg_off = HHI_MPLL_CNTL1, | |
1022 | .shift = 20, | |
1023 | .width = 9, | |
1024 | }, | |
1025 | .ssen = { | |
1026 | .reg_off = HHI_MPLL_CNTL1, | |
1027 | .shift = 29, | |
1028 | .width = 1, | |
1029 | }, | |
1030 | .lock = &meson_clk_lock, | |
76d3fc38 JB |
1031 | .init_regs = g12a_mpll0_init_regs, |
1032 | .init_count = ARRAY_SIZE(g12a_mpll0_init_regs), | |
085a4ea9 JH |
1033 | }, |
1034 | .hw.init = &(struct clk_init_data){ | |
1035 | .name = "mpll0_div", | |
1036 | .ops = &meson_clk_mpll_ops, | |
1037 | .parent_names = (const char *[]){ "mpll_prediv" }, | |
1038 | .num_parents = 1, | |
1039 | }, | |
1040 | }; | |
1041 | ||
1042 | static struct clk_regmap g12a_mpll0 = { | |
1043 | .data = &(struct clk_regmap_gate_data){ | |
1044 | .offset = HHI_MPLL_CNTL1, | |
1045 | .bit_idx = 31, | |
1046 | }, | |
1047 | .hw.init = &(struct clk_init_data){ | |
1048 | .name = "mpll0", | |
1049 | .ops = &clk_regmap_gate_ops, | |
1050 | .parent_names = (const char *[]){ "mpll0_div" }, | |
1051 | .num_parents = 1, | |
1052 | .flags = CLK_SET_RATE_PARENT, | |
1053 | }, | |
1054 | }; | |
1055 | ||
76d3fc38 JB |
1056 | static const struct reg_sequence g12a_mpll1_init_regs[] = { |
1057 | { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 }, | |
1058 | }; | |
1059 | ||
085a4ea9 JH |
1060 | static struct clk_regmap g12a_mpll1_div = { |
1061 | .data = &(struct meson_clk_mpll_data){ | |
1062 | .sdm = { | |
1063 | .reg_off = HHI_MPLL_CNTL3, | |
1064 | .shift = 0, | |
1065 | .width = 14, | |
1066 | }, | |
1067 | .sdm_en = { | |
1068 | .reg_off = HHI_MPLL_CNTL3, | |
1069 | .shift = 30, | |
1070 | .width = 1, | |
1071 | }, | |
1072 | .n2 = { | |
1073 | .reg_off = HHI_MPLL_CNTL3, | |
1074 | .shift = 20, | |
1075 | .width = 9, | |
1076 | }, | |
1077 | .ssen = { | |
1078 | .reg_off = HHI_MPLL_CNTL3, | |
1079 | .shift = 29, | |
1080 | .width = 1, | |
1081 | }, | |
1082 | .lock = &meson_clk_lock, | |
76d3fc38 JB |
1083 | .init_regs = g12a_mpll1_init_regs, |
1084 | .init_count = ARRAY_SIZE(g12a_mpll1_init_regs), | |
085a4ea9 JH |
1085 | }, |
1086 | .hw.init = &(struct clk_init_data){ | |
1087 | .name = "mpll1_div", | |
1088 | .ops = &meson_clk_mpll_ops, | |
1089 | .parent_names = (const char *[]){ "mpll_prediv" }, | |
1090 | .num_parents = 1, | |
1091 | }, | |
1092 | }; | |
1093 | ||
1094 | static struct clk_regmap g12a_mpll1 = { | |
1095 | .data = &(struct clk_regmap_gate_data){ | |
1096 | .offset = HHI_MPLL_CNTL3, | |
1097 | .bit_idx = 31, | |
1098 | }, | |
1099 | .hw.init = &(struct clk_init_data){ | |
1100 | .name = "mpll1", | |
1101 | .ops = &clk_regmap_gate_ops, | |
1102 | .parent_names = (const char *[]){ "mpll1_div" }, | |
1103 | .num_parents = 1, | |
1104 | .flags = CLK_SET_RATE_PARENT, | |
1105 | }, | |
1106 | }; | |
1107 | ||
76d3fc38 JB |
1108 | static const struct reg_sequence g12a_mpll2_init_regs[] = { |
1109 | { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 }, | |
1110 | }; | |
1111 | ||
085a4ea9 JH |
1112 | static struct clk_regmap g12a_mpll2_div = { |
1113 | .data = &(struct meson_clk_mpll_data){ | |
1114 | .sdm = { | |
1115 | .reg_off = HHI_MPLL_CNTL5, | |
1116 | .shift = 0, | |
1117 | .width = 14, | |
1118 | }, | |
1119 | .sdm_en = { | |
1120 | .reg_off = HHI_MPLL_CNTL5, | |
1121 | .shift = 30, | |
1122 | .width = 1, | |
1123 | }, | |
1124 | .n2 = { | |
1125 | .reg_off = HHI_MPLL_CNTL5, | |
1126 | .shift = 20, | |
1127 | .width = 9, | |
1128 | }, | |
1129 | .ssen = { | |
1130 | .reg_off = HHI_MPLL_CNTL5, | |
1131 | .shift = 29, | |
1132 | .width = 1, | |
1133 | }, | |
1134 | .lock = &meson_clk_lock, | |
76d3fc38 JB |
1135 | .init_regs = g12a_mpll2_init_regs, |
1136 | .init_count = ARRAY_SIZE(g12a_mpll2_init_regs), | |
085a4ea9 JH |
1137 | }, |
1138 | .hw.init = &(struct clk_init_data){ | |
1139 | .name = "mpll2_div", | |
1140 | .ops = &meson_clk_mpll_ops, | |
1141 | .parent_names = (const char *[]){ "mpll_prediv" }, | |
1142 | .num_parents = 1, | |
1143 | }, | |
1144 | }; | |
1145 | ||
1146 | static struct clk_regmap g12a_mpll2 = { | |
1147 | .data = &(struct clk_regmap_gate_data){ | |
1148 | .offset = HHI_MPLL_CNTL5, | |
1149 | .bit_idx = 31, | |
1150 | }, | |
1151 | .hw.init = &(struct clk_init_data){ | |
1152 | .name = "mpll2", | |
1153 | .ops = &clk_regmap_gate_ops, | |
1154 | .parent_names = (const char *[]){ "mpll2_div" }, | |
1155 | .num_parents = 1, | |
1156 | .flags = CLK_SET_RATE_PARENT, | |
1157 | }, | |
1158 | }; | |
1159 | ||
76d3fc38 JB |
1160 | static const struct reg_sequence g12a_mpll3_init_regs[] = { |
1161 | { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 }, | |
1162 | }; | |
1163 | ||
085a4ea9 JH |
1164 | static struct clk_regmap g12a_mpll3_div = { |
1165 | .data = &(struct meson_clk_mpll_data){ | |
1166 | .sdm = { | |
1167 | .reg_off = HHI_MPLL_CNTL7, | |
1168 | .shift = 0, | |
1169 | .width = 14, | |
1170 | }, | |
1171 | .sdm_en = { | |
1172 | .reg_off = HHI_MPLL_CNTL7, | |
1173 | .shift = 30, | |
1174 | .width = 1, | |
1175 | }, | |
1176 | .n2 = { | |
1177 | .reg_off = HHI_MPLL_CNTL7, | |
1178 | .shift = 20, | |
1179 | .width = 9, | |
1180 | }, | |
1181 | .ssen = { | |
1182 | .reg_off = HHI_MPLL_CNTL7, | |
1183 | .shift = 29, | |
1184 | .width = 1, | |
1185 | }, | |
1186 | .lock = &meson_clk_lock, | |
76d3fc38 JB |
1187 | .init_regs = g12a_mpll3_init_regs, |
1188 | .init_count = ARRAY_SIZE(g12a_mpll3_init_regs), | |
085a4ea9 JH |
1189 | }, |
1190 | .hw.init = &(struct clk_init_data){ | |
1191 | .name = "mpll3_div", | |
1192 | .ops = &meson_clk_mpll_ops, | |
1193 | .parent_names = (const char *[]){ "mpll_prediv" }, | |
1194 | .num_parents = 1, | |
1195 | }, | |
1196 | }; | |
1197 | ||
1198 | static struct clk_regmap g12a_mpll3 = { | |
1199 | .data = &(struct clk_regmap_gate_data){ | |
1200 | .offset = HHI_MPLL_CNTL7, | |
1201 | .bit_idx = 31, | |
1202 | }, | |
1203 | .hw.init = &(struct clk_init_data){ | |
1204 | .name = "mpll3", | |
1205 | .ops = &clk_regmap_gate_ops, | |
1206 | .parent_names = (const char *[]){ "mpll3_div" }, | |
1207 | .num_parents = 1, | |
1208 | .flags = CLK_SET_RATE_PARENT, | |
1209 | }, | |
1210 | }; | |
1211 | ||
1212 | static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; | |
1213 | static const char * const clk81_parent_names[] = { | |
1214 | IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", | |
1215 | "fclk_div3", "fclk_div5" | |
1216 | }; | |
1217 | ||
1218 | static struct clk_regmap g12a_mpeg_clk_sel = { | |
1219 | .data = &(struct clk_regmap_mux_data){ | |
1220 | .offset = HHI_MPEG_CLK_CNTL, | |
1221 | .mask = 0x7, | |
1222 | .shift = 12, | |
1223 | .table = mux_table_clk81, | |
1224 | }, | |
1225 | .hw.init = &(struct clk_init_data){ | |
1226 | .name = "mpeg_clk_sel", | |
1227 | .ops = &clk_regmap_mux_ro_ops, | |
1228 | .parent_names = clk81_parent_names, | |
1229 | .num_parents = ARRAY_SIZE(clk81_parent_names), | |
1230 | }, | |
1231 | }; | |
1232 | ||
1233 | static struct clk_regmap g12a_mpeg_clk_div = { | |
1234 | .data = &(struct clk_regmap_div_data){ | |
1235 | .offset = HHI_MPEG_CLK_CNTL, | |
1236 | .shift = 0, | |
1237 | .width = 7, | |
1238 | }, | |
1239 | .hw.init = &(struct clk_init_data){ | |
1240 | .name = "mpeg_clk_div", | |
1241 | .ops = &clk_regmap_divider_ops, | |
1242 | .parent_names = (const char *[]){ "mpeg_clk_sel" }, | |
1243 | .num_parents = 1, | |
1244 | .flags = CLK_SET_RATE_PARENT, | |
1245 | }, | |
1246 | }; | |
1247 | ||
1248 | static struct clk_regmap g12a_clk81 = { | |
1249 | .data = &(struct clk_regmap_gate_data){ | |
1250 | .offset = HHI_MPEG_CLK_CNTL, | |
1251 | .bit_idx = 7, | |
1252 | }, | |
1253 | .hw.init = &(struct clk_init_data){ | |
1254 | .name = "clk81", | |
1255 | .ops = &clk_regmap_gate_ops, | |
1256 | .parent_names = (const char *[]){ "mpeg_clk_div" }, | |
1257 | .num_parents = 1, | |
1258 | .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), | |
1259 | }, | |
1260 | }; | |
1261 | ||
1262 | static const char * const g12a_sd_emmc_clk0_parent_names[] = { | |
1263 | IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", | |
1264 | ||
1265 | /* | |
1266 | * Following these parent clocks, we should also have had mpll2, mpll3 | |
1267 | * and gp0_pll but these clocks are too precious to be used here. All | |
1268 | * the necessary rates for MMC and NAND operation can be acheived using | |
1269 | * g12a_ee_core or fclk_div clocks | |
1270 | */ | |
1271 | }; | |
1272 | ||
1273 | /* SDIO clock */ | |
1274 | static struct clk_regmap g12a_sd_emmc_a_clk0_sel = { | |
1275 | .data = &(struct clk_regmap_mux_data){ | |
1276 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1277 | .mask = 0x7, | |
1278 | .shift = 9, | |
1279 | }, | |
1280 | .hw.init = &(struct clk_init_data) { | |
1281 | .name = "sd_emmc_a_clk0_sel", | |
1282 | .ops = &clk_regmap_mux_ops, | |
1283 | .parent_names = g12a_sd_emmc_clk0_parent_names, | |
1284 | .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), | |
1285 | .flags = CLK_SET_RATE_PARENT, | |
1286 | }, | |
1287 | }; | |
1288 | ||
1289 | static struct clk_regmap g12a_sd_emmc_a_clk0_div = { | |
1290 | .data = &(struct clk_regmap_div_data){ | |
1291 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1292 | .shift = 0, | |
1293 | .width = 7, | |
1294 | }, | |
1295 | .hw.init = &(struct clk_init_data) { | |
1296 | .name = "sd_emmc_a_clk0_div", | |
1297 | .ops = &clk_regmap_divider_ops, | |
1298 | .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, | |
1299 | .num_parents = 1, | |
1300 | .flags = CLK_SET_RATE_PARENT, | |
1301 | }, | |
1302 | }; | |
1303 | ||
1304 | static struct clk_regmap g12a_sd_emmc_a_clk0 = { | |
1305 | .data = &(struct clk_regmap_gate_data){ | |
1306 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1307 | .bit_idx = 7, | |
1308 | }, | |
1309 | .hw.init = &(struct clk_init_data){ | |
1310 | .name = "sd_emmc_a_clk0", | |
1311 | .ops = &clk_regmap_gate_ops, | |
1312 | .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, | |
1313 | .num_parents = 1, | |
1314 | .flags = CLK_SET_RATE_PARENT, | |
1315 | }, | |
1316 | }; | |
1317 | ||
1318 | /* SDcard clock */ | |
1319 | static struct clk_regmap g12a_sd_emmc_b_clk0_sel = { | |
1320 | .data = &(struct clk_regmap_mux_data){ | |
1321 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1322 | .mask = 0x7, | |
1323 | .shift = 25, | |
1324 | }, | |
1325 | .hw.init = &(struct clk_init_data) { | |
1326 | .name = "sd_emmc_b_clk0_sel", | |
1327 | .ops = &clk_regmap_mux_ops, | |
1328 | .parent_names = g12a_sd_emmc_clk0_parent_names, | |
1329 | .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), | |
1330 | .flags = CLK_SET_RATE_PARENT, | |
1331 | }, | |
1332 | }; | |
1333 | ||
1334 | static struct clk_regmap g12a_sd_emmc_b_clk0_div = { | |
1335 | .data = &(struct clk_regmap_div_data){ | |
1336 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1337 | .shift = 16, | |
1338 | .width = 7, | |
1339 | }, | |
1340 | .hw.init = &(struct clk_init_data) { | |
1341 | .name = "sd_emmc_b_clk0_div", | |
1342 | .ops = &clk_regmap_divider_ops, | |
1343 | .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, | |
1344 | .num_parents = 1, | |
1345 | .flags = CLK_SET_RATE_PARENT, | |
1346 | }, | |
1347 | }; | |
1348 | ||
1349 | static struct clk_regmap g12a_sd_emmc_b_clk0 = { | |
1350 | .data = &(struct clk_regmap_gate_data){ | |
1351 | .offset = HHI_SD_EMMC_CLK_CNTL, | |
1352 | .bit_idx = 23, | |
1353 | }, | |
1354 | .hw.init = &(struct clk_init_data){ | |
1355 | .name = "sd_emmc_b_clk0", | |
1356 | .ops = &clk_regmap_gate_ops, | |
1357 | .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, | |
1358 | .num_parents = 1, | |
1359 | .flags = CLK_SET_RATE_PARENT, | |
1360 | }, | |
1361 | }; | |
1362 | ||
1363 | /* EMMC/NAND clock */ | |
1364 | static struct clk_regmap g12a_sd_emmc_c_clk0_sel = { | |
1365 | .data = &(struct clk_regmap_mux_data){ | |
1366 | .offset = HHI_NAND_CLK_CNTL, | |
1367 | .mask = 0x7, | |
1368 | .shift = 9, | |
1369 | }, | |
1370 | .hw.init = &(struct clk_init_data) { | |
1371 | .name = "sd_emmc_c_clk0_sel", | |
1372 | .ops = &clk_regmap_mux_ops, | |
1373 | .parent_names = g12a_sd_emmc_clk0_parent_names, | |
1374 | .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), | |
1375 | .flags = CLK_SET_RATE_PARENT, | |
1376 | }, | |
1377 | }; | |
1378 | ||
1379 | static struct clk_regmap g12a_sd_emmc_c_clk0_div = { | |
1380 | .data = &(struct clk_regmap_div_data){ | |
1381 | .offset = HHI_NAND_CLK_CNTL, | |
1382 | .shift = 0, | |
1383 | .width = 7, | |
1384 | }, | |
1385 | .hw.init = &(struct clk_init_data) { | |
1386 | .name = "sd_emmc_c_clk0_div", | |
1387 | .ops = &clk_regmap_divider_ops, | |
1388 | .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, | |
1389 | .num_parents = 1, | |
1390 | .flags = CLK_SET_RATE_PARENT, | |
1391 | }, | |
1392 | }; | |
1393 | ||
1394 | static struct clk_regmap g12a_sd_emmc_c_clk0 = { | |
1395 | .data = &(struct clk_regmap_gate_data){ | |
1396 | .offset = HHI_NAND_CLK_CNTL, | |
1397 | .bit_idx = 7, | |
1398 | }, | |
1399 | .hw.init = &(struct clk_init_data){ | |
1400 | .name = "sd_emmc_c_clk0", | |
1401 | .ops = &clk_regmap_gate_ops, | |
1402 | .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, | |
1403 | .num_parents = 1, | |
1404 | .flags = CLK_SET_RATE_PARENT, | |
1405 | }, | |
1406 | }; | |
1407 | ||
1408 | /* VPU Clock */ | |
1409 | ||
1410 | static const char * const g12a_vpu_parent_names[] = { | |
9e05e49c | 1411 | "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", |
085a4ea9 JH |
1412 | "mpll1", "vid_pll", "hifi_pll", "gp0_pll", |
1413 | }; | |
1414 | ||
1415 | static struct clk_regmap g12a_vpu_0_sel = { | |
1416 | .data = &(struct clk_regmap_mux_data){ | |
1417 | .offset = HHI_VPU_CLK_CNTL, | |
f53b9f14 | 1418 | .mask = 0x7, |
085a4ea9 JH |
1419 | .shift = 9, |
1420 | }, | |
1421 | .hw.init = &(struct clk_init_data){ | |
1422 | .name = "vpu_0_sel", | |
1423 | .ops = &clk_regmap_mux_ops, | |
1424 | .parent_names = g12a_vpu_parent_names, | |
1425 | .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), | |
1426 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1427 | }, | |
1428 | }; | |
1429 | ||
1430 | static struct clk_regmap g12a_vpu_0_div = { | |
1431 | .data = &(struct clk_regmap_div_data){ | |
1432 | .offset = HHI_VPU_CLK_CNTL, | |
1433 | .shift = 0, | |
1434 | .width = 7, | |
1435 | }, | |
1436 | .hw.init = &(struct clk_init_data){ | |
1437 | .name = "vpu_0_div", | |
1438 | .ops = &clk_regmap_divider_ops, | |
1439 | .parent_names = (const char *[]){ "vpu_0_sel" }, | |
1440 | .num_parents = 1, | |
1441 | .flags = CLK_SET_RATE_PARENT, | |
1442 | }, | |
1443 | }; | |
1444 | ||
1445 | static struct clk_regmap g12a_vpu_0 = { | |
1446 | .data = &(struct clk_regmap_gate_data){ | |
1447 | .offset = HHI_VPU_CLK_CNTL, | |
1448 | .bit_idx = 8, | |
1449 | }, | |
1450 | .hw.init = &(struct clk_init_data) { | |
1451 | .name = "vpu_0", | |
1452 | .ops = &clk_regmap_gate_ops, | |
1453 | .parent_names = (const char *[]){ "vpu_0_div" }, | |
1454 | .num_parents = 1, | |
1455 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1456 | }, | |
1457 | }; | |
1458 | ||
1459 | static struct clk_regmap g12a_vpu_1_sel = { | |
1460 | .data = &(struct clk_regmap_mux_data){ | |
1461 | .offset = HHI_VPU_CLK_CNTL, | |
f53b9f14 | 1462 | .mask = 0x7, |
085a4ea9 JH |
1463 | .shift = 25, |
1464 | }, | |
1465 | .hw.init = &(struct clk_init_data){ | |
1466 | .name = "vpu_1_sel", | |
1467 | .ops = &clk_regmap_mux_ops, | |
1468 | .parent_names = g12a_vpu_parent_names, | |
1469 | .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), | |
1470 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1471 | }, | |
1472 | }; | |
1473 | ||
1474 | static struct clk_regmap g12a_vpu_1_div = { | |
1475 | .data = &(struct clk_regmap_div_data){ | |
1476 | .offset = HHI_VPU_CLK_CNTL, | |
1477 | .shift = 16, | |
1478 | .width = 7, | |
1479 | }, | |
1480 | .hw.init = &(struct clk_init_data){ | |
1481 | .name = "vpu_1_div", | |
1482 | .ops = &clk_regmap_divider_ops, | |
1483 | .parent_names = (const char *[]){ "vpu_1_sel" }, | |
1484 | .num_parents = 1, | |
1485 | .flags = CLK_SET_RATE_PARENT, | |
1486 | }, | |
1487 | }; | |
1488 | ||
1489 | static struct clk_regmap g12a_vpu_1 = { | |
1490 | .data = &(struct clk_regmap_gate_data){ | |
1491 | .offset = HHI_VPU_CLK_CNTL, | |
1492 | .bit_idx = 24, | |
1493 | }, | |
1494 | .hw.init = &(struct clk_init_data) { | |
1495 | .name = "vpu_1", | |
1496 | .ops = &clk_regmap_gate_ops, | |
1497 | .parent_names = (const char *[]){ "vpu_1_div" }, | |
1498 | .num_parents = 1, | |
1499 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1500 | }, | |
1501 | }; | |
1502 | ||
1503 | static struct clk_regmap g12a_vpu = { | |
1504 | .data = &(struct clk_regmap_mux_data){ | |
1505 | .offset = HHI_VPU_CLK_CNTL, | |
1506 | .mask = 1, | |
1507 | .shift = 31, | |
1508 | }, | |
1509 | .hw.init = &(struct clk_init_data){ | |
1510 | .name = "vpu", | |
1511 | .ops = &clk_regmap_mux_ops, | |
1512 | /* | |
1513 | * bit 31 selects from 2 possible parents: | |
1514 | * vpu_0 or vpu_1 | |
1515 | */ | |
1516 | .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, | |
1517 | .num_parents = 2, | |
1518 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1519 | }, | |
1520 | }; | |
1521 | ||
4b0f7305 MJ |
1522 | /* VDEC clocks */ |
1523 | ||
1524 | static const char * const g12a_vdec_parent_names[] = { | |
1525 | "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", | |
1526 | "hifi_pll", "gp0_pll", | |
1527 | }; | |
1528 | ||
1529 | static struct clk_regmap g12a_vdec_1_sel = { | |
1530 | .data = &(struct clk_regmap_mux_data){ | |
1531 | .offset = HHI_VDEC_CLK_CNTL, | |
1532 | .mask = 0x7, | |
1533 | .shift = 9, | |
1534 | .flags = CLK_MUX_ROUND_CLOSEST, | |
1535 | }, | |
1536 | .hw.init = &(struct clk_init_data){ | |
1537 | .name = "vdec_1_sel", | |
1538 | .ops = &clk_regmap_mux_ops, | |
1539 | .parent_names = g12a_vdec_parent_names, | |
1540 | .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), | |
1541 | .flags = CLK_SET_RATE_PARENT, | |
1542 | }, | |
1543 | }; | |
1544 | ||
1545 | static struct clk_regmap g12a_vdec_1_div = { | |
1546 | .data = &(struct clk_regmap_div_data){ | |
1547 | .offset = HHI_VDEC_CLK_CNTL, | |
1548 | .shift = 0, | |
1549 | .width = 7, | |
1550 | .flags = CLK_DIVIDER_ROUND_CLOSEST, | |
1551 | }, | |
1552 | .hw.init = &(struct clk_init_data){ | |
1553 | .name = "vdec_1_div", | |
1554 | .ops = &clk_regmap_divider_ops, | |
1555 | .parent_names = (const char *[]){ "vdec_1_sel" }, | |
1556 | .num_parents = 1, | |
1557 | .flags = CLK_SET_RATE_PARENT, | |
1558 | }, | |
1559 | }; | |
1560 | ||
1561 | static struct clk_regmap g12a_vdec_1 = { | |
1562 | .data = &(struct clk_regmap_gate_data){ | |
1563 | .offset = HHI_VDEC_CLK_CNTL, | |
1564 | .bit_idx = 8, | |
1565 | }, | |
1566 | .hw.init = &(struct clk_init_data) { | |
1567 | .name = "vdec_1", | |
1568 | .ops = &clk_regmap_gate_ops, | |
1569 | .parent_names = (const char *[]){ "vdec_1_div" }, | |
1570 | .num_parents = 1, | |
1571 | .flags = CLK_SET_RATE_PARENT, | |
1572 | }, | |
1573 | }; | |
1574 | ||
1575 | static struct clk_regmap g12a_vdec_hevcf_sel = { | |
1576 | .data = &(struct clk_regmap_mux_data){ | |
1577 | .offset = HHI_VDEC2_CLK_CNTL, | |
1578 | .mask = 0x7, | |
1579 | .shift = 9, | |
1580 | .flags = CLK_MUX_ROUND_CLOSEST, | |
1581 | }, | |
1582 | .hw.init = &(struct clk_init_data){ | |
1583 | .name = "vdec_hevcf_sel", | |
1584 | .ops = &clk_regmap_mux_ops, | |
1585 | .parent_names = g12a_vdec_parent_names, | |
1586 | .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), | |
1587 | .flags = CLK_SET_RATE_PARENT, | |
1588 | }, | |
1589 | }; | |
1590 | ||
1591 | static struct clk_regmap g12a_vdec_hevcf_div = { | |
1592 | .data = &(struct clk_regmap_div_data){ | |
1593 | .offset = HHI_VDEC2_CLK_CNTL, | |
1594 | .shift = 0, | |
1595 | .width = 7, | |
1596 | .flags = CLK_DIVIDER_ROUND_CLOSEST, | |
1597 | }, | |
1598 | .hw.init = &(struct clk_init_data){ | |
1599 | .name = "vdec_hevcf_div", | |
1600 | .ops = &clk_regmap_divider_ops, | |
1601 | .parent_names = (const char *[]){ "vdec_hevcf_sel" }, | |
1602 | .num_parents = 1, | |
1603 | .flags = CLK_SET_RATE_PARENT, | |
1604 | }, | |
1605 | }; | |
1606 | ||
1607 | static struct clk_regmap g12a_vdec_hevcf = { | |
1608 | .data = &(struct clk_regmap_gate_data){ | |
1609 | .offset = HHI_VDEC2_CLK_CNTL, | |
1610 | .bit_idx = 8, | |
1611 | }, | |
1612 | .hw.init = &(struct clk_init_data) { | |
1613 | .name = "vdec_hevcf", | |
1614 | .ops = &clk_regmap_gate_ops, | |
1615 | .parent_names = (const char *[]){ "vdec_hevcf_div" }, | |
1616 | .num_parents = 1, | |
1617 | .flags = CLK_SET_RATE_PARENT, | |
1618 | }, | |
1619 | }; | |
1620 | ||
1621 | static struct clk_regmap g12a_vdec_hevc_sel = { | |
1622 | .data = &(struct clk_regmap_mux_data){ | |
1623 | .offset = HHI_VDEC2_CLK_CNTL, | |
1624 | .mask = 0x7, | |
1625 | .shift = 25, | |
1626 | .flags = CLK_MUX_ROUND_CLOSEST, | |
1627 | }, | |
1628 | .hw.init = &(struct clk_init_data){ | |
1629 | .name = "vdec_hevc_sel", | |
1630 | .ops = &clk_regmap_mux_ops, | |
1631 | .parent_names = g12a_vdec_parent_names, | |
1632 | .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), | |
1633 | .flags = CLK_SET_RATE_PARENT, | |
1634 | }, | |
1635 | }; | |
1636 | ||
1637 | static struct clk_regmap g12a_vdec_hevc_div = { | |
1638 | .data = &(struct clk_regmap_div_data){ | |
1639 | .offset = HHI_VDEC2_CLK_CNTL, | |
1640 | .shift = 16, | |
1641 | .width = 7, | |
1642 | .flags = CLK_DIVIDER_ROUND_CLOSEST, | |
1643 | }, | |
1644 | .hw.init = &(struct clk_init_data){ | |
1645 | .name = "vdec_hevc_div", | |
1646 | .ops = &clk_regmap_divider_ops, | |
1647 | .parent_names = (const char *[]){ "vdec_hevc_sel" }, | |
1648 | .num_parents = 1, | |
1649 | .flags = CLK_SET_RATE_PARENT, | |
1650 | }, | |
1651 | }; | |
1652 | ||
1653 | static struct clk_regmap g12a_vdec_hevc = { | |
1654 | .data = &(struct clk_regmap_gate_data){ | |
1655 | .offset = HHI_VDEC2_CLK_CNTL, | |
1656 | .bit_idx = 24, | |
1657 | }, | |
1658 | .hw.init = &(struct clk_init_data) { | |
1659 | .name = "vdec_hevc", | |
1660 | .ops = &clk_regmap_gate_ops, | |
1661 | .parent_names = (const char *[]){ "vdec_hevc_div" }, | |
1662 | .num_parents = 1, | |
1663 | .flags = CLK_SET_RATE_PARENT, | |
1664 | }, | |
1665 | }; | |
1666 | ||
085a4ea9 JH |
1667 | /* VAPB Clock */ |
1668 | ||
1669 | static const char * const g12a_vapb_parent_names[] = { | |
1670 | "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", | |
1671 | "mpll1", "vid_pll", "mpll2", "fclk_div2p5", | |
1672 | }; | |
1673 | ||
1674 | static struct clk_regmap g12a_vapb_0_sel = { | |
1675 | .data = &(struct clk_regmap_mux_data){ | |
1676 | .offset = HHI_VAPBCLK_CNTL, | |
1677 | .mask = 0x3, | |
1678 | .shift = 9, | |
1679 | }, | |
1680 | .hw.init = &(struct clk_init_data){ | |
1681 | .name = "vapb_0_sel", | |
1682 | .ops = &clk_regmap_mux_ops, | |
1683 | .parent_names = g12a_vapb_parent_names, | |
1684 | .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), | |
1685 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1686 | }, | |
1687 | }; | |
1688 | ||
1689 | static struct clk_regmap g12a_vapb_0_div = { | |
1690 | .data = &(struct clk_regmap_div_data){ | |
1691 | .offset = HHI_VAPBCLK_CNTL, | |
1692 | .shift = 0, | |
1693 | .width = 7, | |
1694 | }, | |
1695 | .hw.init = &(struct clk_init_data){ | |
1696 | .name = "vapb_0_div", | |
1697 | .ops = &clk_regmap_divider_ops, | |
1698 | .parent_names = (const char *[]){ "vapb_0_sel" }, | |
1699 | .num_parents = 1, | |
1700 | .flags = CLK_SET_RATE_PARENT, | |
1701 | }, | |
1702 | }; | |
1703 | ||
1704 | static struct clk_regmap g12a_vapb_0 = { | |
1705 | .data = &(struct clk_regmap_gate_data){ | |
1706 | .offset = HHI_VAPBCLK_CNTL, | |
1707 | .bit_idx = 8, | |
1708 | }, | |
1709 | .hw.init = &(struct clk_init_data) { | |
1710 | .name = "vapb_0", | |
1711 | .ops = &clk_regmap_gate_ops, | |
1712 | .parent_names = (const char *[]){ "vapb_0_div" }, | |
1713 | .num_parents = 1, | |
1714 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1715 | }, | |
1716 | }; | |
1717 | ||
1718 | static struct clk_regmap g12a_vapb_1_sel = { | |
1719 | .data = &(struct clk_regmap_mux_data){ | |
1720 | .offset = HHI_VAPBCLK_CNTL, | |
1721 | .mask = 0x3, | |
1722 | .shift = 25, | |
1723 | }, | |
1724 | .hw.init = &(struct clk_init_data){ | |
1725 | .name = "vapb_1_sel", | |
1726 | .ops = &clk_regmap_mux_ops, | |
1727 | .parent_names = g12a_vapb_parent_names, | |
1728 | .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), | |
1729 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1730 | }, | |
1731 | }; | |
1732 | ||
1733 | static struct clk_regmap g12a_vapb_1_div = { | |
1734 | .data = &(struct clk_regmap_div_data){ | |
1735 | .offset = HHI_VAPBCLK_CNTL, | |
1736 | .shift = 16, | |
1737 | .width = 7, | |
1738 | }, | |
1739 | .hw.init = &(struct clk_init_data){ | |
1740 | .name = "vapb_1_div", | |
1741 | .ops = &clk_regmap_divider_ops, | |
1742 | .parent_names = (const char *[]){ "vapb_1_sel" }, | |
1743 | .num_parents = 1, | |
1744 | .flags = CLK_SET_RATE_PARENT, | |
1745 | }, | |
1746 | }; | |
1747 | ||
1748 | static struct clk_regmap g12a_vapb_1 = { | |
1749 | .data = &(struct clk_regmap_gate_data){ | |
1750 | .offset = HHI_VAPBCLK_CNTL, | |
1751 | .bit_idx = 24, | |
1752 | }, | |
1753 | .hw.init = &(struct clk_init_data) { | |
1754 | .name = "vapb_1", | |
1755 | .ops = &clk_regmap_gate_ops, | |
1756 | .parent_names = (const char *[]){ "vapb_1_div" }, | |
1757 | .num_parents = 1, | |
1758 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1759 | }, | |
1760 | }; | |
1761 | ||
1762 | static struct clk_regmap g12a_vapb_sel = { | |
1763 | .data = &(struct clk_regmap_mux_data){ | |
1764 | .offset = HHI_VAPBCLK_CNTL, | |
1765 | .mask = 1, | |
1766 | .shift = 31, | |
1767 | }, | |
1768 | .hw.init = &(struct clk_init_data){ | |
1769 | .name = "vapb_sel", | |
1770 | .ops = &clk_regmap_mux_ops, | |
1771 | /* | |
1772 | * bit 31 selects from 2 possible parents: | |
1773 | * vapb_0 or vapb_1 | |
1774 | */ | |
1775 | .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, | |
1776 | .num_parents = 2, | |
1777 | .flags = CLK_SET_RATE_NO_REPARENT, | |
1778 | }, | |
1779 | }; | |
1780 | ||
1781 | static struct clk_regmap g12a_vapb = { | |
1782 | .data = &(struct clk_regmap_gate_data){ | |
1783 | .offset = HHI_VAPBCLK_CNTL, | |
1784 | .bit_idx = 30, | |
1785 | }, | |
1786 | .hw.init = &(struct clk_init_data) { | |
1787 | .name = "vapb", | |
1788 | .ops = &clk_regmap_gate_ops, | |
1789 | .parent_names = (const char *[]){ "vapb_sel" }, | |
1790 | .num_parents = 1, | |
1791 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1792 | }, | |
1793 | }; | |
1794 | ||
1795 | /* Video Clocks */ | |
1796 | ||
1797 | static struct clk_regmap g12a_vid_pll_div = { | |
1798 | .data = &(struct meson_vid_pll_div_data){ | |
1799 | .val = { | |
1800 | .reg_off = HHI_VID_PLL_CLK_DIV, | |
1801 | .shift = 0, | |
1802 | .width = 15, | |
1803 | }, | |
1804 | .sel = { | |
1805 | .reg_off = HHI_VID_PLL_CLK_DIV, | |
1806 | .shift = 16, | |
1807 | .width = 2, | |
1808 | }, | |
1809 | }, | |
1810 | .hw.init = &(struct clk_init_data) { | |
1811 | .name = "vid_pll_div", | |
1812 | .ops = &meson_vid_pll_div_ro_ops, | |
1813 | .parent_names = (const char *[]){ "hdmi_pll" }, | |
1814 | .num_parents = 1, | |
1815 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, | |
1816 | }, | |
1817 | }; | |
1818 | ||
1819 | static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div", | |
1820 | "hdmi_pll" }; | |
1821 | ||
1822 | static struct clk_regmap g12a_vid_pll_sel = { | |
1823 | .data = &(struct clk_regmap_mux_data){ | |
1824 | .offset = HHI_VID_PLL_CLK_DIV, | |
1825 | .mask = 0x1, | |
1826 | .shift = 18, | |
1827 | }, | |
1828 | .hw.init = &(struct clk_init_data){ | |
1829 | .name = "vid_pll_sel", | |
1830 | .ops = &clk_regmap_mux_ops, | |
1831 | /* | |
1832 | * bit 18 selects from 2 possible parents: | |
1833 | * vid_pll_div or hdmi_pll | |
1834 | */ | |
1835 | .parent_names = g12a_vid_pll_parent_names, | |
1836 | .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names), | |
1837 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
1838 | }, | |
1839 | }; | |
1840 | ||
1841 | static struct clk_regmap g12a_vid_pll = { | |
1842 | .data = &(struct clk_regmap_gate_data){ | |
1843 | .offset = HHI_VID_PLL_CLK_DIV, | |
1844 | .bit_idx = 19, | |
1845 | }, | |
1846 | .hw.init = &(struct clk_init_data) { | |
1847 | .name = "vid_pll", | |
1848 | .ops = &clk_regmap_gate_ops, | |
1849 | .parent_names = (const char *[]){ "vid_pll_sel" }, | |
1850 | .num_parents = 1, | |
1851 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1852 | }, | |
1853 | }; | |
1854 | ||
1855 | static const char * const g12a_vclk_parent_names[] = { | |
1856 | "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4", | |
1857 | "fclk_div5", "fclk_div7" | |
1858 | }; | |
1859 | ||
1860 | static struct clk_regmap g12a_vclk_sel = { | |
1861 | .data = &(struct clk_regmap_mux_data){ | |
1862 | .offset = HHI_VID_CLK_CNTL, | |
1863 | .mask = 0x7, | |
1864 | .shift = 16, | |
1865 | }, | |
1866 | .hw.init = &(struct clk_init_data){ | |
1867 | .name = "vclk_sel", | |
1868 | .ops = &clk_regmap_mux_ops, | |
1869 | .parent_names = g12a_vclk_parent_names, | |
1870 | .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), | |
1871 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
1872 | }, | |
1873 | }; | |
1874 | ||
1875 | static struct clk_regmap g12a_vclk2_sel = { | |
1876 | .data = &(struct clk_regmap_mux_data){ | |
1877 | .offset = HHI_VIID_CLK_CNTL, | |
1878 | .mask = 0x7, | |
1879 | .shift = 16, | |
1880 | }, | |
1881 | .hw.init = &(struct clk_init_data){ | |
1882 | .name = "vclk2_sel", | |
1883 | .ops = &clk_regmap_mux_ops, | |
1884 | .parent_names = g12a_vclk_parent_names, | |
1885 | .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), | |
1886 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
1887 | }, | |
1888 | }; | |
1889 | ||
1890 | static struct clk_regmap g12a_vclk_input = { | |
1891 | .data = &(struct clk_regmap_gate_data){ | |
1892 | .offset = HHI_VID_CLK_DIV, | |
1893 | .bit_idx = 16, | |
1894 | }, | |
1895 | .hw.init = &(struct clk_init_data) { | |
1896 | .name = "vclk_input", | |
1897 | .ops = &clk_regmap_gate_ops, | |
1898 | .parent_names = (const char *[]){ "vclk_sel" }, | |
1899 | .num_parents = 1, | |
1900 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1901 | }, | |
1902 | }; | |
1903 | ||
1904 | static struct clk_regmap g12a_vclk2_input = { | |
1905 | .data = &(struct clk_regmap_gate_data){ | |
1906 | .offset = HHI_VIID_CLK_DIV, | |
1907 | .bit_idx = 16, | |
1908 | }, | |
1909 | .hw.init = &(struct clk_init_data) { | |
1910 | .name = "vclk2_input", | |
1911 | .ops = &clk_regmap_gate_ops, | |
1912 | .parent_names = (const char *[]){ "vclk2_sel" }, | |
1913 | .num_parents = 1, | |
1914 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1915 | }, | |
1916 | }; | |
1917 | ||
1918 | static struct clk_regmap g12a_vclk_div = { | |
1919 | .data = &(struct clk_regmap_div_data){ | |
1920 | .offset = HHI_VID_CLK_DIV, | |
1921 | .shift = 0, | |
1922 | .width = 8, | |
1923 | }, | |
1924 | .hw.init = &(struct clk_init_data){ | |
1925 | .name = "vclk_div", | |
1926 | .ops = &clk_regmap_divider_ops, | |
1927 | .parent_names = (const char *[]){ "vclk_input" }, | |
1928 | .num_parents = 1, | |
1929 | .flags = CLK_GET_RATE_NOCACHE, | |
1930 | }, | |
1931 | }; | |
1932 | ||
1933 | static struct clk_regmap g12a_vclk2_div = { | |
1934 | .data = &(struct clk_regmap_div_data){ | |
1935 | .offset = HHI_VIID_CLK_DIV, | |
1936 | .shift = 0, | |
1937 | .width = 8, | |
1938 | }, | |
1939 | .hw.init = &(struct clk_init_data){ | |
1940 | .name = "vclk2_div", | |
1941 | .ops = &clk_regmap_divider_ops, | |
1942 | .parent_names = (const char *[]){ "vclk2_input" }, | |
1943 | .num_parents = 1, | |
1944 | .flags = CLK_GET_RATE_NOCACHE, | |
1945 | }, | |
1946 | }; | |
1947 | ||
1948 | static struct clk_regmap g12a_vclk = { | |
1949 | .data = &(struct clk_regmap_gate_data){ | |
1950 | .offset = HHI_VID_CLK_CNTL, | |
1951 | .bit_idx = 19, | |
1952 | }, | |
1953 | .hw.init = &(struct clk_init_data) { | |
1954 | .name = "vclk", | |
1955 | .ops = &clk_regmap_gate_ops, | |
1956 | .parent_names = (const char *[]){ "vclk_div" }, | |
1957 | .num_parents = 1, | |
1958 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1959 | }, | |
1960 | }; | |
1961 | ||
1962 | static struct clk_regmap g12a_vclk2 = { | |
1963 | .data = &(struct clk_regmap_gate_data){ | |
1964 | .offset = HHI_VIID_CLK_CNTL, | |
1965 | .bit_idx = 19, | |
1966 | }, | |
1967 | .hw.init = &(struct clk_init_data) { | |
1968 | .name = "vclk2", | |
1969 | .ops = &clk_regmap_gate_ops, | |
1970 | .parent_names = (const char *[]){ "vclk2_div" }, | |
1971 | .num_parents = 1, | |
1972 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1973 | }, | |
1974 | }; | |
1975 | ||
1976 | static struct clk_regmap g12a_vclk_div1 = { | |
1977 | .data = &(struct clk_regmap_gate_data){ | |
1978 | .offset = HHI_VID_CLK_CNTL, | |
1979 | .bit_idx = 0, | |
1980 | }, | |
1981 | .hw.init = &(struct clk_init_data) { | |
1982 | .name = "vclk_div1", | |
1983 | .ops = &clk_regmap_gate_ops, | |
1984 | .parent_names = (const char *[]){ "vclk" }, | |
1985 | .num_parents = 1, | |
1986 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1987 | }, | |
1988 | }; | |
1989 | ||
1990 | static struct clk_regmap g12a_vclk_div2_en = { | |
1991 | .data = &(struct clk_regmap_gate_data){ | |
1992 | .offset = HHI_VID_CLK_CNTL, | |
1993 | .bit_idx = 1, | |
1994 | }, | |
1995 | .hw.init = &(struct clk_init_data) { | |
1996 | .name = "vclk_div2_en", | |
1997 | .ops = &clk_regmap_gate_ops, | |
1998 | .parent_names = (const char *[]){ "vclk" }, | |
1999 | .num_parents = 1, | |
2000 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2001 | }, | |
2002 | }; | |
2003 | ||
2004 | static struct clk_regmap g12a_vclk_div4_en = { | |
2005 | .data = &(struct clk_regmap_gate_data){ | |
2006 | .offset = HHI_VID_CLK_CNTL, | |
2007 | .bit_idx = 2, | |
2008 | }, | |
2009 | .hw.init = &(struct clk_init_data) { | |
2010 | .name = "vclk_div4_en", | |
2011 | .ops = &clk_regmap_gate_ops, | |
2012 | .parent_names = (const char *[]){ "vclk" }, | |
2013 | .num_parents = 1, | |
2014 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2015 | }, | |
2016 | }; | |
2017 | ||
2018 | static struct clk_regmap g12a_vclk_div6_en = { | |
2019 | .data = &(struct clk_regmap_gate_data){ | |
2020 | .offset = HHI_VID_CLK_CNTL, | |
2021 | .bit_idx = 3, | |
2022 | }, | |
2023 | .hw.init = &(struct clk_init_data) { | |
2024 | .name = "vclk_div6_en", | |
2025 | .ops = &clk_regmap_gate_ops, | |
2026 | .parent_names = (const char *[]){ "vclk" }, | |
2027 | .num_parents = 1, | |
2028 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2029 | }, | |
2030 | }; | |
2031 | ||
2032 | static struct clk_regmap g12a_vclk_div12_en = { | |
2033 | .data = &(struct clk_regmap_gate_data){ | |
2034 | .offset = HHI_VID_CLK_CNTL, | |
2035 | .bit_idx = 4, | |
2036 | }, | |
2037 | .hw.init = &(struct clk_init_data) { | |
2038 | .name = "vclk_div12_en", | |
2039 | .ops = &clk_regmap_gate_ops, | |
2040 | .parent_names = (const char *[]){ "vclk" }, | |
2041 | .num_parents = 1, | |
2042 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2043 | }, | |
2044 | }; | |
2045 | ||
2046 | static struct clk_regmap g12a_vclk2_div1 = { | |
2047 | .data = &(struct clk_regmap_gate_data){ | |
2048 | .offset = HHI_VIID_CLK_CNTL, | |
2049 | .bit_idx = 0, | |
2050 | }, | |
2051 | .hw.init = &(struct clk_init_data) { | |
2052 | .name = "vclk2_div1", | |
2053 | .ops = &clk_regmap_gate_ops, | |
2054 | .parent_names = (const char *[]){ "vclk2" }, | |
2055 | .num_parents = 1, | |
2056 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2057 | }, | |
2058 | }; | |
2059 | ||
2060 | static struct clk_regmap g12a_vclk2_div2_en = { | |
2061 | .data = &(struct clk_regmap_gate_data){ | |
2062 | .offset = HHI_VIID_CLK_CNTL, | |
2063 | .bit_idx = 1, | |
2064 | }, | |
2065 | .hw.init = &(struct clk_init_data) { | |
2066 | .name = "vclk2_div2_en", | |
2067 | .ops = &clk_regmap_gate_ops, | |
2068 | .parent_names = (const char *[]){ "vclk2" }, | |
2069 | .num_parents = 1, | |
2070 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2071 | }, | |
2072 | }; | |
2073 | ||
2074 | static struct clk_regmap g12a_vclk2_div4_en = { | |
2075 | .data = &(struct clk_regmap_gate_data){ | |
2076 | .offset = HHI_VIID_CLK_CNTL, | |
2077 | .bit_idx = 2, | |
2078 | }, | |
2079 | .hw.init = &(struct clk_init_data) { | |
2080 | .name = "vclk2_div4_en", | |
2081 | .ops = &clk_regmap_gate_ops, | |
2082 | .parent_names = (const char *[]){ "vclk2" }, | |
2083 | .num_parents = 1, | |
2084 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2085 | }, | |
2086 | }; | |
2087 | ||
2088 | static struct clk_regmap g12a_vclk2_div6_en = { | |
2089 | .data = &(struct clk_regmap_gate_data){ | |
2090 | .offset = HHI_VIID_CLK_CNTL, | |
2091 | .bit_idx = 3, | |
2092 | }, | |
2093 | .hw.init = &(struct clk_init_data) { | |
2094 | .name = "vclk2_div6_en", | |
2095 | .ops = &clk_regmap_gate_ops, | |
2096 | .parent_names = (const char *[]){ "vclk2" }, | |
2097 | .num_parents = 1, | |
2098 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2099 | }, | |
2100 | }; | |
2101 | ||
2102 | static struct clk_regmap g12a_vclk2_div12_en = { | |
2103 | .data = &(struct clk_regmap_gate_data){ | |
2104 | .offset = HHI_VIID_CLK_CNTL, | |
2105 | .bit_idx = 4, | |
2106 | }, | |
2107 | .hw.init = &(struct clk_init_data) { | |
2108 | .name = "vclk2_div12_en", | |
2109 | .ops = &clk_regmap_gate_ops, | |
2110 | .parent_names = (const char *[]){ "vclk2" }, | |
2111 | .num_parents = 1, | |
2112 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2113 | }, | |
2114 | }; | |
2115 | ||
2116 | static struct clk_fixed_factor g12a_vclk_div2 = { | |
2117 | .mult = 1, | |
2118 | .div = 2, | |
2119 | .hw.init = &(struct clk_init_data){ | |
2120 | .name = "vclk_div2", | |
2121 | .ops = &clk_fixed_factor_ops, | |
2122 | .parent_names = (const char *[]){ "vclk_div2_en" }, | |
2123 | .num_parents = 1, | |
2124 | }, | |
2125 | }; | |
2126 | ||
2127 | static struct clk_fixed_factor g12a_vclk_div4 = { | |
2128 | .mult = 1, | |
2129 | .div = 4, | |
2130 | .hw.init = &(struct clk_init_data){ | |
2131 | .name = "vclk_div4", | |
2132 | .ops = &clk_fixed_factor_ops, | |
2133 | .parent_names = (const char *[]){ "vclk_div4_en" }, | |
2134 | .num_parents = 1, | |
2135 | }, | |
2136 | }; | |
2137 | ||
2138 | static struct clk_fixed_factor g12a_vclk_div6 = { | |
2139 | .mult = 1, | |
2140 | .div = 6, | |
2141 | .hw.init = &(struct clk_init_data){ | |
2142 | .name = "vclk_div6", | |
2143 | .ops = &clk_fixed_factor_ops, | |
2144 | .parent_names = (const char *[]){ "vclk_div6_en" }, | |
2145 | .num_parents = 1, | |
2146 | }, | |
2147 | }; | |
2148 | ||
2149 | static struct clk_fixed_factor g12a_vclk_div12 = { | |
2150 | .mult = 1, | |
2151 | .div = 12, | |
2152 | .hw.init = &(struct clk_init_data){ | |
2153 | .name = "vclk_div12", | |
2154 | .ops = &clk_fixed_factor_ops, | |
2155 | .parent_names = (const char *[]){ "vclk_div12_en" }, | |
2156 | .num_parents = 1, | |
2157 | }, | |
2158 | }; | |
2159 | ||
2160 | static struct clk_fixed_factor g12a_vclk2_div2 = { | |
2161 | .mult = 1, | |
2162 | .div = 2, | |
2163 | .hw.init = &(struct clk_init_data){ | |
2164 | .name = "vclk2_div2", | |
2165 | .ops = &clk_fixed_factor_ops, | |
2166 | .parent_names = (const char *[]){ "vclk2_div2_en" }, | |
2167 | .num_parents = 1, | |
2168 | }, | |
2169 | }; | |
2170 | ||
2171 | static struct clk_fixed_factor g12a_vclk2_div4 = { | |
2172 | .mult = 1, | |
2173 | .div = 4, | |
2174 | .hw.init = &(struct clk_init_data){ | |
2175 | .name = "vclk2_div4", | |
2176 | .ops = &clk_fixed_factor_ops, | |
2177 | .parent_names = (const char *[]){ "vclk2_div4_en" }, | |
2178 | .num_parents = 1, | |
2179 | }, | |
2180 | }; | |
2181 | ||
2182 | static struct clk_fixed_factor g12a_vclk2_div6 = { | |
2183 | .mult = 1, | |
2184 | .div = 6, | |
2185 | .hw.init = &(struct clk_init_data){ | |
2186 | .name = "vclk2_div6", | |
2187 | .ops = &clk_fixed_factor_ops, | |
2188 | .parent_names = (const char *[]){ "vclk2_div6_en" }, | |
2189 | .num_parents = 1, | |
2190 | }, | |
2191 | }; | |
2192 | ||
2193 | static struct clk_fixed_factor g12a_vclk2_div12 = { | |
2194 | .mult = 1, | |
2195 | .div = 12, | |
2196 | .hw.init = &(struct clk_init_data){ | |
2197 | .name = "vclk2_div12", | |
2198 | .ops = &clk_fixed_factor_ops, | |
2199 | .parent_names = (const char *[]){ "vclk2_div12_en" }, | |
2200 | .num_parents = 1, | |
2201 | }, | |
2202 | }; | |
2203 | ||
2204 | static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; | |
2205 | static const char * const g12a_cts_parent_names[] = { | |
2206 | "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", | |
2207 | "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", | |
2208 | "vclk2_div6", "vclk2_div12" | |
2209 | }; | |
2210 | ||
2211 | static struct clk_regmap g12a_cts_enci_sel = { | |
2212 | .data = &(struct clk_regmap_mux_data){ | |
2213 | .offset = HHI_VID_CLK_DIV, | |
2214 | .mask = 0xf, | |
2215 | .shift = 28, | |
2216 | .table = mux_table_cts_sel, | |
2217 | }, | |
2218 | .hw.init = &(struct clk_init_data){ | |
2219 | .name = "cts_enci_sel", | |
2220 | .ops = &clk_regmap_mux_ops, | |
2221 | .parent_names = g12a_cts_parent_names, | |
2222 | .num_parents = ARRAY_SIZE(g12a_cts_parent_names), | |
2223 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
2224 | }, | |
2225 | }; | |
2226 | ||
2227 | static struct clk_regmap g12a_cts_encp_sel = { | |
2228 | .data = &(struct clk_regmap_mux_data){ | |
2229 | .offset = HHI_VID_CLK_DIV, | |
2230 | .mask = 0xf, | |
2231 | .shift = 20, | |
2232 | .table = mux_table_cts_sel, | |
2233 | }, | |
2234 | .hw.init = &(struct clk_init_data){ | |
2235 | .name = "cts_encp_sel", | |
2236 | .ops = &clk_regmap_mux_ops, | |
2237 | .parent_names = g12a_cts_parent_names, | |
2238 | .num_parents = ARRAY_SIZE(g12a_cts_parent_names), | |
2239 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
2240 | }, | |
2241 | }; | |
2242 | ||
2243 | static struct clk_regmap g12a_cts_vdac_sel = { | |
2244 | .data = &(struct clk_regmap_mux_data){ | |
2245 | .offset = HHI_VIID_CLK_DIV, | |
2246 | .mask = 0xf, | |
2247 | .shift = 28, | |
2248 | .table = mux_table_cts_sel, | |
2249 | }, | |
2250 | .hw.init = &(struct clk_init_data){ | |
2251 | .name = "cts_vdac_sel", | |
2252 | .ops = &clk_regmap_mux_ops, | |
2253 | .parent_names = g12a_cts_parent_names, | |
2254 | .num_parents = ARRAY_SIZE(g12a_cts_parent_names), | |
2255 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
2256 | }, | |
2257 | }; | |
2258 | ||
2259 | /* TOFIX: add support for cts_tcon */ | |
2260 | static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; | |
2261 | static const char * const g12a_cts_hdmi_tx_parent_names[] = { | |
2262 | "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", | |
2263 | "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", | |
2264 | "vclk2_div6", "vclk2_div12" | |
2265 | }; | |
2266 | ||
2267 | static struct clk_regmap g12a_hdmi_tx_sel = { | |
2268 | .data = &(struct clk_regmap_mux_data){ | |
2269 | .offset = HHI_HDMI_CLK_CNTL, | |
2270 | .mask = 0xf, | |
2271 | .shift = 16, | |
2272 | .table = mux_table_hdmi_tx_sel, | |
2273 | }, | |
2274 | .hw.init = &(struct clk_init_data){ | |
2275 | .name = "hdmi_tx_sel", | |
2276 | .ops = &clk_regmap_mux_ops, | |
2277 | .parent_names = g12a_cts_hdmi_tx_parent_names, | |
2278 | .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names), | |
2279 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
2280 | }, | |
2281 | }; | |
2282 | ||
2283 | static struct clk_regmap g12a_cts_enci = { | |
2284 | .data = &(struct clk_regmap_gate_data){ | |
2285 | .offset = HHI_VID_CLK_CNTL2, | |
2286 | .bit_idx = 0, | |
2287 | }, | |
2288 | .hw.init = &(struct clk_init_data) { | |
2289 | .name = "cts_enci", | |
2290 | .ops = &clk_regmap_gate_ops, | |
2291 | .parent_names = (const char *[]){ "cts_enci_sel" }, | |
2292 | .num_parents = 1, | |
2293 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2294 | }, | |
2295 | }; | |
2296 | ||
2297 | static struct clk_regmap g12a_cts_encp = { | |
2298 | .data = &(struct clk_regmap_gate_data){ | |
2299 | .offset = HHI_VID_CLK_CNTL2, | |
2300 | .bit_idx = 2, | |
2301 | }, | |
2302 | .hw.init = &(struct clk_init_data) { | |
2303 | .name = "cts_encp", | |
2304 | .ops = &clk_regmap_gate_ops, | |
2305 | .parent_names = (const char *[]){ "cts_encp_sel" }, | |
2306 | .num_parents = 1, | |
2307 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2308 | }, | |
2309 | }; | |
2310 | ||
2311 | static struct clk_regmap g12a_cts_vdac = { | |
2312 | .data = &(struct clk_regmap_gate_data){ | |
2313 | .offset = HHI_VID_CLK_CNTL2, | |
2314 | .bit_idx = 4, | |
2315 | }, | |
2316 | .hw.init = &(struct clk_init_data) { | |
2317 | .name = "cts_vdac", | |
2318 | .ops = &clk_regmap_gate_ops, | |
2319 | .parent_names = (const char *[]){ "cts_vdac_sel" }, | |
2320 | .num_parents = 1, | |
2321 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2322 | }, | |
2323 | }; | |
2324 | ||
2325 | static struct clk_regmap g12a_hdmi_tx = { | |
2326 | .data = &(struct clk_regmap_gate_data){ | |
2327 | .offset = HHI_VID_CLK_CNTL2, | |
2328 | .bit_idx = 5, | |
2329 | }, | |
2330 | .hw.init = &(struct clk_init_data) { | |
2331 | .name = "hdmi_tx", | |
2332 | .ops = &clk_regmap_gate_ops, | |
2333 | .parent_names = (const char *[]){ "hdmi_tx_sel" }, | |
2334 | .num_parents = 1, | |
2335 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2336 | }, | |
2337 | }; | |
2338 | ||
2339 | /* HDMI Clocks */ | |
2340 | ||
2341 | static const char * const g12a_hdmi_parent_names[] = { | |
2342 | IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" | |
2343 | }; | |
2344 | ||
2345 | static struct clk_regmap g12a_hdmi_sel = { | |
2346 | .data = &(struct clk_regmap_mux_data){ | |
2347 | .offset = HHI_HDMI_CLK_CNTL, | |
2348 | .mask = 0x3, | |
2349 | .shift = 9, | |
2350 | .flags = CLK_MUX_ROUND_CLOSEST, | |
2351 | }, | |
2352 | .hw.init = &(struct clk_init_data){ | |
2353 | .name = "hdmi_sel", | |
2354 | .ops = &clk_regmap_mux_ops, | |
2355 | .parent_names = g12a_hdmi_parent_names, | |
2356 | .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names), | |
2357 | .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, | |
2358 | }, | |
2359 | }; | |
2360 | ||
2361 | static struct clk_regmap g12a_hdmi_div = { | |
2362 | .data = &(struct clk_regmap_div_data){ | |
2363 | .offset = HHI_HDMI_CLK_CNTL, | |
2364 | .shift = 0, | |
2365 | .width = 7, | |
2366 | }, | |
2367 | .hw.init = &(struct clk_init_data){ | |
2368 | .name = "hdmi_div", | |
2369 | .ops = &clk_regmap_divider_ops, | |
2370 | .parent_names = (const char *[]){ "hdmi_sel" }, | |
2371 | .num_parents = 1, | |
2372 | .flags = CLK_GET_RATE_NOCACHE, | |
2373 | }, | |
2374 | }; | |
2375 | ||
2376 | static struct clk_regmap g12a_hdmi = { | |
2377 | .data = &(struct clk_regmap_gate_data){ | |
2378 | .offset = HHI_HDMI_CLK_CNTL, | |
2379 | .bit_idx = 8, | |
2380 | }, | |
2381 | .hw.init = &(struct clk_init_data) { | |
2382 | .name = "hdmi", | |
2383 | .ops = &clk_regmap_gate_ops, | |
2384 | .parent_names = (const char *[]){ "hdmi_div" }, | |
2385 | .num_parents = 1, | |
2386 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2387 | }, | |
2388 | }; | |
2389 | ||
2390 | /* | |
2391 | * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) | |
2392 | * muxed by a glitch-free switch. | |
2393 | */ | |
2394 | ||
2395 | static const char * const g12a_mali_0_1_parent_names[] = { | |
2396 | IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5", | |
2397 | "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7" | |
2398 | }; | |
2399 | ||
2400 | static struct clk_regmap g12a_mali_0_sel = { | |
2401 | .data = &(struct clk_regmap_mux_data){ | |
2402 | .offset = HHI_MALI_CLK_CNTL, | |
2403 | .mask = 0x7, | |
2404 | .shift = 9, | |
2405 | }, | |
2406 | .hw.init = &(struct clk_init_data){ | |
2407 | .name = "mali_0_sel", | |
2408 | .ops = &clk_regmap_mux_ops, | |
2409 | .parent_names = g12a_mali_0_1_parent_names, | |
2410 | .num_parents = 8, | |
2411 | .flags = CLK_SET_RATE_NO_REPARENT, | |
2412 | }, | |
2413 | }; | |
2414 | ||
2415 | static struct clk_regmap g12a_mali_0_div = { | |
2416 | .data = &(struct clk_regmap_div_data){ | |
2417 | .offset = HHI_MALI_CLK_CNTL, | |
2418 | .shift = 0, | |
2419 | .width = 7, | |
2420 | }, | |
2421 | .hw.init = &(struct clk_init_data){ | |
2422 | .name = "mali_0_div", | |
2423 | .ops = &clk_regmap_divider_ops, | |
2424 | .parent_names = (const char *[]){ "mali_0_sel" }, | |
2425 | .num_parents = 1, | |
2426 | .flags = CLK_SET_RATE_NO_REPARENT, | |
2427 | }, | |
2428 | }; | |
2429 | ||
2430 | static struct clk_regmap g12a_mali_0 = { | |
2431 | .data = &(struct clk_regmap_gate_data){ | |
2432 | .offset = HHI_MALI_CLK_CNTL, | |
2433 | .bit_idx = 8, | |
2434 | }, | |
2435 | .hw.init = &(struct clk_init_data){ | |
2436 | .name = "mali_0", | |
2437 | .ops = &clk_regmap_gate_ops, | |
2438 | .parent_names = (const char *[]){ "mali_0_div" }, | |
2439 | .num_parents = 1, | |
2440 | .flags = CLK_SET_RATE_PARENT, | |
2441 | }, | |
2442 | }; | |
2443 | ||
2444 | static struct clk_regmap g12a_mali_1_sel = { | |
2445 | .data = &(struct clk_regmap_mux_data){ | |
2446 | .offset = HHI_MALI_CLK_CNTL, | |
2447 | .mask = 0x7, | |
2448 | .shift = 25, | |
2449 | }, | |
2450 | .hw.init = &(struct clk_init_data){ | |
2451 | .name = "mali_1_sel", | |
2452 | .ops = &clk_regmap_mux_ops, | |
2453 | .parent_names = g12a_mali_0_1_parent_names, | |
2454 | .num_parents = 8, | |
2455 | .flags = CLK_SET_RATE_NO_REPARENT, | |
2456 | }, | |
2457 | }; | |
2458 | ||
2459 | static struct clk_regmap g12a_mali_1_div = { | |
2460 | .data = &(struct clk_regmap_div_data){ | |
2461 | .offset = HHI_MALI_CLK_CNTL, | |
2462 | .shift = 16, | |
2463 | .width = 7, | |
2464 | }, | |
2465 | .hw.init = &(struct clk_init_data){ | |
2466 | .name = "mali_1_div", | |
2467 | .ops = &clk_regmap_divider_ops, | |
2468 | .parent_names = (const char *[]){ "mali_1_sel" }, | |
2469 | .num_parents = 1, | |
2470 | .flags = CLK_SET_RATE_NO_REPARENT, | |
2471 | }, | |
2472 | }; | |
2473 | ||
2474 | static struct clk_regmap g12a_mali_1 = { | |
2475 | .data = &(struct clk_regmap_gate_data){ | |
2476 | .offset = HHI_MALI_CLK_CNTL, | |
2477 | .bit_idx = 24, | |
2478 | }, | |
2479 | .hw.init = &(struct clk_init_data){ | |
2480 | .name = "mali_1", | |
2481 | .ops = &clk_regmap_gate_ops, | |
2482 | .parent_names = (const char *[]){ "mali_1_div" }, | |
2483 | .num_parents = 1, | |
2484 | .flags = CLK_SET_RATE_PARENT, | |
2485 | }, | |
2486 | }; | |
2487 | ||
2488 | static const char * const g12a_mali_parent_names[] = { | |
2489 | "mali_0", "mali_1" | |
2490 | }; | |
2491 | ||
2492 | static struct clk_regmap g12a_mali = { | |
2493 | .data = &(struct clk_regmap_mux_data){ | |
2494 | .offset = HHI_MALI_CLK_CNTL, | |
2495 | .mask = 1, | |
2496 | .shift = 31, | |
2497 | }, | |
2498 | .hw.init = &(struct clk_init_data){ | |
2499 | .name = "mali", | |
2500 | .ops = &clk_regmap_mux_ops, | |
2501 | .parent_names = g12a_mali_parent_names, | |
2502 | .num_parents = 2, | |
2503 | .flags = CLK_SET_RATE_NO_REPARENT, | |
2504 | }, | |
2505 | }; | |
2506 | ||
ad517d52 GLR |
2507 | static struct clk_regmap g12a_ts_div = { |
2508 | .data = &(struct clk_regmap_div_data){ | |
2509 | .offset = HHI_TS_CLK_CNTL, | |
2510 | .shift = 0, | |
2511 | .width = 8, | |
2512 | }, | |
2513 | .hw.init = &(struct clk_init_data){ | |
2514 | .name = "ts_div", | |
2515 | .ops = &clk_regmap_divider_ro_ops, | |
2516 | .parent_names = (const char *[]){ "xtal" }, | |
2517 | .num_parents = 1, | |
2518 | }, | |
2519 | }; | |
2520 | ||
2521 | static struct clk_regmap g12a_ts = { | |
2522 | .data = &(struct clk_regmap_gate_data){ | |
2523 | .offset = HHI_TS_CLK_CNTL, | |
2524 | .bit_idx = 8, | |
2525 | }, | |
2526 | .hw.init = &(struct clk_init_data){ | |
2527 | .name = "ts", | |
2528 | .ops = &clk_regmap_gate_ops, | |
2529 | .parent_names = (const char *[]){ "ts_div" }, | |
2530 | .num_parents = 1, | |
2531 | }, | |
2532 | }; | |
2533 | ||
085a4ea9 JH |
2534 | /* Everything Else (EE) domain gates */ |
2535 | static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); | |
2536 | static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); | |
2537 | static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2); | |
2538 | static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); | |
2539 | static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4); | |
2540 | static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5); | |
2541 | static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6); | |
2542 | static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7); | |
2543 | static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8); | |
2544 | static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9); | |
2545 | static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10); | |
2546 | static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11); | |
2547 | static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12); | |
2548 | static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13); | |
2549 | static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14); | |
2550 | static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); | |
2551 | static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); | |
2552 | static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23); | |
2553 | static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4); | |
2554 | static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25); | |
2555 | static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26); | |
2556 | static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28); | |
2557 | ||
2558 | static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0); | |
2559 | static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3); | |
2560 | static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4); | |
2561 | static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); | |
2562 | static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13); | |
2563 | static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16); | |
2564 | static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20); | |
2565 | static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23); | |
2566 | static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); | |
2567 | static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25); | |
2568 | static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26); | |
2569 | static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); | |
2570 | static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); | |
2571 | ||
2572 | static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); | |
2573 | static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); | |
2574 | static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); | |
2575 | static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); | |
2576 | static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6); | |
2577 | static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); | |
2578 | static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); | |
2579 | static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); | |
2580 | static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); | |
2581 | static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); | |
2582 | ||
2583 | static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); | |
2584 | static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); | |
2585 | static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); | |
2586 | static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); | |
2587 | static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); | |
2588 | static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); | |
2589 | static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7); | |
2590 | static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); | |
2591 | static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); | |
2592 | static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10); | |
2593 | static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); | |
2594 | static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16); | |
2595 | static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20); | |
2596 | static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21); | |
2597 | static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); | |
2598 | static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); | |
2599 | static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); | |
2600 | static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); | |
2601 | static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); | |
2602 | ||
2603 | static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0); | |
2604 | static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); | |
2605 | static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); | |
2606 | static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); | |
2607 | static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); | |
2608 | ||
2609 | /* Array of all clocks provided by this provider */ | |
2610 | static struct clk_hw_onecell_data g12a_hw_onecell_data = { | |
2611 | .hws = { | |
2612 | [CLKID_SYS_PLL] = &g12a_sys_pll.hw, | |
2613 | [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, | |
2614 | [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, | |
2615 | [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, | |
2616 | [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, | |
2617 | [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, | |
2618 | [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, | |
2619 | [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, | |
2620 | [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, | |
2621 | [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, | |
2622 | [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, | |
2623 | [CLKID_CLK81] = &g12a_clk81.hw, | |
2624 | [CLKID_MPLL0] = &g12a_mpll0.hw, | |
2625 | [CLKID_MPLL1] = &g12a_mpll1.hw, | |
2626 | [CLKID_MPLL2] = &g12a_mpll2.hw, | |
2627 | [CLKID_MPLL3] = &g12a_mpll3.hw, | |
2628 | [CLKID_DDR] = &g12a_ddr.hw, | |
2629 | [CLKID_DOS] = &g12a_dos.hw, | |
2630 | [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, | |
2631 | [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, | |
2632 | [CLKID_ETH_PHY] = &g12a_eth_phy.hw, | |
2633 | [CLKID_ISA] = &g12a_isa.hw, | |
2634 | [CLKID_PL301] = &g12a_pl301.hw, | |
2635 | [CLKID_PERIPHS] = &g12a_periphs.hw, | |
2636 | [CLKID_SPICC0] = &g12a_spicc_0.hw, | |
2637 | [CLKID_I2C] = &g12a_i2c.hw, | |
2638 | [CLKID_SANA] = &g12a_sana.hw, | |
2639 | [CLKID_SD] = &g12a_sd.hw, | |
2640 | [CLKID_RNG0] = &g12a_rng0.hw, | |
2641 | [CLKID_UART0] = &g12a_uart0.hw, | |
2642 | [CLKID_SPICC1] = &g12a_spicc_1.hw, | |
2643 | [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, | |
2644 | [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, | |
2645 | [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, | |
2646 | [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, | |
2647 | [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, | |
2648 | [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, | |
2649 | [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, | |
2650 | [CLKID_AUDIO] = &g12a_audio.hw, | |
2651 | [CLKID_ETH] = &g12a_eth_core.hw, | |
2652 | [CLKID_DEMUX] = &g12a_demux.hw, | |
2653 | [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, | |
2654 | [CLKID_ADC] = &g12a_adc.hw, | |
2655 | [CLKID_UART1] = &g12a_uart1.hw, | |
2656 | [CLKID_G2D] = &g12a_g2d.hw, | |
2657 | [CLKID_RESET] = &g12a_reset.hw, | |
2658 | [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, | |
2659 | [CLKID_PARSER] = &g12a_parser.hw, | |
2660 | [CLKID_USB] = &g12a_usb_general.hw, | |
2661 | [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, | |
2662 | [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, | |
2663 | [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, | |
2664 | [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, | |
2665 | [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, | |
2666 | [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, | |
2667 | [CLKID_BT656] = &g12a_bt656.hw, | |
2668 | [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, | |
2669 | [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, | |
2670 | [CLKID_UART2] = &g12a_uart2.hw, | |
2671 | [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, | |
2672 | [CLKID_GIC] = &g12a_gic.hw, | |
2673 | [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, | |
2674 | [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, | |
2675 | [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, | |
2676 | [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, | |
2677 | [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, | |
2678 | [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, | |
2679 | [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, | |
2680 | [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, | |
2681 | [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, | |
2682 | [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, | |
2683 | [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, | |
2684 | [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, | |
2685 | [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, | |
2686 | [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, | |
2687 | [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, | |
2688 | [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, | |
2689 | [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, | |
2690 | [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, | |
2691 | [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, | |
2692 | [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, | |
2693 | [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, | |
2694 | [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, | |
2695 | [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, | |
2696 | [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, | |
2697 | [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, | |
2698 | [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, | |
2699 | [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, | |
2700 | [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, | |
2701 | [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, | |
2702 | [CLKID_DAC_CLK] = &g12a_dac_clk.hw, | |
2703 | [CLKID_AOCLK] = &g12a_aoclk_gate.hw, | |
2704 | [CLKID_IEC958] = &g12a_iec958_gate.hw, | |
2705 | [CLKID_ENC480P] = &g12a_enc480p.hw, | |
2706 | [CLKID_RNG1] = &g12a_rng1.hw, | |
2707 | [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, | |
2708 | [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, | |
2709 | [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, | |
2710 | [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, | |
2711 | [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, | |
2712 | [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, | |
2713 | [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, | |
2714 | [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, | |
2715 | [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, | |
2716 | [CLKID_DMA] = &g12a_dma.hw, | |
2717 | [CLKID_EFUSE] = &g12a_efuse.hw, | |
2718 | [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, | |
2719 | [CLKID_RESET_SEC] = &g12a_reset_sec.hw, | |
2720 | [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, | |
2721 | [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, | |
2722 | [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, | |
2723 | [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, | |
2724 | [CLKID_VPU_0] = &g12a_vpu_0.hw, | |
2725 | [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, | |
2726 | [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, | |
2727 | [CLKID_VPU_1] = &g12a_vpu_1.hw, | |
2728 | [CLKID_VPU] = &g12a_vpu.hw, | |
2729 | [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, | |
2730 | [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, | |
2731 | [CLKID_VAPB_0] = &g12a_vapb_0.hw, | |
2732 | [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, | |
2733 | [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, | |
2734 | [CLKID_VAPB_1] = &g12a_vapb_1.hw, | |
2735 | [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, | |
2736 | [CLKID_VAPB] = &g12a_vapb.hw, | |
2737 | [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, | |
2738 | [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, | |
2739 | [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, | |
2740 | [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, | |
2741 | [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, | |
2742 | [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, | |
2743 | [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, | |
2744 | [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, | |
2745 | [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, | |
2746 | [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, | |
2747 | [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, | |
2748 | [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, | |
2749 | [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, | |
2750 | [CLKID_VCLK] = &g12a_vclk.hw, | |
2751 | [CLKID_VCLK2] = &g12a_vclk2.hw, | |
2752 | [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, | |
2753 | [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, | |
2754 | [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, | |
2755 | [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, | |
2756 | [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, | |
2757 | [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, | |
2758 | [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, | |
2759 | [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, | |
2760 | [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, | |
2761 | [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, | |
2762 | [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, | |
2763 | [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, | |
2764 | [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, | |
2765 | [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, | |
2766 | [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, | |
2767 | [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, | |
2768 | [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, | |
2769 | [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, | |
2770 | [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, | |
2771 | [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, | |
2772 | [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, | |
2773 | [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, | |
2774 | [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, | |
2775 | [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, | |
2776 | [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, | |
2777 | [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, | |
2778 | [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, | |
2779 | [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, | |
2780 | [CLKID_HDMI] = &g12a_hdmi.hw, | |
2781 | [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, | |
2782 | [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, | |
2783 | [CLKID_MALI_0] = &g12a_mali_0.hw, | |
2784 | [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, | |
2785 | [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, | |
2786 | [CLKID_MALI_1] = &g12a_mali_1.hw, | |
2787 | [CLKID_MALI] = &g12a_mali.hw, | |
e63b063e JB |
2788 | [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, |
2789 | [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, | |
370294e2 NA |
2790 | [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, |
2791 | [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, | |
2792 | [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, | |
2793 | [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, | |
2794 | [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, | |
2795 | [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, | |
2796 | [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, | |
2797 | [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, | |
2798 | [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, | |
2799 | [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, | |
2800 | [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, | |
2801 | [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, | |
2802 | [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, | |
2803 | [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, | |
2804 | [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, | |
2805 | [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, | |
2806 | [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, | |
2807 | [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, | |
2808 | [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, | |
2809 | [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, | |
34775209 NA |
2810 | [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, |
2811 | [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, | |
2812 | [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, | |
2813 | [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, | |
4b0f7305 MJ |
2814 | [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, |
2815 | [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, | |
2816 | [CLKID_VDEC_1] = &g12a_vdec_1.hw, | |
2817 | [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, | |
2818 | [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, | |
2819 | [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, | |
2820 | [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, | |
2821 | [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, | |
2822 | [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, | |
ad517d52 GLR |
2823 | [CLKID_TS_DIV] = &g12a_ts_div.hw, |
2824 | [CLKID_TS] = &g12a_ts.hw, | |
085a4ea9 JH |
2825 | [NR_CLKS] = NULL, |
2826 | }, | |
2827 | .num = NR_CLKS, | |
2828 | }; | |
2829 | ||
2830 | /* Convenience table to populate regmap in .probe */ | |
2831 | static struct clk_regmap *const g12a_clk_regmaps[] = { | |
2832 | &g12a_clk81, | |
2833 | &g12a_dos, | |
2834 | &g12a_ddr, | |
2835 | &g12a_audio_locker, | |
2836 | &g12a_mipi_dsi_host, | |
2837 | &g12a_eth_phy, | |
2838 | &g12a_isa, | |
2839 | &g12a_pl301, | |
2840 | &g12a_periphs, | |
2841 | &g12a_spicc_0, | |
2842 | &g12a_i2c, | |
2843 | &g12a_sana, | |
2844 | &g12a_sd, | |
2845 | &g12a_rng0, | |
2846 | &g12a_uart0, | |
2847 | &g12a_spicc_1, | |
2848 | &g12a_hiu_reg, | |
2849 | &g12a_mipi_dsi_phy, | |
2850 | &g12a_assist_misc, | |
2851 | &g12a_emmc_a, | |
2852 | &g12a_emmc_b, | |
2853 | &g12a_emmc_c, | |
2854 | &g12a_audio_codec, | |
2855 | &g12a_audio, | |
2856 | &g12a_eth_core, | |
2857 | &g12a_demux, | |
2858 | &g12a_audio_ififo, | |
2859 | &g12a_adc, | |
2860 | &g12a_uart1, | |
2861 | &g12a_g2d, | |
2862 | &g12a_reset, | |
2863 | &g12a_pcie_comb, | |
2864 | &g12a_parser, | |
2865 | &g12a_usb_general, | |
2866 | &g12a_pcie_phy, | |
2867 | &g12a_ahb_arb0, | |
2868 | &g12a_ahb_data_bus, | |
2869 | &g12a_ahb_ctrl_bus, | |
2870 | &g12a_htx_hdcp22, | |
2871 | &g12a_htx_pclk, | |
2872 | &g12a_bt656, | |
2873 | &g12a_usb1_to_ddr, | |
2874 | &g12a_mmc_pclk, | |
2875 | &g12a_vpu_intr, | |
2876 | &g12a_gic, | |
2877 | &g12a_sd_emmc_a_clk0, | |
2878 | &g12a_sd_emmc_b_clk0, | |
2879 | &g12a_sd_emmc_c_clk0, | |
2880 | &g12a_mpeg_clk_div, | |
2881 | &g12a_sd_emmc_a_clk0_div, | |
2882 | &g12a_sd_emmc_b_clk0_div, | |
2883 | &g12a_sd_emmc_c_clk0_div, | |
2884 | &g12a_mpeg_clk_sel, | |
2885 | &g12a_sd_emmc_a_clk0_sel, | |
2886 | &g12a_sd_emmc_b_clk0_sel, | |
2887 | &g12a_sd_emmc_c_clk0_sel, | |
2888 | &g12a_mpll0, | |
2889 | &g12a_mpll1, | |
2890 | &g12a_mpll2, | |
2891 | &g12a_mpll3, | |
2892 | &g12a_mpll0_div, | |
2893 | &g12a_mpll1_div, | |
2894 | &g12a_mpll2_div, | |
2895 | &g12a_mpll3_div, | |
2896 | &g12a_fixed_pll, | |
2897 | &g12a_sys_pll, | |
2898 | &g12a_gp0_pll, | |
2899 | &g12a_hifi_pll, | |
2900 | &g12a_vclk2_venci0, | |
2901 | &g12a_vclk2_venci1, | |
2902 | &g12a_vclk2_vencp0, | |
2903 | &g12a_vclk2_vencp1, | |
2904 | &g12a_vclk2_venct0, | |
2905 | &g12a_vclk2_venct1, | |
2906 | &g12a_vclk2_other, | |
2907 | &g12a_vclk2_enci, | |
2908 | &g12a_vclk2_encp, | |
2909 | &g12a_dac_clk, | |
2910 | &g12a_aoclk_gate, | |
2911 | &g12a_iec958_gate, | |
2912 | &g12a_enc480p, | |
2913 | &g12a_rng1, | |
2914 | &g12a_vclk2_enct, | |
2915 | &g12a_vclk2_encl, | |
2916 | &g12a_vclk2_venclmmc, | |
2917 | &g12a_vclk2_vencl, | |
2918 | &g12a_vclk2_other1, | |
2919 | &g12a_fixed_pll_dco, | |
2920 | &g12a_sys_pll_dco, | |
2921 | &g12a_gp0_pll_dco, | |
2922 | &g12a_hifi_pll_dco, | |
2923 | &g12a_fclk_div2, | |
2924 | &g12a_fclk_div3, | |
2925 | &g12a_fclk_div4, | |
2926 | &g12a_fclk_div5, | |
2927 | &g12a_fclk_div7, | |
2928 | &g12a_fclk_div2p5, | |
2929 | &g12a_dma, | |
2930 | &g12a_efuse, | |
2931 | &g12a_rom_boot, | |
2932 | &g12a_reset_sec, | |
2933 | &g12a_sec_ahb_apb3, | |
2934 | &g12a_vpu_0_sel, | |
2935 | &g12a_vpu_0_div, | |
2936 | &g12a_vpu_0, | |
2937 | &g12a_vpu_1_sel, | |
2938 | &g12a_vpu_1_div, | |
2939 | &g12a_vpu_1, | |
2940 | &g12a_vpu, | |
2941 | &g12a_vapb_0_sel, | |
2942 | &g12a_vapb_0_div, | |
2943 | &g12a_vapb_0, | |
2944 | &g12a_vapb_1_sel, | |
2945 | &g12a_vapb_1_div, | |
2946 | &g12a_vapb_1, | |
2947 | &g12a_vapb_sel, | |
2948 | &g12a_vapb, | |
2949 | &g12a_hdmi_pll_dco, | |
2950 | &g12a_hdmi_pll_od, | |
2951 | &g12a_hdmi_pll_od2, | |
2952 | &g12a_hdmi_pll, | |
2953 | &g12a_vid_pll_div, | |
2954 | &g12a_vid_pll_sel, | |
2955 | &g12a_vid_pll, | |
2956 | &g12a_vclk_sel, | |
2957 | &g12a_vclk2_sel, | |
2958 | &g12a_vclk_input, | |
2959 | &g12a_vclk2_input, | |
2960 | &g12a_vclk_div, | |
2961 | &g12a_vclk2_div, | |
2962 | &g12a_vclk, | |
2963 | &g12a_vclk2, | |
2964 | &g12a_vclk_div1, | |
2965 | &g12a_vclk_div2_en, | |
2966 | &g12a_vclk_div4_en, | |
2967 | &g12a_vclk_div6_en, | |
2968 | &g12a_vclk_div12_en, | |
2969 | &g12a_vclk2_div1, | |
2970 | &g12a_vclk2_div2_en, | |
2971 | &g12a_vclk2_div4_en, | |
2972 | &g12a_vclk2_div6_en, | |
2973 | &g12a_vclk2_div12_en, | |
2974 | &g12a_cts_enci_sel, | |
2975 | &g12a_cts_encp_sel, | |
2976 | &g12a_cts_vdac_sel, | |
2977 | &g12a_hdmi_tx_sel, | |
2978 | &g12a_cts_enci, | |
2979 | &g12a_cts_encp, | |
2980 | &g12a_cts_vdac, | |
2981 | &g12a_hdmi_tx, | |
2982 | &g12a_hdmi_sel, | |
2983 | &g12a_hdmi_div, | |
2984 | &g12a_hdmi, | |
2985 | &g12a_mali_0_sel, | |
2986 | &g12a_mali_0_div, | |
2987 | &g12a_mali_0, | |
2988 | &g12a_mali_1_sel, | |
2989 | &g12a_mali_1_div, | |
2990 | &g12a_mali_1, | |
2991 | &g12a_mali, | |
2992 | &g12a_mpll_50m, | |
370294e2 NA |
2993 | &g12a_sys_pll_div16_en, |
2994 | &g12a_cpu_clk_premux0, | |
2995 | &g12a_cpu_clk_mux0_div, | |
2996 | &g12a_cpu_clk_postmux0, | |
2997 | &g12a_cpu_clk_premux1, | |
2998 | &g12a_cpu_clk_mux1_div, | |
2999 | &g12a_cpu_clk_postmux1, | |
3000 | &g12a_cpu_clk_dyn, | |
3001 | &g12a_cpu_clk, | |
3002 | &g12a_cpu_clk_div16_en, | |
3003 | &g12a_cpu_clk_apb_div, | |
3004 | &g12a_cpu_clk_apb, | |
3005 | &g12a_cpu_clk_atb_div, | |
3006 | &g12a_cpu_clk_atb, | |
3007 | &g12a_cpu_clk_axi_div, | |
3008 | &g12a_cpu_clk_axi, | |
3009 | &g12a_cpu_clk_trace_div, | |
3010 | &g12a_cpu_clk_trace, | |
34775209 NA |
3011 | &g12a_pcie_pll_od, |
3012 | &g12a_pcie_pll_dco, | |
4b0f7305 MJ |
3013 | &g12a_vdec_1_sel, |
3014 | &g12a_vdec_1_div, | |
3015 | &g12a_vdec_1, | |
3016 | &g12a_vdec_hevc_sel, | |
3017 | &g12a_vdec_hevc_div, | |
3018 | &g12a_vdec_hevc, | |
3019 | &g12a_vdec_hevcf_sel, | |
3020 | &g12a_vdec_hevcf_div, | |
3021 | &g12a_vdec_hevcf, | |
ad517d52 GLR |
3022 | &g12a_ts_div, |
3023 | &g12a_ts, | |
085a4ea9 JH |
3024 | }; |
3025 | ||
a9f7b199 JB |
3026 | static const struct reg_sequence g12a_init_regs[] = { |
3027 | { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, | |
3028 | }; | |
3029 | ||
6682bd4d JB |
3030 | static const struct meson_eeclkc_data g12a_clkc_data = { |
3031 | .regmap_clks = g12a_clk_regmaps, | |
3032 | .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), | |
a9f7b199 JB |
3033 | .hw_onecell_data = &g12a_hw_onecell_data, |
3034 | .init_regs = g12a_init_regs, | |
3035 | .init_count = ARRAY_SIZE(g12a_init_regs), | |
6682bd4d JB |
3036 | }; |
3037 | ||
085a4ea9 | 3038 | static const struct of_device_id clkc_match_table[] = { |
6682bd4d | 3039 | { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data }, |
085a4ea9 JH |
3040 | {} |
3041 | }; | |
3042 | ||
085a4ea9 | 3043 | static struct platform_driver g12a_driver = { |
6682bd4d | 3044 | .probe = meson_eeclkc_probe, |
085a4ea9 JH |
3045 | .driver = { |
3046 | .name = "g12a-clkc", | |
3047 | .of_match_table = clkc_match_table, | |
3048 | }, | |
3049 | }; | |
3050 | ||
3051 | builtin_platform_driver(g12a_driver); |