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clk: meson: poke pll CNTL last
[linux-2.6-block.git] / drivers / clk / meson / axg.c
CommitLineData
78b4af31
QD		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * AmLogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
161f6e5b 14#include <linux/init.h>
78b4af31
QD		 15#include <linux/of_address.h>
16#include <linux/of_device.h>
4162dd5b 17#include <linux/mfd/syscon.h>
78b4af31 18#include <linux/platform_device.h>
161f6e5b 19#include <linux/regmap.h>
78b4af31
QD		 20
21#include "clkc.h"
22#include "axg.h"
23
24static DEFINE_SPINLOCK(meson_clk_lock);
25
722825dc
JB		 26static struct clk_regmap axg_fixed_pll = {
27 .data = &(struct meson_clk_pll_data){
28 .m = {
29 .reg_off = HHI_MPLL_CNTL,
30 .shift = 0,
31 .width = 9,
32 },
33 .n = {
34 .reg_off = HHI_MPLL_CNTL,
35 .shift = 9,
36 .width = 5,
37 },
38 .od = {
39 .reg_off = HHI_MPLL_CNTL,
40 .shift = 16,
41 .width = 2,
42 },
43 .frac = {
44 .reg_off = HHI_MPLL_CNTL2,
45 .shift = 0,
46 .width = 12,
47 },
48 .l = {
49 .reg_off = HHI_MPLL_CNTL,
50 .shift = 31,
51 .width = 1,
52 },
53 .rst = {
54 .reg_off = HHI_MPLL_CNTL,
55 .shift = 29,
56 .width = 1,
57 },
58 },
78b4af31
QD		 59 .hw.init = &(struct clk_init_data){
60 .name = "fixed_pll",
61 .ops = &meson_clk_pll_ro_ops,
62 .parent_names = (const char *[]){ "xtal" },
63 .num_parents = 1,
64 },
65};
66
722825dc
JB		 67static struct clk_regmap axg_sys_pll = {
68 .data = &(struct meson_clk_pll_data){
69 .m = {
70 .reg_off = HHI_SYS_PLL_CNTL,
71 .shift = 0,
72 .width = 9,
73 },
74 .n = {
75 .reg_off = HHI_SYS_PLL_CNTL,
76 .shift = 9,
77 .width = 5,
78 },
79 .od = {
80 .reg_off = HHI_SYS_PLL_CNTL,
81 .shift = 16,
82 .width = 2,
83 },
84 .l = {
85 .reg_off = HHI_SYS_PLL_CNTL,
86 .shift = 31,
87 .width = 1,
88 },
89 .rst = {
90 .reg_off = HHI_SYS_PLL_CNTL,
91 .shift = 29,
92 .width = 1,
93 },
78b4af31 94 },
78b4af31
QD		 95 .hw.init = &(struct clk_init_data){
96 .name = "sys_pll",
97 .ops = &meson_clk_pll_ro_ops,
98 .parent_names = (const char *[]){ "xtal" },
99 .num_parents = 1,
100 .flags = CLK_GET_RATE_NOCACHE,
101 },
102};
103
104static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
105 PLL_RATE(240000000, 40, 1, 2),
106 PLL_RATE(246000000, 41, 1, 2),
107 PLL_RATE(252000000, 42, 1, 2),
108 PLL_RATE(258000000, 43, 1, 2),
109 PLL_RATE(264000000, 44, 1, 2),
110 PLL_RATE(270000000, 45, 1, 2),
111 PLL_RATE(276000000, 46, 1, 2),
112 PLL_RATE(282000000, 47, 1, 2),
113 PLL_RATE(288000000, 48, 1, 2),
114 PLL_RATE(294000000, 49, 1, 2),
115 PLL_RATE(300000000, 50, 1, 2),
116 PLL_RATE(306000000, 51, 1, 2),
117 PLL_RATE(312000000, 52, 1, 2),
118 PLL_RATE(318000000, 53, 1, 2),
119 PLL_RATE(324000000, 54, 1, 2),
120 PLL_RATE(330000000, 55, 1, 2),
121 PLL_RATE(336000000, 56, 1, 2),
122 PLL_RATE(342000000, 57, 1, 2),
123 PLL_RATE(348000000, 58, 1, 2),
124 PLL_RATE(354000000, 59, 1, 2),
125 PLL_RATE(360000000, 60, 1, 2),
126 PLL_RATE(366000000, 61, 1, 2),
127 PLL_RATE(372000000, 62, 1, 2),
128 PLL_RATE(378000000, 63, 1, 2),
129 PLL_RATE(384000000, 64, 1, 2),
130 PLL_RATE(390000000, 65, 1, 3),
131 PLL_RATE(396000000, 66, 1, 3),
132 PLL_RATE(402000000, 67, 1, 3),
133 PLL_RATE(408000000, 68, 1, 3),
134 PLL_RATE(480000000, 40, 1, 1),
135 PLL_RATE(492000000, 41, 1, 1),
136 PLL_RATE(504000000, 42, 1, 1),
137 PLL_RATE(516000000, 43, 1, 1),
138 PLL_RATE(528000000, 44, 1, 1),
139 PLL_RATE(540000000, 45, 1, 1),
140 PLL_RATE(552000000, 46, 1, 1),
141 PLL_RATE(564000000, 47, 1, 1),
142 PLL_RATE(576000000, 48, 1, 1),
143 PLL_RATE(588000000, 49, 1, 1),
144 PLL_RATE(600000000, 50, 1, 1),
145 PLL_RATE(612000000, 51, 1, 1),
146 PLL_RATE(624000000, 52, 1, 1),
147 PLL_RATE(636000000, 53, 1, 1),
148 PLL_RATE(648000000, 54, 1, 1),
149 PLL_RATE(660000000, 55, 1, 1),
150 PLL_RATE(672000000, 56, 1, 1),
151 PLL_RATE(684000000, 57, 1, 1),
152 PLL_RATE(696000000, 58, 1, 1),
153 PLL_RATE(708000000, 59, 1, 1),
154 PLL_RATE(720000000, 60, 1, 1),
155 PLL_RATE(732000000, 61, 1, 1),
156 PLL_RATE(744000000, 62, 1, 1),
157 PLL_RATE(756000000, 63, 1, 1),
158 PLL_RATE(768000000, 64, 1, 1),
159 PLL_RATE(780000000, 65, 1, 1),
160 PLL_RATE(792000000, 66, 1, 1),
161 PLL_RATE(804000000, 67, 1, 1),
162 PLL_RATE(816000000, 68, 1, 1),
163 PLL_RATE(960000000, 40, 1, 0),
164 PLL_RATE(984000000, 41, 1, 0),
165 PLL_RATE(1008000000, 42, 1, 0),
166 PLL_RATE(1032000000, 43, 1, 0),
167 PLL_RATE(1056000000, 44, 1, 0),
168 PLL_RATE(1080000000, 45, 1, 0),
169 PLL_RATE(1104000000, 46, 1, 0),
170 PLL_RATE(1128000000, 47, 1, 0),
171 PLL_RATE(1152000000, 48, 1, 0),
172 PLL_RATE(1176000000, 49, 1, 0),
173 PLL_RATE(1200000000, 50, 1, 0),
174 PLL_RATE(1224000000, 51, 1, 0),
175 PLL_RATE(1248000000, 52, 1, 0),
176 PLL_RATE(1272000000, 53, 1, 0),
177 PLL_RATE(1296000000, 54, 1, 0),
178 PLL_RATE(1320000000, 55, 1, 0),
179 PLL_RATE(1344000000, 56, 1, 0),
180 PLL_RATE(1368000000, 57, 1, 0),
181 PLL_RATE(1392000000, 58, 1, 0),
182 PLL_RATE(1416000000, 59, 1, 0),
183 PLL_RATE(1440000000, 60, 1, 0),
184 PLL_RATE(1464000000, 61, 1, 0),
185 PLL_RATE(1488000000, 62, 1, 0),
186 PLL_RATE(1512000000, 63, 1, 0),
187 PLL_RATE(1536000000, 64, 1, 0),
188 PLL_RATE(1560000000, 65, 1, 0),
189 PLL_RATE(1584000000, 66, 1, 0),
190 PLL_RATE(1608000000, 67, 1, 0),
191 PLL_RATE(1632000000, 68, 1, 0),
192 { /* sentinel */ },
193};
194
722825dc 195const struct reg_sequence axg_gp0_init_regs[] = {
722825dc
JB		 196 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
197 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
198 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
199 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
200 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
117863e8 201 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
78b4af31
QD		 202};
203
722825dc
JB		 204static struct clk_regmap axg_gp0_pll = {
205 .data = &(struct meson_clk_pll_data){
206 .m = {
207 .reg_off = HHI_GP0_PLL_CNTL,
208 .shift = 0,
209 .width = 9,
210 },
211 .n = {
212 .reg_off = HHI_GP0_PLL_CNTL,
213 .shift = 9,
214 .width = 5,
215 },
216 .od = {
217 .reg_off = HHI_GP0_PLL_CNTL,
218 .shift = 16,
219 .width = 2,
220 },
221 .l = {
222 .reg_off = HHI_GP0_PLL_CNTL,
223 .shift = 31,
224 .width = 1,
225 },
226 .rst = {
227 .reg_off = HHI_GP0_PLL_CNTL,
228 .shift = 29,
229 .width = 1,
230 },
231 .table = axg_gp0_pll_rate_table,
232 .init_regs = axg_gp0_init_regs,
233 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
234 .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
235 },
78b4af31
QD		 236 .hw.init = &(struct clk_init_data){
237 .name = "gp0_pll",
238 .ops = &meson_clk_pll_ops,
239 .parent_names = (const char *[]){ "xtal" },
240 .num_parents = 1,
241 },
242};
243
244
245static struct clk_fixed_factor axg_fclk_div2 = {
246 .mult = 1,
247 .div = 2,
248 .hw.init = &(struct clk_init_data){
249 .name = "fclk_div2",
250 .ops = &clk_fixed_factor_ops,
251 .parent_names = (const char *[]){ "fixed_pll" },
252 .num_parents = 1,
253 },
254};
255
256static struct clk_fixed_factor axg_fclk_div3 = {
257 .mult = 1,
258 .div = 3,
259 .hw.init = &(struct clk_init_data){
260 .name = "fclk_div3",
261 .ops = &clk_fixed_factor_ops,
262 .parent_names = (const char *[]){ "fixed_pll" },
263 .num_parents = 1,
264 },
265};
266
267static struct clk_fixed_factor axg_fclk_div4 = {
268 .mult = 1,
269 .div = 4,
270 .hw.init = &(struct clk_init_data){
271 .name = "fclk_div4",
272 .ops = &clk_fixed_factor_ops,
273 .parent_names = (const char *[]){ "fixed_pll" },
274 .num_parents = 1,
275 },
276};
277
278static struct clk_fixed_factor axg_fclk_div5 = {
279 .mult = 1,
280 .div = 5,
281 .hw.init = &(struct clk_init_data){
282 .name = "fclk_div5",
283 .ops = &clk_fixed_factor_ops,
284 .parent_names = (const char *[]){ "fixed_pll" },
285 .num_parents = 1,
286 },
287};
288
289static struct clk_fixed_factor axg_fclk_div7 = {
290 .mult = 1,
291 .div = 7,
292 .hw.init = &(struct clk_init_data){
293 .name = "fclk_div7",
294 .ops = &clk_fixed_factor_ops,
295 .parent_names = (const char *[]){ "fixed_pll" },
296 .num_parents = 1,
297 },
298};
299
d610b54f 300static struct clk_regmap axg_mpll0_div = {
c763e61a
JB		 301 .data = &(struct meson_clk_mpll_data){
302 .sdm = {
303 .reg_off = HHI_MPLL_CNTL7,
304 .shift = 0,
305 .width = 14,
306 },
307 .sdm_en = {
308 .reg_off = HHI_MPLL_CNTL7,
309 .shift = 15,
310 .width = 1,
311 },
312 .n2 = {
313 .reg_off = HHI_MPLL_CNTL7,
314 .shift = 16,
315 .width = 9,
316 },
c763e61a
JB		 317 .ssen = {
318 .reg_off = HHI_MPLL_CNTL,
319 .shift = 25,
320 .width = 1,
321 },
322 .misc = {
323 .reg_off = HHI_PLL_TOP_MISC,
324 .shift = 0,
325 .width = 1,
326 },
327 .lock = &meson_clk_lock,
78b4af31 328 },
78b4af31 329 .hw.init = &(struct clk_init_data){
d610b54f 330 .name = "mpll0_div",
78b4af31
QD		 331 .ops = &meson_clk_mpll_ops,
332 .parent_names = (const char *[]){ "fixed_pll" },
333 .num_parents = 1,
334 },
335};
336
d610b54f
JB		 337static struct clk_regmap axg_mpll0 = {
338 .data = &(struct clk_regmap_gate_data){
339 .offset = HHI_MPLL_CNTL7,
340 .bit_idx = 14,
341 },
342 .hw.init = &(struct clk_init_data){
343 .name = "mpll0",
344 .ops = &clk_regmap_gate_ops,
345 .parent_names = (const char *[]){ "mpll0_div" },
346 .num_parents = 1,
347 .flags = CLK_SET_RATE_PARENT,
348 },
349};
350
351static struct clk_regmap axg_mpll1_div = {
c763e61a
JB		 352 .data = &(struct meson_clk_mpll_data){
353 .sdm = {
354 .reg_off = HHI_MPLL_CNTL8,
355 .shift = 0,
356 .width = 14,
357 },
358 .sdm_en = {
359 .reg_off = HHI_MPLL_CNTL8,
360 .shift = 15,
361 .width = 1,
362 },
363 .n2 = {
364 .reg_off = HHI_MPLL_CNTL8,
365 .shift = 16,
366 .width = 9,
367 },
c763e61a
JB		 368 .misc = {
369 .reg_off = HHI_PLL_TOP_MISC,
370 .shift = 1,
371 .width = 1,
372 },
373 .lock = &meson_clk_lock,
78b4af31 374 },
78b4af31 375 .hw.init = &(struct clk_init_data){
d610b54f 376 .name = "mpll1_div",
78b4af31
QD		 377 .ops = &meson_clk_mpll_ops,
378 .parent_names = (const char *[]){ "fixed_pll" },
379 .num_parents = 1,
380 },
381};
382
d610b54f
JB		 383static struct clk_regmap axg_mpll1 = {
384 .data = &(struct clk_regmap_gate_data){
385 .offset = HHI_MPLL_CNTL8,
386 .bit_idx = 14,
387 },
388 .hw.init = &(struct clk_init_data){
389 .name = "mpll1",
390 .ops = &clk_regmap_gate_ops,
391 .parent_names = (const char *[]){ "mpll1_div" },
392 .num_parents = 1,
393 .flags = CLK_SET_RATE_PARENT,
394 },
395};
396
397static struct clk_regmap axg_mpll2_div = {
c763e61a
JB		 398 .data = &(struct meson_clk_mpll_data){
399 .sdm = {
400 .reg_off = HHI_MPLL_CNTL9,
401 .shift = 0,
402 .width = 14,
403 },
404 .sdm_en = {
405 .reg_off = HHI_MPLL_CNTL9,
406 .shift = 15,
407 .width = 1,
408 },
409 .n2 = {
410 .reg_off = HHI_MPLL_CNTL9,
411 .shift = 16,
412 .width = 9,
413 },
c763e61a
JB		 414 .misc = {
415 .reg_off = HHI_PLL_TOP_MISC,
416 .shift = 2,
417 .width = 1,
418 },
419 .lock = &meson_clk_lock,
78b4af31 420 },
78b4af31 421 .hw.init = &(struct clk_init_data){
d610b54f 422 .name = "mpll2_div",
78b4af31
QD		 423 .ops = &meson_clk_mpll_ops,
424 .parent_names = (const char *[]){ "fixed_pll" },
425 .num_parents = 1,
426 },
427};
428
d610b54f
JB		 429static struct clk_regmap axg_mpll2 = {
430 .data = &(struct clk_regmap_gate_data){
431 .offset = HHI_MPLL_CNTL9,
432 .bit_idx = 14,
433 },
434 .hw.init = &(struct clk_init_data){
435 .name = "mpll2",
436 .ops = &clk_regmap_gate_ops,
437 .parent_names = (const char *[]){ "mpll2_div" },
438 .num_parents = 1,
439 .flags = CLK_SET_RATE_PARENT,
440 },
441};
442
443static struct clk_regmap axg_mpll3_div = {
c763e61a
JB		 444 .data = &(struct meson_clk_mpll_data){
445 .sdm = {
446 .reg_off = HHI_MPLL3_CNTL0,
447 .shift = 12,
448 .width = 14,
449 },
450 .sdm_en = {
451 .reg_off = HHI_MPLL3_CNTL0,
452 .shift = 11,
453 .width = 1,
454 },
455 .n2 = {
456 .reg_off = HHI_MPLL3_CNTL0,
457 .shift = 2,
458 .width = 9,
459 },
c763e61a
JB		 460 .misc = {
461 .reg_off = HHI_PLL_TOP_MISC,
462 .shift = 3,
463 .width = 1,
464 },
465 .lock = &meson_clk_lock,
78b4af31 466 },
78b4af31 467 .hw.init = &(struct clk_init_data){
d610b54f 468 .name = "mpll3_div",
78b4af31
QD		 469 .ops = &meson_clk_mpll_ops,
470 .parent_names = (const char *[]){ "fixed_pll" },
471 .num_parents = 1,
472 },
473};
474
d610b54f
JB		 475static struct clk_regmap axg_mpll3 = {
476 .data = &(struct clk_regmap_gate_data){
477 .offset = HHI_MPLL3_CNTL0,
478 .bit_idx = 0,
479 },
480 .hw.init = &(struct clk_init_data){
481 .name = "mpll3",
482 .ops = &clk_regmap_gate_ops,
483 .parent_names = (const char *[]){ "mpll3_div" },
484 .num_parents = 1,
485 .flags = CLK_SET_RATE_PARENT,
486 },
487};
488
78b4af31
QD		 489static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
490static const char * const clk81_parent_names[] = {
491 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
492 "fclk_div3", "fclk_div5"
493};
494
2513a28c
JB		 495static struct clk_regmap axg_mpeg_clk_sel = {
496 .data = &(struct clk_regmap_mux_data){
497 .offset = HHI_MPEG_CLK_CNTL,
498 .mask = 0x7,
499 .shift = 12,
500 .table = mux_table_clk81,
501 },
78b4af31
QD		 502 .hw.init = &(struct clk_init_data){
503 .name = "mpeg_clk_sel",
2513a28c 504 .ops = &clk_regmap_mux_ro_ops,
78b4af31
QD		 505 .parent_names = clk81_parent_names,
506 .num_parents = ARRAY_SIZE(clk81_parent_names),
507 },
508};
509
f06ddd28
JB		 510static struct clk_regmap axg_mpeg_clk_div = {
511 .data = &(struct clk_regmap_div_data){
512 .offset = HHI_MPEG_CLK_CNTL,
513 .shift = 0,
514 .width = 7,
515 },
78b4af31
QD		 516 .hw.init = &(struct clk_init_data){
517 .name = "mpeg_clk_div",
f06ddd28 518 .ops = &clk_regmap_divider_ops,
78b4af31
QD		 519 .parent_names = (const char *[]){ "mpeg_clk_sel" },
520 .num_parents = 1,
521 .flags = CLK_SET_RATE_PARENT,
522 },
523};
524
7f9768a5
JB		 525static struct clk_regmap axg_clk81 = {
526 .data = &(struct clk_regmap_gate_data){
527 .offset = HHI_MPEG_CLK_CNTL,
528 .bit_idx = 7,
529 },
78b4af31
QD		 530 .hw.init = &(struct clk_init_data){
531 .name = "clk81",
7f9768a5 532 .ops = &clk_regmap_gate_ops,
78b4af31
QD		 533 .parent_names = (const char *[]){ "mpeg_clk_div" },
534 .num_parents = 1,
535 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
536 },
537};
538
539static const char * const axg_sd_emmc_clk0_parent_names[] = {
540 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
541
542 /*
543 * Following these parent clocks, we should also have had mpll2, mpll3
544 * and gp0_pll but these clocks are too precious to be used here. All
545 * the necessary rates for MMC and NAND operation can be acheived using
546 * xtal or fclk_div clocks
547 */
548};
549
550/* SDcard clock */
2513a28c
JB		 551static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
552 .data = &(struct clk_regmap_mux_data){
553 .offset = HHI_SD_EMMC_CLK_CNTL,
554 .mask = 0x7,
555 .shift = 25,
556 },
78b4af31
QD		 557 .hw.init = &(struct clk_init_data) {
558 .name = "sd_emmc_b_clk0_sel",
2513a28c 559 .ops = &clk_regmap_mux_ops,
78b4af31
QD		 560 .parent_names = axg_sd_emmc_clk0_parent_names,
561 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
562 .flags = CLK_SET_RATE_PARENT,
563 },
564};
565
f06ddd28
JB		 566static struct clk_regmap axg_sd_emmc_b_clk0_div = {
567 .data = &(struct clk_regmap_div_data){
568 .offset = HHI_SD_EMMC_CLK_CNTL,
569 .shift = 16,
570 .width = 7,
571 .flags = CLK_DIVIDER_ROUND_CLOSEST,
572 },
78b4af31
QD		 573 .hw.init = &(struct clk_init_data) {
574 .name = "sd_emmc_b_clk0_div",
f06ddd28 575 .ops = &clk_regmap_divider_ops,
78b4af31
QD		 576 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
577 .num_parents = 1,
578 .flags = CLK_SET_RATE_PARENT,
579 },
580};
581
7f9768a5
JB		 582static struct clk_regmap axg_sd_emmc_b_clk0 = {
583 .data = &(struct clk_regmap_gate_data){
584 .offset = HHI_SD_EMMC_CLK_CNTL,
585 .bit_idx = 23,
586 },
78b4af31
QD		 587 .hw.init = &(struct clk_init_data){
588 .name = "sd_emmc_b_clk0",
7f9768a5 589 .ops = &clk_regmap_gate_ops,
78b4af31
QD		 590 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
591 .num_parents = 1,
592 .flags = CLK_SET_RATE_PARENT,
593 },
594};
595
596/* EMMC/NAND clock */
2513a28c
JB		 597static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
598 .data = &(struct clk_regmap_mux_data){
599 .offset = HHI_NAND_CLK_CNTL,
600 .mask = 0x7,
601 .shift = 9,
602 },
78b4af31
QD		 603 .hw.init = &(struct clk_init_data) {
604 .name = "sd_emmc_c_clk0_sel",
2513a28c 605 .ops = &clk_regmap_mux_ops,
78b4af31
QD		 606 .parent_names = axg_sd_emmc_clk0_parent_names,
607 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
608 .flags = CLK_SET_RATE_PARENT,
609 },
610};
611
f06ddd28
JB		 612static struct clk_regmap axg_sd_emmc_c_clk0_div = {
613 .data = &(struct clk_regmap_div_data){
614 .offset = HHI_NAND_CLK_CNTL,
615 .shift = 0,
616 .width = 7,
617 .flags = CLK_DIVIDER_ROUND_CLOSEST,
618 },
78b4af31
QD		 619 .hw.init = &(struct clk_init_data) {
620 .name = "sd_emmc_c_clk0_div",
f06ddd28 621 .ops = &clk_regmap_divider_ops,
78b4af31
QD		 622 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
623 .num_parents = 1,
624 .flags = CLK_SET_RATE_PARENT,
625 },
626};
627
7f9768a5
JB		 628static struct clk_regmap axg_sd_emmc_c_clk0 = {
629 .data = &(struct clk_regmap_gate_data){
630 .offset = HHI_NAND_CLK_CNTL,
631 .bit_idx = 7,
632 },
78b4af31
QD		 633 .hw.init = &(struct clk_init_data){
634 .name = "sd_emmc_c_clk0",
7f9768a5 635 .ops = &clk_regmap_gate_ops,
78b4af31
QD		 636 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
637 .num_parents = 1,
638 .flags = CLK_SET_RATE_PARENT,
639 },
640};
641
642/* Everything Else (EE) domain gates */
643static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
644static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
645static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
646static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
647static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
648static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
649static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
650static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
651static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
652static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
653static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
654static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
655static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
656static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
657static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
658static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
659static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
660static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
661static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
662static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
663
664static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
665static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
666static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
667static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
668static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
669static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
670static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
671static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
672static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
673static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
674static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
675
676static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
677static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
678static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
679static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
680static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
681static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
682static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
683static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
684
685/* Always On (AO) domain gates */
686
687static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
688static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
689static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
690static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
691static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
692
693/* Array of all clocks provided by this provider */
694
695static struct clk_hw_onecell_data axg_hw_onecell_data = {
696 .hws = {
697 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
698 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
699 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
700 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
701 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
702 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
703 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
704 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
705 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
706 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
707 [CLKID_CLK81] = &axg_clk81.hw,
708 [CLKID_MPLL0] = &axg_mpll0.hw,
709 [CLKID_MPLL1] = &axg_mpll1.hw,
710 [CLKID_MPLL2] = &axg_mpll2.hw,
711 [CLKID_MPLL3] = &axg_mpll3.hw,
712 [CLKID_DDR] = &axg_ddr.hw,
713 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
714 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
715 [CLKID_ISA] = &axg_isa.hw,
716 [CLKID_PL301] = &axg_pl301.hw,
717 [CLKID_PERIPHS] = &axg_periphs.hw,
718 [CLKID_SPICC0] = &axg_spicc_0.hw,
719 [CLKID_I2C] = &axg_i2c.hw,
720 [CLKID_RNG0] = &axg_rng0.hw,
721 [CLKID_UART0] = &axg_uart0.hw,
722 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
723 [CLKID_SPICC1] = &axg_spicc_1.hw,
724 [CLKID_PCIE_A] = &axg_pcie_a.hw,
725 [CLKID_PCIE_B] = &axg_pcie_b.hw,
726 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
727 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
728 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
729 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
730 [CLKID_DMA] = &axg_dma.hw,
731 [CLKID_SPI] = &axg_spi.hw,
732 [CLKID_AUDIO] = &axg_audio.hw,
733 [CLKID_ETH] = &axg_eth_core.hw,
734 [CLKID_UART1] = &axg_uart1.hw,
735 [CLKID_G2D] = &axg_g2d.hw,
736 [CLKID_USB0] = &axg_usb0.hw,
737 [CLKID_USB1] = &axg_usb1.hw,
738 [CLKID_RESET] = &axg_reset.hw,
739 [CLKID_USB] = &axg_usb_general.hw,
740 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
741 [CLKID_EFUSE] = &axg_efuse.hw,
742 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
743 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
744 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
745 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
746 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
747 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
748 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
749 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
750 [CLKID_GIC] = &axg_gic.hw,
751 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
752 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
753 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
754 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
755 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
756 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
757 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
758 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
759 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
760 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
761 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
d610b54f
JB		 762 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
763 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
764 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
765 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
78b4af31
QD		 766 [NR_CLKS] = NULL,
767 },
768 .num = NR_CLKS,
769};
770
722825dc 771/* Convenience table to populate regmap in .probe */
7f9768a5 772static struct clk_regmap *const axg_clk_regmaps[] = {
78b4af31
QD		 773 &axg_clk81,
774 &axg_ddr,
775 &axg_audio_locker,
776 &axg_mipi_dsi_host,
777 &axg_isa,
778 &axg_pl301,
779 &axg_periphs,
780 &axg_spicc_0,
781 &axg_i2c,
782 &axg_rng0,
783 &axg_uart0,
784 &axg_mipi_dsi_phy,
785 &axg_spicc_1,
786 &axg_pcie_a,
787 &axg_pcie_b,
788 &axg_hiu_reg,
789 &axg_assist_misc,
790 &axg_emmc_b,
791 &axg_emmc_c,
792 &axg_dma,
793 &axg_spi,
794 &axg_audio,
795 &axg_eth_core,
796 &axg_uart1,
797 &axg_g2d,
798 &axg_usb0,
799 &axg_usb1,
800 &axg_reset,
801 &axg_usb_general,
802 &axg_ahb_arb0,
803 &axg_efuse,
804 &axg_boot_rom,
805 &axg_ahb_data_bus,
806 &axg_ahb_ctrl_bus,
807 &axg_usb1_to_ddr,
808 &axg_usb0_to_ddr,
809 &axg_mmc_pclk,
810 &axg_vpu_intr,
811 &axg_sec_ahb_ahb3_bridge,
812 &axg_gic,
813 &axg_ao_media_cpu,
814 &axg_ao_ahb_sram,
815 &axg_ao_ahb_bus,
816 &axg_ao_iface,
817 &axg_ao_i2c,
818 &axg_sd_emmc_b_clk0,
819 &axg_sd_emmc_c_clk0,
f06ddd28
JB		 820 &axg_mpeg_clk_div,
821 &axg_sd_emmc_b_clk0_div,
822 &axg_sd_emmc_c_clk0_div,
2513a28c
JB		 823 &axg_mpeg_clk_sel,
824 &axg_sd_emmc_b_clk0_sel,
825 &axg_sd_emmc_c_clk0_sel,
c763e61a
JB		 826 &axg_mpll0,
827 &axg_mpll1,
828 &axg_mpll2,
829 &axg_mpll3,
d610b54f
JB		 830 &axg_mpll0_div,
831 &axg_mpll1_div,
832 &axg_mpll2_div,
833 &axg_mpll3_div,
722825dc
JB		 834 &axg_fixed_pll,
835 &axg_sys_pll,
836 &axg_gp0_pll,
78b4af31
QD		 837};
838
839static const struct of_device_id clkc_match_table[] = {
722825dc 840 { .compatible = "amlogic,axg-clkc" },
78b4af31
QD		 841 {}
842};
843
161f6e5b
JB		 844static const struct regmap_config clkc_regmap_config = {
845 .reg_bits = 32,
846 .val_bits = 32,
847 .reg_stride = 4,
848};
849
78b4af31
QD		 850static int axg_clkc_probe(struct platform_device *pdev)
851{
852 struct device *dev = &pdev->dev;
78b4af31 853 struct resource *res;
4162dd5b 854 void __iomem *clk_base = NULL;
161f6e5b 855 struct regmap *map;
14bd7b9c 856 int ret, i;
78b4af31 857
4162dd5b
JB		 858 /* Get the hhi system controller node if available */
859 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
860 if (IS_ERR(map)) {
861 dev_err(dev,
862 "failed to get HHI regmap - Trying obsolete regs\n");
863
864 /*
865 * FIXME: HHI registers should be accessed through
866 * the appropriate system controller. This is required because
867 * there is more than just clocks in this register space
868 *
869 * This fallback method is only provided temporarily until
870 * all the platform DTs are properly using the syscon node
871 */
872 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
873 if (!res)
874 return -EINVAL;
875
876
877 clk_base = devm_ioremap(dev, res->start, resource_size(res));
878 if (!clk_base) {
879 dev_err(dev, "Unable to map clk base\n");
880 return -ENXIO;
881 }
161f6e5b 882
4162dd5b
JB		 883 map = devm_regmap_init_mmio(dev, clk_base,
884 &clkc_regmap_config);
885 if (IS_ERR(map))
886 return PTR_ERR(map);
78b4af31
QD		 887 }
888
7f9768a5
JB		 889 /* Populate regmap for the regmap backed clocks */
890 for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
891 axg_clk_regmaps[i]->map = map;
892
722825dc 893 for (i = 0; i < axg_hw_onecell_data.num; i++) {
78b4af31 894 /* array might be sparse */
722825dc 895 if (!axg_hw_onecell_data.hws[i])
78b4af31
QD		 896 continue;
897
722825dc 898 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
78b4af31 899 if (ret) {
323346d3 900 dev_err(dev, "Clock registration failed\n");
78b4af31
QD		 901 return ret;
902 }
903 }
904
332b32a2 905 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
722825dc 906 &axg_hw_onecell_data);
78b4af31
QD		 907}
908
909static struct platform_driver axg_driver = {
910 .probe = axg_clkc_probe,
911 .driver = {
912 .name = "axg-clkc",
913 .of_match_table = clkc_match_table,
914 },
915};
916
917builtin_platform_driver(axg_driver);
Linux 6.x block layer and io_uring tree(s)