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4b471943 SS |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (c) 2023 MediaTek Inc. | |
4 | * Author: Sam Shih <sam.shih@mediatek.com> | |
5 | * Author: Xiufeng Li <Xiufeng.Li@mediatek.com> | |
6 | */ | |
7 | ||
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/of_address.h> | |
11 | #include <linux/of_device.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include "clk-mtk.h" | |
14 | #include "clk-gate.h" | |
15 | #include "clk-mux.h" | |
16 | #include <dt-bindings/clock/mediatek,mt7988-clk.h> | |
7fcf1ef8 FW |
17 | #include <dt-bindings/reset/mediatek,mt7988-resets.h> |
18 | ||
19 | #define MT7988_INFRA_RST0_SET_OFFSET 0x70 | |
20 | #define MT7988_INFRA_RST1_SET_OFFSET 0x80 | |
4b471943 SS |
21 | |
22 | static DEFINE_SPINLOCK(mt7988_clk_lock); | |
23 | ||
24 | static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel", | |
25 | "uart_sel" }; | |
26 | ||
27 | static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel", | |
28 | "uart_sel" }; | |
29 | ||
30 | static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel", | |
31 | "uart_sel" }; | |
32 | ||
33 | static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" }; | |
34 | ||
35 | static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" }; | |
36 | ||
37 | static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k", | |
38 | "csw_infra_f26m_sel", "sysaxi_sel", | |
39 | "pwm_sel" }; | |
40 | ||
41 | static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { | |
42 | "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel" | |
43 | }; | |
44 | ||
45 | static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { | |
46 | "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel" | |
47 | }; | |
48 | ||
49 | static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { | |
50 | "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel" | |
51 | }; | |
52 | ||
53 | static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { | |
54 | "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel" | |
55 | }; | |
56 | ||
57 | static const struct mtk_mux infra_muxes[] = { | |
58 | /* MODULE_CLK_SEL_0 */ | |
59 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", | |
60 | infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), | |
61 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", | |
62 | infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), | |
63 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", | |
64 | infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), | |
65 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, | |
66 | 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), | |
67 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, | |
68 | 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), | |
69 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, | |
70 | 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), | |
71 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018, | |
72 | 0x0010, 0x0014, 14, 2, -1, -1, -1), | |
73 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, | |
74 | 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1), | |
75 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, | |
76 | 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1), | |
77 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, | |
78 | 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1), | |
79 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, | |
80 | 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1), | |
81 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, | |
82 | 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1), | |
83 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, | |
84 | 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1), | |
85 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, | |
86 | 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1), | |
87 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, | |
88 | 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1), | |
89 | /* MODULE_CLK_SEL_1 */ | |
90 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", | |
91 | infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, | |
92 | -1, -1), | |
93 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", | |
94 | infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1, | |
95 | -1, -1), | |
96 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", | |
97 | infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1, | |
98 | -1, -1), | |
99 | MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", | |
100 | infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1, | |
101 | -1, -1), | |
102 | }; | |
103 | ||
104 | static const struct mtk_gate_regs infra0_cg_regs = { | |
105 | .set_ofs = 0x10, | |
106 | .clr_ofs = 0x14, | |
107 | .sta_ofs = 0x18, | |
108 | }; | |
109 | ||
110 | static const struct mtk_gate_regs infra1_cg_regs = { | |
111 | .set_ofs = 0x40, | |
112 | .clr_ofs = 0x44, | |
113 | .sta_ofs = 0x48, | |
114 | }; | |
115 | ||
116 | static const struct mtk_gate_regs infra2_cg_regs = { | |
117 | .set_ofs = 0x50, | |
118 | .clr_ofs = 0x54, | |
119 | .sta_ofs = 0x58, | |
120 | }; | |
121 | ||
122 | static const struct mtk_gate_regs infra3_cg_regs = { | |
123 | .set_ofs = 0x60, | |
124 | .clr_ofs = 0x64, | |
125 | .sta_ofs = 0x68, | |
126 | }; | |
127 | ||
128 | #define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ | |
129 | GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ | |
130 | _flags) | |
131 | ||
132 | #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ | |
133 | GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ | |
134 | _flags) | |
135 | ||
136 | #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ | |
137 | GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ | |
138 | _flags) | |
139 | ||
140 | #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ | |
141 | GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ | |
142 | _flags) | |
143 | ||
144 | #define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) | |
145 | ||
146 | #define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) | |
147 | ||
148 | #define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) | |
149 | ||
150 | #define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) | |
151 | ||
152 | static const struct mtk_gate infra_clks[] = { | |
153 | /* INFRA0 */ | |
154 | GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0", | |
155 | "csw_infra_f26m_sel", 7), | |
156 | GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", | |
157 | "csw_infra_f26m_sel", 8), | |
158 | GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", | |
159 | "csw_infra_f26m_sel", 9), | |
160 | GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", | |
161 | "csw_infra_f26m_sel", 10), | |
162 | /* INFRA1 */ | |
163 | GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0), | |
164 | GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1), | |
165 | GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2), | |
166 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3), | |
167 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4), | |
168 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5), | |
169 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6), | |
170 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7), | |
171 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8), | |
172 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9), | |
173 | GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10), | |
174 | GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12), | |
175 | GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13), | |
176 | GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14), | |
177 | GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), | |
178 | GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), | |
179 | GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), | |
180 | GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19, | |
181 | CLK_IS_CRITICAL), | |
182 | /* JTAG */ | |
183 | GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20, | |
184 | CLK_IS_CRITICAL), | |
185 | GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21), | |
186 | GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29), | |
187 | GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30), | |
188 | /* INFRA2 */ | |
189 | GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel", | |
190 | 0), | |
191 | GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), | |
192 | GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3), | |
193 | GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4), | |
194 | GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5), | |
195 | GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), | |
196 | GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), | |
197 | GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, | |
198 | CLK_IS_CRITICAL), | |
199 | GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, | |
200 | CLK_IS_CRITICAL), | |
201 | GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), | |
202 | GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), | |
203 | GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, | |
204 | CLK_IS_CRITICAL), | |
205 | GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), | |
206 | GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), | |
207 | GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), | |
208 | GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL), | |
209 | GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), | |
210 | GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21), | |
211 | GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22), | |
212 | GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23), | |
213 | GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24), | |
214 | GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25), | |
215 | GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26), | |
216 | GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), | |
217 | GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), | |
218 | GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), | |
219 | /* INFRA3 */ | |
220 | GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0), | |
221 | GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1), | |
222 | GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2), | |
223 | GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3), | |
224 | GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), | |
225 | GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5), | |
226 | GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), | |
227 | GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), | |
228 | GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8, | |
229 | CLK_IS_CRITICAL), | |
230 | GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel", | |
231 | 9, CLK_IS_CRITICAL), | |
232 | GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), | |
233 | GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11), | |
234 | GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), | |
235 | GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13), | |
236 | GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), | |
237 | GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15), | |
238 | GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", | |
239 | "infra_pcie_gfmux_tl_o_p0_sel", 20), | |
240 | GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", | |
241 | "infra_pcie_gfmux_tl_o_p1_sel", 21), | |
242 | GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", | |
243 | "infra_pcie_gfmux_tl_o_p2_sel", 22), | |
244 | GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", | |
245 | "infra_pcie_gfmux_tl_o_p3_sel", 23), | |
246 | GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24), | |
247 | GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25), | |
248 | GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26), | |
249 | GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27), | |
250 | GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28), | |
251 | GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29), | |
252 | GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30), | |
253 | GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), | |
254 | }; | |
255 | ||
7fcf1ef8 FW |
256 | static u16 infra_rst_ofs[] = { |
257 | MT7988_INFRA_RST0_SET_OFFSET, | |
258 | MT7988_INFRA_RST1_SET_OFFSET, | |
259 | }; | |
260 | ||
261 | static u16 infra_idx_map[] = { | |
262 | [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, | |
263 | [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, | |
264 | }; | |
265 | ||
266 | static struct mtk_clk_rst_desc infra_rst_desc = { | |
267 | .version = MTK_RST_SET_CLR, | |
268 | .rst_bank_ofs = infra_rst_ofs, | |
269 | .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), | |
270 | .rst_idx_map = infra_idx_map, | |
271 | .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), | |
272 | }; | |
273 | ||
4b471943 SS |
274 | static const struct mtk_clk_desc infra_desc = { |
275 | .clks = infra_clks, | |
276 | .num_clks = ARRAY_SIZE(infra_clks), | |
277 | .mux_clks = infra_muxes, | |
278 | .num_mux_clks = ARRAY_SIZE(infra_muxes), | |
279 | .clk_lock = &mt7988_clk_lock, | |
7fcf1ef8 | 280 | .rst_desc = &infra_rst_desc, |
4b471943 SS |
281 | }; |
282 | ||
283 | static const struct of_device_id of_match_clk_mt7988_infracfg[] = { | |
284 | { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, | |
285 | { /* sentinel */ } | |
286 | }; | |
287 | MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); | |
288 | ||
289 | static struct platform_driver clk_mt7988_infracfg_drv = { | |
290 | .driver = { | |
291 | .name = "clk-mt7988-infracfg", | |
292 | .of_match_table = of_match_clk_mt7988_infracfg, | |
293 | }, | |
294 | .probe = mtk_clk_simple_probe, | |
295 | .remove_new = mtk_clk_simple_remove, | |
296 | }; | |
297 | module_platform_driver(clk_mt7988_infracfg_drv); | |
298 | MODULE_LICENSE("GPL"); |