[linux-2.6-block.git] / drivers / clk / imx / clk.h

#ifndef __MACH_IMX_CLK_H
#define __MACH_IMX_CLK_H

#include <linux/spinlock.h>
#include <linux/clk-provider.h>

extern spinlock_t imx_ccm_lock;

void imx_check_clocks(struct clk *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);

extern void imx_cscmr1_fixup(u32 *val);

enum imx_pllv1_type {
	IMX_PLLV1_IMX1,
	IMX_PLLV1_IMX21,
	IMX_PLLV1_IMX25,
	IMX_PLLV1_IMX27,
	IMX_PLLV1_IMX31,
	IMX_PLLV1_IMX35,
};

struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
		const char *parent, void __iomem *base);

struct clk *imx_clk_pllv2(const char *name, const char *parent,
		void __iomem *base);

enum imx_pllv3_type {
	IMX_PLLV3_GENERIC,
	IMX_PLLV3_SYS,
	IMX_PLLV3_USB,
	IMX_PLLV3_USB_VF610,
	IMX_PLLV3_AV,
	IMX_PLLV3_ENET,
	IMX_PLLV3_ENET_IMX7,
};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
		const char *parent_name, void __iomem *base, u32 div_mask);

struct clk *clk_register_gate2(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx, u8 cgr_val,
		u8 clk_gate_flags, spinlock_t *lock,
		unsigned int *share_count);

struct clk * imx_obtain_fixed_clock(
			const char *name, unsigned long rate);

struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
	 void __iomem *reg, u8 shift, u32 exclusive_mask);

struct clk *imx_clk_pfd(const char *name, const char *parent_name,
		void __iomem *reg, u8 idx);

struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
				 void __iomem *reg, u8 shift, u8 width,
				 void __iomem *busy_reg, u8 busy_shift);

struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
			     u8 width, void __iomem *busy_reg, u8 busy_shift,
			     const char **parent_names, int num_parents);

struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
				  void __iomem *reg, u8 shift, u8 width,
				  void (*fixup)(u32 *val));

struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
			      u8 shift, u8 width, const char **parents,
			      int num_parents, void (*fixup)(u32 *val));

static inline struct clk *imx_clk_fixed(const char *name, int rate)
{
	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}

static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
		u8 shift, u8 width, const char **parents, int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
			shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
}

static inline struct clk *imx_clk_fixed_factor(const char *name,
		const char *parent, unsigned int mult, unsigned int div)
{
	return clk_register_fixed_factor(NULL, name, parent,
			CLK_SET_RATE_PARENT, mult, div);
}

static inline struct clk *imx_clk_divider(const char *name, const char *parent,
		void __iomem *reg, u8 shift, u8 width)
{
	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
			reg, shift, width, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_divider_flags(const char *name,
		const char *parent, void __iomem *reg, u8 shift, u8 width,
		unsigned long flags)
{
	return clk_register_divider(NULL, name, parent, flags,
			reg, shift, width, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
		void __iomem *reg, u8 shift, u8 width)
{
	return clk_register_divider(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, width, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_gate(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
}

static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, 0x3, 0, &imx_ccm_lock, NULL);
}

static inline struct clk *imx_clk_gate2_shared(const char *name,
		const char *parent, void __iomem *reg, u8 shift,
		unsigned int *share_count)
{
	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, 0x3, 0, &imx_ccm_lock, share_count);
}

static inline struct clk *imx_clk_gate2_shared2(const char *name,
		const char *parent, void __iomem *reg, u8 shift,
		unsigned int *share_count)
{
	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
				  CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
				  &imx_ccm_lock, share_count);
}

static inline struct clk *imx_clk_gate2_cgr(const char *name,
		const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
{
	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, cgr_val, 0, &imx_ccm_lock, NULL);
}

static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate2(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
}

static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
		u8 shift, u8 width, const char **parents, int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			CLK_SET_RATE_NO_REPARENT, reg, shift,
			width, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
		u8 shift, u8 width, const char **parents, int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, width, 0, &imx_ccm_lock);
}

static inline struct clk *imx_clk_mux_flags(const char *name,
		void __iomem *reg, u8 shift, u8 width, const char **parents,
		int num_parents, unsigned long flags)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
			&imx_ccm_lock);
}

struct clk *imx_clk_cpu(const char *name, const char *parent_name,
		struct clk *div, struct clk *mux, struct clk *pll,
		struct clk *step);

#endif
Commit	Line	Data
6c7b0685 SH	1	#ifndef __MACH_IMX_CLK_H
	2	#define __MACH_IMX_CLK_H
	3
	4	#include <linux/spinlock.h>
	5	#include <linux/clk-provider.h>
3a84d17b SH	6
3a84d17b SH	7	extern spinlock_t imx_ccm_lock;
6c7b0685	8
229be9c1	9	void imx_check_clocks(struct clk *clks[], unsigned int count);
55adc61c	10	void imx_register_uart_clocks(struct clk ** const clks[]);
229be9c1	11
dfd87144 LY	12	extern void imx_cscmr1_fixup(u32 *val);
dfd87144 LY	13
3bec5f81 SG	14	enum imx_pllv1_type {
	15	IMX_PLLV1_IMX1,
	16	IMX_PLLV1_IMX21,
	17	IMX_PLLV1_IMX25,
	18	IMX_PLLV1_IMX27,
	19	IMX_PLLV1_IMX31,
	20	IMX_PLLV1_IMX35,
	21	};
	22
	23	struct clk imx_clk_pllv1(enum imx_pllv1_type type, const char name,
	24	const char parent, void __iomem base);
6c7b0685	25
a547b816 SH	26	struct clk imx_clk_pllv2(const char name, const char *parent,
	27	void __iomem *base);
	28
a3f6b9db SG	29	enum imx_pllv3_type {
	30	IMX_PLLV3_GENERIC,
	31	IMX_PLLV3_SYS,
	32	IMX_PLLV3_USB,
60ad8467	33	IMX_PLLV3_USB_VF610,
a3f6b9db SG	34	IMX_PLLV3_AV,
a3f6b9db SG	35	IMX_PLLV3_ENET,
f5394745	36	IMX_PLLV3_ENET_IMX7,
a3f6b9db SG	37	};
	38
	39	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
2b254693	40	const char parent_name, void __iomem base, u32 div_mask);
a3f6b9db	41
b75c0151 SH	42	struct clk clk_register_gate2(struct device dev, const char *name,
b75c0151 SH	43	const char *parent_name, unsigned long flags,
45682922	44	void __iomem *reg, u8 bit_idx, u8 cgr_val,
f9f28cdf SG	45	u8 clk_gate_flags, spinlock_t *lock,
f9f28cdf SG	46	unsigned int *share_count);
b75c0151	47
75f83d06 MF	48	struct clk * imx_obtain_fixed_clock(
	49	const char *name, unsigned long rate);
	50
19d86344 SG	51	struct clk imx_clk_gate_exclusive(const char name, const char *parent,
	52	void __iomem *reg, u8 shift, u32 exclusive_mask);
	53
a10bd67f SG	54	struct clk imx_clk_pfd(const char name, const char *parent_name,
	55	void __iomem *reg, u8 idx);
	56
32af7a83 SG	57	struct clk imx_clk_busy_divider(const char name, const char *parent_name,
	58	void __iomem *reg, u8 shift, u8 width,
	59	void __iomem *busy_reg, u8 busy_shift);
	60
	61	struct clk imx_clk_busy_mux(const char name, void __iomem *reg, u8 shift,
	62	u8 width, void __iomem *busy_reg, u8 busy_shift,
	63	const char **parent_names, int num_parents);
	64
cbe7fc8a LY	65	struct clk imx_clk_fixup_divider(const char name, const char *parent,
	66	void __iomem *reg, u8 shift, u8 width,
	67	void (fixup)(u32 val));
	68
a49e6c4b LY	69	struct clk imx_clk_fixup_mux(const char name, void __iomem *reg,
	70	u8 shift, u8 width, const char **parents,
	71	int num_parents, void (fixup)(u32 val));
	72
6c7b0685 SH	73	static inline struct clk imx_clk_fixed(const char name, int rate)
6c7b0685 SH	74	{
38c7035f	75	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
6c7b0685 SH	76	}
6c7b0685 SH	77
03d576f2 PZ	78	static inline struct clk imx_clk_mux_ldb(const char name, void __iomem *reg,
	79	u8 shift, u8 width, const char **parents, int num_parents)
	80	{
	81	return clk_register_mux(NULL, name, parents, num_parents,
	82	CLK_SET_RATE_NO_REPARENT \| CLK_SET_RATE_PARENT, reg,
	83	shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
	84	}
	85
5afc9941 DA	86	static inline struct clk imx_clk_fixed_factor(const char name,
	87	const char *parent, unsigned int mult, unsigned int div)
	88	{
	89	return clk_register_fixed_factor(NULL, name, parent,
	90	CLK_SET_RATE_PARENT, mult, div);
	91	}
	92
6c7b0685 SH	93	static inline struct clk imx_clk_divider(const char name, const char *parent,
	94	void __iomem *reg, u8 shift, u8 width)
	95	{
	96	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
	97	reg, shift, width, 0, &imx_ccm_lock);
	98	}
	99
3ce92170 PZ	100	static inline struct clk imx_clk_divider_flags(const char name,
	101	const char parent, void __iomem reg, u8 shift, u8 width,
	102	unsigned long flags)
	103	{
	104	return clk_register_divider(NULL, name, parent, flags,
	105	reg, shift, width, 0, &imx_ccm_lock);
	106	}
	107
39c29498 DA	108	static inline struct clk imx_clk_divider2(const char name, const char *parent,
	109	void __iomem *reg, u8 shift, u8 width)
	110	{
	111	return clk_register_divider(NULL, name, parent,
	112	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	113	reg, shift, width, 0, &imx_ccm_lock);
	114	}
	115
6c7b0685 SH	116	static inline struct clk imx_clk_gate(const char name, const char *parent,
	117	void __iomem *reg, u8 shift)
	118	{
	119	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	120	shift, 0, &imx_ccm_lock);
	121	}
	122
65251690 AS	123	static inline struct clk imx_clk_gate_dis(const char name, const char *parent,
	124	void __iomem *reg, u8 shift)
	125	{
	126	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	127	shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
	128	}
	129
5afc9941 DA	130	static inline struct clk imx_clk_gate2(const char name, const char *parent,
	131	void __iomem *reg, u8 shift)
	132	{
	133	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	134	shift, 0x3, 0, &imx_ccm_lock, NULL);
	135	}
	136
	137	static inline struct clk imx_clk_gate2_shared(const char name,
	138	const char parent, void __iomem reg, u8 shift,
	139	unsigned int *share_count)
	140	{
	141	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	142	shift, 0x3, 0, &imx_ccm_lock, share_count);
	143	}
	144
d5ebf5fa FE	145	static inline struct clk imx_clk_gate2_shared2(const char name,
	146	const char parent, void __iomem reg, u8 shift,
	147	unsigned int *share_count)
	148	{
	149	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT \|
	150	CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
	151	&imx_ccm_lock, share_count);
	152	}
	153
5afc9941 DA	154	static inline struct clk imx_clk_gate2_cgr(const char name,
	155	const char parent, void __iomem reg, u8 shift, u8 cgr_val)
	156	{
	157	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	158	shift, cgr_val, 0, &imx_ccm_lock, NULL);
	159	}
	160
39c29498 DA	161	static inline struct clk imx_clk_gate3(const char name, const char *parent,
	162	void __iomem *reg, u8 shift)
	163	{
	164	return clk_register_gate(NULL, name, parent,
	165	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	166	reg, shift, 0, &imx_ccm_lock);
	167	}
	168
	169	static inline struct clk imx_clk_gate4(const char name, const char *parent,
	170	void __iomem *reg, u8 shift)
	171	{
	172	return clk_register_gate2(NULL, name, parent,
	173	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	174	reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
	175	}
	176
6c7b0685 SH	177	static inline struct clk imx_clk_mux(const char name, void __iomem *reg,
	178	u8 shift, u8 width, const char **parents, int num_parents)
	179	{
819c1de3 JH	180	return clk_register_mux(NULL, name, parents, num_parents,
819c1de3 JH	181	CLK_SET_RATE_NO_REPARENT, reg, shift,
6c7b0685 SH	182	width, 0, &imx_ccm_lock);
	183	}
	184
39c29498 DA	185	static inline struct clk imx_clk_mux2(const char name, void __iomem *reg,
	186	u8 shift, u8 width, const char **parents, int num_parents)
	187	{
	188	return clk_register_mux(NULL, name, parents, num_parents,
	189	CLK_SET_RATE_NO_REPARENT \| CLK_OPS_PARENT_ENABLE,
	190	reg, shift, width, 0, &imx_ccm_lock);
	191	}
	192
3ce92170 PZ	193	static inline struct clk imx_clk_mux_flags(const char name,
	194	void __iomem reg, u8 shift, u8 width, const char *parents,
	195	int num_parents, unsigned long flags)
	196	{
	197	return clk_register_mux(NULL, name, parents, num_parents,
819c1de3	198	flags \| CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
3ce92170 PZ	199	&imx_ccm_lock);
	200	}
	201
e0fed513 LS	202	struct clk imx_clk_cpu(const char name, const char *parent_name,
	203	struct clk div, struct clk mux, struct clk *pll,
	204	struct clk *step);
	205
6c7b0685	206	#endif