[linux-2.6-block.git] / drivers / clk / imx / clk-pllv3.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2012 Linaro Ltd.
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include "clk.h"

#define PLL_NUM_OFFSET		0x10
#define PLL_DENOM_OFFSET	0x20
#define PLL_IMX7_NUM_OFFSET	0x20
#define PLL_IMX7_DENOM_OFFSET	0x30

#define PLL_VF610_NUM_OFFSET	0x20
#define PLL_VF610_DENOM_OFFSET	0x30

#define BM_PLL_POWER		(0x1 << 12)
#define BM_PLL_LOCK		(0x1 << 31)
#define IMX7_ENET_PLL_POWER	(0x1 << 5)
#define IMX7_DDR_PLL_POWER	(0x1 << 20)

#define PLL_LOCK_TIMEOUT	10000

/**
 * struct clk_pllv3 - IMX PLL clock version 3
 * @hw:		clock source
 * @base:	 base address of PLL registers
 * @power_bit:	 pll power bit mask
 * @powerup_set: set power_bit to power up the PLL
 * @div_mask:	 mask of divider bits
 * @div_shift:	 shift of divider bits
 * @ref_clock:	reference clock rate
 * @num_offset:	num register offset
 * @denom_offset: denom register offset
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
 * is actually a multiplier, and always sits at bit 0.
 */
struct clk_pllv3 {
	struct clk_hw	hw;
	void __iomem	*base;
	u32		power_bit;
	bool		powerup_set;
	u32		div_mask;
	u32		div_shift;
	unsigned long	ref_clock;
	u32		num_offset;
	u32		denom_offset;
};

#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)

static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
	u32 val = readl_relaxed(pll->base) & pll->power_bit;

	/* No need to wait for lock when pll is not powered up */
	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
		return 0;

	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
					  500, PLL_LOCK_TIMEOUT);
}

static int clk_pllv3_prepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	if (pll->powerup_set)
		val |= pll->power_bit;
	else
		val &= ~pll->power_bit;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static void clk_pllv3_unprepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	if (pll->powerup_set)
		val &= ~pll->power_bit;
	else
		val |= pll->power_bit;
	writel_relaxed(val, pll->base);
}

static int clk_pllv3_is_prepared(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
		return 1;

	return 0;
}

static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;

	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}

static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{
	unsigned long parent_rate = *prate;

	return (rate >= parent_rate * 22) ? parent_rate * 22 :
					    parent_rate * 20;
}

static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val, div;

	if (rate == parent_rate * 22)
		div = 1;
	else if (rate == parent_rate * 20)
		div = 0;
	else
		return -EINVAL;

	val = readl_relaxed(pll->base);
	val &= ~(pll->div_mask << pll->div_shift);
	val |= (div << pll->div_shift);
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_recalc_rate,
	.round_rate	= clk_pllv3_round_rate,
	.set_rate	= clk_pllv3_set_rate,
};

static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return parent_rate * div / 2;
}

static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 div;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;
	div = rate * 2 / parent_rate;

	return parent_rate * div / 2;
}

static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 val, div;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate * 2 / parent_rate;
	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_sys_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_sys_recalc_rate,
	.round_rate	= clk_pllv3_sys_round_rate,
	.set_rate	= clk_pllv3_sys_set_rate,
};

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	u64 temp64 = (u64)parent_rate;

	temp64 *= mfn;
	do_div(temp64, mfd);

	return parent_rate * div + (unsigned long)temp64;
}

static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 div;
	u32 mfn, mfd = 1000000;
	u32 max_mfd = 0x3FFFFFFF;
	u64 temp64;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;

	if (parent_rate <= max_mfd)
		mfd = parent_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	temp64 = div64_ul(temp64, parent_rate);
	mfn = temp64;

	temp64 = (u64)parent_rate;
	temp64 *= mfn;
	do_div(temp64, mfd);

	return parent_rate * div + (unsigned long)temp64;
}

static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 val, div;
	u32 mfn, mfd = 1000000;
	u32 max_mfd = 0x3FFFFFFF;
	u64 temp64;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	if (parent_rate <= max_mfd)
		mfd = parent_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	temp64 = div64_ul(temp64, parent_rate);
	mfn = temp64;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);
	writel_relaxed(mfn, pll->base + pll->num_offset);
	writel_relaxed(mfd, pll->base + pll->denom_offset);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_av_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_av_recalc_rate,
	.round_rate	= clk_pllv3_av_round_rate,
	.set_rate	= clk_pllv3_av_set_rate,
};

struct clk_pllv3_vf610_mf {
	u32 mfi;	/* integer part, can be 20 or 22 */
	u32 mfn;	/* numerator, 30-bit value */
	u32 mfd;	/* denominator, 30-bit value, must be less than mfn */
};

static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
		struct clk_pllv3_vf610_mf mf)
{
	u64 temp64;

	temp64 = parent_rate;
	temp64 *= mf.mfn;
	do_div(temp64, mf.mfd);

	return (parent_rate * mf.mfi) + temp64;
}

static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
		unsigned long parent_rate, unsigned long rate)
{
	struct clk_pllv3_vf610_mf mf;
	u64 temp64;

	mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
	mf.mfd = 0x3fffffff;	/* use max supported value for best accuracy */

	if (rate <= parent_rate * mf.mfi)
		mf.mfn = 0;
	else if (rate >= parent_rate * (mf.mfi + 1))
		mf.mfn = mf.mfd - 1;
	else {
		/* rate = parent_rate * (mfi + mfn/mfd) */
		temp64 = rate - parent_rate * mf.mfi;
		temp64 *= mf.mfd;
		temp64 = div64_ul(temp64, parent_rate);
		mf.mfn = temp64;
	}

	return mf;
}

static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	struct clk_pllv3_vf610_mf mf;

	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;

	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
}

static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{
	struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);

	return clk_pllv3_vf610_mf_to_rate(*prate, mf);
}

static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	struct clk_pllv3_vf610_mf mf =
			clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
	u32 val;

	val = readl_relaxed(pll->base);
	if (mf.mfi == 20)
		val &= ~pll->div_mask;	/* clear bit for mfi=20 */
	else
		val |= pll->div_mask;	/* set bit for mfi=22 */
	writel_relaxed(val, pll->base);

	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_vf610_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_vf610_recalc_rate,
	.round_rate	= clk_pllv3_vf610_round_rate,
	.set_rate	= clk_pllv3_vf610_set_rate,
};

static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	return pll->ref_clock;
}

static const struct clk_ops clk_pllv3_enet_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_enet_recalc_rate,
};

struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask)
{
	struct clk_pllv3 *pll;
	const struct clk_ops *ops;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	pll->power_bit = BM_PLL_POWER;
	pll->num_offset = PLL_NUM_OFFSET;
	pll->denom_offset = PLL_DENOM_OFFSET;

	switch (type) {
	case IMX_PLLV3_SYS:
		ops = &clk_pllv3_sys_ops;
		break;
	case IMX_PLLV3_SYS_VF610:
		ops = &clk_pllv3_vf610_ops;
		pll->num_offset = PLL_VF610_NUM_OFFSET;
		pll->denom_offset = PLL_VF610_DENOM_OFFSET;
		break;
	case IMX_PLLV3_USB_VF610:
		pll->div_shift = 1;
		fallthrough;
	case IMX_PLLV3_USB:
		ops = &clk_pllv3_ops;
		pll->powerup_set = true;
		break;
	case IMX_PLLV3_AV_IMX7:
		pll->num_offset = PLL_IMX7_NUM_OFFSET;
		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
		fallthrough;
	case IMX_PLLV3_AV:
		ops = &clk_pllv3_av_ops;
		break;
	case IMX_PLLV3_ENET_IMX7:
		pll->power_bit = IMX7_ENET_PLL_POWER;
		pll->ref_clock = 1000000000;
		ops = &clk_pllv3_enet_ops;
		break;
	case IMX_PLLV3_ENET:
		pll->ref_clock = 500000000;
		ops = &clk_pllv3_enet_ops;
		break;
	case IMX_PLLV3_DDR_IMX7:
		pll->power_bit = IMX7_DDR_PLL_POWER;
		pll->num_offset = PLL_IMX7_NUM_OFFSET;
		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
		ops = &clk_pllv3_av_ops;
		break;
	default:
		ops = &clk_pllv3_ops;
	}
	pll->base = base;
	pll->div_mask = div_mask;

	init.name = name;
	init.ops = ops;
	init.flags = 0;
	init.parent_names = &parent_name;
	init.num_parents = 1;

	pll->hw.init = &init;
	hw = &pll->hw;

	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(pll);
		return ERR_PTR(ret);
	}

	return hw;
}
EXPORT_SYMBOL_GPL(imx_clk_hw_pllv3);
Commit	Line	Data
fcaf2036	1	// SPDX-License-Identifier: GPL-2.0-or-later
a3f6b9db SG	2	/*
	3	* Copyright 2012 Freescale Semiconductor, Inc.
	4	* Copyright 2012 Linaro Ltd.
a3f6b9db SG	5	*/
a3f6b9db SG	6
a3f6b9db	7	#include <linux/clk-provider.h>
322503a1	8	#include <linux/delay.h>
64ea30d1	9	#include <linux/export.h>
a3f6b9db	10	#include <linux/io.h>
9558b51a	11	#include <linux/iopoll.h>
a3f6b9db SG	12	#include <linux/slab.h>
	13	#include <linux/jiffies.h>
	14	#include <linux/err.h>
	15	#include "clk.h"
	16
	17	#define PLL_NUM_OFFSET 0x10
	18	#define PLL_DENOM_OFFSET 0x20
b4a4cb5a AH	19	#define PLL_IMX7_NUM_OFFSET 0x20
b4a4cb5a AH	20	#define PLL_IMX7_DENOM_OFFSET 0x30
a3f6b9db	21
c77cbdd1 NY	22	#define PLL_VF610_NUM_OFFSET 0x20
	23	#define PLL_VF610_DENOM_OFFSET 0x30
	24
a3f6b9db	25	#define BM_PLL_POWER (0x1 << 12)
a3f6b9db	26	#define BM_PLL_LOCK (0x1 << 31)
f5394745	27	#define IMX7_ENET_PLL_POWER (0x1 << 5)
ad149724	28	#define IMX7_DDR_PLL_POWER (0x1 << 20)
a3f6b9db	29
9558b51a AH	30	#define PLL_LOCK_TIMEOUT 10000
9558b51a AH	31
a3f6b9db SG	32	/**
a3f6b9db SG	33	* struct clk_pllv3 - IMX PLL clock version 3
cca87e5c	34	* @hw: clock source
a3f6b9db	35	* @base: base address of PLL registers
c6847663 DA	36	* @power_bit: pll power bit mask
c6847663 DA	37	* @powerup_set: set power_bit to power up the PLL
a3f6b9db	38	* @div_mask: mask of divider bits
60ad8467	39	* @div_shift: shift of divider bits
cca87e5c KK	40	* @ref_clock: reference clock rate
	41	* @num_offset: num register offset
	42	* @denom_offset: denom register offset
a3f6b9db SG	43	*
	44	* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
	45	* is actually a multiplier, and always sits at bit 0.
	46	*/
	47	struct clk_pllv3 {
	48	struct clk_hw hw;
	49	void __iomem *base;
c6847663	50	u32 power_bit;
a3f6b9db	51	bool powerup_set;
a3f6b9db	52	u32 div_mask;
60ad8467	53	u32 div_shift;
585a60f2	54	unsigned long ref_clock;
b4a4cb5a AH	55	u32 num_offset;
b4a4cb5a AH	56	u32 denom_offset;
a3f6b9db SG	57	};
	58
	59	#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
	60
bc3b84da	61	static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
a3f6b9db	62	{
c6847663	63	u32 val = readl_relaxed(pll->base) & pll->power_bit;
a3f6b9db	64
bc3b84da SG	65	/* No need to wait for lock when pll is not powered up */
	66	if ((pll->powerup_set && !val) \|\| (!pll->powerup_set && val))
	67	return 0;
a3f6b9db	68
9558b51a AH	69	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
9558b51a AH	70	500, PLL_LOCK_TIMEOUT);
bc3b84da SG	71	}
	72
	73	static int clk_pllv3_prepare(struct clk_hw *hw)
	74	{
	75	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	76	u32 val;
	77
	78	val = readl_relaxed(pll->base);
bc3b84da	79	if (pll->powerup_set)
c6847663	80	val \|= pll->power_bit;
0a036388	81	else
c6847663	82	val &= ~pll->power_bit;
bc3b84da SG	83	writel_relaxed(val, pll->base);
bc3b84da SG	84
c400f7a2	85	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	86	}
	87
	88	static void clk_pllv3_unprepare(struct clk_hw *hw)
	89	{
	90	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	91	u32 val;
	92
	93	val = readl_relaxed(pll->base);
a3f6b9db	94	if (pll->powerup_set)
c6847663	95	val &= ~pll->power_bit;
a3f6b9db	96	else
c6847663	97	val \|= pll->power_bit;
a3f6b9db SG	98	writel_relaxed(val, pll->base);
	99	}
	100
4824b61c BP	101	static int clk_pllv3_is_prepared(struct clk_hw *hw)
	102	{
	103	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	104
	105	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
	106	return 1;
	107
	108	return 0;
	109	}
	110
a3f6b9db SG	111	static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
	112	unsigned long parent_rate)
	113	{
	114	struct clk_pllv3 *pll = to_clk_pllv3(hw);
60ad8467	115	u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
a3f6b9db SG	116
	117	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
	118	}
	119
	120	static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
	121	unsigned long *prate)
	122	{
	123	unsigned long parent_rate = *prate;
	124
	125	return (rate >= parent_rate * 22) ? parent_rate * 22 :
	126	parent_rate * 20;
	127	}
	128
	129	static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
	130	unsigned long parent_rate)
	131	{
	132	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	133	u32 val, div;
	134
	135	if (rate == parent_rate * 22)
	136	div = 1;
	137	else if (rate == parent_rate * 20)
	138	div = 0;
	139	else
	140	return -EINVAL;
	141
	142	val = readl_relaxed(pll->base);
60ad8467 SA	143	val &= ~(pll->div_mask << pll->div_shift);
60ad8467 SA	144	val \|= (div << pll->div_shift);
a3f6b9db SG	145	writel_relaxed(val, pll->base);
a3f6b9db SG	146
bc3b84da	147	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	148	}
	149
	150	static const struct clk_ops clk_pllv3_ops = {
	151	.prepare = clk_pllv3_prepare,
	152	.unprepare = clk_pllv3_unprepare,
4824b61c	153	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	154	.recalc_rate = clk_pllv3_recalc_rate,
	155	.round_rate = clk_pllv3_round_rate,
	156	.set_rate = clk_pllv3_set_rate,
	157	};
	158
	159	static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
	160	unsigned long parent_rate)
	161	{
	162	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	163	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	164
	165	return parent_rate * div / 2;
	166	}
	167
	168	static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
	169	unsigned long *prate)
	170	{
	171	unsigned long parent_rate = *prate;
	172	unsigned long min_rate = parent_rate * 54 / 2;
	173	unsigned long max_rate = parent_rate * 108 / 2;
	174	u32 div;
	175
	176	if (rate > max_rate)
	177	rate = max_rate;
	178	else if (rate < min_rate)
	179	rate = min_rate;
	180	div = rate * 2 / parent_rate;
	181
	182	return parent_rate * div / 2;
	183	}
	184
	185	static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
	186	unsigned long parent_rate)
	187	{
	188	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	189	unsigned long min_rate = parent_rate * 54 / 2;
	190	unsigned long max_rate = parent_rate * 108 / 2;
	191	u32 val, div;
	192
	193	if (rate < min_rate \|\| rate > max_rate)
	194	return -EINVAL;
	195
	196	div = rate * 2 / parent_rate;
	197	val = readl_relaxed(pll->base);
	198	val &= ~pll->div_mask;
	199	val \|= div;
	200	writel_relaxed(val, pll->base);
	201
bc3b84da	202	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	203	}
	204
	205	static const struct clk_ops clk_pllv3_sys_ops = {
	206	.prepare = clk_pllv3_prepare,
	207	.unprepare = clk_pllv3_unprepare,
4824b61c	208	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	209	.recalc_rate = clk_pllv3_sys_recalc_rate,
	210	.round_rate = clk_pllv3_sys_round_rate,
	211	.set_rate = clk_pllv3_sys_set_rate,
	212	};
	213
	214	static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
	215	unsigned long parent_rate)
	216	{
	217	struct clk_pllv3 *pll = to_clk_pllv3(hw);
b4a4cb5a AH	218	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
b4a4cb5a AH	219	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
a3f6b9db	220	u32 div = readl_relaxed(pll->base) & pll->div_mask;
ba7f4f55	221	u64 temp64 = (u64)parent_rate;
a3f6b9db	222
ba7f4f55 AH	223	temp64 *= mfn;
	224	do_div(temp64, mfd);
	225
5c2f117a	226	return parent_rate * div + (unsigned long)temp64;
a3f6b9db SG	227	}
	228
	229	static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
	230	unsigned long *prate)
	231	{
	232	unsigned long parent_rate = *prate;
	233	unsigned long min_rate = parent_rate * 27;
	234	unsigned long max_rate = parent_rate * 54;
	235	u32 div;
	236	u32 mfn, mfd = 1000000;
c5a8045a	237	u32 max_mfd = 0x3FFFFFFF;
7a5568ce	238	u64 temp64;
a3f6b9db SG	239
	240	if (rate > max_rate)
	241	rate = max_rate;
	242	else if (rate < min_rate)
	243	rate = min_rate;
	244
c5a8045a EL	245	if (parent_rate <= max_mfd)
	246	mfd = parent_rate;
	247
a3f6b9db SG	248	div = rate / parent_rate;
	249	temp64 = (u64) (rate - div * parent_rate);
	250	temp64 *= mfd;
c1b6ad9a	251	temp64 = div64_ul(temp64, parent_rate);
a3f6b9db SG	252	mfn = temp64;
a3f6b9db SG	253
5c2f117a EL	254	temp64 = (u64)parent_rate;
	255	temp64 *= mfn;
	256	do_div(temp64, mfd);
	257
	258	return parent_rate * div + (unsigned long)temp64;
a3f6b9db SG	259	}
	260
	261	static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
	262	unsigned long parent_rate)
	263	{
	264	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	265	unsigned long min_rate = parent_rate * 27;
	266	unsigned long max_rate = parent_rate * 54;
	267	u32 val, div;
	268	u32 mfn, mfd = 1000000;
c5a8045a	269	u32 max_mfd = 0x3FFFFFFF;
7a5568ce	270	u64 temp64;
a3f6b9db SG	271
	272	if (rate < min_rate \|\| rate > max_rate)
	273	return -EINVAL;
	274
c5a8045a EL	275	if (parent_rate <= max_mfd)
	276	mfd = parent_rate;
	277
a3f6b9db SG	278	div = rate / parent_rate;
	279	temp64 = (u64) (rate - div * parent_rate);
	280	temp64 *= mfd;
c1b6ad9a	281	temp64 = div64_ul(temp64, parent_rate);
a3f6b9db SG	282	mfn = temp64;
	283
	284	val = readl_relaxed(pll->base);
	285	val &= ~pll->div_mask;
	286	val \|= div;
	287	writel_relaxed(val, pll->base);
b4a4cb5a AH	288	writel_relaxed(mfn, pll->base + pll->num_offset);
b4a4cb5a AH	289	writel_relaxed(mfd, pll->base + pll->denom_offset);
a3f6b9db	290
bc3b84da	291	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	292	}
	293
	294	static const struct clk_ops clk_pllv3_av_ops = {
	295	.prepare = clk_pllv3_prepare,
	296	.unprepare = clk_pllv3_unprepare,
4824b61c	297	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	298	.recalc_rate = clk_pllv3_av_recalc_rate,
	299	.round_rate = clk_pllv3_av_round_rate,
	300	.set_rate = clk_pllv3_av_set_rate,
	301	};
	302
c77cbdd1 NY	303	struct clk_pllv3_vf610_mf {
	304	u32 mfi; /* integer part, can be 20 or 22 */
	305	u32 mfn; /* numerator, 30-bit value */
	306	u32 mfd; /* denominator, 30-bit value, must be less than mfn */
	307	};
	308
	309	static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
	310	struct clk_pllv3_vf610_mf mf)
	311	{
	312	u64 temp64;
	313
	314	temp64 = parent_rate;
	315	temp64 *= mf.mfn;
	316	do_div(temp64, mf.mfd);
	317
	318	return (parent_rate * mf.mfi) + temp64;
	319	}
	320
	321	static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
	322	unsigned long parent_rate, unsigned long rate)
	323	{
	324	struct clk_pllv3_vf610_mf mf;
	325	u64 temp64;
	326
	327	mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
	328	mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */
	329
	330	if (rate <= parent_rate * mf.mfi)
	331	mf.mfn = 0;
	332	else if (rate >= parent_rate * (mf.mfi + 1))
	333	mf.mfn = mf.mfd - 1;
	334	else {
	335	/* rate = parent_rate * (mfi + mfn/mfd) */
	336	temp64 = rate - parent_rate * mf.mfi;
	337	temp64 *= mf.mfd;
c1b6ad9a	338	temp64 = div64_ul(temp64, parent_rate);
c77cbdd1 NY	339	mf.mfn = temp64;
	340	}
	341
	342	return mf;
	343	}
	344
	345	static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
	346	unsigned long parent_rate)
	347	{
	348	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	349	struct clk_pllv3_vf610_mf mf;
	350
b4a4cb5a AH	351	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
b4a4cb5a AH	352	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
c77cbdd1 NY	353	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
	354
	355	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
	356	}
	357
	358	static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
	359	unsigned long *prate)
	360	{
	361	struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
	362
	363	return clk_pllv3_vf610_mf_to_rate(*prate, mf);
	364	}
	365
	366	static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
	367	unsigned long parent_rate)
	368	{
	369	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	370	struct clk_pllv3_vf610_mf mf =
	371	clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
	372	u32 val;
	373
	374	val = readl_relaxed(pll->base);
	375	if (mf.mfi == 20)
	376	val &= ~pll->div_mask; /* clear bit for mfi=20 */
	377	else
	378	val \|= pll->div_mask; /* set bit for mfi=22 */
	379	writel_relaxed(val, pll->base);
	380
b4a4cb5a AH	381	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
b4a4cb5a AH	382	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
c77cbdd1 NY	383
	384	return clk_pllv3_wait_lock(pll);
	385	}
	386
	387	static const struct clk_ops clk_pllv3_vf610_ops = {
	388	.prepare = clk_pllv3_prepare,
	389	.unprepare = clk_pllv3_unprepare,
	390	.is_prepared = clk_pllv3_is_prepared,
	391	.recalc_rate = clk_pllv3_vf610_recalc_rate,
	392	.round_rate = clk_pllv3_vf610_round_rate,
	393	.set_rate = clk_pllv3_vf610_set_rate,
	394	};
	395
a3f6b9db SG	396	static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
	397	unsigned long parent_rate)
	398	{
585a60f2 SA	399	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	400
	401	return pll->ref_clock;
a3f6b9db SG	402	}
	403
	404	static const struct clk_ops clk_pllv3_enet_ops = {
	405	.prepare = clk_pllv3_prepare,
	406	.unprepare = clk_pllv3_unprepare,
4824b61c	407	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db	408	.recalc_rate = clk_pllv3_enet_recalc_rate,
a3f6b9db SG	409	};
a3f6b9db SG	410
e5674a4d	411	struct clk_hw imx_clk_hw_pllv3(enum imx_pllv3_type type, const char name,
a3f6b9db	412	const char parent_name, void __iomem base,
2b254693	413	u32 div_mask)
a3f6b9db SG	414	{
	415	struct clk_pllv3 *pll;
	416	const struct clk_ops *ops;
e5674a4d	417	struct clk_hw *hw;
a3f6b9db	418	struct clk_init_data init;
e5674a4d	419	int ret;
a3f6b9db SG	420
	421	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	422	if (!pll)
	423	return ERR_PTR(-ENOMEM);
	424
c6847663	425	pll->power_bit = BM_PLL_POWER;
b4a4cb5a AH	426	pll->num_offset = PLL_NUM_OFFSET;
b4a4cb5a AH	427	pll->denom_offset = PLL_DENOM_OFFSET;
f5394745	428
a3f6b9db SG	429	switch (type) {
	430	case IMX_PLLV3_SYS:
	431	ops = &clk_pllv3_sys_ops;
	432	break;
c77cbdd1 NY	433	case IMX_PLLV3_SYS_VF610:
c77cbdd1 NY	434	ops = &clk_pllv3_vf610_ops;
b4a4cb5a AH	435	pll->num_offset = PLL_VF610_NUM_OFFSET;
b4a4cb5a AH	436	pll->denom_offset = PLL_VF610_DENOM_OFFSET;
c77cbdd1	437	break;
60ad8467 SA	438	case IMX_PLLV3_USB_VF610:
60ad8467 SA	439	pll->div_shift = 1;
d388e18f	440	fallthrough;
a3f6b9db SG	441	case IMX_PLLV3_USB:
	442	ops = &clk_pllv3_ops;
	443	pll->powerup_set = true;
	444	break;
b4a4cb5a AH	445	case IMX_PLLV3_AV_IMX7:
	446	pll->num_offset = PLL_IMX7_NUM_OFFSET;
	447	pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
d388e18f	448	fallthrough;
a3f6b9db SG	449	case IMX_PLLV3_AV:
	450	ops = &clk_pllv3_av_ops;
	451	break;
f5394745	452	case IMX_PLLV3_ENET_IMX7:
c6847663	453	pll->power_bit = IMX7_ENET_PLL_POWER;
585a60f2 SA	454	pll->ref_clock = 1000000000;
	455	ops = &clk_pllv3_enet_ops;
	456	break;
a3f6b9db	457	case IMX_PLLV3_ENET:
585a60f2	458	pll->ref_clock = 500000000;
a3f6b9db SG	459	ops = &clk_pllv3_enet_ops;
a3f6b9db SG	460	break;
ad149724	461	case IMX_PLLV3_DDR_IMX7:
b608a892	462	pll->power_bit = IMX7_DDR_PLL_POWER;
b4a4cb5a AH	463	pll->num_offset = PLL_IMX7_NUM_OFFSET;
b4a4cb5a AH	464	pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
ad149724 FE	465	ops = &clk_pllv3_av_ops;
ad149724 FE	466	break;
a3f6b9db SG	467	default:
	468	ops = &clk_pllv3_ops;
	469	}
	470	pll->base = base;
a3f6b9db SG	471	pll->div_mask = div_mask;
	472
	473	init.name = name;
	474	init.ops = ops;
	475	init.flags = 0;
	476	init.parent_names = &parent_name;
	477	init.num_parents = 1;
	478
	479	pll->hw.init = &init;
e5674a4d	480	hw = &pll->hw;
a3f6b9db	481
e5674a4d AV	482	ret = clk_hw_register(NULL, hw);
e5674a4d AV	483	if (ret) {
a3f6b9db	484	kfree(pll);
e5674a4d AV	485	return ERR_PTR(ret);
e5674a4d AV	486	}
a3f6b9db	487
e5674a4d	488	return hw;
a3f6b9db	489	}
64ea30d1	490	EXPORT_SYMBOL_GPL(imx_clk_hw_pllv3);