[linux-2.6-block.git] / drivers / clk / imx / clk-pllv3.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2012 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include "clk.h"

#define PLL_NUM_OFFSET		0x10
#define PLL_DENOM_OFFSET	0x20

#define BM_PLL_POWER		(0x1 << 12)
#define BM_PLL_LOCK		(0x1 << 31)
#define IMX7_ENET_PLL_POWER	(0x1 << 5)

/**
 * struct clk_pllv3 - IMX PLL clock version 3
 * @clk_hw:	 clock source
 * @base:	 base address of PLL registers
 * @power_bit:	 pll power bit mask
 * @powerup_set: set power_bit to power up the PLL
 * @div_mask:	 mask of divider bits
 * @div_shift:	 shift of divider bits
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
 * is actually a multiplier, and always sits at bit 0.
 */
struct clk_pllv3 {
	struct clk_hw	hw;
	void __iomem	*base;
	u32		power_bit;
	bool		powerup_set;
	u32		div_mask;
	u32		div_shift;
	unsigned long	ref_clock;
};

#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)

static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(10);
	u32 val = readl_relaxed(pll->base) & pll->power_bit;

	/* No need to wait for lock when pll is not powered up */
	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
		return 0;

	/* Wait for PLL to lock */
	do {
		if (readl_relaxed(pll->base) & BM_PLL_LOCK)
			break;
		if (time_after(jiffies, timeout))
			break;
		usleep_range(50, 500);
	} while (1);

	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
}

static int clk_pllv3_prepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	if (pll->powerup_set)
		val |= pll->power_bit;
	else
		val &= ~pll->power_bit;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static void clk_pllv3_unprepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	if (pll->powerup_set)
		val &= ~pll->power_bit;
	else
		val |= pll->power_bit;
	writel_relaxed(val, pll->base);
}

static int clk_pllv3_is_prepared(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
		return 1;

	return 0;
}

static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;

	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}

static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{
	unsigned long parent_rate = *prate;

	return (rate >= parent_rate * 22) ? parent_rate * 22 :
					    parent_rate * 20;
}

static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val, div;

	if (rate == parent_rate * 22)
		div = 1;
	else if (rate == parent_rate * 20)
		div = 0;
	else
		return -EINVAL;

	val = readl_relaxed(pll->base);
	val &= ~(pll->div_mask << pll->div_shift);
	val |= (div << pll->div_shift);
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_recalc_rate,
	.round_rate	= clk_pllv3_round_rate,
	.set_rate	= clk_pllv3_set_rate,
};

static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return parent_rate * div / 2;
}

static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 div;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;
	div = rate * 2 / parent_rate;

	return parent_rate * div / 2;
}

static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 val, div;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate * 2 / parent_rate;
	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_sys_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_sys_recalc_rate,
	.round_rate	= clk_pllv3_sys_round_rate,
	.set_rate	= clk_pllv3_sys_set_rate,
};

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	u64 temp64 = (u64)parent_rate;

	temp64 *= mfn;
	do_div(temp64, mfd);

	return parent_rate * div + (unsigned long)temp64;
}

static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 div;
	u32 mfn, mfd = 1000000;
	u32 max_mfd = 0x3FFFFFFF;
	u64 temp64;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;

	if (parent_rate <= max_mfd)
		mfd = parent_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	temp64 = (u64)parent_rate;
	temp64 *= mfn;
	do_div(temp64, mfd);

	return parent_rate * div + (unsigned long)temp64;
}

static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 val, div;
	u32 mfn, mfd = 1000000;
	u32 max_mfd = 0x3FFFFFFF;
	u64 temp64;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	if (parent_rate <= max_mfd)
		mfd = parent_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);
	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_av_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_av_recalc_rate,
	.round_rate	= clk_pllv3_av_round_rate,
	.set_rate	= clk_pllv3_av_set_rate,
};

static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	return pll->ref_clock;
}

static const struct clk_ops clk_pllv3_enet_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.is_prepared	= clk_pllv3_is_prepared,
	.recalc_rate	= clk_pllv3_enet_recalc_rate,
};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask)
{
	struct clk_pllv3 *pll;
	const struct clk_ops *ops;
	struct clk *clk;
	struct clk_init_data init;

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	pll->power_bit = BM_PLL_POWER;

	switch (type) {
	case IMX_PLLV3_SYS:
		ops = &clk_pllv3_sys_ops;
		break;
	case IMX_PLLV3_USB_VF610:
		pll->div_shift = 1;
	case IMX_PLLV3_USB:
		ops = &clk_pllv3_ops;
		pll->powerup_set = true;
		break;
	case IMX_PLLV3_AV:
		ops = &clk_pllv3_av_ops;
		break;
	case IMX_PLLV3_ENET_IMX7:
		pll->power_bit = IMX7_ENET_PLL_POWER;
		pll->ref_clock = 1000000000;
		ops = &clk_pllv3_enet_ops;
		break;
	case IMX_PLLV3_ENET:
		pll->ref_clock = 500000000;
		ops = &clk_pllv3_enet_ops;
		break;
	default:
		ops = &clk_pllv3_ops;
	}
	pll->base = base;
	pll->div_mask = div_mask;

	init.name = name;
	init.ops = ops;
	init.flags = 0;
	init.parent_names = &parent_name;
	init.num_parents = 1;

	pll->hw.init = &init;

	clk = clk_register(NULL, &pll->hw);
	if (IS_ERR(clk))
		kfree(pll);

	return clk;
}
Commit	Line	Data
a3f6b9db SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Copyright 2012 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a3f6b9db	13	#include <linux/clk-provider.h>
322503a1	14	#include <linux/delay.h>
a3f6b9db SG	15	#include <linux/io.h>
	16	#include <linux/slab.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/err.h>
	19	#include "clk.h"
	20
	21	#define PLL_NUM_OFFSET 0x10
	22	#define PLL_DENOM_OFFSET 0x20
	23
	24	#define BM_PLL_POWER (0x1 << 12)
a3f6b9db	25	#define BM_PLL_LOCK (0x1 << 31)
f5394745	26	#define IMX7_ENET_PLL_POWER (0x1 << 5)
a3f6b9db SG	27
	28	/**
	29	* struct clk_pllv3 - IMX PLL clock version 3
	30	* @clk_hw: clock source
	31	* @base: base address of PLL registers
c6847663 DA	32	* @power_bit: pll power bit mask
c6847663 DA	33	* @powerup_set: set power_bit to power up the PLL
a3f6b9db	34	* @div_mask: mask of divider bits
60ad8467	35	* @div_shift: shift of divider bits
a3f6b9db SG	36	*
	37	* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
	38	* is actually a multiplier, and always sits at bit 0.
	39	*/
	40	struct clk_pllv3 {
	41	struct clk_hw hw;
	42	void __iomem *base;
c6847663	43	u32 power_bit;
a3f6b9db	44	bool powerup_set;
a3f6b9db	45	u32 div_mask;
60ad8467	46	u32 div_shift;
585a60f2	47	unsigned long ref_clock;
a3f6b9db SG	48	};
	49
	50	#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
	51
bc3b84da	52	static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
a3f6b9db	53	{
bc3b84da	54	unsigned long timeout = jiffies + msecs_to_jiffies(10);
c6847663	55	u32 val = readl_relaxed(pll->base) & pll->power_bit;
a3f6b9db	56
bc3b84da SG	57	/* No need to wait for lock when pll is not powered up */
	58	if ((pll->powerup_set && !val) \|\| (!pll->powerup_set && val))
	59	return 0;
a3f6b9db SG	60
a3f6b9db SG	61	/* Wait for PLL to lock */
0a036388 PC	62	do {
	63	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
	64	break;
a3f6b9db	65	if (time_after(jiffies, timeout))
0a036388	66	break;
322503a1	67	usleep_range(50, 500);
0a036388	68	} while (1);
a3f6b9db	69
bc3b84da SG	70	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
	71	}
	72
	73	static int clk_pllv3_prepare(struct clk_hw *hw)
	74	{
	75	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	76	u32 val;
	77
	78	val = readl_relaxed(pll->base);
bc3b84da	79	if (pll->powerup_set)
c6847663	80	val \|= pll->power_bit;
0a036388	81	else
c6847663	82	val &= ~pll->power_bit;
bc3b84da SG	83	writel_relaxed(val, pll->base);
bc3b84da SG	84
c400f7a2	85	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	86	}
	87
	88	static void clk_pllv3_unprepare(struct clk_hw *hw)
	89	{
	90	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	91	u32 val;
	92
	93	val = readl_relaxed(pll->base);
a3f6b9db	94	if (pll->powerup_set)
c6847663	95	val &= ~pll->power_bit;
a3f6b9db	96	else
c6847663	97	val \|= pll->power_bit;
a3f6b9db SG	98	writel_relaxed(val, pll->base);
	99	}
	100
4824b61c BP	101	static int clk_pllv3_is_prepared(struct clk_hw *hw)
	102	{
	103	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	104
	105	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
	106	return 1;
	107
	108	return 0;
	109	}
	110
a3f6b9db SG	111	static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
	112	unsigned long parent_rate)
	113	{
	114	struct clk_pllv3 *pll = to_clk_pllv3(hw);
60ad8467	115	u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
a3f6b9db SG	116
	117	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
	118	}
	119
	120	static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
	121	unsigned long *prate)
	122	{
	123	unsigned long parent_rate = *prate;
	124
	125	return (rate >= parent_rate * 22) ? parent_rate * 22 :
	126	parent_rate * 20;
	127	}
	128
	129	static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
	130	unsigned long parent_rate)
	131	{
	132	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	133	u32 val, div;
	134
	135	if (rate == parent_rate * 22)
	136	div = 1;
	137	else if (rate == parent_rate * 20)
	138	div = 0;
	139	else
	140	return -EINVAL;
	141
	142	val = readl_relaxed(pll->base);
60ad8467 SA	143	val &= ~(pll->div_mask << pll->div_shift);
60ad8467 SA	144	val \|= (div << pll->div_shift);
a3f6b9db SG	145	writel_relaxed(val, pll->base);
a3f6b9db SG	146
bc3b84da	147	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	148	}
	149
	150	static const struct clk_ops clk_pllv3_ops = {
	151	.prepare = clk_pllv3_prepare,
	152	.unprepare = clk_pllv3_unprepare,
4824b61c	153	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	154	.recalc_rate = clk_pllv3_recalc_rate,
	155	.round_rate = clk_pllv3_round_rate,
	156	.set_rate = clk_pllv3_set_rate,
	157	};
	158
	159	static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
	160	unsigned long parent_rate)
	161	{
	162	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	163	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	164
	165	return parent_rate * div / 2;
	166	}
	167
	168	static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
	169	unsigned long *prate)
	170	{
	171	unsigned long parent_rate = *prate;
	172	unsigned long min_rate = parent_rate * 54 / 2;
	173	unsigned long max_rate = parent_rate * 108 / 2;
	174	u32 div;
	175
	176	if (rate > max_rate)
	177	rate = max_rate;
	178	else if (rate < min_rate)
	179	rate = min_rate;
	180	div = rate * 2 / parent_rate;
	181
	182	return parent_rate * div / 2;
	183	}
	184
	185	static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
	186	unsigned long parent_rate)
	187	{
	188	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	189	unsigned long min_rate = parent_rate * 54 / 2;
	190	unsigned long max_rate = parent_rate * 108 / 2;
	191	u32 val, div;
	192
	193	if (rate < min_rate \|\| rate > max_rate)
	194	return -EINVAL;
	195
	196	div = rate * 2 / parent_rate;
	197	val = readl_relaxed(pll->base);
	198	val &= ~pll->div_mask;
	199	val \|= div;
	200	writel_relaxed(val, pll->base);
	201
bc3b84da	202	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	203	}
	204
	205	static const struct clk_ops clk_pllv3_sys_ops = {
	206	.prepare = clk_pllv3_prepare,
	207	.unprepare = clk_pllv3_unprepare,
4824b61c	208	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	209	.recalc_rate = clk_pllv3_sys_recalc_rate,
	210	.round_rate = clk_pllv3_sys_round_rate,
	211	.set_rate = clk_pllv3_sys_set_rate,
	212	};
	213
	214	static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
	215	unsigned long parent_rate)
	216	{
	217	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	218	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	219	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	220	u32 div = readl_relaxed(pll->base) & pll->div_mask;
ba7f4f55	221	u64 temp64 = (u64)parent_rate;
a3f6b9db	222
ba7f4f55 AH	223	temp64 *= mfn;
	224	do_div(temp64, mfd);
	225
5c2f117a	226	return parent_rate * div + (unsigned long)temp64;
a3f6b9db SG	227	}
	228
	229	static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
	230	unsigned long *prate)
	231	{
	232	unsigned long parent_rate = *prate;
	233	unsigned long min_rate = parent_rate * 27;
	234	unsigned long max_rate = parent_rate * 54;
	235	u32 div;
	236	u32 mfn, mfd = 1000000;
c5a8045a	237	u32 max_mfd = 0x3FFFFFFF;
7a5568ce	238	u64 temp64;
a3f6b9db SG	239
	240	if (rate > max_rate)
	241	rate = max_rate;
	242	else if (rate < min_rate)
	243	rate = min_rate;
	244
c5a8045a EL	245	if (parent_rate <= max_mfd)
	246	mfd = parent_rate;
	247
a3f6b9db SG	248	div = rate / parent_rate;
	249	temp64 = (u64) (rate - div * parent_rate);
	250	temp64 *= mfd;
	251	do_div(temp64, parent_rate);
	252	mfn = temp64;
	253
5c2f117a EL	254	temp64 = (u64)parent_rate;
	255	temp64 *= mfn;
	256	do_div(temp64, mfd);
	257
	258	return parent_rate * div + (unsigned long)temp64;
a3f6b9db SG	259	}
	260
	261	static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
	262	unsigned long parent_rate)
	263	{
	264	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	265	unsigned long min_rate = parent_rate * 27;
	266	unsigned long max_rate = parent_rate * 54;
	267	u32 val, div;
	268	u32 mfn, mfd = 1000000;
c5a8045a	269	u32 max_mfd = 0x3FFFFFFF;
7a5568ce	270	u64 temp64;
a3f6b9db SG	271
	272	if (rate < min_rate \|\| rate > max_rate)
	273	return -EINVAL;
	274
c5a8045a EL	275	if (parent_rate <= max_mfd)
	276	mfd = parent_rate;
	277
a3f6b9db SG	278	div = rate / parent_rate;
	279	temp64 = (u64) (rate - div * parent_rate);
	280	temp64 *= mfd;
	281	do_div(temp64, parent_rate);
	282	mfn = temp64;
	283
	284	val = readl_relaxed(pll->base);
	285	val &= ~pll->div_mask;
	286	val \|= div;
	287	writel_relaxed(val, pll->base);
	288	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
	289	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
	290
bc3b84da	291	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	292	}
	293
	294	static const struct clk_ops clk_pllv3_av_ops = {
	295	.prepare = clk_pllv3_prepare,
	296	.unprepare = clk_pllv3_unprepare,
4824b61c	297	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db SG	298	.recalc_rate = clk_pllv3_av_recalc_rate,
	299	.round_rate = clk_pllv3_av_round_rate,
	300	.set_rate = clk_pllv3_av_set_rate,
	301	};
	302
	303	static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
	304	unsigned long parent_rate)
	305	{
585a60f2 SA	306	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	307
	308	return pll->ref_clock;
a3f6b9db SG	309	}
	310
	311	static const struct clk_ops clk_pllv3_enet_ops = {
	312	.prepare = clk_pllv3_prepare,
	313	.unprepare = clk_pllv3_unprepare,
4824b61c	314	.is_prepared = clk_pllv3_is_prepared,
a3f6b9db	315	.recalc_rate = clk_pllv3_enet_recalc_rate,
a3f6b9db SG	316	};
a3f6b9db SG	317
a3f6b9db SG	318	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
a3f6b9db SG	319	const char parent_name, void __iomem base,
2b254693	320	u32 div_mask)
a3f6b9db SG	321	{
	322	struct clk_pllv3 *pll;
	323	const struct clk_ops *ops;
	324	struct clk *clk;
	325	struct clk_init_data init;
	326
	327	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	328	if (!pll)
	329	return ERR_PTR(-ENOMEM);
	330
c6847663	331	pll->power_bit = BM_PLL_POWER;
f5394745	332
a3f6b9db SG	333	switch (type) {
	334	case IMX_PLLV3_SYS:
	335	ops = &clk_pllv3_sys_ops;
	336	break;
60ad8467 SA	337	case IMX_PLLV3_USB_VF610:
60ad8467 SA	338	pll->div_shift = 1;
a3f6b9db SG	339	case IMX_PLLV3_USB:
	340	ops = &clk_pllv3_ops;
	341	pll->powerup_set = true;
	342	break;
	343	case IMX_PLLV3_AV:
	344	ops = &clk_pllv3_av_ops;
	345	break;
f5394745	346	case IMX_PLLV3_ENET_IMX7:
c6847663	347	pll->power_bit = IMX7_ENET_PLL_POWER;
585a60f2 SA	348	pll->ref_clock = 1000000000;
	349	ops = &clk_pllv3_enet_ops;
	350	break;
a3f6b9db	351	case IMX_PLLV3_ENET:
585a60f2	352	pll->ref_clock = 500000000;
a3f6b9db SG	353	ops = &clk_pllv3_enet_ops;
a3f6b9db SG	354	break;
a3f6b9db SG	355	default:
	356	ops = &clk_pllv3_ops;
	357	}
	358	pll->base = base;
a3f6b9db SG	359	pll->div_mask = div_mask;
	360
	361	init.name = name;
	362	init.ops = ops;
	363	init.flags = 0;
	364	init.parent_names = &parent_name;
	365	init.num_parents = 1;
	366
	367	pll->hw.init = &init;
	368
	369	clk = clk_register(NULL, &pll->hw);
	370	if (IS_ERR(clk))
	371	kfree(pll);
	372
	373	return clk;
	374	}