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b8d4176f SH |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | #include <linux/mm.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clkdev.h> | |
4d9d18a5 | 14 | #include <linux/clk-provider.h> |
b8d4176f | 15 | #include <linux/err.h> |
bfcc7bce FE |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
0c831317 | 19 | #include <soc/imx/revision.h> |
490dd880 | 20 | #include <dt-bindings/clock/imx5-clock.h> |
b8d4176f | 21 | |
b8d4176f SH |
22 | #include "clk.h" |
23 | ||
20484c13 SG |
24 | #define MX51_DPLL1_BASE 0x83f80000 |
25 | #define MX51_DPLL2_BASE 0x83f84000 | |
26 | #define MX51_DPLL3_BASE 0x83f88000 | |
27 | ||
28 | #define MX53_DPLL1_BASE 0x63f80000 | |
29 | #define MX53_DPLL2_BASE 0x63f84000 | |
30 | #define MX53_DPLL3_BASE 0x63f88000 | |
31 | #define MX53_DPLL4_BASE 0x63f8c000 | |
e7d5eb3c | 32 | |
18c1d989 SG |
33 | #define MXC_CCM_CCR (ccm_base + 0x00) |
34 | #define MXC_CCM_CCDR (ccm_base + 0x04) | |
35 | #define MXC_CCM_CSR (ccm_base + 0x08) | |
36 | #define MXC_CCM_CCSR (ccm_base + 0x0c) | |
37 | #define MXC_CCM_CACRR (ccm_base + 0x10) | |
38 | #define MXC_CCM_CBCDR (ccm_base + 0x14) | |
39 | #define MXC_CCM_CBCMR (ccm_base + 0x18) | |
40 | #define MXC_CCM_CSCMR1 (ccm_base + 0x1c) | |
41 | #define MXC_CCM_CSCMR2 (ccm_base + 0x20) | |
42 | #define MXC_CCM_CSCDR1 (ccm_base + 0x24) | |
43 | #define MXC_CCM_CS1CDR (ccm_base + 0x28) | |
44 | #define MXC_CCM_CS2CDR (ccm_base + 0x2c) | |
45 | #define MXC_CCM_CDCDR (ccm_base + 0x30) | |
46 | #define MXC_CCM_CHSCDR (ccm_base + 0x34) | |
47 | #define MXC_CCM_CSCDR2 (ccm_base + 0x38) | |
48 | #define MXC_CCM_CSCDR3 (ccm_base + 0x3c) | |
49 | #define MXC_CCM_CSCDR4 (ccm_base + 0x40) | |
50 | #define MXC_CCM_CWDR (ccm_base + 0x44) | |
51 | #define MXC_CCM_CDHIPR (ccm_base + 0x48) | |
52 | #define MXC_CCM_CDCR (ccm_base + 0x4c) | |
53 | #define MXC_CCM_CTOR (ccm_base + 0x50) | |
54 | #define MXC_CCM_CLPCR (ccm_base + 0x54) | |
55 | #define MXC_CCM_CISR (ccm_base + 0x58) | |
56 | #define MXC_CCM_CIMR (ccm_base + 0x5c) | |
57 | #define MXC_CCM_CCOSR (ccm_base + 0x60) | |
58 | #define MXC_CCM_CGPR (ccm_base + 0x64) | |
59 | #define MXC_CCM_CCGR0 (ccm_base + 0x68) | |
60 | #define MXC_CCM_CCGR1 (ccm_base + 0x6c) | |
61 | #define MXC_CCM_CCGR2 (ccm_base + 0x70) | |
62 | #define MXC_CCM_CCGR3 (ccm_base + 0x74) | |
63 | #define MXC_CCM_CCGR4 (ccm_base + 0x78) | |
64 | #define MXC_CCM_CCGR5 (ccm_base + 0x7c) | |
65 | #define MXC_CCM_CCGR6 (ccm_base + 0x80) | |
66 | #define MXC_CCM_CCGR7 (ccm_base + 0x84) | |
e7d5eb3c | 67 | |
b8d4176f SH |
68 | /* Low-power Audio Playback Mode clock */ |
69 | static const char *lp_apm_sel[] = { "osc", }; | |
70 | ||
71 | /* This is used multiple times */ | |
72 | static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", }; | |
73 | static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", }; | |
74 | static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", }; | |
75 | static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", }; | |
76 | static const char *per_root_sel[] = { "per_podf", "ipg", }; | |
77 | static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
78 | static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
13b3a07a SG |
79 | static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", }; |
80 | static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", }; | |
81 | static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", }; | |
82 | static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", }; | |
83 | static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; | |
b8d4176f SH |
84 | static const char *emi_slow_sel[] = { "main_bus", "ahb", }; |
85 | static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; | |
86 | static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; | |
51f66191 | 87 | static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; |
b8d4176f SH |
88 | static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; |
89 | static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; | |
51f66191 | 90 | static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; |
b8d4176f SH |
91 | static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; |
92 | static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; | |
93 | static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; | |
3f487bed | 94 | static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", }; |
b8d4176f | 95 | static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
8ecb167f PZ |
96 | static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; |
97 | static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; | |
b8d4176f | 98 | static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
a745f039 | 99 | static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; |
04b41e84 MF |
100 | static const char *mx53_cko1_sel[] = { |
101 | "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw", | |
102 | "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy", | |
103 | "di_pred", "dummy", "dummy", "ahb", | |
104 | "ipg", "per_root", "ckil", "dummy",}; | |
105 | static const char *mx53_cko2_sel[] = { | |
106 | "dummy"/* dptc_core */, "dummy"/* dptc_perich */, | |
107 | "dummy", "esdhc_a_podf", | |
108 | "usboh3_podf", "dummy"/* wrck_clk_root */, | |
109 | "ecspi_podf", "dummy"/* pll1_ref_clk */, | |
110 | "esdhc_b_podf", "dummy"/* ddr_clk_root */, | |
111 | "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */, | |
112 | "vpu_sel", "ipu_sel", | |
113 | "osc", "ckih1", | |
114 | "dummy", "esdhc_c_sel", | |
115 | "ssi1_root_podf", "ssi2_root_podf", | |
116 | "dummy", "dummy", | |
117 | "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */, | |
118 | "dummy"/* tve_out */, "usb_phy_sel", | |
119 | "tve_sel", "lp_apm", | |
120 | "uart_root", "dummy"/* spdif0_clk_root */, | |
121 | "dummy", "dummy", }; | |
beb2d1c1 PZ |
122 | static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", }; |
123 | static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", }; | |
124 | static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; | |
125 | static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; | |
126 | static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; | |
6f0628aa LS |
127 | static const char *step_sels[] = { "lp_apm", }; |
128 | static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" }; | |
377d6479 | 129 | static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ }; |
beb2d1c1 | 130 | |
490dd880 | 131 | static struct clk *clk[IMX5_CLK_END]; |
f40f38d1 | 132 | static struct clk_onecell_data clk_data; |
b8d4176f | 133 | |
a275b315 FE |
134 | static struct clk ** const uart_clks_mx51[] __initconst = { |
135 | &clk[IMX5_CLK_UART1_IPG_GATE], | |
136 | &clk[IMX5_CLK_UART1_PER_GATE], | |
137 | &clk[IMX5_CLK_UART2_IPG_GATE], | |
138 | &clk[IMX5_CLK_UART2_PER_GATE], | |
139 | &clk[IMX5_CLK_UART3_IPG_GATE], | |
140 | &clk[IMX5_CLK_UART3_PER_GATE], | |
141 | NULL | |
142 | }; | |
143 | ||
144 | static struct clk ** const uart_clks_mx50_mx53[] __initconst = { | |
89981a6f LS |
145 | &clk[IMX5_CLK_UART1_IPG_GATE], |
146 | &clk[IMX5_CLK_UART1_PER_GATE], | |
147 | &clk[IMX5_CLK_UART2_IPG_GATE], | |
148 | &clk[IMX5_CLK_UART2_PER_GATE], | |
149 | &clk[IMX5_CLK_UART3_IPG_GATE], | |
150 | &clk[IMX5_CLK_UART3_PER_GATE], | |
151 | &clk[IMX5_CLK_UART4_IPG_GATE], | |
152 | &clk[IMX5_CLK_UART4_PER_GATE], | |
153 | &clk[IMX5_CLK_UART5_IPG_GATE], | |
154 | &clk[IMX5_CLK_UART5_PER_GATE], | |
155 | NULL | |
156 | }; | |
157 | ||
18c1d989 | 158 | static void __init mx5_clocks_common_init(void __iomem *ccm_base) |
b8d4176f | 159 | { |
490dd880 | 160 | clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
b674cf2f SG |
161 | clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); |
162 | clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); | |
163 | clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); | |
164 | clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); | |
490dd880 | 165 | |
490dd880 LS |
166 | clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, |
167 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | |
168 | clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, | |
169 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); | |
170 | clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, | |
171 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); | |
172 | clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); | |
173 | clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); | |
174 | clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); | |
175 | clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, | |
176 | per_root_sel, ARRAY_SIZE(per_root_sel)); | |
177 | clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); | |
178 | clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); | |
179 | clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); | |
180 | clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); | |
181 | clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); | |
182 | clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); | |
183 | clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); | |
184 | clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); | |
185 | clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); | |
186 | clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); | |
187 | clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); | |
188 | clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, | |
189 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
190 | clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); | |
191 | clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); | |
192 | ||
193 | clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, | |
194 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
195 | clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, | |
196 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
197 | clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); | |
198 | clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); | |
199 | clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); | |
200 | clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); | |
201 | clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); | |
202 | clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); | |
203 | ||
204 | clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, | |
205 | emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); | |
206 | clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); | |
207 | clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); | |
208 | clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, | |
209 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
210 | clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); | |
211 | clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); | |
212 | clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, | |
213 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
214 | clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); | |
215 | clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); | |
216 | clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); | |
217 | clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); | |
218 | clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, | |
219 | usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); | |
6f0628aa LS |
220 | clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels)); |
221 | clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels)); | |
222 | clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3); | |
490dd880 LS |
223 | clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); |
224 | clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); | |
225 | clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); | |
226 | clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); | |
227 | clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); | |
228 | clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); | |
229 | clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); | |
230 | clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); | |
231 | clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); | |
232 | clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); | |
233 | clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); | |
234 | clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); | |
235 | clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); | |
236 | clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); | |
237 | clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); | |
238 | clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); | |
239 | clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); | |
240 | clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); | |
241 | clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); | |
242 | clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); | |
243 | clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); | |
244 | clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); | |
245 | clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); | |
246 | clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); | |
247 | clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); | |
248 | clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); | |
249 | clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); | |
250 | clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); | |
251 | clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); | |
252 | clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); | |
253 | clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); | |
254 | clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); | |
255 | clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); | |
256 | clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); | |
257 | clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); | |
258 | clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); | |
259 | clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); | |
260 | clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); | |
261 | clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); | |
262 | clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); | |
263 | clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); | |
264 | clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); | |
265 | clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); | |
266 | clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); | |
267 | clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); | |
268 | clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); | |
269 | clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); | |
490dd880 LS |
270 | clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); |
271 | ||
272 | clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); | |
273 | clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
274 | clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
275 | clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); | |
276 | clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
277 | clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
278 | clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); | |
279 | clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); | |
280 | clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); | |
281 | clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); | |
282 | clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); | |
283 | clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); | |
284 | clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); | |
285 | clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); | |
286 | clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); | |
287 | clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); | |
288 | clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); | |
289 | clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); | |
290 | clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); | |
291 | clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); | |
292 | clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); | |
293 | clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); | |
294 | clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); | |
295 | clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); | |
296 | clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); | |
297 | clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); | |
298 | clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); | |
299 | clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); | |
300 | clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); | |
301 | clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); | |
302 | clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); | |
303 | clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, | |
304 | spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); | |
305 | clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); | |
306 | clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); | |
307 | clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); | |
6fb8954b | 308 | clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); |
13b3a07a | 309 | |
490dd880 | 310 | clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); |
490dd880 | 311 | clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); |
b8d4176f SH |
312 | |
313 | /* Set SDHC parents to be PLL2 */ | |
490dd880 LS |
314 | clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); |
315 | clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); | |
b8d4176f SH |
316 | |
317 | /* move usb phy clk to 24MHz */ | |
490dd880 LS |
318 | clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); |
319 | ||
320 | clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); | |
321 | clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ | |
322 | clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); | |
323 | clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ | |
324 | clk_prepare_enable(clk[IMX5_CLK_SPBA]); | |
325 | clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ | |
326 | clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ | |
327 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); | |
328 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); | |
329 | clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); | |
330 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); | |
331 | clk_prepare_enable(clk[IMX5_CLK_TMAX1]); | |
332 | clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ | |
333 | clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ | |
b8d4176f SH |
334 | } |
335 | ||
7a9cc1ad GU |
336 | static void __init mx50_clocks_init(struct device_node *np) |
337 | { | |
18c1d989 | 338 | void __iomem *ccm_base; |
20484c13 | 339 | void __iomem *pll_base; |
7a9cc1ad | 340 | unsigned long r; |
7a9cc1ad | 341 | |
20484c13 SG |
342 | pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); |
343 | WARN_ON(!pll_base); | |
344 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); | |
345 | ||
346 | pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); | |
347 | WARN_ON(!pll_base); | |
348 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | |
349 | ||
350 | pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); | |
351 | WARN_ON(!pll_base); | |
352 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | |
7a9cc1ad | 353 | |
18c1d989 SG |
354 | ccm_base = of_iomap(np, 0); |
355 | WARN_ON(!ccm_base); | |
356 | ||
229be9c1 AS |
357 | mx5_clocks_common_init(ccm_base); |
358 | ||
630a2125 MKB |
359 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, |
360 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | |
490dd880 LS |
361 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); |
362 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); | |
363 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); | |
364 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
365 | clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); | |
366 | clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); | |
367 | clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); | |
59dc3d8c PZ |
368 | clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); |
369 | clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); | |
370 | clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); | |
371 | clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); | |
7a9cc1ad | 372 | |
490dd880 LS |
373 | clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, |
374 | mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); | |
375 | clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); | |
376 | clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); | |
7a9cc1ad | 377 | |
490dd880 LS |
378 | clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, |
379 | mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); | |
380 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | |
381 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | |
7a9cc1ad | 382 | |
229be9c1 | 383 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
7a9cc1ad GU |
384 | |
385 | clk_data.clks = clk; | |
386 | clk_data.clk_num = ARRAY_SIZE(clk); | |
387 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
388 | ||
7a9cc1ad | 389 | /* set SDHC root clock to 200MHZ*/ |
490dd880 LS |
390 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
391 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | |
7a9cc1ad | 392 | |
490dd880 | 393 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
7a9cc1ad | 394 | imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); |
490dd880 | 395 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
7a9cc1ad | 396 | |
490dd880 LS |
397 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
398 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | |
a275b315 FE |
399 | |
400 | imx_register_uart_clocks(uart_clks_mx50_mx53); | |
7a9cc1ad GU |
401 | } |
402 | CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); | |
403 | ||
c16cc8a0 | 404 | static void __init mx51_clocks_init(struct device_node *np) |
b8d4176f | 405 | { |
18c1d989 | 406 | void __iomem *ccm_base; |
20484c13 | 407 | void __iomem *pll_base; |
69155fd6 | 408 | u32 val; |
b8d4176f | 409 | |
20484c13 SG |
410 | pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K); |
411 | WARN_ON(!pll_base); | |
412 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); | |
413 | ||
414 | pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K); | |
415 | WARN_ON(!pll_base); | |
416 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | |
417 | ||
418 | pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K); | |
419 | WARN_ON(!pll_base); | |
420 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | |
18c1d989 SG |
421 | |
422 | ccm_base = of_iomap(np, 0); | |
423 | WARN_ON(!ccm_base); | |
424 | ||
229be9c1 AS |
425 | mx5_clocks_common_init(ccm_base); |
426 | ||
630a2125 MKB |
427 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, |
428 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | |
fa0abb18 LS |
429 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, |
430 | mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT); | |
431 | clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
432 | mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT); | |
490dd880 LS |
433 | clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, |
434 | mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); | |
435 | clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, | |
436 | mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); | |
437 | clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); | |
438 | clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); | |
439 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
440 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); | |
441 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); | |
442 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
443 | clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); | |
444 | clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); | |
445 | clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); | |
446 | clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); | |
447 | clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); | |
448 | clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); | |
449 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, | |
450 | mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); | |
451 | clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, | |
452 | spdif_sel, ARRAY_SIZE(spdif_sel)); | |
453 | clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); | |
454 | clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); | |
455 | clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, | |
456 | mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); | |
457 | clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); | |
b8d4176f | 458 | |
229be9c1 | 459 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
b8d4176f | 460 | |
f40f38d1 FE |
461 | clk_data.clks = clk; |
462 | clk_data.clk_num = ARRAY_SIZE(clk); | |
463 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
464 | ||
b8d4176f | 465 | /* set the usboh3 parent to pll2_sw */ |
490dd880 | 466 | clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); |
b8d4176f SH |
467 | |
468 | /* set SDHC root clock to 166.25MHZ*/ | |
490dd880 LS |
469 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); |
470 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); | |
b8d4176f | 471 | |
490dd880 | 472 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 473 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
490dd880 | 474 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
69155fd6 SH |
475 | |
476 | /* | |
477 | * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no | |
478 | * longer supported. Set to one for better power saving. | |
479 | * | |
480 | * The effect of not setting these bits is that MIPI clocks can't be | |
481 | * enabled without the IPU clock being enabled aswell. | |
482 | */ | |
483 | val = readl(MXC_CCM_CCDR); | |
484 | val |= 1 << 18; | |
485 | writel(val, MXC_CCM_CCDR); | |
486 | ||
487 | val = readl(MXC_CCM_CLPCR); | |
488 | val |= 1 << 23; | |
489 | writel(val, MXC_CCM_CLPCR); | |
a275b315 FE |
490 | |
491 | imx_register_uart_clocks(uart_clks_mx51); | |
4d9d18a5 | 492 | } |
c16cc8a0 | 493 | CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init); |
4d9d18a5 SH |
494 | |
495 | static void __init mx53_clocks_init(struct device_node *np) | |
b8d4176f | 496 | { |
18c1d989 | 497 | void __iomem *ccm_base; |
20484c13 | 498 | void __iomem *pll_base; |
b8d4176f SH |
499 | unsigned long r; |
500 | ||
20484c13 SG |
501 | pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); |
502 | WARN_ON(!pll_base); | |
503 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); | |
504 | ||
505 | pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); | |
506 | WARN_ON(!pll_base); | |
507 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | |
508 | ||
509 | pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); | |
510 | WARN_ON(!pll_base); | |
511 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | |
512 | ||
513 | pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K); | |
514 | WARN_ON(!pll_base); | |
515 | clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base); | |
490dd880 | 516 | |
18c1d989 SG |
517 | ccm_base = of_iomap(np, 0); |
518 | WARN_ON(!ccm_base); | |
519 | ||
229be9c1 AS |
520 | mx5_clocks_common_init(ccm_base); |
521 | ||
630a2125 MKB |
522 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, |
523 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | |
490dd880 LS |
524 | clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); |
525 | clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); | |
526 | clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, | |
527 | mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); | |
528 | clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); | |
529 | clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | |
530 | clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); | |
531 | clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, | |
532 | mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); | |
d5e9b243 | 533 | clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); |
490dd880 | 534 | clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); |
c20737a2 PB |
535 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, |
536 | mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT); | |
537 | clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
538 | mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT); | |
490dd880 LS |
539 | clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, |
540 | mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); | |
541 | clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); | |
542 | clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); | |
543 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
544 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); | |
545 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); | |
546 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
547 | clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); | |
548 | clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); | |
549 | clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, | |
550 | mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); | |
551 | clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); | |
552 | clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); | |
553 | clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); | |
554 | clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); | |
555 | clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); | |
556 | clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); | |
557 | clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); | |
558 | ||
377d6479 KK |
559 | clk[IMX5_CLK_FIRI_SEL] = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2, |
560 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
561 | clk[IMX5_CLK_FIRI_PRED] = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3); | |
562 | clk[IMX5_CLK_FIRI_PODF] = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6); | |
563 | clk[IMX5_CLK_FIRI_SERIAL_GATE] = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28); | |
564 | clk[IMX5_CLK_FIRI_IPG_GATE] = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26); | |
565 | ||
566 | clk[IMX5_CLK_CSI0_MCLK1_SEL] = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2, | |
567 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
568 | clk[IMX5_CLK_CSI0_MCLK1_PRED] = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3); | |
569 | clk[IMX5_CLK_CSI0_MCLK1_PODF] = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6); | |
570 | clk[IMX5_CLK_CSI0_MCLK1_GATE] = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4); | |
571 | ||
572 | clk[IMX5_CLK_IEEE1588_SEL] = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2, | |
573 | ieee1588_sels, ARRAY_SIZE(ieee1588_sels)); | |
574 | clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3); | |
575 | clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6); | |
576 | clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6); | |
59dc3d8c PZ |
577 | clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); |
578 | clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); | |
579 | clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); | |
580 | clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); | |
377d6479 | 581 | |
490dd880 LS |
582 | clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, |
583 | mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); | |
584 | clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); | |
585 | clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); | |
586 | ||
587 | clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, | |
588 | mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); | |
589 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | |
590 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | |
591 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, | |
592 | mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); | |
82a40b54 LS |
593 | clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf", |
594 | clk[IMX5_CLK_CPU_PODF], | |
595 | clk[IMX5_CLK_CPU_PODF_SEL], | |
596 | clk[IMX5_CLK_PLL1_SW], | |
597 | clk[IMX5_CLK_STEP_SEL]); | |
04b41e84 | 598 | |
229be9c1 | 599 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
b8d4176f | 600 | |
f40f38d1 FE |
601 | clk_data.clks = clk; |
602 | clk_data.clk_num = ARRAY_SIZE(clk); | |
603 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
604 | ||
b8d4176f | 605 | /* set SDHC root clock to 200MHZ*/ |
490dd880 LS |
606 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
607 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | |
b8d4176f | 608 | |
10471fa3 MKB |
609 | /* move can bus clk to 24MHz */ |
610 | clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); | |
611 | ||
6f0628aa LS |
612 | /* make sure step clock is running from 24MHz */ |
613 | clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); | |
614 | ||
490dd880 | 615 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 616 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
490dd880 | 617 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 618 | |
490dd880 LS |
619 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
620 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | |
a275b315 FE |
621 | |
622 | imx_register_uart_clocks(uart_clks_mx50_mx53); | |
b8d4176f | 623 | } |
4d9d18a5 | 624 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |