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5efaf090 ZG |
1 | /* |
2 | * Copyright (c) 2014 Linaro Ltd. | |
3 | * Copyright (c) 2014 Hisilicon Limited. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/of_address.h> | |
11 | #include <dt-bindings/clock/hix5hd2-clock.h> | |
20e07558 ZG |
12 | #include <linux/slab.h> |
13 | #include <linux/delay.h> | |
5efaf090 ZG |
14 | #include "clk.h" |
15 | ||
16 | static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { | |
f61990f3 SB |
17 | { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, |
18 | { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, }, | |
19 | { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, }, | |
20 | { HIX5HD2_FIXED_24M, "24m", NULL, 0, 24000000, }, | |
21 | { HIX5HD2_FIXED_600M, "600m", NULL, 0, 600000000, }, | |
22 | { HIX5HD2_FIXED_300M, "300m", NULL, 0, 300000000, }, | |
23 | { HIX5HD2_FIXED_75M, "75m", NULL, 0, 75000000, }, | |
24 | { HIX5HD2_FIXED_200M, "200m", NULL, 0, 200000000, }, | |
25 | { HIX5HD2_FIXED_100M, "100m", NULL, 0, 100000000, }, | |
26 | { HIX5HD2_FIXED_40M, "40m", NULL, 0, 40000000, }, | |
27 | { HIX5HD2_FIXED_150M, "150m", NULL, 0, 150000000, }, | |
28 | { HIX5HD2_FIXED_1728M, "1728m", NULL, 0, 1728000000, }, | |
29 | { HIX5HD2_FIXED_28P8M, "28p8m", NULL, 0, 28000000, }, | |
30 | { HIX5HD2_FIXED_432M, "432m", NULL, 0, 432000000, }, | |
31 | { HIX5HD2_FIXED_345P6M, "345p6m", NULL, 0, 345000000, }, | |
32 | { HIX5HD2_FIXED_288M, "288m", NULL, 0, 288000000, }, | |
33 | { HIX5HD2_FIXED_60M, "60m", NULL, 0, 60000000, }, | |
34 | { HIX5HD2_FIXED_750M, "750m", NULL, 0, 750000000, }, | |
35 | { HIX5HD2_FIXED_500M, "500m", NULL, 0, 500000000, }, | |
36 | { HIX5HD2_FIXED_54M, "54m", NULL, 0, 54000000, }, | |
37 | { HIX5HD2_FIXED_27M, "27m", NULL, 0, 27000000, }, | |
38 | { HIX5HD2_FIXED_1500M, "1500m", NULL, 0, 1500000000, }, | |
39 | { HIX5HD2_FIXED_375M, "375m", NULL, 0, 375000000, }, | |
40 | { HIX5HD2_FIXED_187M, "187m", NULL, 0, 187000000, }, | |
41 | { HIX5HD2_FIXED_250M, "250m", NULL, 0, 250000000, }, | |
42 | { HIX5HD2_FIXED_125M, "125m", NULL, 0, 125000000, }, | |
43 | { HIX5HD2_FIXED_2P02M, "2m", NULL, 0, 2000000, }, | |
44 | { HIX5HD2_FIXED_50M, "50m", NULL, 0, 50000000, }, | |
45 | { HIX5HD2_FIXED_25M, "25m", NULL, 0, 25000000, }, | |
46 | { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, }, | |
5efaf090 ZG |
47 | }; |
48 | ||
4a1caed3 | 49 | static const char *const sfc_mux_p[] __initconst = { |
5efaf090 ZG |
50 | "24m", "150m", "200m", "100m", "75m", }; |
51 | static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; | |
52 | ||
4a1caed3 | 53 | static const char *const sdio_mux_p[] __initconst = { |
5efaf090 | 54 | "75m", "100m", "50m", "15m", }; |
cc855dd9 | 55 | static u32 sdio_mux_table[] = {0, 1, 2, 3}; |
5efaf090 | 56 | |
4a1caed3 | 57 | static const char *const fephy_mux_p[] __initconst = { "25m", "125m"}; |
5efaf090 ZG |
58 | static u32 fephy_mux_table[] = {0, 1}; |
59 | ||
60 | ||
61 | static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = { | |
62 | { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), | |
63 | CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, | |
cc855dd9 JX |
64 | { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), |
65 | CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, }, | |
66 | { HIX5HD2_SD_MUX, "sd_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), | |
67 | CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, }, | |
5efaf090 ZG |
68 | { HIX5HD2_FEPHY_MUX, "fephy_mux", |
69 | fephy_mux_p, ARRAY_SIZE(fephy_mux_p), | |
70 | CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, | |
71 | }; | |
72 | ||
73 | static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { | |
cc855dd9 | 74 | /* sfc */ |
5efaf090 ZG |
75 | { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", |
76 | CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, | |
77 | { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc", | |
78 | CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, }, | |
cc855dd9 JX |
79 | /* sdio0 */ |
80 | { HIX5HD2_SD_BIU_CLK, "clk_sd_biu", "200m", | |
81 | CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, | |
82 | { HIX5HD2_SD_CIU_CLK, "clk_sd_ciu", "sd_mux", | |
83 | CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, | |
84 | { HIX5HD2_SD_CIU_RST, "rst_sd_ciu", "clk_sd_ciu", | |
85 | CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, }, | |
86 | /* sdio1 */ | |
5efaf090 ZG |
87 | { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m", |
88 | CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, | |
89 | { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", | |
90 | CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, | |
91 | { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu", | |
92 | CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, }, | |
20e07558 ZG |
93 | /* gsf */ |
94 | { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, }, | |
95 | { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, }, | |
96 | { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys", | |
97 | CLK_SET_RATE_PARENT, 0x120, 0, 0, }, | |
1463fba3 GY |
98 | /* wdg0 */ |
99 | { HIX5HD2_WDG0_CLK, "clk_wdg0", "24m", | |
100 | CLK_SET_RATE_PARENT, 0x178, 0, 0, }, | |
101 | { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0", | |
102 | CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, }, | |
45bcf9c6 WY |
103 | /* I2C */ |
104 | {HIX5HD2_I2C0_CLK, "clk_i2c0", "100m", | |
105 | CLK_SET_RATE_PARENT, 0x06c, 4, 0, }, | |
106 | {HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0", | |
107 | CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, }, | |
108 | {HIX5HD2_I2C1_CLK, "clk_i2c1", "100m", | |
109 | CLK_SET_RATE_PARENT, 0x06c, 8, 0, }, | |
110 | {HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1", | |
111 | CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, }, | |
112 | {HIX5HD2_I2C2_CLK, "clk_i2c2", "100m", | |
113 | CLK_SET_RATE_PARENT, 0x06c, 12, 0, }, | |
114 | {HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2", | |
115 | CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, }, | |
116 | {HIX5HD2_I2C3_CLK, "clk_i2c3", "100m", | |
117 | CLK_SET_RATE_PARENT, 0x06c, 16, 0, }, | |
118 | {HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3", | |
119 | CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, }, | |
120 | {HIX5HD2_I2C4_CLK, "clk_i2c4", "100m", | |
121 | CLK_SET_RATE_PARENT, 0x06c, 20, 0, }, | |
122 | {HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4", | |
123 | CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, }, | |
124 | {HIX5HD2_I2C5_CLK, "clk_i2c5", "100m", | |
125 | CLK_SET_RATE_PARENT, 0x06c, 0, 0, }, | |
126 | {HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5", | |
127 | CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, }, | |
5efaf090 ZG |
128 | }; |
129 | ||
20e07558 ZG |
130 | enum hix5hd2_clk_type { |
131 | TYPE_COMPLEX, | |
132 | TYPE_ETHER, | |
133 | }; | |
134 | ||
135 | struct hix5hd2_complex_clock { | |
136 | const char *name; | |
137 | const char *parent_name; | |
138 | u32 id; | |
139 | u32 ctrl_reg; | |
140 | u32 ctrl_clk_mask; | |
141 | u32 ctrl_rst_mask; | |
142 | u32 phy_reg; | |
143 | u32 phy_clk_mask; | |
144 | u32 phy_rst_mask; | |
145 | enum hix5hd2_clk_type type; | |
146 | }; | |
147 | ||
148 | struct hix5hd2_clk_complex { | |
149 | struct clk_hw hw; | |
150 | u32 id; | |
151 | void __iomem *ctrl_reg; | |
152 | u32 ctrl_clk_mask; | |
153 | u32 ctrl_rst_mask; | |
154 | void __iomem *phy_reg; | |
155 | u32 phy_clk_mask; | |
156 | u32 phy_rst_mask; | |
157 | }; | |
158 | ||
159 | static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = { | |
160 | {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, | |
161 | 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, | |
162 | {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, | |
163 | 0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER}, | |
164 | {"clk_sata", NULL, HIX5HD2_SATA_CLK, | |
165 | 0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX}, | |
166 | {"clk_usb", NULL, HIX5HD2_USB_CLK, | |
167 | 0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX}, | |
168 | }; | |
169 | ||
170 | #define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw) | |
171 | ||
172 | static int clk_ether_prepare(struct clk_hw *hw) | |
173 | { | |
174 | struct hix5hd2_clk_complex *clk = to_complex_clk(hw); | |
175 | u32 val; | |
176 | ||
177 | val = readl_relaxed(clk->ctrl_reg); | |
178 | val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; | |
179 | writel_relaxed(val, clk->ctrl_reg); | |
180 | val &= ~(clk->ctrl_rst_mask); | |
181 | writel_relaxed(val, clk->ctrl_reg); | |
182 | ||
183 | val = readl_relaxed(clk->phy_reg); | |
184 | val |= clk->phy_clk_mask; | |
185 | val &= ~(clk->phy_rst_mask); | |
186 | writel_relaxed(val, clk->phy_reg); | |
187 | mdelay(10); | |
188 | ||
189 | val &= ~(clk->phy_clk_mask); | |
190 | val |= clk->phy_rst_mask; | |
191 | writel_relaxed(val, clk->phy_reg); | |
192 | mdelay(10); | |
193 | ||
194 | val |= clk->phy_clk_mask; | |
195 | val &= ~(clk->phy_rst_mask); | |
196 | writel_relaxed(val, clk->phy_reg); | |
197 | mdelay(30); | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static void clk_ether_unprepare(struct clk_hw *hw) | |
202 | { | |
203 | struct hix5hd2_clk_complex *clk = to_complex_clk(hw); | |
204 | u32 val; | |
205 | ||
206 | val = readl_relaxed(clk->ctrl_reg); | |
207 | val &= ~(clk->ctrl_clk_mask); | |
208 | writel_relaxed(val, clk->ctrl_reg); | |
209 | } | |
210 | ||
211 | static struct clk_ops clk_ether_ops = { | |
212 | .prepare = clk_ether_prepare, | |
213 | .unprepare = clk_ether_unprepare, | |
214 | }; | |
215 | ||
216 | static int clk_complex_enable(struct clk_hw *hw) | |
217 | { | |
218 | struct hix5hd2_clk_complex *clk = to_complex_clk(hw); | |
219 | u32 val; | |
220 | ||
221 | val = readl_relaxed(clk->ctrl_reg); | |
222 | val |= clk->ctrl_clk_mask; | |
223 | val &= ~(clk->ctrl_rst_mask); | |
224 | writel_relaxed(val, clk->ctrl_reg); | |
225 | ||
226 | val = readl_relaxed(clk->phy_reg); | |
227 | val |= clk->phy_clk_mask; | |
228 | val &= ~(clk->phy_rst_mask); | |
229 | writel_relaxed(val, clk->phy_reg); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | static void clk_complex_disable(struct clk_hw *hw) | |
235 | { | |
236 | struct hix5hd2_clk_complex *clk = to_complex_clk(hw); | |
237 | u32 val; | |
238 | ||
239 | val = readl_relaxed(clk->ctrl_reg); | |
240 | val |= clk->ctrl_rst_mask; | |
241 | val &= ~(clk->ctrl_clk_mask); | |
242 | writel_relaxed(val, clk->ctrl_reg); | |
243 | ||
244 | val = readl_relaxed(clk->phy_reg); | |
245 | val |= clk->phy_rst_mask; | |
246 | val &= ~(clk->phy_clk_mask); | |
247 | writel_relaxed(val, clk->phy_reg); | |
248 | } | |
249 | ||
250 | static struct clk_ops clk_complex_ops = { | |
251 | .enable = clk_complex_enable, | |
252 | .disable = clk_complex_disable, | |
253 | }; | |
254 | ||
4a77f817 SB |
255 | static void __init |
256 | hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, | |
257 | struct hisi_clock_data *data) | |
20e07558 ZG |
258 | { |
259 | void __iomem *base = data->base; | |
260 | int i; | |
261 | ||
262 | for (i = 0; i < nums; i++) { | |
263 | struct hix5hd2_clk_complex *p_clk; | |
264 | struct clk *clk; | |
265 | struct clk_init_data init; | |
266 | ||
267 | p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); | |
268 | if (!p_clk) | |
269 | return; | |
270 | ||
271 | init.name = clks[i].name; | |
272 | if (clks[i].type == TYPE_ETHER) | |
273 | init.ops = &clk_ether_ops; | |
274 | else | |
275 | init.ops = &clk_complex_ops; | |
276 | ||
277 | init.flags = CLK_IS_BASIC; | |
278 | init.parent_names = | |
279 | (clks[i].parent_name ? &clks[i].parent_name : NULL); | |
280 | init.num_parents = (clks[i].parent_name ? 1 : 0); | |
281 | ||
282 | p_clk->ctrl_reg = base + clks[i].ctrl_reg; | |
283 | p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask; | |
284 | p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask; | |
285 | p_clk->phy_reg = base + clks[i].phy_reg; | |
286 | p_clk->phy_clk_mask = clks[i].phy_clk_mask; | |
287 | p_clk->phy_rst_mask = clks[i].phy_rst_mask; | |
288 | p_clk->hw.init = &init; | |
289 | ||
290 | clk = clk_register(NULL, &p_clk->hw); | |
291 | if (IS_ERR(clk)) { | |
292 | kfree(p_clk); | |
293 | pr_err("%s: failed to register clock %s\n", | |
294 | __func__, clks[i].name); | |
295 | continue; | |
296 | } | |
297 | ||
298 | data->clk_data.clks[clks[i].id] = clk; | |
299 | } | |
300 | } | |
301 | ||
5efaf090 ZG |
302 | static void __init hix5hd2_clk_init(struct device_node *np) |
303 | { | |
304 | struct hisi_clock_data *clk_data; | |
305 | ||
306 | clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS); | |
307 | if (!clk_data) | |
308 | return; | |
309 | ||
310 | hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, | |
311 | ARRAY_SIZE(hix5hd2_fixed_rate_clks), | |
312 | clk_data); | |
313 | hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), | |
314 | clk_data); | |
315 | hisi_clk_register_gate(hix5hd2_gate_clks, | |
316 | ARRAY_SIZE(hix5hd2_gate_clks), clk_data); | |
20e07558 ZG |
317 | hix5hd2_clk_register_complex(hix5hd2_complex_clks, |
318 | ARRAY_SIZE(hix5hd2_complex_clks), | |
319 | clk_data); | |
5efaf090 ZG |
320 | } |
321 | ||
322 | CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); |