[linux-block.git] / drivers / clk / hisilicon / clk-hi6220-stub.c

/*
 * Hi6220 stub clock driver
 *
 * Copyright (c) 2015 Hisilicon Limited.
 * Copyright (c) 2015 Linaro Limited.
 *
 * Author: Leo Yan <leo.yan@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mailbox_client.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>

/* Stub clocks id */
#define HI6220_STUB_ACPU0		0
#define HI6220_STUB_ACPU1		1
#define HI6220_STUB_GPU			2
#define HI6220_STUB_DDR			5

/* Mailbox message */
#define HI6220_MBOX_MSG_LEN		8

#define HI6220_MBOX_FREQ		0xA
#define HI6220_MBOX_CMD_SET		0x3
#define HI6220_MBOX_OBJ_AP		0x0

/* CPU dynamic frequency scaling */
#define ACPU_DFS_FREQ_MAX		0x1724
#define ACPU_DFS_CUR_FREQ		0x17CC
#define ACPU_DFS_FLAG			0x1B30
#define ACPU_DFS_FREQ_REQ		0x1B34
#define ACPU_DFS_FREQ_LMT		0x1B38
#define ACPU_DFS_LOCK_FLAG		0xAEAEAEAE

#define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)

struct hi6220_stub_clk {
	u32 id;

	struct device *dev;
	struct clk_hw hw;

	struct regmap *dfs_map;
	struct mbox_client cl;
	struct mbox_chan *mbox;
};

struct hi6220_mbox_msg {
	unsigned char type;
	unsigned char cmd;
	unsigned char obj;
	unsigned char src;
	unsigned char para[4];
};

union hi6220_mbox_data {
	unsigned int data[HI6220_MBOX_MSG_LEN];
	struct hi6220_mbox_msg msg;
};

static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
{
	unsigned int freq;

	regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
	return freq;
}

static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
				unsigned int freq)
{
	union hi6220_mbox_data data;

	/* set the frequency in sram */
	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);

	/* compound mailbox message */
	data.msg.type = HI6220_MBOX_FREQ;
	data.msg.cmd  = HI6220_MBOX_CMD_SET;
	data.msg.obj  = HI6220_MBOX_OBJ_AP;
	data.msg.src  = HI6220_MBOX_OBJ_AP;

	mbox_send_message(stub_clk->mbox, &data);
	return 0;
}

static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
				  unsigned int freq)
{
	unsigned int limit_flag, limit_freq = UINT_MAX;
	unsigned int max_freq;

	/* check the constrained frequency */
	regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
	if (limit_flag == ACPU_DFS_LOCK_FLAG)
		regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);

	/* check the supported maximum frequency */
	regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);

	/* calculate the real maximum frequency */
	max_freq = min(max_freq, limit_freq);

	if (WARN_ON(freq > max_freq))
		freq = max_freq;

	return freq;
}

static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	u32 rate = 0;
	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);

	switch (stub_clk->id) {
	case HI6220_STUB_ACPU0:
		rate = hi6220_acpu_get_freq(stub_clk);

		/* convert from kHz to Hz */
		rate *= 1000;
		break;

	default:
		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
			__func__, stub_clk->id);
		break;
	}

	return rate;
}

static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
	unsigned long new_rate = rate / 1000;  /* kHz */
	int ret = 0;

	switch (stub_clk->id) {
	case HI6220_STUB_ACPU0:
		ret = hi6220_acpu_set_freq(stub_clk, new_rate);
		if (ret < 0)
			return ret;

		break;

	default:
		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
			__func__, stub_clk->id);
		break;
	}

	pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
	return ret;
}

static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
	unsigned long new_rate = rate / 1000;  /* kHz */

	switch (stub_clk->id) {
	case HI6220_STUB_ACPU0:
		new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);

		/* convert from kHz to Hz */
		new_rate *= 1000;
		break;

	default:
		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
			__func__, stub_clk->id);
		break;
	}

	return new_rate;
}

static const struct clk_ops hi6220_stub_clk_ops = {
	.recalc_rate	= hi6220_stub_clk_recalc_rate,
	.round_rate	= hi6220_stub_clk_round_rate,
	.set_rate	= hi6220_stub_clk_set_rate,
};

static int hi6220_stub_clk_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct clk_init_data init;
	struct hi6220_stub_clk *stub_clk;
	struct clk *clk;
	struct device_node *np = pdev->dev.of_node;
	int ret;

	stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
	if (!stub_clk)
		return -ENOMEM;

	stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
				"hisilicon,hi6220-clk-sram");
	if (IS_ERR(stub_clk->dfs_map)) {
		dev_err(dev, "failed to get sram regmap\n");
		return PTR_ERR(stub_clk->dfs_map);
	}

	stub_clk->hw.init = &init;
	stub_clk->dev = dev;
	stub_clk->id = HI6220_STUB_ACPU0;

	/* Use mailbox client with blocking mode */
	stub_clk->cl.dev = dev;
	stub_clk->cl.tx_done = NULL;
	stub_clk->cl.tx_block = true;
	stub_clk->cl.tx_tout = 500;
	stub_clk->cl.knows_txdone = false;

	/* Allocate mailbox channel */
	stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
	if (IS_ERR(stub_clk->mbox)) {
		dev_err(dev, "failed get mailbox channel\n");
		return PTR_ERR(stub_clk->mbox);
	}

	init.name = "acpu0";
	init.ops = &hi6220_stub_clk_ops;
	init.num_parents = 0;
	init.flags = 0;

	clk = devm_clk_register(dev, &stub_clk->hw);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
	if (ret) {
		dev_err(dev, "failed to register OF clock provider\n");
		return ret;
	}

	/* initialize buffer to zero */
	regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);

	dev_dbg(dev, "Registered clock '%s'\n", init.name);
	return 0;
}

static const struct of_device_id hi6220_stub_clk_of_match[] = {
	{ .compatible = "hisilicon,hi6220-stub-clk", },
	{}
};

static struct platform_driver hi6220_stub_clk_driver = {
	.driver	= {
		.name = "hi6220-stub-clk",
		.of_match_table = hi6220_stub_clk_of_match,
	},
	.probe = hi6220_stub_clk_probe,
};

static int __init hi6220_stub_clk_init(void)
{
	return platform_driver_register(&hi6220_stub_clk_driver);
}
subsys_initcall(hi6220_stub_clk_init);
Commit	Line	Data
c1628a2c LY	1	/*
	2	* Hi6220 stub clock driver
	3	*
	4	* Copyright (c) 2015 Hisilicon Limited.
	5	* Copyright (c) 2015 Linaro Limited.
	6	*
	7	* Author: Leo Yan <leo.yan@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/clk-provider.h>
	16	#include <linux/err.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mailbox_client.h>
	20	#include <linux/of.h>
	21	#include <linux/of_device.h>
	22	#include <linux/regmap.h>
	23
	24	/* Stub clocks id */
	25	#define HI6220_STUB_ACPU0 0
	26	#define HI6220_STUB_ACPU1 1
	27	#define HI6220_STUB_GPU 2
	28	#define HI6220_STUB_DDR 5
	29
	30	/* Mailbox message */
	31	#define HI6220_MBOX_MSG_LEN 8
	32
	33	#define HI6220_MBOX_FREQ 0xA
	34	#define HI6220_MBOX_CMD_SET 0x3
	35	#define HI6220_MBOX_OBJ_AP 0x0
	36
	37	/* CPU dynamic frequency scaling */
	38	#define ACPU_DFS_FREQ_MAX 0x1724
	39	#define ACPU_DFS_CUR_FREQ 0x17CC
	40	#define ACPU_DFS_FLAG 0x1B30
	41	#define ACPU_DFS_FREQ_REQ 0x1B34
	42	#define ACPU_DFS_FREQ_LMT 0x1B38
	43	#define ACPU_DFS_LOCK_FLAG 0xAEAEAEAE
	44
	45	#define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)
	46
	47	struct hi6220_stub_clk {
	48	u32 id;
	49
	50	struct device *dev;
	51	struct clk_hw hw;
	52
	53	struct regmap *dfs_map;
	54	struct mbox_client cl;
	55	struct mbox_chan *mbox;
	56	};
	57
	58	struct hi6220_mbox_msg {
	59	unsigned char type;
	60	unsigned char cmd;
	61	unsigned char obj;
	62	unsigned char src;
	63	unsigned char para[4];
	64	};
65
66	union hi6220_mbox_data {
67	unsigned int data[HI6220_MBOX_MSG_LEN];
68	struct hi6220_mbox_msg msg;
69	};
70
71	static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
72	{
73	unsigned int freq;
74
75	regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
76	return freq;
77	}
78
79	static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
80	unsigned int freq)
81	{
82	union hi6220_mbox_data data;
83
84	/* set the frequency in sram */
85	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);
86
87	/* compound mailbox message */
88	data.msg.type = HI6220_MBOX_FREQ;
89	data.msg.cmd = HI6220_MBOX_CMD_SET;
90	data.msg.obj = HI6220_MBOX_OBJ_AP;
91	data.msg.src = HI6220_MBOX_OBJ_AP;
92
93	mbox_send_message(stub_clk->mbox, &data);
94	return 0;
95	}
96
97	static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
98	unsigned int freq)
99	{
100	unsigned int limit_flag, limit_freq = UINT_MAX;
101	unsigned int max_freq;
102
103	/* check the constrained frequency */
104	regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
105	if (limit_flag == ACPU_DFS_LOCK_FLAG)
106	regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);
107
108	/* check the supported maximum frequency */
109	regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);
110
111	/* calculate the real maximum frequency */
112	max_freq = min(max_freq, limit_freq);
113
114	if (WARN_ON(freq > max_freq))
115	freq = max_freq;
116
117	return freq;
118	}
119
120	static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
121	unsigned long parent_rate)
122	{
123	u32 rate = 0;
124	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
125
126	switch (stub_clk->id) {
127	case HI6220_STUB_ACPU0:
128	rate = hi6220_acpu_get_freq(stub_clk);
129
130	/* convert from kHz to Hz */
131	rate *= 1000;
132	break;
133
134	default:
135	dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
136	__func__, stub_clk->id);
137	break;
138	}
139
140	return rate;
141	}
142
143	static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
144	unsigned long parent_rate)
145	{
146	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
147	unsigned long new_rate = rate / 1000; /* kHz */
148	int ret = 0;
149
150	switch (stub_clk->id) {
151	case HI6220_STUB_ACPU0:
152	ret = hi6220_acpu_set_freq(stub_clk, new_rate);
153	if (ret < 0)
154	return ret;
155
156	break;
157
158	default:
159	dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
160	__func__, stub_clk->id);
161	break;
162	}
163
164	pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
165	return ret;
166	}
167
168	static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
169	unsigned long *parent_rate)
170	{
171	struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
172	unsigned long new_rate = rate / 1000; /* kHz */
173
174	switch (stub_clk->id) {
175	case HI6220_STUB_ACPU0:
176	new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);
177
178	/* convert from kHz to Hz */
179	new_rate *= 1000;
180	break;
181
182	default:
183	dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
184	__func__, stub_clk->id);
185	break;
186	}
187
188	return new_rate;
189	}
190
191	static const struct clk_ops hi6220_stub_clk_ops = {
192	.recalc_rate = hi6220_stub_clk_recalc_rate,
193	.round_rate = hi6220_stub_clk_round_rate,
194	.set_rate = hi6220_stub_clk_set_rate,
195	};
196
197	static int hi6220_stub_clk_probe(struct platform_device *pdev)
198	{
199	struct device *dev = &pdev->dev;
200	struct clk_init_data init;
201	struct hi6220_stub_clk *stub_clk;
202	struct clk *clk;
203	struct device_node *np = pdev->dev.of_node;
204	int ret;
205
206	stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
207	if (!stub_clk)
208	return -ENOMEM;
209
210	stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
211	"hisilicon,hi6220-clk-sram");
212	if (IS_ERR(stub_clk->dfs_map)) {
213	dev_err(dev, "failed to get sram regmap\n");
214	return PTR_ERR(stub_clk->dfs_map);
215	}
216
217	stub_clk->hw.init = &init;
218	stub_clk->dev = dev;
219	stub_clk->id = HI6220_STUB_ACPU0;
220
221	/* Use mailbox client with blocking mode */
222	stub_clk->cl.dev = dev;
223	stub_clk->cl.tx_done = NULL;
224	stub_clk->cl.tx_block = true;
225	stub_clk->cl.tx_tout = 500;
226	stub_clk->cl.knows_txdone = false;
227
228	/* Allocate mailbox channel */
229	stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
230	if (IS_ERR(stub_clk->mbox)) {
231	dev_err(dev, "failed get mailbox channel\n");
232	return PTR_ERR(stub_clk->mbox);
90c53547	233	}
c1628a2c LY	234
	235	init.name = "acpu0";
	236	init.ops = &hi6220_stub_clk_ops;
	237	init.num_parents = 0;
f61990f3	238	init.flags = 0;
c1628a2c LY	239
	240	clk = devm_clk_register(dev, &stub_clk->hw);
	241	if (IS_ERR(clk))
	242	return PTR_ERR(clk);
	243
	244	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
	245	if (ret) {
	246	dev_err(dev, "failed to register OF clock provider\n");
	247	return ret;
	248	}
	249
	250	/* initialize buffer to zero */
	251	regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
	252	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
	253	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);
	254
	255	dev_dbg(dev, "Registered clock '%s'\n", init.name);
	256	return 0;
	257	}
	258
	259	static const struct of_device_id hi6220_stub_clk_of_match[] = {
	260	{ .compatible = "hisilicon,hi6220-stub-clk", },
	261	{}
	262	};
	263
	264	static struct platform_driver hi6220_stub_clk_driver = {
	265	.driver = {
	266	.name = "hi6220-stub-clk",
	267	.of_match_table = hi6220_stub_clk_of_match,
	268	},
	269	.probe = hi6220_stub_clk_probe,
	270	};
	271
	272	static int __init hi6220_stub_clk_init(void)
	273	{
	274	return platform_driver_register(&hi6220_stub_clk_driver);
	275	}
	276	subsys_initcall(hi6220_stub_clk_init);