[linux-block.git] / drivers / clk / davinci / psc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Clock driver for TI Davinci PSC controllers
 *
 * Copyright (C) 2017 David Lechner <david@lechnology.com>
 *
 * Based on: drivers/clk/keystone/gate.c
 * Copyright (C) 2013 Texas Instruments.
 *	Murali Karicheri <m-karicheri2@ti.com>
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * And: arch/arm/mach-davinci/psc.c
 * Copyright (C) 2006 Texas Instruments.
 */

#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>

#include "psc.h"

/* PSC register offsets */
#define EPCPR			0x070
#define PTCMD			0x120
#define PTSTAT			0x128
#define PDSTAT(n)		(0x200 + 4 * (n))
#define PDCTL(n)		(0x300 + 4 * (n))
#define MDSTAT(n)		(0x800 + 4 * (n))
#define MDCTL(n)		(0xa00 + 4 * (n))

/* PSC module states */
enum davinci_lpsc_state {
	LPSC_STATE_SWRSTDISABLE	= 0,
	LPSC_STATE_SYNCRST	= 1,
	LPSC_STATE_DISABLE	= 2,
	LPSC_STATE_ENABLE	= 3,
};

#define MDSTAT_STATE_MASK	GENMASK(5, 0)
#define MDSTAT_MCKOUT		BIT(12)
#define PDSTAT_STATE_MASK	GENMASK(4, 0)
#define MDCTL_FORCE		BIT(31)
#define MDCTL_LRESET		BIT(8)
#define PDCTL_EPCGOOD		BIT(8)
#define PDCTL_NEXT		BIT(0)

struct davinci_psc_data {
	struct clk_onecell_data clk_data;
	struct genpd_onecell_data pm_data;
	struct reset_controller_dev rcdev;
};

/**
 * struct davinci_lpsc_clk - LPSC clock structure
 * @dev: the device that provides this LPSC
 * @hw: clk_hw for the LPSC
 * @pm_domain: power domain for the LPSC
 * @genpd_clk: clock reference owned by @pm_domain
 * @regmap: PSC MMIO region
 * @md: Module domain (LPSC module id)
 * @pd: Power domain
 * @flags: LPSC_* quirk flags
 */
struct davinci_lpsc_clk {
	struct device *dev;
	struct clk_hw hw;
	struct generic_pm_domain pm_domain;
	struct clk *genpd_clk;
	struct regmap *regmap;
	u32 md;
	u32 pd;
	u32 flags;
};

#define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
#define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)

/**
 * best_dev_name - get the "best" device name.
 * @dev: the device
 *
 * Returns the device tree compatible name if the device has a DT node,
 * otherwise return the device name. This is mainly needed because clkdev
 * lookups are limited to 20 chars for dev_id and when using device tree,
 * dev_name(dev) is much longer than that.
 */
static inline const char *best_dev_name(struct device *dev)
{
	const char *compatible;

	if (!of_property_read_string(dev->of_node, "compatible", &compatible))
		return compatible;

	return dev_name(dev);
}

static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
				enum davinci_lpsc_state next_state)
{
	u32 epcpr, pdstat, mdstat, ptstat;

	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
			  next_state);

	if (lpsc->flags & LPSC_FORCE)
		regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
				  MDCTL_FORCE);

	regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
	if ((pdstat & PDSTAT_STATE_MASK) == 0) {
		regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
				  PDCTL_NEXT);

		regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));

		regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
					 epcpr & BIT(lpsc->pd), 0, 0);

		regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
				  PDCTL_EPCGOOD);
	} else {
		regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
	}

	regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
				 !(ptstat & BIT(lpsc->pd)), 0, 0);

	regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
				 (mdstat & MDSTAT_STATE_MASK) == next_state,
				 0, 0);
}

static int davinci_lpsc_clk_enable(struct clk_hw *hw)
{
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);

	davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);

	return 0;
}

static void davinci_lpsc_clk_disable(struct clk_hw *hw)
{
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);

	davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
}

static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
{
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
	u32 mdstat;

	regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);

	return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
}

static const struct clk_ops davinci_lpsc_clk_ops = {
	.enable		= davinci_lpsc_clk_enable,
	.disable	= davinci_lpsc_clk_disable,
	.is_enabled	= davinci_lpsc_clk_is_enabled,
};

static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
					struct device *dev)
{
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
	struct clk *clk;
	int ret;

	/*
	 * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
	 * to get the clock instead of using lpsc->hw.clk directly.
	 */
	clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
	if (IS_ERR(clk))
		return (PTR_ERR(clk));

	ret = pm_clk_create(dev);
	if (ret < 0)
		goto fail_clk_put;

	ret = pm_clk_add_clk(dev, clk);
	if (ret < 0)
		goto fail_pm_clk_destroy;

	lpsc->genpd_clk = clk;

	return 0;

fail_pm_clk_destroy:
	pm_clk_destroy(dev);
fail_clk_put:
	clk_put(clk);

	return ret;
}

static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
					 struct device *dev)
{
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);

	pm_clk_remove_clk(dev, lpsc->genpd_clk);
	pm_clk_destroy(dev);

	lpsc->genpd_clk = NULL;
}

/**
 * davinci_lpsc_clk_register - register LPSC clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @regmap: PSC MMIO region
 * @md: local PSC number
 * @pd: power domain
 * @flags: LPSC_* flags
 */
static struct davinci_lpsc_clk *
davinci_lpsc_clk_register(struct device *dev, const char *name,
			  const char *parent_name, struct regmap *regmap,
			  u32 md, u32 pd, u32 flags)
{
	struct clk_init_data init;
	struct davinci_lpsc_clk *lpsc;
	int ret;
	bool is_on;

	lpsc = devm_kzalloc(dev, sizeof(*lpsc), GFP_KERNEL);
	if (!lpsc)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &davinci_lpsc_clk_ops;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	init.flags = 0;

	if (flags & LPSC_ALWAYS_ENABLED)
		init.flags |= CLK_IS_CRITICAL;

	if (flags & LPSC_SET_RATE_PARENT)
		init.flags |= CLK_SET_RATE_PARENT;

	lpsc->dev = dev;
	lpsc->regmap = regmap;
	lpsc->hw.init = &init;
	lpsc->md = md;
	lpsc->pd = pd;
	lpsc->flags = flags;

	ret = devm_clk_hw_register(dev, &lpsc->hw);
	if (ret < 0)
		return ERR_PTR(ret);

	/* genpd attach needs a way to look up this clock */
	ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));

	lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
					      best_dev_name(dev), name);
	lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
	lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
	lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;

	is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
	pm_genpd_init(&lpsc->pm_domain, NULL, is_on);

	return lpsc;
}

static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
{
	struct clk_hw *hw = __clk_get_hw(clk);
	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
	u32 mdctl;

	if (IS_ERR_OR_NULL(lpsc))
		return -EINVAL;

	mdctl = reset ? 0 : MDCTL_LRESET;
	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);

	return 0;
}

/*
 * REVISIT: These exported functions can be removed after a non-DT lookup is
 * added to the reset controller framework and the davinci-rproc driver is
 * updated to use the generic reset controller framework.
 */

int davinci_clk_reset_assert(struct clk *clk)
{
	return davinci_lpsc_clk_reset(clk, true);
}
EXPORT_SYMBOL(davinci_clk_reset_assert);

int davinci_clk_reset_deassert(struct clk *clk)
{
	return davinci_lpsc_clk_reset(clk, false);
}
EXPORT_SYMBOL(davinci_clk_reset_deassert);

static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
				    unsigned long id)
{
	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
	struct clk *clk = psc->clk_data.clks[id];

	return davinci_lpsc_clk_reset(clk, true);
}

static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
				      unsigned long id)
{
	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
	struct clk *clk = psc->clk_data.clks[id];

	return davinci_lpsc_clk_reset(clk, false);
}

static const struct reset_control_ops davinci_psc_reset_ops = {
	.assert		= davinci_psc_reset_assert,
	.deassert	= davinci_psc_reset_deassert,
};

static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
				      const struct of_phandle_args *reset_spec)
{
	struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */
	struct clk *clk;
	struct clk_hw *hw;
	struct davinci_lpsc_clk *lpsc;

	/* the clock node is the same as the reset node */
	clk = of_clk_get_from_provider(&clkspec);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	hw = __clk_get_hw(clk);
	lpsc = to_davinci_lpsc_clk(hw);
	clk_put(clk);

	/* not all modules support local reset */
	if (!(lpsc->flags & LPSC_LOCAL_RESET))
		return -EINVAL;

	return lpsc->md;
}

static const struct regmap_config davinci_psc_regmap_config = {
	.reg_bits	= 32,
	.reg_stride	= 4,
	.val_bits	= 32,
};

static struct davinci_psc_data *
__davinci_psc_register_clocks(struct device *dev,
			      const struct davinci_lpsc_clk_info *info,
			      int num_clks,
			      void __iomem *base)
{
	struct davinci_psc_data *psc;
	struct clk **clks;
	struct generic_pm_domain **pm_domains;
	struct regmap *regmap;
	int i, ret;

	psc = devm_kzalloc(dev, sizeof(*psc), GFP_KERNEL);
	if (!psc)
		return ERR_PTR(-ENOMEM);

	clks = devm_kmalloc_array(dev, num_clks, sizeof(*clks), GFP_KERNEL);
	if (!clks)
		return ERR_PTR(-ENOMEM);

	psc->clk_data.clks = clks;
	psc->clk_data.clk_num = num_clks;

	/*
	 * init array with error so that of_clk_src_onecell_get() doesn't
	 * return NULL for gaps in the sparse array
	 */
	for (i = 0; i < num_clks; i++)
		clks[i] = ERR_PTR(-ENOENT);

	pm_domains = devm_kcalloc(dev, num_clks, sizeof(*pm_domains), GFP_KERNEL);
	if (!pm_domains)
		return ERR_PTR(-ENOMEM);

	psc->pm_data.domains = pm_domains;
	psc->pm_data.num_domains = num_clks;

	regmap = devm_regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
	if (IS_ERR(regmap))
		return ERR_CAST(regmap);

	for (; info->name; info++) {
		struct davinci_lpsc_clk *lpsc;

		lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
						 regmap, info->md, info->pd,
						 info->flags);
		if (IS_ERR(lpsc)) {
			dev_warn(dev, "Failed to register %s (%ld)\n",
				 info->name, PTR_ERR(lpsc));
			continue;
		}

		clks[info->md] = lpsc->hw.clk;
		pm_domains[info->md] = &lpsc->pm_domain;
	}

	psc->rcdev.ops = &davinci_psc_reset_ops;
	psc->rcdev.owner = THIS_MODULE;
	psc->rcdev.dev = dev;
	psc->rcdev.of_node = dev->of_node;
	psc->rcdev.of_reset_n_cells = 1;
	psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
	psc->rcdev.nr_resets = num_clks;

	ret = devm_reset_controller_register(dev, &psc->rcdev);
	if (ret < 0)
		dev_warn(dev, "Failed to register reset controller (%d)\n", ret);

	return psc;
}

int davinci_psc_register_clocks(struct device *dev,
				const struct davinci_lpsc_clk_info *info,
				u8 num_clks,
				void __iomem *base)
{
	struct davinci_psc_data *psc;

	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
	if (IS_ERR(psc))
		return PTR_ERR(psc);

	for (; info->name; info++) {
		const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
		struct clk *clk = psc->clk_data.clks[info->md];

		if (!cdevs || IS_ERR_OR_NULL(clk))
			continue;

		for (; cdevs->con_id || cdevs->dev_id; cdevs++)
			clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
	}

	return 0;
}

int of_davinci_psc_clk_init(struct device *dev,
			    const struct davinci_lpsc_clk_info *info,
			    u8 num_clks,
			    void __iomem *base)
{
	struct device_node *node = dev->of_node;
	struct davinci_psc_data *psc;

	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
	if (IS_ERR(psc))
		return PTR_ERR(psc);

	of_genpd_add_provider_onecell(node, &psc->pm_data);

	of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);

	return 0;
}

static const struct of_device_id davinci_psc_of_match[] = {
	{ .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
	{ .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
	{ }
};

static const struct platform_device_id davinci_psc_id_table[] = {
	{ .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
	{ .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
	{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
	{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
	{ .name = "dm355-psc",  .driver_data = (kernel_ulong_t)&dm355_psc_init_data  },
	{ .name = "dm365-psc",  .driver_data = (kernel_ulong_t)&dm365_psc_init_data  },
	{ .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
	{ .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
	{ }
};

static int davinci_psc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	const struct davinci_psc_init_data *init_data = NULL;
	struct resource *res;
	void __iomem *base;
	int ret;

	of_id = of_match_device(davinci_psc_of_match, dev);
	if (of_id)
		init_data = of_id->data;
	else if (pdev->id_entry)
		init_data = (void *)pdev->id_entry->driver_data;

	if (!init_data) {
		dev_err(dev, "unable to find driver init data\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
				init_data->parent_clks);
	if (ret < 0)
		return ret;

	return init_data->psc_init(dev, base);
}

static struct platform_driver davinci_psc_driver = {
	.probe		= davinci_psc_probe,
	.driver		= {
		.name		= "davinci-psc-clk",
		.of_match_table	= davinci_psc_of_match,
	},
	.id_table	= davinci_psc_id_table,
};

static int __init davinci_psc_driver_init(void)
{
	return platform_driver_register(&davinci_psc_driver);
}

/* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
postcore_initcall(davinci_psc_driver_init);
Commit	Line	Data
c6ed4d73 DL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Clock driver for TI Davinci PSC controllers
	4	*
	5	* Copyright (C) 2017 David Lechner <david@lechnology.com>
	6	*
	7	* Based on: drivers/clk/keystone/gate.c
	8	* Copyright (C) 2013 Texas Instruments.
	9	* Murali Karicheri <m-karicheri2@ti.com>
	10	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
	12	* And: arch/arm/mach-davinci/psc.c
	13	* Copyright (C) 2006 Texas Instruments.
	14	*/
	15
	16	#include <linux/clk-provider.h>
	17	#include <linux/clk.h>
	18	#include <linux/clkdev.h>
	19	#include <linux/err.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_device.h>
	22	#include <linux/of.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/pm_clock.h>
	25	#include <linux/pm_domain.h>
	26	#include <linux/regmap.h>
	27	#include <linux/reset-controller.h>
	28	#include <linux/slab.h>
	29	#include <linux/types.h>
	30
	31	#include "psc.h"
	32
	33	/* PSC register offsets */
	34	#define EPCPR 0x070
	35	#define PTCMD 0x120
	36	#define PTSTAT 0x128
	37	#define PDSTAT(n) (0x200 + 4 * (n))
	38	#define PDCTL(n) (0x300 + 4 * (n))
	39	#define MDSTAT(n) (0x800 + 4 * (n))
	40	#define MDCTL(n) (0xa00 + 4 * (n))
	41
	42	/* PSC module states */
	43	enum davinci_lpsc_state {
	44	LPSC_STATE_SWRSTDISABLE = 0,
	45	LPSC_STATE_SYNCRST = 1,
	46	LPSC_STATE_DISABLE = 2,
	47	LPSC_STATE_ENABLE = 3,
	48	};
	49
	50	#define MDSTAT_STATE_MASK GENMASK(5, 0)
	51	#define MDSTAT_MCKOUT BIT(12)
	52	#define PDSTAT_STATE_MASK GENMASK(4, 0)
	53	#define MDCTL_FORCE BIT(31)
	54	#define MDCTL_LRESET BIT(8)
	55	#define PDCTL_EPCGOOD BIT(8)
	56	#define PDCTL_NEXT BIT(0)
	57
	58	struct davinci_psc_data {
	59	struct clk_onecell_data clk_data;
	60	struct genpd_onecell_data pm_data;
	61	struct reset_controller_dev rcdev;
	62	};
	63
	64	/**
65	* struct davinci_lpsc_clk - LPSC clock structure
66	* @dev: the device that provides this LPSC
67	* @hw: clk_hw for the LPSC
68	* @pm_domain: power domain for the LPSC
69	* @genpd_clk: clock reference owned by @pm_domain
70	* @regmap: PSC MMIO region
71	* @md: Module domain (LPSC module id)
72	* @pd: Power domain
73	* @flags: LPSC_* quirk flags
74	*/
75	struct davinci_lpsc_clk {
76	struct device *dev;
77	struct clk_hw hw;
78	struct generic_pm_domain pm_domain;
79	struct clk *genpd_clk;
80	struct regmap *regmap;
81	u32 md;
82	u32 pd;
83	u32 flags;
84	};
85
86	#define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
87	#define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)
88
89	/**
90	* best_dev_name - get the "best" device name.
91	* @dev: the device
92	*
93	* Returns the device tree compatible name if the device has a DT node,
94	* otherwise return the device name. This is mainly needed because clkdev
95	* lookups are limited to 20 chars for dev_id and when using device tree,
96	* dev_name(dev) is much longer than that.
97	*/
98	static inline const char best_dev_name(struct device dev)
99	{
100	const char *compatible;
101
102	if (!of_property_read_string(dev->of_node, "compatible", &compatible))
103	return compatible;
104
105	return dev_name(dev);
106	}
107
108	static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
109	enum davinci_lpsc_state next_state)
110	{
111	u32 epcpr, pdstat, mdstat, ptstat;
112
113	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
114	next_state);
115
116	if (lpsc->flags & LPSC_FORCE)
117	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
118	MDCTL_FORCE);
119
120	regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
121	if ((pdstat & PDSTAT_STATE_MASK) == 0) {
122	regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
123	PDCTL_NEXT);
124
125	regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
126
127	regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
128	epcpr & BIT(lpsc->pd), 0, 0);
129
130	regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
131	PDCTL_EPCGOOD);
132	} else {
133	regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
134	}
135
136	regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
137	!(ptstat & BIT(lpsc->pd)), 0, 0);
138
139	regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
140	(mdstat & MDSTAT_STATE_MASK) == next_state,
141	0, 0);
142	}
143
144	static int davinci_lpsc_clk_enable(struct clk_hw *hw)
145	{
146	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
147
148	davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);
149
150	return 0;
151	}
152
153	static void davinci_lpsc_clk_disable(struct clk_hw *hw)
154	{
155	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
156
157	davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
158	}
159
160	static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
161	{
162	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
163	u32 mdstat;
164
165	regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);
166
167	return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
168	}
169
170	static const struct clk_ops davinci_lpsc_clk_ops = {
171	.enable = davinci_lpsc_clk_enable,
172	.disable = davinci_lpsc_clk_disable,
173	.is_enabled = davinci_lpsc_clk_is_enabled,
174	};
175
176	static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
177	struct device *dev)
178	{
179	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
180	struct clk *clk;
181	int ret;
182
183	/*
184	* pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
185	* to get the clock instead of using lpsc->hw.clk directly.
186	*/
187	clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
188	if (IS_ERR(clk))
189	return (PTR_ERR(clk));
190
191	ret = pm_clk_create(dev);
192	if (ret < 0)
193	goto fail_clk_put;
194
195	ret = pm_clk_add_clk(dev, clk);
196	if (ret < 0)
197	goto fail_pm_clk_destroy;
198
199	lpsc->genpd_clk = clk;
200
201	return 0;
202
203	fail_pm_clk_destroy:
204	pm_clk_destroy(dev);
205	fail_clk_put:
206	clk_put(clk);
207
208	return ret;
209	}
210
211	static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
212	struct device *dev)
213	{
214	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
215
216	pm_clk_remove_clk(dev, lpsc->genpd_clk);
217	pm_clk_destroy(dev);
218
219	lpsc->genpd_clk = NULL;
220	}
221
222	/**
223	* davinci_lpsc_clk_register - register LPSC clock
224	* @name: name of this clock
225	* @parent_name: name of clock's parent
226	* @regmap: PSC MMIO region
227	* @md: local PSC number
228	* @pd: power domain
229	* @flags: LPSC_* flags
230	*/
231	static struct davinci_lpsc_clk *
232	davinci_lpsc_clk_register(struct device dev, const char name,
233	const char parent_name, struct regmap regmap,
234	u32 md, u32 pd, u32 flags)
235	{
236	struct clk_init_data init;
237	struct davinci_lpsc_clk *lpsc;
238	int ret;
239	bool is_on;
240
241	lpsc = devm_kzalloc(dev, sizeof(*lpsc), GFP_KERNEL);
242	if (!lpsc)
243	return ERR_PTR(-ENOMEM);
244
245	init.name = name;
246	init.ops = &davinci_lpsc_clk_ops;
247	init.parent_names = (parent_name ? &parent_name : NULL);
248	init.num_parents = (parent_name ? 1 : 0);
249	init.flags = 0;
250
251	if (flags & LPSC_ALWAYS_ENABLED)
252	init.flags \|= CLK_IS_CRITICAL;
253
254	if (flags & LPSC_SET_RATE_PARENT)
255	init.flags \|= CLK_SET_RATE_PARENT;
256
257	lpsc->dev = dev;
258	lpsc->regmap = regmap;
259	lpsc->hw.init = &init;
260	lpsc->md = md;
261	lpsc->pd = pd;
262	lpsc->flags = flags;
263
264	ret = devm_clk_hw_register(dev, &lpsc->hw);
265	if (ret < 0)
266	return ERR_PTR(ret);
267
268	/* genpd attach needs a way to look up this clock */
269	ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
270
271	lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
272	best_dev_name(dev), name);
273	lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
274	lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
275	lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;
276
277	is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
278	pm_genpd_init(&lpsc->pm_domain, NULL, is_on);
279
280	return lpsc;
281	}
282
283	static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
284	{
285	struct clk_hw *hw = __clk_get_hw(clk);
286	struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
287	u32 mdctl;
288
289	if (IS_ERR_OR_NULL(lpsc))
290	return -EINVAL;
291
292	mdctl = reset ? 0 : MDCTL_LRESET;
293	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);
294
295	return 0;
296	}
297
298	/*
299	* REVISIT: These exported functions can be removed after a non-DT lookup is
300	* added to the reset controller framework and the davinci-rproc driver is
301	* updated to use the generic reset controller framework.
302	*/
303
304	int davinci_clk_reset_assert(struct clk *clk)
305	{
306	return davinci_lpsc_clk_reset(clk, true);
307	}
308	EXPORT_SYMBOL(davinci_clk_reset_assert);
309
310	int davinci_clk_reset_deassert(struct clk *clk)
311	{
312	return davinci_lpsc_clk_reset(clk, false);
313	}
314	EXPORT_SYMBOL(davinci_clk_reset_deassert);
315
316	static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
317	unsigned long id)
318	{
319	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
320	struct clk *clk = psc->clk_data.clks[id];
321
322	return davinci_lpsc_clk_reset(clk, true);
323	}
324
325	static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
326	unsigned long id)
327	{
328	struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
329	struct clk *clk = psc->clk_data.clks[id];
330
331	return davinci_lpsc_clk_reset(clk, false);
332	}
333
334	static const struct reset_control_ops davinci_psc_reset_ops = {
335	.assert = davinci_psc_reset_assert,
336	.deassert = davinci_psc_reset_deassert,
337	};
338
339	static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
340	const struct of_phandle_args *reset_spec)
341	{
342	struct of_phandle_args clkspec = reset_spec; / discard const qualifier */
343	struct clk *clk;
344	struct clk_hw *hw;
345	struct davinci_lpsc_clk *lpsc;
346
347	/* the clock node is the same as the reset node */
348	clk = of_clk_get_from_provider(&clkspec);
349	if (IS_ERR(clk))
350	return PTR_ERR(clk);
351
352	hw = __clk_get_hw(clk);
353	lpsc = to_davinci_lpsc_clk(hw);
354	clk_put(clk);
355
356	/* not all modules support local reset */
357	if (!(lpsc->flags & LPSC_LOCAL_RESET))
358	return -EINVAL;
359
360	return lpsc->md;
361	}
362
363	static const struct regmap_config davinci_psc_regmap_config = {
364	.reg_bits = 32,
365	.reg_stride = 4,
366	.val_bits = 32,
367	};
368
369	static struct davinci_psc_data *
370	__davinci_psc_register_clocks(struct device *dev,
371	const struct davinci_lpsc_clk_info *info,
372	int num_clks,
373	void __iomem *base)
374	{
375	struct davinci_psc_data *psc;
376	struct clk **clks;
377	struct generic_pm_domain **pm_domains;
378	struct regmap *regmap;
379	int i, ret;
380
381	psc = devm_kzalloc(dev, sizeof(*psc), GFP_KERNEL);
382	if (!psc)
383	return ERR_PTR(-ENOMEM);
384
385	clks = devm_kmalloc_array(dev, num_clks, sizeof(*clks), GFP_KERNEL);
386	if (!clks)
387	return ERR_PTR(-ENOMEM);
388
389	psc->clk_data.clks = clks;
390	psc->clk_data.clk_num = num_clks;
391
392	/*
393	* init array with error so that of_clk_src_onecell_get() doesn't
394	* return NULL for gaps in the sparse array
395	*/
396	for (i = 0; i < num_clks; i++)
397	clks[i] = ERR_PTR(-ENOENT);
398
399	pm_domains = devm_kcalloc(dev, num_clks, sizeof(*pm_domains), GFP_KERNEL);
400	if (!pm_domains)
401	return ERR_PTR(-ENOMEM);
402
403	psc->pm_data.domains = pm_domains;
404	psc->pm_data.num_domains = num_clks;
405
406	regmap = devm_regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
407	if (IS_ERR(regmap))
408	return ERR_CAST(regmap);
409
410	for (; info->name; info++) {
411	struct davinci_lpsc_clk *lpsc;
412
413	lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
414	regmap, info->md, info->pd,
415	info->flags);
416	if (IS_ERR(lpsc)) {
417	dev_warn(dev, "Failed to register %s (%ld)\n",
418	info->name, PTR_ERR(lpsc));
419	continue;
420	}
421
422	clks[info->md] = lpsc->hw.clk;
423	pm_domains[info->md] = &lpsc->pm_domain;
424	}
425
426	psc->rcdev.ops = &davinci_psc_reset_ops;
427	psc->rcdev.owner = THIS_MODULE;
5ced1923	428	psc->rcdev.dev = dev;
c6ed4d73 DL	429	psc->rcdev.of_node = dev->of_node;
	430	psc->rcdev.of_reset_n_cells = 1;
	431	psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
	432	psc->rcdev.nr_resets = num_clks;
	433
	434	ret = devm_reset_controller_register(dev, &psc->rcdev);
	435	if (ret < 0)
	436	dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
	437
	438	return psc;
	439	}
	440
	441	int davinci_psc_register_clocks(struct device *dev,
	442	const struct davinci_lpsc_clk_info *info,
	443	u8 num_clks,
	444	void __iomem *base)
	445	{
	446	struct davinci_psc_data *psc;
	447
	448	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
	449	if (IS_ERR(psc))
	450	return PTR_ERR(psc);
	451
	452	for (; info->name; info++) {
	453	const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
	454	struct clk *clk = psc->clk_data.clks[info->md];
	455
	456	if (!cdevs \|\| IS_ERR_OR_NULL(clk))
	457	continue;
	458
	459	for (; cdevs->con_id \|\| cdevs->dev_id; cdevs++)
	460	clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
	461	}
	462
	463	return 0;
	464	}
	465
	466	int of_davinci_psc_clk_init(struct device *dev,
	467	const struct davinci_lpsc_clk_info *info,
	468	u8 num_clks,
	469	void __iomem *base)
	470	{
	471	struct device_node *node = dev->of_node;
	472	struct davinci_psc_data *psc;
	473
	474	psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
	475	if (IS_ERR(psc))
	476	return PTR_ERR(psc);
	477
	478	of_genpd_add_provider_onecell(node, &psc->pm_data);
	479
	480	of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);
	481
	482	return 0;
	483	}
	484
	485	static const struct of_device_id davinci_psc_of_match[] = {
a47d6040 DL	486	{ .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
a47d6040 DL	487	{ .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
c6ed4d73 DL	488	{ }
	489	};
	490
	491	static const struct platform_device_id davinci_psc_id_table[] = {
c2952e27 DL	492	{ .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
c2952e27 DL	493	{ .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
a47d6040 DL	494	{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
a47d6040 DL	495	{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
b99bfca5	496	{ .name = "dm355-psc", .driver_data = (kernel_ulong_t)&dm355_psc_init_data },
9ab1102c	497	{ .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data },
f41e5275	498	{ .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
aad739f9	499	{ .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
c6ed4d73 DL	500	{ }
	501	};
	502
	503	static int davinci_psc_probe(struct platform_device *pdev)
	504	{
	505	struct device *dev = &pdev->dev;
	506	const struct of_device_id *of_id;
	507	const struct davinci_psc_init_data *init_data = NULL;
	508	struct resource *res;
	509	void __iomem *base;
	510	int ret;
	511
	512	of_id = of_match_device(davinci_psc_of_match, dev);
	513	if (of_id)
	514	init_data = of_id->data;
	515	else if (pdev->id_entry)
	516	init_data = (void *)pdev->id_entry->driver_data;
	517
	518	if (!init_data) {
	519	dev_err(dev, "unable to find driver init data\n");
	520	return -EINVAL;
	521	}
	522
	523	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	524	base = devm_ioremap_resource(dev, res);
fc3fcb4f	525	if (IS_ERR(base))
c6ed4d73	526	return PTR_ERR(base);
c6ed4d73 DL	527
	528	ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
	529	init_data->parent_clks);
	530	if (ret < 0)
	531	return ret;
	532
	533	return init_data->psc_init(dev, base);
	534	}
	535
	536	static struct platform_driver davinci_psc_driver = {
	537	.probe = davinci_psc_probe,
	538	.driver = {
	539	.name = "davinci-psc-clk",
	540	.of_match_table = davinci_psc_of_match,
	541	},
	542	.id_table = davinci_psc_id_table,
	543	};
	544
	545	static int __init davinci_psc_driver_init(void)
	546	{
	547	return platform_driver_register(&davinci_psc_driver);
	548	}
	549
	550	/* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
	551	postcore_initcall(davinci_psc_driver_init);