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41d59175 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2d172691 DL |
2 | /* |
3 | * Clock driver for TI Davinci PSC controllers | |
4 | * | |
5 | * Copyright (C) 2018 David Lechner <david@lechnology.com> | |
6 | */ | |
7 | ||
8 | #ifndef __CLK_DAVINCI_PLL_H___ | |
9 | #define __CLK_DAVINCI_PLL_H___ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/of.h> | |
76c9dd9d | 14 | #include <linux/regmap.h> |
2d172691 DL |
15 | #include <linux/types.h> |
16 | ||
17 | #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ | |
18 | #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */ | |
19 | #define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */ | |
20 | #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */ | |
21 | #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */ | |
22 | #define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */ | |
23 | #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */ | |
24 | #define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */ | |
25 | #define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */ | |
26 | #define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */ | |
27 | ||
28 | /** davinci_pll_clk_info - controller-specific PLL info | |
29 | * @name: The name of the PLL | |
30 | * @unlock_reg: Option CFGCHIP register for unlocking PLL | |
31 | * @unlock_mask: Bitmask used with @unlock_reg | |
32 | * @pllm_mask: Bitmask for PLLM[PLLM] value | |
33 | * @pllm_min: Minimum allowable value for PLLM[PLLM] | |
34 | * @pllm_max: Maximum allowable value for PLLM[PLLM] | |
35 | * @pllout_min_rate: Minimum allowable rate for PLLOUT | |
36 | * @pllout_max_rate: Maximum allowable rate for PLLOUT | |
37 | * @flags: Bitmap of PLL_* flags. | |
38 | */ | |
39 | struct davinci_pll_clk_info { | |
40 | const char *name; | |
41 | u32 unlock_reg; | |
42 | u32 unlock_mask; | |
43 | u32 pllm_mask; | |
44 | u32 pllm_min; | |
45 | u32 pllm_max; | |
46 | unsigned long pllout_min_rate; | |
47 | unsigned long pllout_max_rate; | |
48 | u32 flags; | |
49 | }; | |
50 | ||
51 | #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */ | |
52 | #define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */ | |
53 | #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */ | |
54 | ||
55 | /** davinci_pll_sysclk_info - SYSCLKn-specific info | |
56 | * @name: The name of the clock | |
57 | * @parent_name: The name of the parent clock | |
58 | * @id: "n" in "SYSCLKn" | |
59 | * @ratio_width: Width (in bits) of RATIO in PLLDIVn register | |
60 | * @flags: Bitmap of SYSCLK_* flags. | |
61 | */ | |
62 | struct davinci_pll_sysclk_info { | |
63 | const char *name; | |
64 | const char *parent_name; | |
65 | u32 id; | |
66 | u32 ratio_width; | |
67 | u32 flags; | |
68 | }; | |
69 | ||
70 | #define SYSCLK(i, n, p, w, f) \ | |
71 | static const struct davinci_pll_sysclk_info n = { \ | |
72 | .name = #n, \ | |
73 | .parent_name = #p, \ | |
74 | .id = (i), \ | |
75 | .ratio_width = (w), \ | |
76 | .flags = (f), \ | |
77 | } | |
78 | ||
79 | /** davinci_pll_obsclk_info - OBSCLK-specific info | |
80 | * @name: The name of the clock | |
81 | * @parent_names: Array of names of the parent clocks | |
82 | * @num_parents: Length of @parent_names | |
83 | * @table: Array of values to write to OCSEL[OCSRC] cooresponding to | |
84 | * @parent_names | |
85 | * @ocsrc_mask: Bitmask for OCSEL[OCSRC] | |
86 | */ | |
87 | struct davinci_pll_obsclk_info { | |
88 | const char *name; | |
89 | const char * const *parent_names; | |
90 | u8 num_parents; | |
91 | u32 *table; | |
92 | u32 ocsrc_mask; | |
93 | }; | |
94 | ||
95 | struct clk *davinci_pll_clk_register(struct device *dev, | |
96 | const struct davinci_pll_clk_info *info, | |
97 | const char *parent_name, | |
76c9dd9d DL |
98 | void __iomem *base, |
99 | struct regmap *cfgchip); | |
2d172691 DL |
100 | struct clk *davinci_pll_auxclk_register(struct device *dev, |
101 | const char *name, | |
102 | void __iomem *base); | |
103 | struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, | |
104 | const char *name, | |
105 | void __iomem *base); | |
106 | struct clk * | |
107 | davinci_pll_obsclk_register(struct device *dev, | |
108 | const struct davinci_pll_obsclk_info *info, | |
109 | void __iomem *base); | |
110 | struct clk * | |
111 | davinci_pll_sysclk_register(struct device *dev, | |
112 | const struct davinci_pll_sysclk_info *info, | |
113 | void __iomem *base); | |
114 | ||
76c9dd9d | 115 | int of_davinci_pll_init(struct device *dev, struct device_node *node, |
2d172691 DL |
116 | const struct davinci_pll_clk_info *info, |
117 | const struct davinci_pll_obsclk_info *obsclk_info, | |
118 | const struct davinci_pll_sysclk_info **div_info, | |
119 | u8 max_sysclk_id, | |
76c9dd9d DL |
120 | void __iomem *base, |
121 | struct regmap *cfgchip); | |
2d172691 | 122 | |
c92765fd DL |
123 | /* Platform-specific callbacks */ |
124 | ||
76c9dd9d | 125 | int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); |
17d8bacf | 126 | void of_da850_pll0_init(struct device_node *node); |
76c9dd9d | 127 | int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); |
6ef35851 | 128 | |
2d172691 | 129 | #endif /* __CLK_DAVINCI_PLL_H___ */ |