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2d172691 DL |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * PLL clock driver for TI Davinci SoCs | |
4 | * | |
5 | * Copyright (C) 2018 David Lechner <david@lechnology.com> | |
6 | * | |
7 | * Based on arch/arm/mach-davinci/clock.c | |
8 | * Copyright (C) 2006-2007 Texas Instruments. | |
9 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
10 | */ | |
11 | ||
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/clk.h> | |
76c9dd9d | 14 | #include <linux/clk/davinci.h> |
2d172691 DL |
15 | #include <linux/delay.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/mfd/syscon.h> | |
20 | #include <linux/notifier.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/platform_data/clk-davinci-pll.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/regmap.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/types.h> | |
29 | ||
30 | #include "pll.h" | |
31 | ||
32 | #define MAX_NAME_SIZE 20 | |
33 | #define OSCIN_CLK_NAME "oscin" | |
34 | ||
35 | #define REVID 0x000 | |
36 | #define PLLCTL 0x100 | |
37 | #define OCSEL 0x104 | |
38 | #define PLLSECCTL 0x108 | |
39 | #define PLLM 0x110 | |
40 | #define PREDIV 0x114 | |
41 | #define PLLDIV1 0x118 | |
42 | #define PLLDIV2 0x11c | |
43 | #define PLLDIV3 0x120 | |
44 | #define OSCDIV 0x124 | |
45 | #define POSTDIV 0x128 | |
46 | #define BPDIV 0x12c | |
47 | #define PLLCMD 0x138 | |
48 | #define PLLSTAT 0x13c | |
49 | #define ALNCTL 0x140 | |
50 | #define DCHANGE 0x144 | |
51 | #define CKEN 0x148 | |
52 | #define CKSTAT 0x14c | |
53 | #define SYSTAT 0x150 | |
54 | #define PLLDIV4 0x160 | |
55 | #define PLLDIV5 0x164 | |
56 | #define PLLDIV6 0x168 | |
57 | #define PLLDIV7 0x16c | |
58 | #define PLLDIV8 0x170 | |
59 | #define PLLDIV9 0x174 | |
60 | ||
61 | #define PLLCTL_PLLEN BIT(0) | |
62 | #define PLLCTL_PLLPWRDN BIT(1) | |
63 | #define PLLCTL_PLLRST BIT(3) | |
64 | #define PLLCTL_PLLDIS BIT(4) | |
65 | #define PLLCTL_PLLENSRC BIT(5) | |
66 | #define PLLCTL_CLKMODE BIT(8) | |
67 | ||
68 | /* shared by most *DIV registers */ | |
69 | #define DIV_RATIO_SHIFT 0 | |
70 | #define DIV_RATIO_WIDTH 5 | |
71 | #define DIV_ENABLE_SHIFT 15 | |
72 | ||
73 | #define PLLCMD_GOSET BIT(0) | |
74 | #define PLLSTAT_GOSTAT BIT(0) | |
75 | ||
76 | #define CKEN_OBSCLK_SHIFT 1 | |
77 | #define CKEN_AUXEN_SHIFT 0 | |
78 | ||
79 | /* | |
80 | * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN | |
81 | * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us | |
82 | * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input | |
83 | * is ~25MHz. Units are micro seconds. | |
84 | */ | |
85 | #define PLL_BYPASS_TIME 1 | |
86 | ||
87 | /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ | |
88 | #define PLL_RESET_TIME 1 | |
89 | ||
90 | /* | |
91 | * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 | |
92 | * Units are micro seconds. | |
93 | */ | |
94 | #define PLL_LOCK_TIME 20 | |
95 | ||
96 | /** | |
97 | * struct davinci_pll_clk - Main PLL clock (aka PLLOUT) | |
98 | * @hw: clk_hw for the pll | |
99 | * @base: Base memory address | |
100 | * @pllm_min: The minimum allowable PLLM[PLLM] value | |
101 | * @pllm_max: The maxiumum allowable PLLM[PLLM] value | |
102 | * @pllm_mask: Bitmask for PLLM[PLLM] value | |
103 | */ | |
104 | struct davinci_pll_clk { | |
105 | struct clk_hw hw; | |
106 | void __iomem *base; | |
107 | u32 pllm_min; | |
108 | u32 pllm_max; | |
109 | u32 pllm_mask; | |
110 | }; | |
111 | ||
112 | #define to_davinci_pll_clk(_hw) \ | |
113 | container_of((_hw), struct davinci_pll_clk, hw) | |
114 | ||
115 | static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw, | |
116 | unsigned long parent_rate) | |
117 | { | |
118 | struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); | |
119 | unsigned long rate = parent_rate; | |
120 | u32 mult; | |
121 | ||
122 | mult = readl(pll->base + PLLM) & pll->pllm_mask; | |
123 | rate *= mult + 1; | |
124 | ||
125 | return rate; | |
126 | } | |
127 | ||
128 | static int davinci_pll_determine_rate(struct clk_hw *hw, | |
129 | struct clk_rate_request *req) | |
130 | { | |
131 | struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); | |
132 | struct clk_hw *parent = req->best_parent_hw; | |
133 | unsigned long parent_rate = req->best_parent_rate; | |
134 | unsigned long rate = req->rate; | |
135 | unsigned long best_rate, r; | |
136 | u32 mult; | |
137 | ||
138 | /* there is a limited range of valid outputs (see datasheet) */ | |
139 | if (rate < req->min_rate) | |
140 | return -EINVAL; | |
141 | ||
142 | rate = min(rate, req->max_rate); | |
143 | mult = rate / parent_rate; | |
144 | best_rate = parent_rate * mult; | |
145 | ||
146 | /* easy case when there is no PREDIV */ | |
147 | if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { | |
148 | if (best_rate < req->min_rate) | |
149 | return -EINVAL; | |
150 | ||
151 | if (mult < pll->pllm_min || mult > pll->pllm_max) | |
152 | return -EINVAL; | |
153 | ||
154 | req->rate = best_rate; | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | /* see if the PREDIV clock can help us */ | |
160 | best_rate = 0; | |
161 | ||
162 | for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { | |
163 | parent_rate = clk_hw_round_rate(parent, rate / mult); | |
164 | r = parent_rate * mult; | |
165 | if (r < req->min_rate) | |
166 | continue; | |
167 | if (r > rate || r > req->max_rate) | |
168 | break; | |
169 | if (r > best_rate) { | |
170 | best_rate = r; | |
171 | req->rate = best_rate; | |
172 | req->best_parent_rate = parent_rate; | |
173 | if (best_rate == rate) | |
174 | break; | |
175 | } | |
176 | } | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
182 | unsigned long parent_rate) | |
183 | { | |
184 | struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); | |
185 | u32 mult; | |
186 | ||
187 | mult = rate / parent_rate; | |
188 | writel(mult - 1, pll->base + PLLM); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | #ifdef CONFIG_DEBUG_FS | |
d75d50c0 | 194 | static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry); |
2d172691 DL |
195 | #else |
196 | #define davinci_pll_debug_init NULL | |
197 | #endif | |
198 | ||
199 | static const struct clk_ops davinci_pll_ops = { | |
200 | .recalc_rate = davinci_pll_recalc_rate, | |
201 | .determine_rate = davinci_pll_determine_rate, | |
202 | .set_rate = davinci_pll_set_rate, | |
203 | .debug_init = davinci_pll_debug_init, | |
204 | }; | |
205 | ||
206 | /* PLLM works differently on DM365 */ | |
207 | static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw, | |
208 | unsigned long parent_rate) | |
209 | { | |
210 | struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); | |
211 | unsigned long rate = parent_rate; | |
212 | u32 mult; | |
213 | ||
214 | mult = readl(pll->base + PLLM) & pll->pllm_mask; | |
215 | rate *= mult * 2; | |
216 | ||
217 | return rate; | |
218 | } | |
219 | ||
220 | static const struct clk_ops dm365_pll_ops = { | |
221 | .recalc_rate = dm365_pll_recalc_rate, | |
222 | .debug_init = davinci_pll_debug_init, | |
223 | }; | |
224 | ||
225 | /** | |
226 | * davinci_pll_div_register - common *DIV clock implementation | |
76c9dd9d | 227 | * @dev: The PLL platform device or NULL |
2d172691 DL |
228 | * @name: the clock name |
229 | * @parent_name: the parent clock name | |
230 | * @reg: the *DIV register | |
231 | * @fixed: if true, the divider is a fixed value | |
232 | * @flags: bitmap of CLK_* flags from clock-provider.h | |
233 | */ | |
234 | static struct clk *davinci_pll_div_register(struct device *dev, | |
235 | const char *name, | |
236 | const char *parent_name, | |
237 | void __iomem *reg, | |
238 | bool fixed, u32 flags) | |
239 | { | |
240 | const char * const *parent_names = parent_name ? &parent_name : NULL; | |
241 | int num_parents = parent_name ? 1 : 0; | |
242 | const struct clk_ops *divider_ops = &clk_divider_ops; | |
243 | struct clk_gate *gate; | |
244 | struct clk_divider *divider; | |
76c9dd9d DL |
245 | struct clk *clk; |
246 | int ret; | |
2d172691 | 247 | |
76c9dd9d | 248 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
2d172691 DL |
249 | if (!gate) |
250 | return ERR_PTR(-ENOMEM); | |
251 | ||
252 | gate->reg = reg; | |
253 | gate->bit_idx = DIV_ENABLE_SHIFT; | |
254 | ||
76c9dd9d DL |
255 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
256 | if (!divider) { | |
257 | ret = -ENOMEM; | |
258 | goto err_free_gate; | |
259 | } | |
2d172691 DL |
260 | |
261 | divider->reg = reg; | |
262 | divider->shift = DIV_RATIO_SHIFT; | |
263 | divider->width = DIV_RATIO_WIDTH; | |
264 | ||
265 | if (fixed) { | |
266 | divider->flags |= CLK_DIVIDER_READ_ONLY; | |
267 | divider_ops = &clk_divider_ro_ops; | |
268 | } | |
269 | ||
76c9dd9d DL |
270 | clk = clk_register_composite(dev, name, parent_names, num_parents, |
271 | NULL, NULL, ÷r->hw, divider_ops, | |
272 | &gate->hw, &clk_gate_ops, flags); | |
273 | if (IS_ERR(clk)) { | |
274 | ret = PTR_ERR(clk); | |
275 | goto err_free_divider; | |
276 | } | |
277 | ||
278 | return clk; | |
279 | ||
280 | err_free_divider: | |
281 | kfree(divider); | |
282 | err_free_gate: | |
283 | kfree(gate); | |
284 | ||
285 | return ERR_PTR(ret); | |
2d172691 DL |
286 | } |
287 | ||
288 | struct davinci_pllen_clk { | |
289 | struct clk_hw hw; | |
290 | void __iomem *base; | |
291 | }; | |
292 | ||
293 | #define to_davinci_pllen_clk(_hw) \ | |
294 | container_of((_hw), struct davinci_pllen_clk, hw) | |
295 | ||
296 | static const struct clk_ops davinci_pllen_ops = { | |
297 | /* this clocks just uses the clock notification feature */ | |
298 | }; | |
299 | ||
300 | /* | |
301 | * The PLL has to be switched into bypass mode while we are chaning the rate, | |
302 | * so we do that on the PLLEN clock since it is the end of the line. This will | |
303 | * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are | |
304 | * changed and will switch back to the PLL after the changes have been made. | |
305 | */ | |
306 | static int davinci_pllen_rate_change(struct notifier_block *nb, | |
307 | unsigned long flags, void *data) | |
308 | { | |
309 | struct clk_notifier_data *cnd = data; | |
310 | struct clk_hw *hw = __clk_get_hw(cnd->clk); | |
311 | struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); | |
312 | u32 ctrl; | |
313 | ||
314 | ctrl = readl(pll->base + PLLCTL); | |
315 | ||
316 | if (flags == PRE_RATE_CHANGE) { | |
317 | /* Switch the PLL to bypass mode */ | |
318 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
319 | writel(ctrl, pll->base + PLLCTL); | |
320 | ||
321 | udelay(PLL_BYPASS_TIME); | |
322 | ||
323 | /* Reset and enable PLL */ | |
324 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
325 | writel(ctrl, pll->base + PLLCTL); | |
326 | } else { | |
327 | udelay(PLL_RESET_TIME); | |
328 | ||
329 | /* Bring PLL out of reset */ | |
330 | ctrl |= PLLCTL_PLLRST; | |
331 | writel(ctrl, pll->base + PLLCTL); | |
332 | ||
333 | udelay(PLL_LOCK_TIME); | |
334 | ||
335 | /* Remove PLL from bypass mode */ | |
336 | ctrl |= PLLCTL_PLLEN; | |
337 | writel(ctrl, pll->base + PLLCTL); | |
338 | } | |
339 | ||
340 | return NOTIFY_OK; | |
341 | } | |
342 | ||
2d172691 DL |
343 | static struct notifier_block davinci_pllen_notifier = { |
344 | .notifier_call = davinci_pllen_rate_change, | |
345 | }; | |
346 | ||
347 | /** | |
348 | * davinci_pll_clk_register - Register a PLL clock | |
76c9dd9d | 349 | * @dev: The PLL platform device or NULL |
2d172691 DL |
350 | * @info: The device-specific clock info |
351 | * @parent_name: The parent clock name | |
352 | * @base: The PLL's memory region | |
76c9dd9d | 353 | * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL |
2d172691 DL |
354 | * |
355 | * This creates a series of clocks that represent the PLL. | |
356 | * | |
357 | * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN | |
358 | * | |
359 | * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL) | |
360 | * - PREDIV and POSTDIV are optional (depends on the PLL controller) | |
361 | * - PLL is the PLL output (aka PLLOUT) | |
362 | * - PLLEN is the bypass multiplexer | |
363 | * | |
364 | * Returns: The PLLOUT clock or a negative error code. | |
365 | */ | |
366 | struct clk *davinci_pll_clk_register(struct device *dev, | |
367 | const struct davinci_pll_clk_info *info, | |
368 | const char *parent_name, | |
76c9dd9d DL |
369 | void __iomem *base, |
370 | struct regmap *cfgchip) | |
2d172691 | 371 | { |
2d172691 DL |
372 | char prediv_name[MAX_NAME_SIZE]; |
373 | char pllout_name[MAX_NAME_SIZE]; | |
374 | char postdiv_name[MAX_NAME_SIZE]; | |
375 | char pllen_name[MAX_NAME_SIZE]; | |
376 | struct clk_init_data init; | |
377 | struct davinci_pll_clk *pllout; | |
378 | struct davinci_pllen_clk *pllen; | |
76c9dd9d DL |
379 | struct clk *oscin_clk = NULL; |
380 | struct clk *prediv_clk = NULL; | |
381 | struct clk *pllout_clk; | |
382 | struct clk *postdiv_clk = NULL; | |
383 | struct clk *pllen_clk; | |
384 | int ret; | |
2d172691 DL |
385 | |
386 | if (info->flags & PLL_HAS_CLKMODE) { | |
387 | /* | |
388 | * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL. | |
389 | * We register a clock named "oscin" that serves as the internal | |
390 | * "input clock" domain shared by both PLLs (if there are 2) | |
391 | * and will be the parent clock to the AUXCLK, SYSCLKBP and | |
392 | * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean | |
393 | * a number of different things. In this driver we use it to | |
394 | * mean the signal after the PLLCTL[CLKMODE] switch. | |
395 | */ | |
76c9dd9d DL |
396 | oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME, |
397 | parent_name, 0, 1, 1); | |
398 | if (IS_ERR(oscin_clk)) | |
399 | return oscin_clk; | |
2d172691 DL |
400 | |
401 | parent_name = OSCIN_CLK_NAME; | |
402 | } | |
403 | ||
404 | if (info->flags & PLL_HAS_PREDIV) { | |
405 | bool fixed = info->flags & PLL_PREDIV_FIXED_DIV; | |
406 | u32 flags = 0; | |
407 | ||
408 | snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name); | |
409 | ||
410 | if (info->flags & PLL_PREDIV_ALWAYS_ENABLED) | |
411 | flags |= CLK_IS_CRITICAL; | |
412 | ||
413 | /* Some? DM355 chips don't correctly report the PREDIV value */ | |
414 | if (info->flags & PLL_PREDIV_FIXED8) | |
76c9dd9d DL |
415 | prediv_clk = clk_register_fixed_factor(dev, prediv_name, |
416 | parent_name, flags, 1, 8); | |
2d172691 | 417 | else |
76c9dd9d | 418 | prediv_clk = davinci_pll_div_register(dev, prediv_name, |
2d172691 | 419 | parent_name, base + PREDIV, fixed, flags); |
76c9dd9d DL |
420 | if (IS_ERR(prediv_clk)) { |
421 | ret = PTR_ERR(prediv_clk); | |
422 | goto err_unregister_oscin; | |
423 | } | |
2d172691 DL |
424 | |
425 | parent_name = prediv_name; | |
426 | } | |
427 | ||
428 | /* Unlock writing to PLL registers */ | |
429 | if (info->unlock_reg) { | |
76c9dd9d | 430 | if (IS_ERR_OR_NULL(cfgchip)) |
2d172691 | 431 | dev_warn(dev, "Failed to get CFGCHIP (%ld)\n", |
76c9dd9d | 432 | PTR_ERR(cfgchip)); |
2d172691 | 433 | else |
76c9dd9d | 434 | regmap_write_bits(cfgchip, info->unlock_reg, |
2d172691 DL |
435 | info->unlock_mask, 0); |
436 | } | |
437 | ||
76c9dd9d DL |
438 | pllout = kzalloc(sizeof(*pllout), GFP_KERNEL); |
439 | if (!pllout) { | |
440 | ret = -ENOMEM; | |
441 | goto err_unregister_prediv; | |
442 | } | |
2d172691 DL |
443 | |
444 | snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name); | |
445 | ||
446 | init.name = pllout_name; | |
447 | if (info->flags & PLL_PLLM_2X) | |
448 | init.ops = &dm365_pll_ops; | |
449 | else | |
450 | init.ops = &davinci_pll_ops; | |
451 | init.parent_names = &parent_name; | |
452 | init.num_parents = 1; | |
453 | init.flags = 0; | |
454 | ||
455 | if (info->flags & PLL_HAS_PREDIV) | |
456 | init.flags |= CLK_SET_RATE_PARENT; | |
457 | ||
458 | pllout->hw.init = &init; | |
459 | pllout->base = base; | |
460 | pllout->pllm_mask = info->pllm_mask; | |
461 | pllout->pllm_min = info->pllm_min; | |
462 | pllout->pllm_max = info->pllm_max; | |
463 | ||
76c9dd9d DL |
464 | pllout_clk = clk_register(dev, &pllout->hw); |
465 | if (IS_ERR(pllout_clk)) { | |
466 | ret = PTR_ERR(pllout_clk); | |
467 | goto err_free_pllout; | |
468 | } | |
2d172691 DL |
469 | |
470 | clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate, | |
471 | info->pllout_max_rate); | |
472 | ||
473 | parent_name = pllout_name; | |
474 | ||
475 | if (info->flags & PLL_HAS_POSTDIV) { | |
476 | bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV; | |
477 | u32 flags = CLK_SET_RATE_PARENT; | |
478 | ||
479 | snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name); | |
480 | ||
481 | if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED) | |
482 | flags |= CLK_IS_CRITICAL; | |
483 | ||
76c9dd9d DL |
484 | postdiv_clk = davinci_pll_div_register(dev, postdiv_name, |
485 | parent_name, base + POSTDIV, fixed, flags); | |
486 | if (IS_ERR(postdiv_clk)) { | |
487 | ret = PTR_ERR(postdiv_clk); | |
488 | goto err_unregister_pllout; | |
489 | } | |
2d172691 DL |
490 | |
491 | parent_name = postdiv_name; | |
492 | } | |
493 | ||
3dabfa2b | 494 | pllen = kzalloc(sizeof(*pllen), GFP_KERNEL); |
76c9dd9d DL |
495 | if (!pllen) { |
496 | ret = -ENOMEM; | |
497 | goto err_unregister_postdiv; | |
498 | } | |
2d172691 DL |
499 | |
500 | snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name); | |
501 | ||
502 | init.name = pllen_name; | |
503 | init.ops = &davinci_pllen_ops; | |
504 | init.parent_names = &parent_name; | |
505 | init.num_parents = 1; | |
506 | init.flags = CLK_SET_RATE_PARENT; | |
507 | ||
508 | pllen->hw.init = &init; | |
509 | pllen->base = base; | |
510 | ||
76c9dd9d DL |
511 | pllen_clk = clk_register(dev, &pllen->hw); |
512 | if (IS_ERR(pllen_clk)) { | |
513 | ret = PTR_ERR(pllen_clk); | |
514 | goto err_free_pllen; | |
515 | } | |
2d172691 | 516 | |
76c9dd9d | 517 | clk_notifier_register(pllen_clk, &davinci_pllen_notifier); |
2d172691 DL |
518 | |
519 | return pllout_clk; | |
76c9dd9d DL |
520 | |
521 | err_free_pllen: | |
522 | kfree(pllen); | |
523 | err_unregister_postdiv: | |
524 | clk_unregister(postdiv_clk); | |
525 | err_unregister_pllout: | |
526 | clk_unregister(pllout_clk); | |
527 | err_free_pllout: | |
528 | kfree(pllout); | |
529 | err_unregister_prediv: | |
530 | clk_unregister(prediv_clk); | |
531 | err_unregister_oscin: | |
532 | clk_unregister(oscin_clk); | |
533 | ||
534 | return ERR_PTR(ret); | |
2d172691 DL |
535 | } |
536 | ||
537 | /** | |
538 | * davinci_pll_auxclk_register - Register bypass clock (AUXCLK) | |
76c9dd9d | 539 | * @dev: The PLL platform device or NULL |
2d172691 DL |
540 | * @name: The clock name |
541 | * @base: The PLL memory region | |
542 | */ | |
543 | struct clk *davinci_pll_auxclk_register(struct device *dev, | |
544 | const char *name, | |
545 | void __iomem *base) | |
546 | { | |
547 | return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN, | |
548 | CKEN_AUXEN_SHIFT, 0, NULL); | |
549 | } | |
550 | ||
551 | /** | |
552 | * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP) | |
76c9dd9d | 553 | * @dev: The PLL platform device or NULL |
2d172691 DL |
554 | * @name: The clock name |
555 | * @base: The PLL memory region | |
556 | */ | |
557 | struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, | |
558 | const char *name, | |
559 | void __iomem *base) | |
560 | { | |
561 | return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV, | |
562 | DIV_RATIO_SHIFT, DIV_RATIO_WIDTH, | |
563 | CLK_DIVIDER_READ_ONLY, NULL); | |
564 | } | |
565 | ||
566 | /** | |
567 | * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK) | |
76c9dd9d | 568 | * @dev: The PLL platform device or NULL |
2d172691 DL |
569 | * @info: The clock info |
570 | * @base: The PLL memory region | |
571 | */ | |
572 | struct clk * | |
573 | davinci_pll_obsclk_register(struct device *dev, | |
574 | const struct davinci_pll_obsclk_info *info, | |
575 | void __iomem *base) | |
576 | { | |
577 | struct clk_mux *mux; | |
578 | struct clk_gate *gate; | |
579 | struct clk_divider *divider; | |
76c9dd9d | 580 | struct clk *clk; |
2d172691 | 581 | u32 oscdiv; |
76c9dd9d | 582 | int ret; |
2d172691 | 583 | |
76c9dd9d | 584 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
2d172691 DL |
585 | if (!mux) |
586 | return ERR_PTR(-ENOMEM); | |
587 | ||
588 | mux->reg = base + OCSEL; | |
589 | mux->table = info->table; | |
590 | mux->mask = info->ocsrc_mask; | |
591 | ||
76c9dd9d DL |
592 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
593 | if (!gate) { | |
594 | ret = -ENOMEM; | |
595 | goto err_free_mux; | |
596 | } | |
2d172691 DL |
597 | |
598 | gate->reg = base + CKEN; | |
599 | gate->bit_idx = CKEN_OBSCLK_SHIFT; | |
600 | ||
76c9dd9d DL |
601 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
602 | if (!divider) { | |
603 | ret = -ENOMEM; | |
604 | goto err_free_gate; | |
605 | } | |
2d172691 DL |
606 | |
607 | divider->reg = base + OSCDIV; | |
608 | divider->shift = DIV_RATIO_SHIFT; | |
609 | divider->width = DIV_RATIO_WIDTH; | |
610 | ||
611 | /* make sure divider is enabled just in case bootloader disabled it */ | |
612 | oscdiv = readl(base + OSCDIV); | |
613 | oscdiv |= BIT(DIV_ENABLE_SHIFT); | |
614 | writel(oscdiv, base + OSCDIV); | |
615 | ||
76c9dd9d DL |
616 | clk = clk_register_composite(dev, info->name, info->parent_names, |
617 | info->num_parents, | |
618 | &mux->hw, &clk_mux_ops, | |
619 | ÷r->hw, &clk_divider_ops, | |
620 | &gate->hw, &clk_gate_ops, 0); | |
621 | ||
622 | if (IS_ERR(clk)) { | |
623 | ret = PTR_ERR(clk); | |
624 | goto err_free_divider; | |
625 | } | |
626 | ||
627 | return clk; | |
628 | ||
629 | err_free_divider: | |
630 | kfree(divider); | |
631 | err_free_gate: | |
632 | kfree(gate); | |
633 | err_free_mux: | |
634 | kfree(mux); | |
635 | ||
636 | return ERR_PTR(ret); | |
2d172691 DL |
637 | } |
638 | ||
639 | /* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */ | |
640 | static int davinci_pll_sysclk_rate_change(struct notifier_block *nb, | |
641 | unsigned long flags, void *data) | |
642 | { | |
643 | struct clk_notifier_data *cnd = data; | |
644 | struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk)); | |
645 | struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); | |
646 | u32 pllcmd, pllstat; | |
647 | ||
648 | switch (flags) { | |
649 | case POST_RATE_CHANGE: | |
650 | /* apply the changes */ | |
651 | pllcmd = readl(pll->base + PLLCMD); | |
652 | pllcmd |= PLLCMD_GOSET; | |
653 | writel(pllcmd, pll->base + PLLCMD); | |
7a346a37 | 654 | fallthrough; |
2d172691 DL |
655 | case PRE_RATE_CHANGE: |
656 | /* Wait until for outstanding changes to take effect */ | |
657 | do { | |
658 | pllstat = readl(pll->base + PLLSTAT); | |
659 | } while (pllstat & PLLSTAT_GOSTAT); | |
660 | break; | |
661 | } | |
662 | ||
663 | return NOTIFY_OK; | |
664 | } | |
665 | ||
666 | static struct notifier_block davinci_pll_sysclk_notifier = { | |
667 | .notifier_call = davinci_pll_sysclk_rate_change, | |
668 | }; | |
669 | ||
670 | /** | |
671 | * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn) | |
76c9dd9d | 672 | * @dev: The PLL platform device or NULL |
2d172691 DL |
673 | * @info: The clock info |
674 | * @base: The PLL memory region | |
675 | */ | |
676 | struct clk * | |
677 | davinci_pll_sysclk_register(struct device *dev, | |
678 | const struct davinci_pll_sysclk_info *info, | |
679 | void __iomem *base) | |
680 | { | |
681 | const struct clk_ops *divider_ops = &clk_divider_ops; | |
682 | struct clk_gate *gate; | |
683 | struct clk_divider *divider; | |
684 | struct clk *clk; | |
685 | u32 reg; | |
686 | u32 flags = 0; | |
76c9dd9d | 687 | int ret; |
2d172691 DL |
688 | |
689 | /* PLLDIVn registers are not entirely consecutive */ | |
690 | if (info->id < 4) | |
691 | reg = PLLDIV1 + 4 * (info->id - 1); | |
692 | else | |
693 | reg = PLLDIV4 + 4 * (info->id - 4); | |
694 | ||
76c9dd9d | 695 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
2d172691 DL |
696 | if (!gate) |
697 | return ERR_PTR(-ENOMEM); | |
698 | ||
699 | gate->reg = base + reg; | |
700 | gate->bit_idx = DIV_ENABLE_SHIFT; | |
701 | ||
76c9dd9d DL |
702 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
703 | if (!divider) { | |
704 | ret = -ENOMEM; | |
705 | goto err_free_gate; | |
706 | } | |
2d172691 DL |
707 | |
708 | divider->reg = base + reg; | |
709 | divider->shift = DIV_RATIO_SHIFT; | |
710 | divider->width = info->ratio_width; | |
711 | divider->flags = 0; | |
712 | ||
713 | if (info->flags & SYSCLK_FIXED_DIV) { | |
714 | divider->flags |= CLK_DIVIDER_READ_ONLY; | |
715 | divider_ops = &clk_divider_ro_ops; | |
716 | } | |
717 | ||
718 | /* Only the ARM clock can change the parent PLL rate */ | |
719 | if (info->flags & SYSCLK_ARM_RATE) | |
720 | flags |= CLK_SET_RATE_PARENT; | |
721 | ||
722 | if (info->flags & SYSCLK_ALWAYS_ENABLED) | |
723 | flags |= CLK_IS_CRITICAL; | |
724 | ||
725 | clk = clk_register_composite(dev, info->name, &info->parent_name, 1, | |
726 | NULL, NULL, ÷r->hw, divider_ops, | |
727 | &gate->hw, &clk_gate_ops, flags); | |
76c9dd9d DL |
728 | if (IS_ERR(clk)) { |
729 | ret = PTR_ERR(clk); | |
730 | goto err_free_divider; | |
731 | } | |
2d172691 DL |
732 | |
733 | clk_notifier_register(clk, &davinci_pll_sysclk_notifier); | |
734 | ||
735 | return clk; | |
76c9dd9d DL |
736 | |
737 | err_free_divider: | |
738 | kfree(divider); | |
739 | err_free_gate: | |
740 | kfree(gate); | |
741 | ||
742 | return ERR_PTR(ret); | |
2d172691 DL |
743 | } |
744 | ||
76c9dd9d | 745 | int of_davinci_pll_init(struct device *dev, struct device_node *node, |
2d172691 DL |
746 | const struct davinci_pll_clk_info *info, |
747 | const struct davinci_pll_obsclk_info *obsclk_info, | |
748 | const struct davinci_pll_sysclk_info **div_info, | |
749 | u8 max_sysclk_id, | |
76c9dd9d DL |
750 | void __iomem *base, |
751 | struct regmap *cfgchip) | |
2d172691 | 752 | { |
2d172691 DL |
753 | struct device_node *child; |
754 | const char *parent_name; | |
755 | struct clk *clk; | |
756 | ||
757 | if (info->flags & PLL_HAS_CLKMODE) | |
758 | parent_name = of_clk_get_parent_name(node, 0); | |
759 | else | |
760 | parent_name = OSCIN_CLK_NAME; | |
761 | ||
76c9dd9d | 762 | clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip); |
2d172691 DL |
763 | if (IS_ERR(clk)) { |
764 | dev_err(dev, "failed to register %s\n", info->name); | |
765 | return PTR_ERR(clk); | |
766 | } | |
767 | ||
768 | child = of_get_child_by_name(node, "pllout"); | |
769 | if (of_device_is_available(child)) | |
770 | of_clk_add_provider(child, of_clk_src_simple_get, clk); | |
771 | of_node_put(child); | |
772 | ||
773 | child = of_get_child_by_name(node, "sysclk"); | |
774 | if (of_device_is_available(child)) { | |
775 | struct clk_onecell_data *clk_data; | |
776 | struct clk **clks; | |
777 | int n_clks = max_sysclk_id + 1; | |
778 | int i; | |
779 | ||
76c9dd9d | 780 | clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); |
d55841ce ND |
781 | if (!clk_data) { |
782 | of_node_put(child); | |
2d172691 | 783 | return -ENOMEM; |
d55841ce | 784 | } |
2d172691 | 785 | |
76c9dd9d DL |
786 | clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL); |
787 | if (!clks) { | |
788 | kfree(clk_data); | |
d55841ce | 789 | of_node_put(child); |
2d172691 | 790 | return -ENOMEM; |
76c9dd9d | 791 | } |
2d172691 DL |
792 | |
793 | clk_data->clks = clks; | |
794 | clk_data->clk_num = n_clks; | |
795 | ||
796 | for (i = 0; i < n_clks; i++) | |
797 | clks[i] = ERR_PTR(-ENOENT); | |
798 | ||
799 | for (; *div_info; div_info++) { | |
800 | clk = davinci_pll_sysclk_register(dev, *div_info, base); | |
801 | if (IS_ERR(clk)) | |
802 | dev_warn(dev, "failed to register %s (%ld)\n", | |
803 | (*div_info)->name, PTR_ERR(clk)); | |
804 | else | |
805 | clks[(*div_info)->id] = clk; | |
806 | } | |
807 | of_clk_add_provider(child, of_clk_src_onecell_get, clk_data); | |
808 | } | |
809 | of_node_put(child); | |
810 | ||
811 | child = of_get_child_by_name(node, "auxclk"); | |
812 | if (of_device_is_available(child)) { | |
813 | char child_name[MAX_NAME_SIZE]; | |
814 | ||
815 | snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name); | |
816 | ||
817 | clk = davinci_pll_auxclk_register(dev, child_name, base); | |
818 | if (IS_ERR(clk)) | |
819 | dev_warn(dev, "failed to register %s (%ld)\n", | |
820 | child_name, PTR_ERR(clk)); | |
821 | else | |
822 | of_clk_add_provider(child, of_clk_src_simple_get, clk); | |
823 | } | |
824 | of_node_put(child); | |
825 | ||
826 | child = of_get_child_by_name(node, "obsclk"); | |
827 | if (of_device_is_available(child)) { | |
828 | if (obsclk_info) | |
829 | clk = davinci_pll_obsclk_register(dev, obsclk_info, base); | |
830 | else | |
831 | clk = ERR_PTR(-EINVAL); | |
832 | ||
833 | if (IS_ERR(clk)) | |
834 | dev_warn(dev, "failed to register obsclk (%ld)\n", | |
835 | PTR_ERR(clk)); | |
836 | else | |
837 | of_clk_add_provider(child, of_clk_src_simple_get, clk); | |
838 | } | |
839 | of_node_put(child); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
76c9dd9d DL |
844 | static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev) |
845 | { | |
846 | struct davinci_pll_platform_data *pdata = dev_get_platdata(dev); | |
847 | ||
848 | /* | |
849 | * Platform data is optional, so allocate a new struct if one was not | |
850 | * provided. For device tree, this will always be the case. | |
851 | */ | |
852 | if (!pdata) | |
853 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
854 | if (!pdata) | |
855 | return NULL; | |
856 | ||
857 | /* for device tree, we need to fill in the struct */ | |
858 | if (dev->of_node) | |
859 | pdata->cfgchip = | |
860 | syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); | |
861 | ||
862 | return pdata; | |
863 | } | |
864 | ||
17d8bacf | 865 | /* needed in early boot for clocksource/clockevent */ |
4eff0beb | 866 | #ifdef CONFIG_ARCH_DAVINCI_DA850 |
17d8bacf | 867 | CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); |
4eff0beb | 868 | #endif |
17d8bacf | 869 | |
2d172691 | 870 | static const struct of_device_id davinci_pll_of_match[] = { |
4eff0beb | 871 | #ifdef CONFIG_ARCH_DAVINCI_DA850 |
55b3caed | 872 | { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, |
4eff0beb | 873 | #endif |
2d172691 DL |
874 | { } |
875 | }; | |
876 | ||
877 | static const struct platform_device_id davinci_pll_id_table[] = { | |
4eff0beb | 878 | #ifdef CONFIG_ARCH_DAVINCI_DA830 |
c92765fd | 879 | { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init }, |
4eff0beb DL |
880 | #endif |
881 | #ifdef CONFIG_ARCH_DAVINCI_DA850 | |
55b3caed DL |
882 | { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init }, |
883 | { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init }, | |
4eff0beb DL |
884 | #endif |
885 | #ifdef CONFIG_ARCH_DAVINCI_DM355 | |
dcdd19b2 DL |
886 | { .name = "dm355-pll1", .driver_data = (kernel_ulong_t)dm355_pll1_init }, |
887 | { .name = "dm355-pll2", .driver_data = (kernel_ulong_t)dm355_pll2_init }, | |
4eff0beb DL |
888 | #endif |
889 | #ifdef CONFIG_ARCH_DAVINCI_DM365 | |
650bba61 DL |
890 | { .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init }, |
891 | { .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init }, | |
4eff0beb DL |
892 | #endif |
893 | #ifdef CONFIG_ARCH_DAVINCI_DM644x | |
d67c13ea DL |
894 | { .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init }, |
895 | { .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init }, | |
4eff0beb DL |
896 | #endif |
897 | #ifdef CONFIG_ARCH_DAVINCI_DM646x | |
6ef35851 DL |
898 | { .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init }, |
899 | { .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init }, | |
4eff0beb | 900 | #endif |
2d172691 DL |
901 | { } |
902 | }; | |
903 | ||
76c9dd9d DL |
904 | typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base, |
905 | struct regmap *cfgchip); | |
2d172691 DL |
906 | |
907 | static int davinci_pll_probe(struct platform_device *pdev) | |
908 | { | |
909 | struct device *dev = &pdev->dev; | |
76c9dd9d | 910 | struct davinci_pll_platform_data *pdata; |
2d172691 DL |
911 | const struct of_device_id *of_id; |
912 | davinci_pll_init pll_init = NULL; | |
2d172691 DL |
913 | void __iomem *base; |
914 | ||
915 | of_id = of_match_device(davinci_pll_of_match, dev); | |
916 | if (of_id) | |
917 | pll_init = of_id->data; | |
918 | else if (pdev->id_entry) | |
919 | pll_init = (void *)pdev->id_entry->driver_data; | |
920 | ||
921 | if (!pll_init) { | |
922 | dev_err(dev, "unable to find driver data\n"); | |
923 | return -EINVAL; | |
924 | } | |
925 | ||
76c9dd9d DL |
926 | pdata = davinci_pll_get_pdata(dev); |
927 | if (!pdata) { | |
928 | dev_err(dev, "missing platform data\n"); | |
929 | return -EINVAL; | |
930 | } | |
931 | ||
1f8f3c6b | 932 | base = devm_platform_ioremap_resource(pdev, 0); |
fc3fcb4f | 933 | if (IS_ERR(base)) |
2d172691 | 934 | return PTR_ERR(base); |
2d172691 | 935 | |
76c9dd9d | 936 | return pll_init(dev, base, pdata->cfgchip); |
2d172691 DL |
937 | } |
938 | ||
939 | static struct platform_driver davinci_pll_driver = { | |
940 | .probe = davinci_pll_probe, | |
941 | .driver = { | |
942 | .name = "davinci-pll-clk", | |
943 | .of_match_table = davinci_pll_of_match, | |
944 | }, | |
945 | .id_table = davinci_pll_id_table, | |
946 | }; | |
947 | ||
948 | static int __init davinci_pll_driver_init(void) | |
949 | { | |
950 | return platform_driver_register(&davinci_pll_driver); | |
951 | } | |
952 | ||
953 | /* has to be postcore_initcall because PSC devices depend on PLL parent clocks */ | |
954 | postcore_initcall(davinci_pll_driver_init); | |
955 | ||
956 | #ifdef CONFIG_DEBUG_FS | |
957 | #include <linux/debugfs.h> | |
958 | ||
959 | #define DEBUG_REG(n) \ | |
960 | { \ | |
961 | .name = #n, \ | |
962 | .offset = n, \ | |
963 | } | |
964 | ||
965 | static const struct debugfs_reg32 davinci_pll_regs[] = { | |
966 | DEBUG_REG(REVID), | |
967 | DEBUG_REG(PLLCTL), | |
968 | DEBUG_REG(OCSEL), | |
969 | DEBUG_REG(PLLSECCTL), | |
970 | DEBUG_REG(PLLM), | |
971 | DEBUG_REG(PREDIV), | |
972 | DEBUG_REG(PLLDIV1), | |
973 | DEBUG_REG(PLLDIV2), | |
974 | DEBUG_REG(PLLDIV3), | |
975 | DEBUG_REG(OSCDIV), | |
976 | DEBUG_REG(POSTDIV), | |
977 | DEBUG_REG(BPDIV), | |
978 | DEBUG_REG(PLLCMD), | |
979 | DEBUG_REG(PLLSTAT), | |
980 | DEBUG_REG(ALNCTL), | |
981 | DEBUG_REG(DCHANGE), | |
982 | DEBUG_REG(CKEN), | |
983 | DEBUG_REG(CKSTAT), | |
984 | DEBUG_REG(SYSTAT), | |
985 | DEBUG_REG(PLLDIV4), | |
986 | DEBUG_REG(PLLDIV5), | |
987 | DEBUG_REG(PLLDIV6), | |
988 | DEBUG_REG(PLLDIV7), | |
989 | DEBUG_REG(PLLDIV8), | |
990 | DEBUG_REG(PLLDIV9), | |
991 | }; | |
992 | ||
d75d50c0 | 993 | static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) |
2d172691 DL |
994 | { |
995 | struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); | |
996 | struct debugfs_regset32 *regset; | |
2d172691 DL |
997 | |
998 | regset = kzalloc(sizeof(*regset), GFP_KERNEL); | |
999 | if (!regset) | |
d75d50c0 | 1000 | return; |
2d172691 DL |
1001 | |
1002 | regset->regs = davinci_pll_regs; | |
1003 | regset->nregs = ARRAY_SIZE(davinci_pll_regs); | |
1004 | regset->base = pll->base; | |
1005 | ||
bcee7673 | 1006 | debugfs_create_regset32("registers", 0400, dentry, regset); |
2d172691 DL |
1007 | } |
1008 | #endif |