Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
[linux-2.6-block.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
533ddeb1 24#include <linux/sched.h>
562ef0b0 25#include <linux/clkdev.h>
b2476490 26
d6782c26
SN
27#include "clk.h"
28
b2476490
MT
29static DEFINE_SPINLOCK(enable_lock);
30static DEFINE_MUTEX(prepare_lock);
31
533ddeb1
MT
32static struct task_struct *prepare_owner;
33static struct task_struct *enable_owner;
34
35static int prepare_refcnt;
36static int enable_refcnt;
37
b2476490
MT
38static HLIST_HEAD(clk_root_list);
39static HLIST_HEAD(clk_orphan_list);
40static LIST_HEAD(clk_notifier_list);
41
b09d6d99
MT
42/*** private data structures ***/
43
44struct clk_core {
45 const char *name;
46 const struct clk_ops *ops;
47 struct clk_hw *hw;
48 struct module *owner;
49 struct clk_core *parent;
50 const char **parent_names;
51 struct clk_core **parents;
52 u8 num_parents;
53 u8 new_parent_index;
54 unsigned long rate;
1c8e6004 55 unsigned long req_rate;
b09d6d99
MT
56 unsigned long new_rate;
57 struct clk_core *new_parent;
58 struct clk_core *new_child;
59 unsigned long flags;
e6500344 60 bool orphan;
b09d6d99
MT
61 unsigned int enable_count;
62 unsigned int prepare_count;
9783c0d9
SB
63 unsigned long min_rate;
64 unsigned long max_rate;
b09d6d99
MT
65 unsigned long accuracy;
66 int phase;
67 struct hlist_head children;
68 struct hlist_node child_node;
1c8e6004 69 struct hlist_head clks;
b09d6d99
MT
70 unsigned int notifier_count;
71#ifdef CONFIG_DEBUG_FS
72 struct dentry *dentry;
8c9a8a8f 73 struct hlist_node debug_node;
b09d6d99
MT
74#endif
75 struct kref ref;
76};
77
dfc202ea
SB
78#define CREATE_TRACE_POINTS
79#include <trace/events/clk.h>
80
b09d6d99
MT
81struct clk {
82 struct clk_core *core;
83 const char *dev_id;
84 const char *con_id;
1c8e6004
TV
85 unsigned long min_rate;
86 unsigned long max_rate;
50595f8b 87 struct hlist_node clks_node;
b09d6d99
MT
88};
89
eab89f69
MT
90/*** locking ***/
91static void clk_prepare_lock(void)
92{
533ddeb1
MT
93 if (!mutex_trylock(&prepare_lock)) {
94 if (prepare_owner == current) {
95 prepare_refcnt++;
96 return;
97 }
98 mutex_lock(&prepare_lock);
99 }
100 WARN_ON_ONCE(prepare_owner != NULL);
101 WARN_ON_ONCE(prepare_refcnt != 0);
102 prepare_owner = current;
103 prepare_refcnt = 1;
eab89f69
MT
104}
105
106static void clk_prepare_unlock(void)
107{
533ddeb1
MT
108 WARN_ON_ONCE(prepare_owner != current);
109 WARN_ON_ONCE(prepare_refcnt == 0);
110
111 if (--prepare_refcnt)
112 return;
113 prepare_owner = NULL;
eab89f69
MT
114 mutex_unlock(&prepare_lock);
115}
116
117static unsigned long clk_enable_lock(void)
a57aa185 118 __acquires(enable_lock)
eab89f69
MT
119{
120 unsigned long flags;
533ddeb1
MT
121
122 if (!spin_trylock_irqsave(&enable_lock, flags)) {
123 if (enable_owner == current) {
124 enable_refcnt++;
a57aa185 125 __acquire(enable_lock);
533ddeb1
MT
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
a57aa185 138 __releases(enable_lock)
eab89f69 139{
533ddeb1
MT
140 WARN_ON_ONCE(enable_owner != current);
141 WARN_ON_ONCE(enable_refcnt == 0);
142
a57aa185
SB
143 if (--enable_refcnt) {
144 __release(enable_lock);
533ddeb1 145 return;
a57aa185 146 }
533ddeb1 147 enable_owner = NULL;
eab89f69
MT
148 spin_unlock_irqrestore(&enable_lock, flags);
149}
150
4dff95dc
SB
151static bool clk_core_is_prepared(struct clk_core *core)
152{
153 /*
154 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing
156 */
157 if (!core->ops->is_prepared)
158 return core->prepare_count;
b2476490 159
4dff95dc
SB
160 return core->ops->is_prepared(core->hw);
161}
b2476490 162
4dff95dc
SB
163static bool clk_core_is_enabled(struct clk_core *core)
164{
165 /*
166 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing
168 */
169 if (!core->ops->is_enabled)
170 return core->enable_count;
6b44c854 171
4dff95dc
SB
172 return core->ops->is_enabled(core->hw);
173}
6b44c854 174
4dff95dc 175static void clk_unprepare_unused_subtree(struct clk_core *core)
1af599df 176{
4dff95dc
SB
177 struct clk_core *child;
178
179 lockdep_assert_held(&prepare_lock);
180
181 hlist_for_each_entry(child, &core->children, child_node)
182 clk_unprepare_unused_subtree(child);
183
184 if (core->prepare_count)
1af599df
PG
185 return;
186
4dff95dc
SB
187 if (core->flags & CLK_IGNORE_UNUSED)
188 return;
189
190 if (clk_core_is_prepared(core)) {
191 trace_clk_unprepare(core);
192 if (core->ops->unprepare_unused)
193 core->ops->unprepare_unused(core->hw);
194 else if (core->ops->unprepare)
195 core->ops->unprepare(core->hw);
196 trace_clk_unprepare_complete(core);
197 }
1af599df
PG
198}
199
4dff95dc 200static void clk_disable_unused_subtree(struct clk_core *core)
1af599df 201{
035a61c3 202 struct clk_core *child;
4dff95dc 203 unsigned long flags;
1af599df 204
4dff95dc 205 lockdep_assert_held(&prepare_lock);
1af599df 206
4dff95dc
SB
207 hlist_for_each_entry(child, &core->children, child_node)
208 clk_disable_unused_subtree(child);
1af599df 209
4dff95dc
SB
210 flags = clk_enable_lock();
211
212 if (core->enable_count)
213 goto unlock_out;
214
215 if (core->flags & CLK_IGNORE_UNUSED)
216 goto unlock_out;
217
218 /*
219 * some gate clocks have special needs during the disable-unused
220 * sequence. call .disable_unused if available, otherwise fall
221 * back to .disable
222 */
223 if (clk_core_is_enabled(core)) {
224 trace_clk_disable(core);
225 if (core->ops->disable_unused)
226 core->ops->disable_unused(core->hw);
227 else if (core->ops->disable)
228 core->ops->disable(core->hw);
229 trace_clk_disable_complete(core);
230 }
231
232unlock_out:
233 clk_enable_unlock(flags);
1af599df
PG
234}
235
4dff95dc
SB
236static bool clk_ignore_unused;
237static int __init clk_ignore_unused_setup(char *__unused)
1af599df 238{
4dff95dc
SB
239 clk_ignore_unused = true;
240 return 1;
241}
242__setup("clk_ignore_unused", clk_ignore_unused_setup);
1af599df 243
4dff95dc
SB
244static int clk_disable_unused(void)
245{
246 struct clk_core *core;
247
248 if (clk_ignore_unused) {
249 pr_warn("clk: Not disabling unused clocks\n");
250 return 0;
251 }
1af599df 252
eab89f69 253 clk_prepare_lock();
1af599df 254
4dff95dc
SB
255 hlist_for_each_entry(core, &clk_root_list, child_node)
256 clk_disable_unused_subtree(core);
257
258 hlist_for_each_entry(core, &clk_orphan_list, child_node)
259 clk_disable_unused_subtree(core);
260
261 hlist_for_each_entry(core, &clk_root_list, child_node)
262 clk_unprepare_unused_subtree(core);
263
264 hlist_for_each_entry(core, &clk_orphan_list, child_node)
265 clk_unprepare_unused_subtree(core);
1af599df 266
eab89f69 267 clk_prepare_unlock();
1af599df
PG
268
269 return 0;
270}
4dff95dc 271late_initcall_sync(clk_disable_unused);
1af599df 272
4dff95dc 273/*** helper functions ***/
1af599df 274
b76281cb 275const char *__clk_get_name(const struct clk *clk)
1af599df 276{
4dff95dc 277 return !clk ? NULL : clk->core->name;
1af599df 278}
4dff95dc 279EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 280
e7df6f6e 281const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
282{
283 return hw->core->name;
284}
285EXPORT_SYMBOL_GPL(clk_hw_get_name);
286
4dff95dc
SB
287struct clk_hw *__clk_get_hw(struct clk *clk)
288{
289 return !clk ? NULL : clk->core->hw;
290}
291EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 292
e7df6f6e 293unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
294{
295 return hw->core->num_parents;
296}
297EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
298
e7df6f6e 299struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
300{
301 return hw->core->parent ? hw->core->parent->hw : NULL;
302}
303EXPORT_SYMBOL_GPL(clk_hw_get_parent);
304
4dff95dc
SB
305static struct clk_core *__clk_lookup_subtree(const char *name,
306 struct clk_core *core)
bddca894 307{
035a61c3 308 struct clk_core *child;
4dff95dc 309 struct clk_core *ret;
bddca894 310
4dff95dc
SB
311 if (!strcmp(core->name, name))
312 return core;
bddca894 313
4dff95dc
SB
314 hlist_for_each_entry(child, &core->children, child_node) {
315 ret = __clk_lookup_subtree(name, child);
316 if (ret)
317 return ret;
bddca894
PG
318 }
319
4dff95dc 320 return NULL;
bddca894
PG
321}
322
4dff95dc 323static struct clk_core *clk_core_lookup(const char *name)
bddca894 324{
4dff95dc
SB
325 struct clk_core *root_clk;
326 struct clk_core *ret;
bddca894 327
4dff95dc
SB
328 if (!name)
329 return NULL;
bddca894 330
4dff95dc
SB
331 /* search the 'proper' clk tree first */
332 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
333 ret = __clk_lookup_subtree(name, root_clk);
334 if (ret)
335 return ret;
bddca894
PG
336 }
337
4dff95dc
SB
338 /* if not found, then search the orphan tree */
339 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
340 ret = __clk_lookup_subtree(name, root_clk);
341 if (ret)
342 return ret;
343 }
bddca894 344
4dff95dc 345 return NULL;
bddca894
PG
346}
347
4dff95dc
SB
348static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
349 u8 index)
bddca894 350{
4dff95dc
SB
351 if (!core || index >= core->num_parents)
352 return NULL;
88cfbef2
MY
353
354 if (!core->parents[index])
355 core->parents[index] =
356 clk_core_lookup(core->parent_names[index]);
357
358 return core->parents[index];
bddca894
PG
359}
360
e7df6f6e
SB
361struct clk_hw *
362clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
363{
364 struct clk_core *parent;
365
366 parent = clk_core_get_parent_by_index(hw->core, index);
367
368 return !parent ? NULL : parent->hw;
369}
370EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
371
4dff95dc
SB
372unsigned int __clk_get_enable_count(struct clk *clk)
373{
374 return !clk ? 0 : clk->core->enable_count;
375}
b2476490 376
4dff95dc
SB
377static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
378{
379 unsigned long ret;
b2476490 380
4dff95dc
SB
381 if (!core) {
382 ret = 0;
383 goto out;
384 }
b2476490 385
4dff95dc 386 ret = core->rate;
b2476490 387
47b0eeb3 388 if (!core->num_parents)
4dff95dc 389 goto out;
c646cbf1 390
4dff95dc
SB
391 if (!core->parent)
392 ret = 0;
b2476490 393
b2476490
MT
394out:
395 return ret;
396}
397
e7df6f6e 398unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
399{
400 return clk_core_get_rate_nolock(hw->core);
401}
402EXPORT_SYMBOL_GPL(clk_hw_get_rate);
403
4dff95dc
SB
404static unsigned long __clk_get_accuracy(struct clk_core *core)
405{
406 if (!core)
407 return 0;
b2476490 408
4dff95dc 409 return core->accuracy;
b2476490
MT
410}
411
4dff95dc 412unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 413{
4dff95dc 414 return !clk ? 0 : clk->core->flags;
fcb0ee6a 415}
4dff95dc 416EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 417
e7df6f6e 418unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
419{
420 return hw->core->flags;
421}
422EXPORT_SYMBOL_GPL(clk_hw_get_flags);
423
e7df6f6e 424bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
425{
426 return clk_core_is_prepared(hw->core);
427}
428
be68bf88
JE
429bool clk_hw_is_enabled(const struct clk_hw *hw)
430{
431 return clk_core_is_enabled(hw->core);
432}
433
4dff95dc 434bool __clk_is_enabled(struct clk *clk)
b2476490 435{
4dff95dc
SB
436 if (!clk)
437 return false;
b2476490 438
4dff95dc
SB
439 return clk_core_is_enabled(clk->core);
440}
441EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 442
4dff95dc
SB
443static bool mux_is_better_rate(unsigned long rate, unsigned long now,
444 unsigned long best, unsigned long flags)
445{
446 if (flags & CLK_MUX_ROUND_CLOSEST)
447 return abs(now - rate) < abs(best - rate);
1af599df 448
4dff95dc
SB
449 return now <= rate && now > best;
450}
bddca894 451
0817b62c
BB
452static int
453clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
454 unsigned long flags)
455{
456 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
457 int i, num_parents, ret;
458 unsigned long best = 0;
459 struct clk_rate_request parent_req = *req;
b2476490 460
4dff95dc
SB
461 /* if NO_REPARENT flag set, pass through to current parent */
462 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
463 parent = core->parent;
0817b62c
BB
464 if (core->flags & CLK_SET_RATE_PARENT) {
465 ret = __clk_determine_rate(parent ? parent->hw : NULL,
466 &parent_req);
467 if (ret)
468 return ret;
469
470 best = parent_req.rate;
471 } else if (parent) {
4dff95dc 472 best = clk_core_get_rate_nolock(parent);
0817b62c 473 } else {
4dff95dc 474 best = clk_core_get_rate_nolock(core);
0817b62c
BB
475 }
476
4dff95dc
SB
477 goto out;
478 }
b2476490 479
4dff95dc
SB
480 /* find the parent that can provide the fastest rate <= rate */
481 num_parents = core->num_parents;
482 for (i = 0; i < num_parents; i++) {
483 parent = clk_core_get_parent_by_index(core, i);
484 if (!parent)
485 continue;
0817b62c
BB
486
487 if (core->flags & CLK_SET_RATE_PARENT) {
488 parent_req = *req;
489 ret = __clk_determine_rate(parent->hw, &parent_req);
490 if (ret)
491 continue;
492 } else {
493 parent_req.rate = clk_core_get_rate_nolock(parent);
494 }
495
496 if (mux_is_better_rate(req->rate, parent_req.rate,
497 best, flags)) {
4dff95dc 498 best_parent = parent;
0817b62c 499 best = parent_req.rate;
4dff95dc
SB
500 }
501 }
b2476490 502
57d866e6
BB
503 if (!best_parent)
504 return -EINVAL;
505
4dff95dc
SB
506out:
507 if (best_parent)
0817b62c
BB
508 req->best_parent_hw = best_parent->hw;
509 req->best_parent_rate = best;
510 req->rate = best;
b2476490 511
0817b62c 512 return 0;
b33d212f 513}
4dff95dc
SB
514
515struct clk *__clk_lookup(const char *name)
fcb0ee6a 516{
4dff95dc
SB
517 struct clk_core *core = clk_core_lookup(name);
518
519 return !core ? NULL : core->hw->clk;
fcb0ee6a 520}
b2476490 521
4dff95dc
SB
522static void clk_core_get_boundaries(struct clk_core *core,
523 unsigned long *min_rate,
524 unsigned long *max_rate)
1c155b3d 525{
4dff95dc 526 struct clk *clk_user;
1c155b3d 527
9783c0d9
SB
528 *min_rate = core->min_rate;
529 *max_rate = core->max_rate;
496eadf8 530
4dff95dc
SB
531 hlist_for_each_entry(clk_user, &core->clks, clks_node)
532 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 533
4dff95dc
SB
534 hlist_for_each_entry(clk_user, &core->clks, clks_node)
535 *max_rate = min(*max_rate, clk_user->max_rate);
536}
1c155b3d 537
9783c0d9
SB
538void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
539 unsigned long max_rate)
540{
541 hw->core->min_rate = min_rate;
542 hw->core->max_rate = max_rate;
543}
544EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
545
4dff95dc
SB
546/*
547 * Helper for finding best parent to provide a given frequency. This can be used
548 * directly as a determine_rate callback (e.g. for a mux), or from a more
549 * complex clock that may combine a mux with other operations.
550 */
0817b62c
BB
551int __clk_mux_determine_rate(struct clk_hw *hw,
552 struct clk_rate_request *req)
4dff95dc 553{
0817b62c 554 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 555}
4dff95dc 556EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 557
0817b62c
BB
558int __clk_mux_determine_rate_closest(struct clk_hw *hw,
559 struct clk_rate_request *req)
b2476490 560{
0817b62c 561 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
562}
563EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 564
4dff95dc 565/*** clk api ***/
496eadf8 566
4dff95dc
SB
567static void clk_core_unprepare(struct clk_core *core)
568{
a6334725
SB
569 lockdep_assert_held(&prepare_lock);
570
4dff95dc
SB
571 if (!core)
572 return;
b2476490 573
4dff95dc
SB
574 if (WARN_ON(core->prepare_count == 0))
575 return;
b2476490 576
2e20fbf5
LJ
577 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
578 return;
579
4dff95dc
SB
580 if (--core->prepare_count > 0)
581 return;
b2476490 582
4dff95dc 583 WARN_ON(core->enable_count > 0);
b2476490 584
4dff95dc 585 trace_clk_unprepare(core);
b2476490 586
4dff95dc
SB
587 if (core->ops->unprepare)
588 core->ops->unprepare(core->hw);
589
590 trace_clk_unprepare_complete(core);
591 clk_core_unprepare(core->parent);
b2476490
MT
592}
593
4dff95dc
SB
594/**
595 * clk_unprepare - undo preparation of a clock source
596 * @clk: the clk being unprepared
597 *
598 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
599 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
600 * if the operation may sleep. One example is a clk which is accessed over
601 * I2c. In the complex case a clk gate operation may require a fast and a slow
602 * part. It is this reason that clk_unprepare and clk_disable are not mutually
603 * exclusive. In fact clk_disable must be called before clk_unprepare.
604 */
605void clk_unprepare(struct clk *clk)
1e435256 606{
4dff95dc
SB
607 if (IS_ERR_OR_NULL(clk))
608 return;
609
610 clk_prepare_lock();
611 clk_core_unprepare(clk->core);
612 clk_prepare_unlock();
1e435256 613}
4dff95dc 614EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 615
4dff95dc 616static int clk_core_prepare(struct clk_core *core)
b2476490 617{
4dff95dc 618 int ret = 0;
b2476490 619
a6334725
SB
620 lockdep_assert_held(&prepare_lock);
621
4dff95dc 622 if (!core)
1e435256 623 return 0;
1e435256 624
4dff95dc
SB
625 if (core->prepare_count == 0) {
626 ret = clk_core_prepare(core->parent);
627 if (ret)
628 return ret;
b2476490 629
4dff95dc 630 trace_clk_prepare(core);
b2476490 631
4dff95dc
SB
632 if (core->ops->prepare)
633 ret = core->ops->prepare(core->hw);
b2476490 634
4dff95dc 635 trace_clk_prepare_complete(core);
1c155b3d 636
4dff95dc
SB
637 if (ret) {
638 clk_core_unprepare(core->parent);
639 return ret;
640 }
641 }
1c155b3d 642
4dff95dc 643 core->prepare_count++;
b2476490
MT
644
645 return 0;
646}
b2476490 647
4dff95dc
SB
648/**
649 * clk_prepare - prepare a clock source
650 * @clk: the clk being prepared
651 *
652 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
653 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
654 * operation may sleep. One example is a clk which is accessed over I2c. In
655 * the complex case a clk ungate operation may require a fast and a slow part.
656 * It is this reason that clk_prepare and clk_enable are not mutually
657 * exclusive. In fact clk_prepare must be called before clk_enable.
658 * Returns 0 on success, -EERROR otherwise.
659 */
660int clk_prepare(struct clk *clk)
b2476490 661{
4dff95dc 662 int ret;
b2476490 663
4dff95dc
SB
664 if (!clk)
665 return 0;
b2476490 666
4dff95dc
SB
667 clk_prepare_lock();
668 ret = clk_core_prepare(clk->core);
669 clk_prepare_unlock();
670
671 return ret;
b2476490 672}
4dff95dc 673EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 674
4dff95dc 675static void clk_core_disable(struct clk_core *core)
b2476490 676{
a6334725
SB
677 lockdep_assert_held(&enable_lock);
678
4dff95dc
SB
679 if (!core)
680 return;
035a61c3 681
4dff95dc
SB
682 if (WARN_ON(core->enable_count == 0))
683 return;
b2476490 684
2e20fbf5
LJ
685 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
686 return;
687
4dff95dc
SB
688 if (--core->enable_count > 0)
689 return;
035a61c3 690
2f87a6ea 691 trace_clk_disable_rcuidle(core);
035a61c3 692
4dff95dc
SB
693 if (core->ops->disable)
694 core->ops->disable(core->hw);
035a61c3 695
2f87a6ea 696 trace_clk_disable_complete_rcuidle(core);
035a61c3 697
4dff95dc 698 clk_core_disable(core->parent);
035a61c3 699}
7ef3dcc8 700
4dff95dc
SB
701/**
702 * clk_disable - gate a clock
703 * @clk: the clk being gated
704 *
705 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
706 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
707 * clk if the operation is fast and will never sleep. One example is a
708 * SoC-internal clk which is controlled via simple register writes. In the
709 * complex case a clk gate operation may require a fast and a slow part. It is
710 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
711 * In fact clk_disable must be called before clk_unprepare.
712 */
713void clk_disable(struct clk *clk)
b2476490 714{
4dff95dc
SB
715 unsigned long flags;
716
717 if (IS_ERR_OR_NULL(clk))
718 return;
719
720 flags = clk_enable_lock();
721 clk_core_disable(clk->core);
722 clk_enable_unlock(flags);
b2476490 723}
4dff95dc 724EXPORT_SYMBOL_GPL(clk_disable);
b2476490 725
4dff95dc 726static int clk_core_enable(struct clk_core *core)
b2476490 727{
4dff95dc 728 int ret = 0;
b2476490 729
a6334725
SB
730 lockdep_assert_held(&enable_lock);
731
4dff95dc
SB
732 if (!core)
733 return 0;
b2476490 734
4dff95dc
SB
735 if (WARN_ON(core->prepare_count == 0))
736 return -ESHUTDOWN;
b2476490 737
4dff95dc
SB
738 if (core->enable_count == 0) {
739 ret = clk_core_enable(core->parent);
b2476490 740
4dff95dc
SB
741 if (ret)
742 return ret;
b2476490 743
f17a0dd1 744 trace_clk_enable_rcuidle(core);
035a61c3 745
4dff95dc
SB
746 if (core->ops->enable)
747 ret = core->ops->enable(core->hw);
035a61c3 748
f17a0dd1 749 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
750
751 if (ret) {
752 clk_core_disable(core->parent);
753 return ret;
754 }
755 }
756
757 core->enable_count++;
758 return 0;
035a61c3 759}
b2476490 760
4dff95dc
SB
761/**
762 * clk_enable - ungate a clock
763 * @clk: the clk being ungated
764 *
765 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
766 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
767 * if the operation will never sleep. One example is a SoC-internal clk which
768 * is controlled via simple register writes. In the complex case a clk ungate
769 * operation may require a fast and a slow part. It is this reason that
770 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
771 * must be called before clk_enable. Returns 0 on success, -EERROR
772 * otherwise.
773 */
774int clk_enable(struct clk *clk)
5279fc40 775{
4dff95dc
SB
776 unsigned long flags;
777 int ret;
778
779 if (!clk)
5279fc40
BB
780 return 0;
781
4dff95dc
SB
782 flags = clk_enable_lock();
783 ret = clk_core_enable(clk->core);
784 clk_enable_unlock(flags);
5279fc40 785
4dff95dc 786 return ret;
b2476490 787}
4dff95dc 788EXPORT_SYMBOL_GPL(clk_enable);
b2476490 789
0817b62c
BB
790static int clk_core_round_rate_nolock(struct clk_core *core,
791 struct clk_rate_request *req)
3d6ee287 792{
4dff95dc 793 struct clk_core *parent;
0817b62c 794 long rate;
4dff95dc
SB
795
796 lockdep_assert_held(&prepare_lock);
3d6ee287 797
d6968fca 798 if (!core)
4dff95dc 799 return 0;
3d6ee287 800
4dff95dc 801 parent = core->parent;
0817b62c
BB
802 if (parent) {
803 req->best_parent_hw = parent->hw;
804 req->best_parent_rate = parent->rate;
805 } else {
806 req->best_parent_hw = NULL;
807 req->best_parent_rate = 0;
808 }
3d6ee287 809
4dff95dc 810 if (core->ops->determine_rate) {
0817b62c
BB
811 return core->ops->determine_rate(core->hw, req);
812 } else if (core->ops->round_rate) {
813 rate = core->ops->round_rate(core->hw, req->rate,
814 &req->best_parent_rate);
815 if (rate < 0)
816 return rate;
817
818 req->rate = rate;
819 } else if (core->flags & CLK_SET_RATE_PARENT) {
820 return clk_core_round_rate_nolock(parent, req);
821 } else {
822 req->rate = core->rate;
823 }
824
825 return 0;
3d6ee287
UH
826}
827
4dff95dc
SB
828/**
829 * __clk_determine_rate - get the closest rate actually supported by a clock
830 * @hw: determine the rate of this clock
2d5b520c 831 * @req: target rate request
4dff95dc 832 *
6e5ab41b 833 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 834 */
0817b62c 835int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 836{
0817b62c
BB
837 if (!hw) {
838 req->rate = 0;
4dff95dc 839 return 0;
0817b62c 840 }
035a61c3 841
0817b62c 842 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 843}
4dff95dc 844EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 845
1a9c069c
SB
846unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
847{
848 int ret;
849 struct clk_rate_request req;
850
851 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
852 req.rate = rate;
853
854 ret = clk_core_round_rate_nolock(hw->core, &req);
855 if (ret)
856 return 0;
857
858 return req.rate;
859}
860EXPORT_SYMBOL_GPL(clk_hw_round_rate);
861
4dff95dc
SB
862/**
863 * clk_round_rate - round the given rate for a clk
864 * @clk: the clk for which we are rounding a rate
865 * @rate: the rate which is to be rounded
866 *
867 * Takes in a rate as input and rounds it to a rate that the clk can actually
868 * use which is then returned. If clk doesn't support round_rate operation
869 * then the parent rate is returned.
870 */
871long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 872{
fc4a05d4
SB
873 struct clk_rate_request req;
874 int ret;
4dff95dc 875
035a61c3 876 if (!clk)
4dff95dc 877 return 0;
035a61c3 878
4dff95dc 879 clk_prepare_lock();
fc4a05d4
SB
880
881 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
882 req.rate = rate;
883
884 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
885 clk_prepare_unlock();
886
fc4a05d4
SB
887 if (ret)
888 return ret;
889
890 return req.rate;
035a61c3 891}
4dff95dc 892EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 893
4dff95dc
SB
894/**
895 * __clk_notify - call clk notifier chain
896 * @core: clk that is changing rate
897 * @msg: clk notifier type (see include/linux/clk.h)
898 * @old_rate: old clk rate
899 * @new_rate: new clk rate
900 *
901 * Triggers a notifier call chain on the clk rate-change notification
902 * for 'clk'. Passes a pointer to the struct clk and the previous
903 * and current rates to the notifier callback. Intended to be called by
904 * internal clock code only. Returns NOTIFY_DONE from the last driver
905 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
906 * a driver returns that.
907 */
908static int __clk_notify(struct clk_core *core, unsigned long msg,
909 unsigned long old_rate, unsigned long new_rate)
b2476490 910{
4dff95dc
SB
911 struct clk_notifier *cn;
912 struct clk_notifier_data cnd;
913 int ret = NOTIFY_DONE;
b2476490 914
4dff95dc
SB
915 cnd.old_rate = old_rate;
916 cnd.new_rate = new_rate;
b2476490 917
4dff95dc
SB
918 list_for_each_entry(cn, &clk_notifier_list, node) {
919 if (cn->clk->core == core) {
920 cnd.clk = cn->clk;
921 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
922 &cnd);
923 }
b2476490
MT
924 }
925
4dff95dc 926 return ret;
b2476490
MT
927}
928
4dff95dc
SB
929/**
930 * __clk_recalc_accuracies
931 * @core: first clk in the subtree
932 *
933 * Walks the subtree of clks starting with clk and recalculates accuracies as
934 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 935 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 936 * parent.
4dff95dc
SB
937 */
938static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 939{
4dff95dc
SB
940 unsigned long parent_accuracy = 0;
941 struct clk_core *child;
b2476490 942
4dff95dc 943 lockdep_assert_held(&prepare_lock);
b2476490 944
4dff95dc
SB
945 if (core->parent)
946 parent_accuracy = core->parent->accuracy;
b2476490 947
4dff95dc
SB
948 if (core->ops->recalc_accuracy)
949 core->accuracy = core->ops->recalc_accuracy(core->hw,
950 parent_accuracy);
951 else
952 core->accuracy = parent_accuracy;
b2476490 953
4dff95dc
SB
954 hlist_for_each_entry(child, &core->children, child_node)
955 __clk_recalc_accuracies(child);
b2476490
MT
956}
957
4dff95dc 958static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 959{
4dff95dc 960 unsigned long accuracy;
15a02c1f 961
4dff95dc
SB
962 clk_prepare_lock();
963 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
964 __clk_recalc_accuracies(core);
15a02c1f 965
4dff95dc
SB
966 accuracy = __clk_get_accuracy(core);
967 clk_prepare_unlock();
e366fdd7 968
4dff95dc 969 return accuracy;
e366fdd7 970}
15a02c1f 971
4dff95dc
SB
972/**
973 * clk_get_accuracy - return the accuracy of clk
974 * @clk: the clk whose accuracy is being returned
975 *
976 * Simply returns the cached accuracy of the clk, unless
977 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
978 * issued.
979 * If clk is NULL then returns 0.
980 */
981long clk_get_accuracy(struct clk *clk)
035a61c3 982{
4dff95dc
SB
983 if (!clk)
984 return 0;
035a61c3 985
4dff95dc 986 return clk_core_get_accuracy(clk->core);
035a61c3 987}
4dff95dc 988EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 989
4dff95dc
SB
990static unsigned long clk_recalc(struct clk_core *core,
991 unsigned long parent_rate)
1c8e6004 992{
4dff95dc
SB
993 if (core->ops->recalc_rate)
994 return core->ops->recalc_rate(core->hw, parent_rate);
995 return parent_rate;
1c8e6004
TV
996}
997
4dff95dc
SB
998/**
999 * __clk_recalc_rates
1000 * @core: first clk in the subtree
1001 * @msg: notification type (see include/linux/clk.h)
1002 *
1003 * Walks the subtree of clks starting with clk and recalculates rates as it
1004 * goes. Note that if a clk does not implement the .recalc_rate callback then
1005 * it is assumed that the clock will take on the rate of its parent.
1006 *
1007 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1008 * if necessary.
15a02c1f 1009 */
4dff95dc 1010static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1011{
4dff95dc
SB
1012 unsigned long old_rate;
1013 unsigned long parent_rate = 0;
1014 struct clk_core *child;
e366fdd7 1015
4dff95dc 1016 lockdep_assert_held(&prepare_lock);
15a02c1f 1017
4dff95dc 1018 old_rate = core->rate;
b2476490 1019
4dff95dc
SB
1020 if (core->parent)
1021 parent_rate = core->parent->rate;
b2476490 1022
4dff95dc 1023 core->rate = clk_recalc(core, parent_rate);
b2476490 1024
4dff95dc
SB
1025 /*
1026 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1027 * & ABORT_RATE_CHANGE notifiers
1028 */
1029 if (core->notifier_count && msg)
1030 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1031
4dff95dc
SB
1032 hlist_for_each_entry(child, &core->children, child_node)
1033 __clk_recalc_rates(child, msg);
1034}
b2476490 1035
4dff95dc
SB
1036static unsigned long clk_core_get_rate(struct clk_core *core)
1037{
1038 unsigned long rate;
dfc202ea 1039
4dff95dc 1040 clk_prepare_lock();
b2476490 1041
4dff95dc
SB
1042 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1043 __clk_recalc_rates(core, 0);
1044
1045 rate = clk_core_get_rate_nolock(core);
1046 clk_prepare_unlock();
1047
1048 return rate;
b2476490
MT
1049}
1050
1051/**
4dff95dc
SB
1052 * clk_get_rate - return the rate of clk
1053 * @clk: the clk whose rate is being returned
b2476490 1054 *
4dff95dc
SB
1055 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1056 * is set, which means a recalc_rate will be issued.
1057 * If clk is NULL then returns 0.
b2476490 1058 */
4dff95dc 1059unsigned long clk_get_rate(struct clk *clk)
b2476490 1060{
4dff95dc
SB
1061 if (!clk)
1062 return 0;
63589e92 1063
4dff95dc 1064 return clk_core_get_rate(clk->core);
b2476490 1065}
4dff95dc 1066EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1067
4dff95dc
SB
1068static int clk_fetch_parent_index(struct clk_core *core,
1069 struct clk_core *parent)
b2476490 1070{
4dff95dc 1071 int i;
b2476490 1072
508f884a
MY
1073 if (!parent)
1074 return -EINVAL;
1075
470b5e2f
MY
1076 for (i = 0; i < core->num_parents; i++)
1077 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1078 return i;
b2476490 1079
4dff95dc 1080 return -EINVAL;
b2476490
MT
1081}
1082
e6500344
HS
1083/*
1084 * Update the orphan status of @core and all its children.
1085 */
1086static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1087{
1088 struct clk_core *child;
1089
1090 core->orphan = is_orphan;
1091
1092 hlist_for_each_entry(child, &core->children, child_node)
1093 clk_core_update_orphan_status(child, is_orphan);
1094}
1095
4dff95dc 1096static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1097{
e6500344
HS
1098 bool was_orphan = core->orphan;
1099
4dff95dc 1100 hlist_del(&core->child_node);
035a61c3 1101
4dff95dc 1102 if (new_parent) {
e6500344
HS
1103 bool becomes_orphan = new_parent->orphan;
1104
4dff95dc
SB
1105 /* avoid duplicate POST_RATE_CHANGE notifications */
1106 if (new_parent->new_child == core)
1107 new_parent->new_child = NULL;
b2476490 1108
4dff95dc 1109 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1110
1111 if (was_orphan != becomes_orphan)
1112 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1113 } else {
1114 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1115 if (!was_orphan)
1116 clk_core_update_orphan_status(core, true);
4dff95dc 1117 }
dfc202ea 1118
4dff95dc 1119 core->parent = new_parent;
035a61c3
TV
1120}
1121
4dff95dc
SB
1122static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1123 struct clk_core *parent)
b2476490
MT
1124{
1125 unsigned long flags;
4dff95dc 1126 struct clk_core *old_parent = core->parent;
b2476490 1127
4dff95dc
SB
1128 /*
1129 * Migrate prepare state between parents and prevent race with
1130 * clk_enable().
1131 *
1132 * If the clock is not prepared, then a race with
1133 * clk_enable/disable() is impossible since we already have the
1134 * prepare lock (future calls to clk_enable() need to be preceded by
1135 * a clk_prepare()).
1136 *
1137 * If the clock is prepared, migrate the prepared state to the new
1138 * parent and also protect against a race with clk_enable() by
1139 * forcing the clock and the new parent on. This ensures that all
1140 * future calls to clk_enable() are practically NOPs with respect to
1141 * hardware and software states.
1142 *
1143 * See also: Comment for clk_set_parent() below.
1144 */
1145 if (core->prepare_count) {
1146 clk_core_prepare(parent);
d2a5d46b 1147 flags = clk_enable_lock();
4dff95dc
SB
1148 clk_core_enable(parent);
1149 clk_core_enable(core);
d2a5d46b 1150 clk_enable_unlock(flags);
4dff95dc 1151 }
63589e92 1152
4dff95dc 1153 /* update the clk tree topology */
eab89f69 1154 flags = clk_enable_lock();
4dff95dc 1155 clk_reparent(core, parent);
eab89f69 1156 clk_enable_unlock(flags);
4dff95dc
SB
1157
1158 return old_parent;
b2476490 1159}
b2476490 1160
4dff95dc
SB
1161static void __clk_set_parent_after(struct clk_core *core,
1162 struct clk_core *parent,
1163 struct clk_core *old_parent)
b2476490 1164{
d2a5d46b
DA
1165 unsigned long flags;
1166
4dff95dc
SB
1167 /*
1168 * Finish the migration of prepare state and undo the changes done
1169 * for preventing a race with clk_enable().
1170 */
1171 if (core->prepare_count) {
d2a5d46b 1172 flags = clk_enable_lock();
4dff95dc
SB
1173 clk_core_disable(core);
1174 clk_core_disable(old_parent);
d2a5d46b 1175 clk_enable_unlock(flags);
4dff95dc
SB
1176 clk_core_unprepare(old_parent);
1177 }
1178}
b2476490 1179
4dff95dc
SB
1180static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1181 u8 p_index)
1182{
1183 unsigned long flags;
1184 int ret = 0;
1185 struct clk_core *old_parent;
b2476490 1186
4dff95dc 1187 old_parent = __clk_set_parent_before(core, parent);
b2476490 1188
4dff95dc 1189 trace_clk_set_parent(core, parent);
b2476490 1190
4dff95dc
SB
1191 /* change clock input source */
1192 if (parent && core->ops->set_parent)
1193 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1194
4dff95dc 1195 trace_clk_set_parent_complete(core, parent);
dfc202ea 1196
4dff95dc
SB
1197 if (ret) {
1198 flags = clk_enable_lock();
1199 clk_reparent(core, old_parent);
1200 clk_enable_unlock(flags);
c660b2eb 1201 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1202
4dff95dc 1203 return ret;
b2476490
MT
1204 }
1205
4dff95dc
SB
1206 __clk_set_parent_after(core, parent, old_parent);
1207
b2476490
MT
1208 return 0;
1209}
1210
1211/**
4dff95dc
SB
1212 * __clk_speculate_rates
1213 * @core: first clk in the subtree
1214 * @parent_rate: the "future" rate of clk's parent
b2476490 1215 *
4dff95dc
SB
1216 * Walks the subtree of clks starting with clk, speculating rates as it
1217 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1218 *
1219 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1220 * pre-rate change notifications and returns early if no clks in the
1221 * subtree have subscribed to the notifications. Note that if a clk does not
1222 * implement the .recalc_rate callback then it is assumed that the clock will
1223 * take on the rate of its parent.
b2476490 1224 */
4dff95dc
SB
1225static int __clk_speculate_rates(struct clk_core *core,
1226 unsigned long parent_rate)
b2476490 1227{
4dff95dc
SB
1228 struct clk_core *child;
1229 unsigned long new_rate;
1230 int ret = NOTIFY_DONE;
b2476490 1231
4dff95dc 1232 lockdep_assert_held(&prepare_lock);
864e160a 1233
4dff95dc
SB
1234 new_rate = clk_recalc(core, parent_rate);
1235
1236 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1237 if (core->notifier_count)
1238 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1239
1240 if (ret & NOTIFY_STOP_MASK) {
1241 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1242 __func__, core->name, ret);
1243 goto out;
1244 }
1245
1246 hlist_for_each_entry(child, &core->children, child_node) {
1247 ret = __clk_speculate_rates(child, new_rate);
1248 if (ret & NOTIFY_STOP_MASK)
1249 break;
1250 }
b2476490 1251
4dff95dc 1252out:
b2476490
MT
1253 return ret;
1254}
b2476490 1255
4dff95dc
SB
1256static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1257 struct clk_core *new_parent, u8 p_index)
b2476490 1258{
4dff95dc 1259 struct clk_core *child;
b2476490 1260
4dff95dc
SB
1261 core->new_rate = new_rate;
1262 core->new_parent = new_parent;
1263 core->new_parent_index = p_index;
1264 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1265 core->new_child = NULL;
1266 if (new_parent && new_parent != core->parent)
1267 new_parent->new_child = core;
496eadf8 1268
4dff95dc
SB
1269 hlist_for_each_entry(child, &core->children, child_node) {
1270 child->new_rate = clk_recalc(child, new_rate);
1271 clk_calc_subtree(child, child->new_rate, NULL, 0);
1272 }
1273}
b2476490 1274
4dff95dc
SB
1275/*
1276 * calculate the new rates returning the topmost clock that has to be
1277 * changed.
1278 */
1279static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1280 unsigned long rate)
1281{
1282 struct clk_core *top = core;
1283 struct clk_core *old_parent, *parent;
4dff95dc
SB
1284 unsigned long best_parent_rate = 0;
1285 unsigned long new_rate;
1286 unsigned long min_rate;
1287 unsigned long max_rate;
1288 int p_index = 0;
1289 long ret;
1290
1291 /* sanity */
1292 if (IS_ERR_OR_NULL(core))
1293 return NULL;
1294
1295 /* save parent rate, if it exists */
1296 parent = old_parent = core->parent;
71472c0c 1297 if (parent)
4dff95dc 1298 best_parent_rate = parent->rate;
71472c0c 1299
4dff95dc
SB
1300 clk_core_get_boundaries(core, &min_rate, &max_rate);
1301
1302 /* find the closest rate and parent clk/rate */
d6968fca 1303 if (core->ops->determine_rate) {
0817b62c
BB
1304 struct clk_rate_request req;
1305
1306 req.rate = rate;
1307 req.min_rate = min_rate;
1308 req.max_rate = max_rate;
1309 if (parent) {
1310 req.best_parent_hw = parent->hw;
1311 req.best_parent_rate = parent->rate;
1312 } else {
1313 req.best_parent_hw = NULL;
1314 req.best_parent_rate = 0;
1315 }
1316
1317 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1318 if (ret < 0)
1319 return NULL;
1c8e6004 1320
0817b62c
BB
1321 best_parent_rate = req.best_parent_rate;
1322 new_rate = req.rate;
1323 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1324 } else if (core->ops->round_rate) {
1325 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1326 &best_parent_rate);
4dff95dc
SB
1327 if (ret < 0)
1328 return NULL;
035a61c3 1329
4dff95dc
SB
1330 new_rate = ret;
1331 if (new_rate < min_rate || new_rate > max_rate)
1332 return NULL;
1333 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1334 /* pass-through clock without adjustable parent */
1335 core->new_rate = core->rate;
1336 return NULL;
1337 } else {
1338 /* pass-through clock with adjustable parent */
1339 top = clk_calc_new_rates(parent, rate);
1340 new_rate = parent->new_rate;
1341 goto out;
1342 }
1c8e6004 1343
4dff95dc
SB
1344 /* some clocks must be gated to change parent */
1345 if (parent != old_parent &&
1346 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1347 pr_debug("%s: %s not gated but wants to reparent\n",
1348 __func__, core->name);
1349 return NULL;
1350 }
b2476490 1351
4dff95dc
SB
1352 /* try finding the new parent index */
1353 if (parent && core->num_parents > 1) {
1354 p_index = clk_fetch_parent_index(core, parent);
1355 if (p_index < 0) {
1356 pr_debug("%s: clk %s can not be parent of clk %s\n",
1357 __func__, parent->name, core->name);
1358 return NULL;
1359 }
1360 }
b2476490 1361
4dff95dc
SB
1362 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1363 best_parent_rate != parent->rate)
1364 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1365
4dff95dc
SB
1366out:
1367 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1368
4dff95dc 1369 return top;
b2476490 1370}
b2476490 1371
4dff95dc
SB
1372/*
1373 * Notify about rate changes in a subtree. Always walk down the whole tree
1374 * so that in case of an error we can walk down the whole tree again and
1375 * abort the change.
b2476490 1376 */
4dff95dc
SB
1377static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1378 unsigned long event)
b2476490 1379{
4dff95dc 1380 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1381 int ret = NOTIFY_DONE;
1382
4dff95dc
SB
1383 if (core->rate == core->new_rate)
1384 return NULL;
b2476490 1385
4dff95dc
SB
1386 if (core->notifier_count) {
1387 ret = __clk_notify(core, event, core->rate, core->new_rate);
1388 if (ret & NOTIFY_STOP_MASK)
1389 fail_clk = core;
b2476490
MT
1390 }
1391
4dff95dc
SB
1392 hlist_for_each_entry(child, &core->children, child_node) {
1393 /* Skip children who will be reparented to another clock */
1394 if (child->new_parent && child->new_parent != core)
1395 continue;
1396 tmp_clk = clk_propagate_rate_change(child, event);
1397 if (tmp_clk)
1398 fail_clk = tmp_clk;
1399 }
5279fc40 1400
4dff95dc
SB
1401 /* handle the new child who might not be in core->children yet */
1402 if (core->new_child) {
1403 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1404 if (tmp_clk)
1405 fail_clk = tmp_clk;
1406 }
5279fc40 1407
4dff95dc 1408 return fail_clk;
5279fc40
BB
1409}
1410
4dff95dc
SB
1411/*
1412 * walk down a subtree and set the new rates notifying the rate
1413 * change on the way
1414 */
1415static void clk_change_rate(struct clk_core *core)
035a61c3 1416{
4dff95dc
SB
1417 struct clk_core *child;
1418 struct hlist_node *tmp;
1419 unsigned long old_rate;
1420 unsigned long best_parent_rate = 0;
1421 bool skip_set_rate = false;
1422 struct clk_core *old_parent;
035a61c3 1423
4dff95dc 1424 old_rate = core->rate;
035a61c3 1425
4dff95dc
SB
1426 if (core->new_parent)
1427 best_parent_rate = core->new_parent->rate;
1428 else if (core->parent)
1429 best_parent_rate = core->parent->rate;
035a61c3 1430
2eb8c710
HS
1431 if (core->flags & CLK_SET_RATE_UNGATE) {
1432 unsigned long flags;
1433
1434 clk_core_prepare(core);
1435 flags = clk_enable_lock();
1436 clk_core_enable(core);
1437 clk_enable_unlock(flags);
1438 }
1439
4dff95dc
SB
1440 if (core->new_parent && core->new_parent != core->parent) {
1441 old_parent = __clk_set_parent_before(core, core->new_parent);
1442 trace_clk_set_parent(core, core->new_parent);
5279fc40 1443
4dff95dc
SB
1444 if (core->ops->set_rate_and_parent) {
1445 skip_set_rate = true;
1446 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1447 best_parent_rate,
1448 core->new_parent_index);
1449 } else if (core->ops->set_parent) {
1450 core->ops->set_parent(core->hw, core->new_parent_index);
1451 }
5279fc40 1452
4dff95dc
SB
1453 trace_clk_set_parent_complete(core, core->new_parent);
1454 __clk_set_parent_after(core, core->new_parent, old_parent);
1455 }
8f2c2db1 1456
4dff95dc 1457 trace_clk_set_rate(core, core->new_rate);
b2476490 1458
4dff95dc
SB
1459 if (!skip_set_rate && core->ops->set_rate)
1460 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1461
4dff95dc 1462 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1463
4dff95dc 1464 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1465
2eb8c710
HS
1466 if (core->flags & CLK_SET_RATE_UNGATE) {
1467 unsigned long flags;
1468
1469 flags = clk_enable_lock();
1470 clk_core_disable(core);
1471 clk_enable_unlock(flags);
1472 clk_core_unprepare(core);
1473 }
1474
4dff95dc
SB
1475 if (core->notifier_count && old_rate != core->rate)
1476 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1477
85e88fab
MT
1478 if (core->flags & CLK_RECALC_NEW_RATES)
1479 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1480
b2476490 1481 /*
4dff95dc
SB
1482 * Use safe iteration, as change_rate can actually swap parents
1483 * for certain clock types.
b2476490 1484 */
4dff95dc
SB
1485 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1486 /* Skip children who will be reparented to another clock */
1487 if (child->new_parent && child->new_parent != core)
1488 continue;
1489 clk_change_rate(child);
1490 }
b2476490 1491
4dff95dc
SB
1492 /* handle the new child who might not be in core->children yet */
1493 if (core->new_child)
1494 clk_change_rate(core->new_child);
b2476490
MT
1495}
1496
4dff95dc
SB
1497static int clk_core_set_rate_nolock(struct clk_core *core,
1498 unsigned long req_rate)
a093bde2 1499{
4dff95dc
SB
1500 struct clk_core *top, *fail_clk;
1501 unsigned long rate = req_rate;
a093bde2 1502
4dff95dc
SB
1503 if (!core)
1504 return 0;
a093bde2 1505
4dff95dc
SB
1506 /* bail early if nothing to do */
1507 if (rate == clk_core_get_rate_nolock(core))
1508 return 0;
a093bde2 1509
4dff95dc
SB
1510 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1511 return -EBUSY;
a093bde2 1512
4dff95dc
SB
1513 /* calculate new rates and get the topmost changed clock */
1514 top = clk_calc_new_rates(core, rate);
1515 if (!top)
1516 return -EINVAL;
1517
1518 /* notify that we are about to change rates */
1519 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1520 if (fail_clk) {
1521 pr_debug("%s: failed to set %s rate\n", __func__,
1522 fail_clk->name);
1523 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1524 return -EBUSY;
1525 }
1526
1527 /* change the rates */
1528 clk_change_rate(top);
1529
1530 core->req_rate = req_rate;
1531
06b37e4a 1532 return 0;
a093bde2 1533}
035a61c3
TV
1534
1535/**
4dff95dc
SB
1536 * clk_set_rate - specify a new rate for clk
1537 * @clk: the clk whose rate is being changed
1538 * @rate: the new rate for clk
035a61c3 1539 *
4dff95dc
SB
1540 * In the simplest case clk_set_rate will only adjust the rate of clk.
1541 *
1542 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1543 * propagate up to clk's parent; whether or not this happens depends on the
1544 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1545 * after calling .round_rate then upstream parent propagation is ignored. If
1546 * *parent_rate comes back with a new rate for clk's parent then we propagate
1547 * up to clk's parent and set its rate. Upward propagation will continue
1548 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1549 * .round_rate stops requesting changes to clk's parent_rate.
1550 *
1551 * Rate changes are accomplished via tree traversal that also recalculates the
1552 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1553 *
1554 * Returns 0 on success, -EERROR otherwise.
035a61c3 1555 */
4dff95dc 1556int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1557{
4dff95dc
SB
1558 int ret;
1559
035a61c3
TV
1560 if (!clk)
1561 return 0;
1562
4dff95dc
SB
1563 /* prevent racing with updates to the clock topology */
1564 clk_prepare_lock();
da0f0b2c 1565
4dff95dc 1566 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1567
4dff95dc 1568 clk_prepare_unlock();
4935b22c 1569
4dff95dc 1570 return ret;
4935b22c 1571}
4dff95dc 1572EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1573
4dff95dc
SB
1574/**
1575 * clk_set_rate_range - set a rate range for a clock source
1576 * @clk: clock source
1577 * @min: desired minimum clock rate in Hz, inclusive
1578 * @max: desired maximum clock rate in Hz, inclusive
1579 *
1580 * Returns success (0) or negative errno.
1581 */
1582int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1583{
4dff95dc 1584 int ret = 0;
4935b22c 1585
4dff95dc
SB
1586 if (!clk)
1587 return 0;
903efc55 1588
4dff95dc
SB
1589 if (min > max) {
1590 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1591 __func__, clk->core->name, clk->dev_id, clk->con_id,
1592 min, max);
1593 return -EINVAL;
903efc55 1594 }
4935b22c 1595
4dff95dc 1596 clk_prepare_lock();
4935b22c 1597
4dff95dc
SB
1598 if (min != clk->min_rate || max != clk->max_rate) {
1599 clk->min_rate = min;
1600 clk->max_rate = max;
1601 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1602 }
1603
4dff95dc 1604 clk_prepare_unlock();
4935b22c 1605
4dff95dc 1606 return ret;
3fa2252b 1607}
4dff95dc 1608EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1609
4dff95dc
SB
1610/**
1611 * clk_set_min_rate - set a minimum clock rate for a clock source
1612 * @clk: clock source
1613 * @rate: desired minimum clock rate in Hz, inclusive
1614 *
1615 * Returns success (0) or negative errno.
1616 */
1617int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1618{
4dff95dc
SB
1619 if (!clk)
1620 return 0;
1621
1622 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1623}
4dff95dc 1624EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1625
4dff95dc
SB
1626/**
1627 * clk_set_max_rate - set a maximum clock rate for a clock source
1628 * @clk: clock source
1629 * @rate: desired maximum clock rate in Hz, inclusive
1630 *
1631 * Returns success (0) or negative errno.
1632 */
1633int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1634{
4dff95dc
SB
1635 if (!clk)
1636 return 0;
4935b22c 1637
4dff95dc 1638 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1639}
4dff95dc 1640EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1641
b2476490 1642/**
4dff95dc
SB
1643 * clk_get_parent - return the parent of a clk
1644 * @clk: the clk whose parent gets returned
b2476490 1645 *
4dff95dc 1646 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1647 */
4dff95dc 1648struct clk *clk_get_parent(struct clk *clk)
b2476490 1649{
4dff95dc 1650 struct clk *parent;
b2476490 1651
fc4a05d4
SB
1652 if (!clk)
1653 return NULL;
1654
4dff95dc 1655 clk_prepare_lock();
fc4a05d4
SB
1656 /* TODO: Create a per-user clk and change callers to call clk_put */
1657 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1658 clk_prepare_unlock();
496eadf8 1659
4dff95dc
SB
1660 return parent;
1661}
1662EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1663
4dff95dc
SB
1664static struct clk_core *__clk_init_parent(struct clk_core *core)
1665{
5146e0b0 1666 u8 index = 0;
4dff95dc 1667
2430a94d 1668 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1669 index = core->ops->get_parent(core->hw);
b2476490 1670
5146e0b0 1671 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1672}
1673
4dff95dc
SB
1674static void clk_core_reparent(struct clk_core *core,
1675 struct clk_core *new_parent)
b2476490 1676{
4dff95dc
SB
1677 clk_reparent(core, new_parent);
1678 __clk_recalc_accuracies(core);
1679 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1680}
1681
42c86547
TV
1682void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1683{
1684 if (!hw)
1685 return;
1686
1687 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1688}
1689
4dff95dc
SB
1690/**
1691 * clk_has_parent - check if a clock is a possible parent for another
1692 * @clk: clock source
1693 * @parent: parent clock source
1694 *
1695 * This function can be used in drivers that need to check that a clock can be
1696 * the parent of another without actually changing the parent.
1697 *
1698 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1699 */
4dff95dc 1700bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1701{
4dff95dc
SB
1702 struct clk_core *core, *parent_core;
1703 unsigned int i;
b2476490 1704
4dff95dc
SB
1705 /* NULL clocks should be nops, so return success if either is NULL. */
1706 if (!clk || !parent)
1707 return true;
7452b219 1708
4dff95dc
SB
1709 core = clk->core;
1710 parent_core = parent->core;
71472c0c 1711
4dff95dc
SB
1712 /* Optimize for the case where the parent is already the parent. */
1713 if (core->parent == parent_core)
1714 return true;
1c8e6004 1715
4dff95dc
SB
1716 for (i = 0; i < core->num_parents; i++)
1717 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1718 return true;
03bc10ab 1719
4dff95dc
SB
1720 return false;
1721}
1722EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1723
4dff95dc
SB
1724static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1725{
1726 int ret = 0;
1727 int p_index = 0;
1728 unsigned long p_rate = 0;
1729
1730 if (!core)
1731 return 0;
1732
1733 /* prevent racing with updates to the clock topology */
1734 clk_prepare_lock();
1735
1736 if (core->parent == parent)
1737 goto out;
1738
1739 /* verify ops for for multi-parent clks */
1740 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1741 ret = -ENOSYS;
63f5c3b2 1742 goto out;
7452b219
MT
1743 }
1744
4dff95dc
SB
1745 /* check that we are allowed to re-parent if the clock is in use */
1746 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1747 ret = -EBUSY;
1748 goto out;
b2476490
MT
1749 }
1750
71472c0c 1751 /* try finding the new parent index */
4dff95dc 1752 if (parent) {
d6968fca 1753 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1754 if (p_index < 0) {
71472c0c 1755 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1756 __func__, parent->name, core->name);
1757 ret = p_index;
1758 goto out;
71472c0c 1759 }
e8f0e68e 1760 p_rate = parent->rate;
b2476490
MT
1761 }
1762
4dff95dc
SB
1763 /* propagate PRE_RATE_CHANGE notifications */
1764 ret = __clk_speculate_rates(core, p_rate);
b2476490 1765
4dff95dc
SB
1766 /* abort if a driver objects */
1767 if (ret & NOTIFY_STOP_MASK)
1768 goto out;
b2476490 1769
4dff95dc
SB
1770 /* do the re-parent */
1771 ret = __clk_set_parent(core, parent, p_index);
b2476490 1772
4dff95dc
SB
1773 /* propagate rate an accuracy recalculation accordingly */
1774 if (ret) {
1775 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1776 } else {
1777 __clk_recalc_rates(core, POST_RATE_CHANGE);
1778 __clk_recalc_accuracies(core);
b2476490
MT
1779 }
1780
4dff95dc
SB
1781out:
1782 clk_prepare_unlock();
71472c0c 1783
4dff95dc
SB
1784 return ret;
1785}
b2476490 1786
4dff95dc
SB
1787/**
1788 * clk_set_parent - switch the parent of a mux clk
1789 * @clk: the mux clk whose input we are switching
1790 * @parent: the new input to clk
1791 *
1792 * Re-parent clk to use parent as its new input source. If clk is in
1793 * prepared state, the clk will get enabled for the duration of this call. If
1794 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1795 * that, the reparenting is glitchy in hardware, etc), use the
1796 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1797 *
1798 * After successfully changing clk's parent clk_set_parent will update the
1799 * clk topology, sysfs topology and propagate rate recalculation via
1800 * __clk_recalc_rates.
1801 *
1802 * Returns 0 on success, -EERROR otherwise.
1803 */
1804int clk_set_parent(struct clk *clk, struct clk *parent)
1805{
1806 if (!clk)
1807 return 0;
1808
1809 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1810}
4dff95dc 1811EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1812
4dff95dc
SB
1813/**
1814 * clk_set_phase - adjust the phase shift of a clock signal
1815 * @clk: clock signal source
1816 * @degrees: number of degrees the signal is shifted
1817 *
1818 * Shifts the phase of a clock signal by the specified
1819 * degrees. Returns 0 on success, -EERROR otherwise.
1820 *
1821 * This function makes no distinction about the input or reference
1822 * signal that we adjust the clock signal phase against. For example
1823 * phase locked-loop clock signal generators we may shift phase with
1824 * respect to feedback clock signal input, but for other cases the
1825 * clock phase may be shifted with respect to some other, unspecified
1826 * signal.
1827 *
1828 * Additionally the concept of phase shift does not propagate through
1829 * the clock tree hierarchy, which sets it apart from clock rates and
1830 * clock accuracy. A parent clock phase attribute does not have an
1831 * impact on the phase attribute of a child clock.
b2476490 1832 */
4dff95dc 1833int clk_set_phase(struct clk *clk, int degrees)
b2476490 1834{
4dff95dc 1835 int ret = -EINVAL;
b2476490 1836
4dff95dc
SB
1837 if (!clk)
1838 return 0;
b2476490 1839
4dff95dc
SB
1840 /* sanity check degrees */
1841 degrees %= 360;
1842 if (degrees < 0)
1843 degrees += 360;
bf47b4fd 1844
4dff95dc 1845 clk_prepare_lock();
3fa2252b 1846
023bd716
SL
1847 /* bail early if nothing to do */
1848 if (degrees == clk->core->phase)
1849 goto out;
1850
4dff95dc 1851 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1852
4dff95dc
SB
1853 if (clk->core->ops->set_phase)
1854 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1855
4dff95dc 1856 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1857
4dff95dc
SB
1858 if (!ret)
1859 clk->core->phase = degrees;
b2476490 1860
023bd716 1861out:
4dff95dc 1862 clk_prepare_unlock();
dfc202ea 1863
4dff95dc
SB
1864 return ret;
1865}
1866EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1867
4dff95dc
SB
1868static int clk_core_get_phase(struct clk_core *core)
1869{
1870 int ret;
b2476490 1871
4dff95dc
SB
1872 clk_prepare_lock();
1873 ret = core->phase;
1874 clk_prepare_unlock();
71472c0c 1875
4dff95dc 1876 return ret;
b2476490
MT
1877}
1878
4dff95dc
SB
1879/**
1880 * clk_get_phase - return the phase shift of a clock signal
1881 * @clk: clock signal source
1882 *
1883 * Returns the phase shift of a clock node in degrees, otherwise returns
1884 * -EERROR.
1885 */
1886int clk_get_phase(struct clk *clk)
1c8e6004 1887{
4dff95dc 1888 if (!clk)
1c8e6004
TV
1889 return 0;
1890
4dff95dc
SB
1891 return clk_core_get_phase(clk->core);
1892}
1893EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1894
4dff95dc
SB
1895/**
1896 * clk_is_match - check if two clk's point to the same hardware clock
1897 * @p: clk compared against q
1898 * @q: clk compared against p
1899 *
1900 * Returns true if the two struct clk pointers both point to the same hardware
1901 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1902 * share the same struct clk_core object.
1903 *
1904 * Returns false otherwise. Note that two NULL clks are treated as matching.
1905 */
1906bool clk_is_match(const struct clk *p, const struct clk *q)
1907{
1908 /* trivial case: identical struct clk's or both NULL */
1909 if (p == q)
1910 return true;
1c8e6004 1911
3fe003f9 1912 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
1913 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1914 if (p->core == q->core)
1915 return true;
1c8e6004 1916
4dff95dc
SB
1917 return false;
1918}
1919EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1920
4dff95dc 1921/*** debugfs support ***/
1c8e6004 1922
4dff95dc
SB
1923#ifdef CONFIG_DEBUG_FS
1924#include <linux/debugfs.h>
1c8e6004 1925
4dff95dc
SB
1926static struct dentry *rootdir;
1927static int inited = 0;
1928static DEFINE_MUTEX(clk_debug_lock);
1929static HLIST_HEAD(clk_debug_list);
1c8e6004 1930
4dff95dc
SB
1931static struct hlist_head *all_lists[] = {
1932 &clk_root_list,
1933 &clk_orphan_list,
1934 NULL,
1935};
1936
1937static struct hlist_head *orphan_list[] = {
1938 &clk_orphan_list,
1939 NULL,
1940};
1941
1942static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
1943 int level)
b2476490 1944{
4dff95dc
SB
1945 if (!c)
1946 return;
b2476490 1947
4dff95dc
SB
1948 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1949 level * 3 + 1, "",
1950 30 - level * 3, c->name,
1951 c->enable_count, c->prepare_count, clk_core_get_rate(c),
1952 clk_core_get_accuracy(c), clk_core_get_phase(c));
1953}
89ac8d7a 1954
4dff95dc
SB
1955static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1956 int level)
1957{
1958 struct clk_core *child;
b2476490 1959
4dff95dc
SB
1960 if (!c)
1961 return;
b2476490 1962
4dff95dc 1963 clk_summary_show_one(s, c, level);
0e1c0301 1964
4dff95dc
SB
1965 hlist_for_each_entry(child, &c->children, child_node)
1966 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 1967}
b2476490 1968
4dff95dc 1969static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 1970{
4dff95dc
SB
1971 struct clk_core *c;
1972 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 1973
4dff95dc
SB
1974 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
1975 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 1976
1c8e6004
TV
1977 clk_prepare_lock();
1978
4dff95dc
SB
1979 for (; *lists; lists++)
1980 hlist_for_each_entry(c, *lists, child_node)
1981 clk_summary_show_subtree(s, c, 0);
b2476490 1982
eab89f69 1983 clk_prepare_unlock();
b2476490 1984
4dff95dc 1985 return 0;
b2476490 1986}
1c8e6004 1987
1c8e6004 1988
4dff95dc 1989static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 1990{
4dff95dc 1991 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 1992}
b2476490 1993
4dff95dc
SB
1994static const struct file_operations clk_summary_fops = {
1995 .open = clk_summary_open,
1996 .read = seq_read,
1997 .llseek = seq_lseek,
1998 .release = single_release,
1999};
b2476490 2000
4dff95dc
SB
2001static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2002{
2003 if (!c)
2004 return;
b2476490 2005
7cb81136 2006 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2007 seq_printf(s, "\"%s\": { ", c->name);
2008 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2009 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2010 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2011 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2012 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2013}
b2476490 2014
4dff95dc 2015static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2016{
4dff95dc 2017 struct clk_core *child;
b2476490 2018
4dff95dc
SB
2019 if (!c)
2020 return;
b2476490 2021
4dff95dc 2022 clk_dump_one(s, c, level);
b2476490 2023
4dff95dc
SB
2024 hlist_for_each_entry(child, &c->children, child_node) {
2025 seq_printf(s, ",");
2026 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2027 }
2028
4dff95dc 2029 seq_printf(s, "}");
b2476490
MT
2030}
2031
4dff95dc 2032static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2033{
4dff95dc
SB
2034 struct clk_core *c;
2035 bool first_node = true;
2036 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2037
4dff95dc 2038 seq_printf(s, "{");
4e88f3de 2039
4dff95dc 2040 clk_prepare_lock();
035a61c3 2041
4dff95dc
SB
2042 for (; *lists; lists++) {
2043 hlist_for_each_entry(c, *lists, child_node) {
2044 if (!first_node)
2045 seq_puts(s, ",");
2046 first_node = false;
2047 clk_dump_subtree(s, c, 0);
2048 }
2049 }
4e88f3de 2050
4dff95dc 2051 clk_prepare_unlock();
4e88f3de 2052
70e9f4dd 2053 seq_puts(s, "}\n");
4dff95dc 2054 return 0;
4e88f3de 2055}
4e88f3de 2056
4dff95dc
SB
2057
2058static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2059{
4dff95dc
SB
2060 return single_open(file, clk_dump, inode->i_private);
2061}
b2476490 2062
4dff95dc
SB
2063static const struct file_operations clk_dump_fops = {
2064 .open = clk_dump_open,
2065 .read = seq_read,
2066 .llseek = seq_lseek,
2067 .release = single_release,
2068};
89ac8d7a 2069
4dff95dc
SB
2070static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2071{
2072 struct dentry *d;
2073 int ret = -ENOMEM;
b2476490 2074
4dff95dc
SB
2075 if (!core || !pdentry) {
2076 ret = -EINVAL;
b2476490 2077 goto out;
4dff95dc 2078 }
b2476490 2079
4dff95dc
SB
2080 d = debugfs_create_dir(core->name, pdentry);
2081 if (!d)
b61c43c0 2082 goto out;
b61c43c0 2083
4dff95dc
SB
2084 core->dentry = d;
2085
2086 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2087 (u32 *)&core->rate);
2088 if (!d)
2089 goto err_out;
2090
2091 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2092 (u32 *)&core->accuracy);
2093 if (!d)
2094 goto err_out;
2095
2096 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2097 (u32 *)&core->phase);
2098 if (!d)
2099 goto err_out;
031dcc9b 2100
4dff95dc
SB
2101 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2102 (u32 *)&core->flags);
2103 if (!d)
2104 goto err_out;
031dcc9b 2105
4dff95dc
SB
2106 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2107 (u32 *)&core->prepare_count);
2108 if (!d)
2109 goto err_out;
b2476490 2110
4dff95dc
SB
2111 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2112 (u32 *)&core->enable_count);
2113 if (!d)
2114 goto err_out;
b2476490 2115
4dff95dc
SB
2116 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2117 (u32 *)&core->notifier_count);
2118 if (!d)
2119 goto err_out;
b2476490 2120
4dff95dc
SB
2121 if (core->ops->debug_init) {
2122 ret = core->ops->debug_init(core->hw, core->dentry);
2123 if (ret)
2124 goto err_out;
5279fc40 2125 }
b2476490 2126
4dff95dc
SB
2127 ret = 0;
2128 goto out;
b2476490 2129
4dff95dc
SB
2130err_out:
2131 debugfs_remove_recursive(core->dentry);
2132 core->dentry = NULL;
2133out:
b2476490
MT
2134 return ret;
2135}
035a61c3
TV
2136
2137/**
6e5ab41b
SB
2138 * clk_debug_register - add a clk node to the debugfs clk directory
2139 * @core: the clk being added to the debugfs clk directory
035a61c3 2140 *
6e5ab41b
SB
2141 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2142 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2143 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2144 */
4dff95dc 2145static int clk_debug_register(struct clk_core *core)
035a61c3 2146{
4dff95dc 2147 int ret = 0;
035a61c3 2148
4dff95dc
SB
2149 mutex_lock(&clk_debug_lock);
2150 hlist_add_head(&core->debug_node, &clk_debug_list);
2151
2152 if (!inited)
2153 goto unlock;
2154
2155 ret = clk_debug_create_one(core, rootdir);
2156unlock:
2157 mutex_unlock(&clk_debug_lock);
2158
2159 return ret;
035a61c3 2160}
b2476490 2161
4dff95dc 2162 /**
6e5ab41b
SB
2163 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2164 * @core: the clk being removed from the debugfs clk directory
e59c5371 2165 *
6e5ab41b
SB
2166 * Dynamically removes a clk and all its child nodes from the
2167 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2168 * clk_debug_register in __clk_core_init.
e59c5371 2169 */
4dff95dc 2170static void clk_debug_unregister(struct clk_core *core)
e59c5371 2171{
4dff95dc
SB
2172 mutex_lock(&clk_debug_lock);
2173 hlist_del_init(&core->debug_node);
2174 debugfs_remove_recursive(core->dentry);
2175 core->dentry = NULL;
2176 mutex_unlock(&clk_debug_lock);
2177}
e59c5371 2178
4dff95dc
SB
2179struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2180 void *data, const struct file_operations *fops)
2181{
2182 struct dentry *d = NULL;
e59c5371 2183
4dff95dc
SB
2184 if (hw->core->dentry)
2185 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2186 fops);
e59c5371 2187
4dff95dc
SB
2188 return d;
2189}
2190EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2191
4dff95dc 2192/**
6e5ab41b 2193 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2194 *
6e5ab41b
SB
2195 * clks are often initialized very early during boot before memory can be
2196 * dynamically allocated and well before debugfs is setup. This function
2197 * populates the debugfs clk directory once at boot-time when we know that
2198 * debugfs is setup. It should only be called once at boot-time, all other clks
2199 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2200 */
2201static int __init clk_debug_init(void)
2202{
2203 struct clk_core *core;
2204 struct dentry *d;
dfc202ea 2205
4dff95dc 2206 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2207
4dff95dc
SB
2208 if (!rootdir)
2209 return -ENOMEM;
dfc202ea 2210
4dff95dc
SB
2211 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2212 &clk_summary_fops);
2213 if (!d)
2214 return -ENOMEM;
e59c5371 2215
4dff95dc
SB
2216 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2217 &clk_dump_fops);
2218 if (!d)
2219 return -ENOMEM;
e59c5371 2220
4dff95dc
SB
2221 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2222 &orphan_list, &clk_summary_fops);
2223 if (!d)
2224 return -ENOMEM;
e59c5371 2225
4dff95dc
SB
2226 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2227 &orphan_list, &clk_dump_fops);
2228 if (!d)
2229 return -ENOMEM;
e59c5371 2230
4dff95dc
SB
2231 mutex_lock(&clk_debug_lock);
2232 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2233 clk_debug_create_one(core, rootdir);
e59c5371 2234
4dff95dc
SB
2235 inited = 1;
2236 mutex_unlock(&clk_debug_lock);
e59c5371 2237
4dff95dc
SB
2238 return 0;
2239}
2240late_initcall(clk_debug_init);
2241#else
2242static inline int clk_debug_register(struct clk_core *core) { return 0; }
2243static inline void clk_debug_reparent(struct clk_core *core,
2244 struct clk_core *new_parent)
035a61c3 2245{
035a61c3 2246}
4dff95dc 2247static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2248{
3d3801ef 2249}
4dff95dc 2250#endif
3d3801ef 2251
b2476490 2252/**
be45ebf2 2253 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2254 * @core: clk_core being initialized
b2476490 2255 *
035a61c3 2256 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2257 * parent and rate and sets them both.
b2476490 2258 */
be45ebf2 2259static int __clk_core_init(struct clk_core *core)
b2476490 2260{
d1302a36 2261 int i, ret = 0;
035a61c3 2262 struct clk_core *orphan;
b67bfe0d 2263 struct hlist_node *tmp2;
1c8e6004 2264 unsigned long rate;
b2476490 2265
d35c80c2 2266 if (!core)
d1302a36 2267 return -EINVAL;
b2476490 2268
eab89f69 2269 clk_prepare_lock();
b2476490
MT
2270
2271 /* check to see if a clock with this name is already registered */
d6968fca 2272 if (clk_core_lookup(core->name)) {
d1302a36 2273 pr_debug("%s: clk %s already initialized\n",
d6968fca 2274 __func__, core->name);
d1302a36 2275 ret = -EEXIST;
b2476490 2276 goto out;
d1302a36 2277 }
b2476490 2278
d4d7e3dd 2279 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2280 if (core->ops->set_rate &&
2281 !((core->ops->round_rate || core->ops->determine_rate) &&
2282 core->ops->recalc_rate)) {
c44fccb5
MY
2283 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2284 __func__, core->name);
d1302a36 2285 ret = -EINVAL;
d4d7e3dd
MT
2286 goto out;
2287 }
2288
d6968fca 2289 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2290 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2291 __func__, core->name);
d1302a36 2292 ret = -EINVAL;
d4d7e3dd
MT
2293 goto out;
2294 }
2295
3c8e77dd
MY
2296 if (core->num_parents > 1 && !core->ops->get_parent) {
2297 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2298 __func__, core->name);
2299 ret = -EINVAL;
2300 goto out;
2301 }
2302
d6968fca
SB
2303 if (core->ops->set_rate_and_parent &&
2304 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2305 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2306 __func__, core->name);
3fa2252b
SB
2307 ret = -EINVAL;
2308 goto out;
2309 }
2310
b2476490 2311 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2312 for (i = 0; i < core->num_parents; i++)
2313 WARN(!core->parent_names[i],
b2476490 2314 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2315 __func__, core->name);
b2476490 2316
d6968fca 2317 core->parent = __clk_init_parent(core);
b2476490
MT
2318
2319 /*
706d5c73
SB
2320 * Populate core->parent if parent has already been clk_core_init'd. If
2321 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2322 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2323 * clk list.
2324 *
2325 * Every time a new clk is clk_init'd then we walk the list of orphan
2326 * clocks and re-parent any that are children of the clock currently
2327 * being clk_init'd.
2328 */
e6500344 2329 if (core->parent) {
d6968fca
SB
2330 hlist_add_head(&core->child_node,
2331 &core->parent->children);
e6500344 2332 core->orphan = core->parent->orphan;
47b0eeb3 2333 } else if (!core->num_parents) {
d6968fca 2334 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2335 core->orphan = false;
2336 } else {
d6968fca 2337 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2338 core->orphan = true;
2339 }
b2476490 2340
5279fc40
BB
2341 /*
2342 * Set clk's accuracy. The preferred method is to use
2343 * .recalc_accuracy. For simple clocks and lazy developers the default
2344 * fallback is to use the parent's accuracy. If a clock doesn't have a
2345 * parent (or is orphaned) then accuracy is set to zero (perfect
2346 * clock).
2347 */
d6968fca
SB
2348 if (core->ops->recalc_accuracy)
2349 core->accuracy = core->ops->recalc_accuracy(core->hw,
2350 __clk_get_accuracy(core->parent));
2351 else if (core->parent)
2352 core->accuracy = core->parent->accuracy;
5279fc40 2353 else
d6968fca 2354 core->accuracy = 0;
5279fc40 2355
9824cf73
MR
2356 /*
2357 * Set clk's phase.
2358 * Since a phase is by definition relative to its parent, just
2359 * query the current clock phase, or just assume it's in phase.
2360 */
d6968fca
SB
2361 if (core->ops->get_phase)
2362 core->phase = core->ops->get_phase(core->hw);
9824cf73 2363 else
d6968fca 2364 core->phase = 0;
9824cf73 2365
b2476490
MT
2366 /*
2367 * Set clk's rate. The preferred method is to use .recalc_rate. For
2368 * simple clocks and lazy developers the default fallback is to use the
2369 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2370 * then rate is set to zero.
2371 */
d6968fca
SB
2372 if (core->ops->recalc_rate)
2373 rate = core->ops->recalc_rate(core->hw,
2374 clk_core_get_rate_nolock(core->parent));
2375 else if (core->parent)
2376 rate = core->parent->rate;
b2476490 2377 else
1c8e6004 2378 rate = 0;
d6968fca 2379 core->rate = core->req_rate = rate;
b2476490
MT
2380
2381 /*
0e8f6e49
MY
2382 * walk the list of orphan clocks and reparent any that newly finds a
2383 * parent.
b2476490 2384 */
b67bfe0d 2385 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2386 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2387
0e8f6e49
MY
2388 if (parent)
2389 clk_core_reparent(orphan, parent);
2390 }
b2476490
MT
2391
2392 /*
2393 * optional platform-specific magic
2394 *
2395 * The .init callback is not used by any of the basic clock types, but
2396 * exists for weird hardware that must perform initialization magic.
2397 * Please consider other ways of solving initialization problems before
24ee1a08 2398 * using this callback, as its use is discouraged.
b2476490 2399 */
d6968fca
SB
2400 if (core->ops->init)
2401 core->ops->init(core->hw);
b2476490 2402
32b9b109 2403 if (core->flags & CLK_IS_CRITICAL) {
ef56b79b
MR
2404 unsigned long flags;
2405
32b9b109 2406 clk_core_prepare(core);
ef56b79b
MR
2407
2408 flags = clk_enable_lock();
32b9b109 2409 clk_core_enable(core);
ef56b79b 2410 clk_enable_unlock(flags);
32b9b109
LJ
2411 }
2412
d6968fca 2413 kref_init(&core->ref);
b2476490 2414out:
eab89f69 2415 clk_prepare_unlock();
b2476490 2416
89f7e9de 2417 if (!ret)
d6968fca 2418 clk_debug_register(core);
89f7e9de 2419
d1302a36 2420 return ret;
b2476490
MT
2421}
2422
035a61c3
TV
2423struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2424 const char *con_id)
0197b3ea 2425{
0197b3ea
SK
2426 struct clk *clk;
2427
035a61c3 2428 /* This is to allow this function to be chained to others */
c1de1357 2429 if (IS_ERR_OR_NULL(hw))
035a61c3 2430 return (struct clk *) hw;
0197b3ea 2431
035a61c3
TV
2432 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2433 if (!clk)
2434 return ERR_PTR(-ENOMEM);
2435
2436 clk->core = hw->core;
2437 clk->dev_id = dev_id;
2438 clk->con_id = con_id;
1c8e6004
TV
2439 clk->max_rate = ULONG_MAX;
2440
2441 clk_prepare_lock();
50595f8b 2442 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2443 clk_prepare_unlock();
0197b3ea
SK
2444
2445 return clk;
2446}
035a61c3 2447
73e0e496 2448void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2449{
2450 clk_prepare_lock();
50595f8b 2451 hlist_del(&clk->clks_node);
1c8e6004
TV
2452 clk_prepare_unlock();
2453
2454 kfree(clk);
2455}
0197b3ea 2456
293ba3b4
SB
2457/**
2458 * clk_register - allocate a new clock, register it and return an opaque cookie
2459 * @dev: device that is registering this clock
2460 * @hw: link to hardware-specific clock data
2461 *
2462 * clk_register is the primary interface for populating the clock tree with new
2463 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2464 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2465 * rest of the clock API. In the event of an error clk_register will return an
2466 * error code; drivers must test for an error code after calling clk_register.
2467 */
2468struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2469{
d1302a36 2470 int i, ret;
d6968fca 2471 struct clk_core *core;
293ba3b4 2472
d6968fca
SB
2473 core = kzalloc(sizeof(*core), GFP_KERNEL);
2474 if (!core) {
293ba3b4
SB
2475 ret = -ENOMEM;
2476 goto fail_out;
2477 }
b2476490 2478
d6968fca
SB
2479 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2480 if (!core->name) {
0197b3ea
SK
2481 ret = -ENOMEM;
2482 goto fail_name;
2483 }
d6968fca 2484 core->ops = hw->init->ops;
ac2df527 2485 if (dev && dev->driver)
d6968fca
SB
2486 core->owner = dev->driver->owner;
2487 core->hw = hw;
2488 core->flags = hw->init->flags;
2489 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2490 core->min_rate = 0;
2491 core->max_rate = ULONG_MAX;
d6968fca 2492 hw->core = core;
b2476490 2493
d1302a36 2494 /* allocate local copy in case parent_names is __initdata */
d6968fca 2495 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2496 GFP_KERNEL);
d1302a36 2497
d6968fca 2498 if (!core->parent_names) {
d1302a36
MT
2499 ret = -ENOMEM;
2500 goto fail_parent_names;
2501 }
2502
2503
2504 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2505 for (i = 0; i < core->num_parents; i++) {
2506 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2507 GFP_KERNEL);
d6968fca 2508 if (!core->parent_names[i]) {
d1302a36
MT
2509 ret = -ENOMEM;
2510 goto fail_parent_names_copy;
2511 }
2512 }
2513
176d1169
MY
2514 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2515 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2516 GFP_KERNEL);
2517 if (!core->parents) {
2518 ret = -ENOMEM;
2519 goto fail_parents;
2520 };
2521
d6968fca 2522 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2523
035a61c3
TV
2524 hw->clk = __clk_create_clk(hw, NULL, NULL);
2525 if (IS_ERR(hw->clk)) {
035a61c3 2526 ret = PTR_ERR(hw->clk);
176d1169 2527 goto fail_parents;
035a61c3
TV
2528 }
2529
be45ebf2 2530 ret = __clk_core_init(core);
d1302a36 2531 if (!ret)
035a61c3 2532 return hw->clk;
b2476490 2533
1c8e6004 2534 __clk_free_clk(hw->clk);
035a61c3 2535 hw->clk = NULL;
b2476490 2536
176d1169
MY
2537fail_parents:
2538 kfree(core->parents);
d1302a36
MT
2539fail_parent_names_copy:
2540 while (--i >= 0)
d6968fca
SB
2541 kfree_const(core->parent_names[i]);
2542 kfree(core->parent_names);
d1302a36 2543fail_parent_names:
d6968fca 2544 kfree_const(core->name);
0197b3ea 2545fail_name:
d6968fca 2546 kfree(core);
d1302a36
MT
2547fail_out:
2548 return ERR_PTR(ret);
b2476490
MT
2549}
2550EXPORT_SYMBOL_GPL(clk_register);
2551
4143804c
SB
2552/**
2553 * clk_hw_register - register a clk_hw and return an error code
2554 * @dev: device that is registering this clock
2555 * @hw: link to hardware-specific clock data
2556 *
2557 * clk_hw_register is the primary interface for populating the clock tree with
2558 * new clock nodes. It returns an integer equal to zero indicating success or
2559 * less than zero indicating failure. Drivers must test for an error code after
2560 * calling clk_hw_register().
2561 */
2562int clk_hw_register(struct device *dev, struct clk_hw *hw)
2563{
2564 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
2565}
2566EXPORT_SYMBOL_GPL(clk_hw_register);
2567
6e5ab41b 2568/* Free memory allocated for a clock. */
fcb0ee6a
SN
2569static void __clk_release(struct kref *ref)
2570{
d6968fca
SB
2571 struct clk_core *core = container_of(ref, struct clk_core, ref);
2572 int i = core->num_parents;
fcb0ee6a 2573
496eadf8
KK
2574 lockdep_assert_held(&prepare_lock);
2575
d6968fca 2576 kfree(core->parents);
fcb0ee6a 2577 while (--i >= 0)
d6968fca 2578 kfree_const(core->parent_names[i]);
fcb0ee6a 2579
d6968fca
SB
2580 kfree(core->parent_names);
2581 kfree_const(core->name);
2582 kfree(core);
fcb0ee6a
SN
2583}
2584
2585/*
2586 * Empty clk_ops for unregistered clocks. These are used temporarily
2587 * after clk_unregister() was called on a clock and until last clock
2588 * consumer calls clk_put() and the struct clk object is freed.
2589 */
2590static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2591{
2592 return -ENXIO;
2593}
2594
2595static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2596{
2597 WARN_ON_ONCE(1);
2598}
2599
2600static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2601 unsigned long parent_rate)
2602{
2603 return -ENXIO;
2604}
2605
2606static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2607{
2608 return -ENXIO;
2609}
2610
2611static const struct clk_ops clk_nodrv_ops = {
2612 .enable = clk_nodrv_prepare_enable,
2613 .disable = clk_nodrv_disable_unprepare,
2614 .prepare = clk_nodrv_prepare_enable,
2615 .unprepare = clk_nodrv_disable_unprepare,
2616 .set_rate = clk_nodrv_set_rate,
2617 .set_parent = clk_nodrv_set_parent,
2618};
2619
1df5c939
MB
2620/**
2621 * clk_unregister - unregister a currently registered clock
2622 * @clk: clock to unregister
1df5c939 2623 */
fcb0ee6a
SN
2624void clk_unregister(struct clk *clk)
2625{
2626 unsigned long flags;
2627
6314b679
SB
2628 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2629 return;
2630
035a61c3 2631 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2632
2633 clk_prepare_lock();
2634
035a61c3
TV
2635 if (clk->core->ops == &clk_nodrv_ops) {
2636 pr_err("%s: unregistered clock: %s\n", __func__,
2637 clk->core->name);
4106a3d9 2638 goto unlock;
fcb0ee6a
SN
2639 }
2640 /*
2641 * Assign empty clock ops for consumers that might still hold
2642 * a reference to this clock.
2643 */
2644 flags = clk_enable_lock();
035a61c3 2645 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2646 clk_enable_unlock(flags);
2647
035a61c3
TV
2648 if (!hlist_empty(&clk->core->children)) {
2649 struct clk_core *child;
874f224c 2650 struct hlist_node *t;
fcb0ee6a
SN
2651
2652 /* Reparent all children to the orphan list. */
035a61c3
TV
2653 hlist_for_each_entry_safe(child, t, &clk->core->children,
2654 child_node)
2655 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2656 }
2657
035a61c3 2658 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2659
035a61c3 2660 if (clk->core->prepare_count)
fcb0ee6a 2661 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2662 __func__, clk->core->name);
2663 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2664unlock:
fcb0ee6a
SN
2665 clk_prepare_unlock();
2666}
1df5c939
MB
2667EXPORT_SYMBOL_GPL(clk_unregister);
2668
4143804c
SB
2669/**
2670 * clk_hw_unregister - unregister a currently registered clk_hw
2671 * @hw: hardware-specific clock data to unregister
2672 */
2673void clk_hw_unregister(struct clk_hw *hw)
2674{
2675 clk_unregister(hw->clk);
2676}
2677EXPORT_SYMBOL_GPL(clk_hw_unregister);
2678
46c8773a
SB
2679static void devm_clk_release(struct device *dev, void *res)
2680{
293ba3b4 2681 clk_unregister(*(struct clk **)res);
46c8773a
SB
2682}
2683
4143804c
SB
2684static void devm_clk_hw_release(struct device *dev, void *res)
2685{
2686 clk_hw_unregister(*(struct clk_hw **)res);
2687}
2688
46c8773a
SB
2689/**
2690 * devm_clk_register - resource managed clk_register()
2691 * @dev: device that is registering this clock
2692 * @hw: link to hardware-specific clock data
2693 *
2694 * Managed clk_register(). Clocks returned from this function are
2695 * automatically clk_unregister()ed on driver detach. See clk_register() for
2696 * more information.
2697 */
2698struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2699{
2700 struct clk *clk;
293ba3b4 2701 struct clk **clkp;
46c8773a 2702
293ba3b4
SB
2703 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2704 if (!clkp)
46c8773a
SB
2705 return ERR_PTR(-ENOMEM);
2706
293ba3b4
SB
2707 clk = clk_register(dev, hw);
2708 if (!IS_ERR(clk)) {
2709 *clkp = clk;
2710 devres_add(dev, clkp);
46c8773a 2711 } else {
293ba3b4 2712 devres_free(clkp);
46c8773a
SB
2713 }
2714
2715 return clk;
2716}
2717EXPORT_SYMBOL_GPL(devm_clk_register);
2718
4143804c
SB
2719/**
2720 * devm_clk_hw_register - resource managed clk_hw_register()
2721 * @dev: device that is registering this clock
2722 * @hw: link to hardware-specific clock data
2723 *
c47265ad 2724 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
2725 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
2726 * for more information.
2727 */
2728int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
2729{
2730 struct clk_hw **hwp;
2731 int ret;
2732
2733 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
2734 if (!hwp)
2735 return -ENOMEM;
2736
2737 ret = clk_hw_register(dev, hw);
2738 if (!ret) {
2739 *hwp = hw;
2740 devres_add(dev, hwp);
2741 } else {
2742 devres_free(hwp);
2743 }
2744
2745 return ret;
2746}
2747EXPORT_SYMBOL_GPL(devm_clk_hw_register);
2748
46c8773a
SB
2749static int devm_clk_match(struct device *dev, void *res, void *data)
2750{
2751 struct clk *c = res;
2752 if (WARN_ON(!c))
2753 return 0;
2754 return c == data;
2755}
2756
4143804c
SB
2757static int devm_clk_hw_match(struct device *dev, void *res, void *data)
2758{
2759 struct clk_hw *hw = res;
2760
2761 if (WARN_ON(!hw))
2762 return 0;
2763 return hw == data;
2764}
2765
46c8773a
SB
2766/**
2767 * devm_clk_unregister - resource managed clk_unregister()
2768 * @clk: clock to unregister
2769 *
2770 * Deallocate a clock allocated with devm_clk_register(). Normally
2771 * this function will not need to be called and the resource management
2772 * code will ensure that the resource is freed.
2773 */
2774void devm_clk_unregister(struct device *dev, struct clk *clk)
2775{
2776 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2777}
2778EXPORT_SYMBOL_GPL(devm_clk_unregister);
2779
4143804c
SB
2780/**
2781 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
2782 * @dev: device that is unregistering the hardware-specific clock data
2783 * @hw: link to hardware-specific clock data
2784 *
2785 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
2786 * this function will not need to be called and the resource management
2787 * code will ensure that the resource is freed.
2788 */
2789void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
2790{
2791 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
2792 hw));
2793}
2794EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
2795
ac2df527
SN
2796/*
2797 * clkdev helpers
2798 */
2799int __clk_get(struct clk *clk)
2800{
035a61c3
TV
2801 struct clk_core *core = !clk ? NULL : clk->core;
2802
2803 if (core) {
2804 if (!try_module_get(core->owner))
00efcb1c 2805 return 0;
ac2df527 2806
035a61c3 2807 kref_get(&core->ref);
00efcb1c 2808 }
ac2df527
SN
2809 return 1;
2810}
2811
2812void __clk_put(struct clk *clk)
2813{
10cdfe54
TV
2814 struct module *owner;
2815
00efcb1c 2816 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2817 return;
2818
fcb0ee6a 2819 clk_prepare_lock();
1c8e6004 2820
50595f8b 2821 hlist_del(&clk->clks_node);
ec02ace8
TV
2822 if (clk->min_rate > clk->core->req_rate ||
2823 clk->max_rate < clk->core->req_rate)
2824 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2825
1c8e6004
TV
2826 owner = clk->core->owner;
2827 kref_put(&clk->core->ref, __clk_release);
2828
fcb0ee6a
SN
2829 clk_prepare_unlock();
2830
10cdfe54 2831 module_put(owner);
035a61c3 2832
035a61c3 2833 kfree(clk);
ac2df527
SN
2834}
2835
b2476490
MT
2836/*** clk rate change notifiers ***/
2837
2838/**
2839 * clk_notifier_register - add a clk rate change notifier
2840 * @clk: struct clk * to watch
2841 * @nb: struct notifier_block * with callback info
2842 *
2843 * Request notification when clk's rate changes. This uses an SRCU
2844 * notifier because we want it to block and notifier unregistrations are
2845 * uncommon. The callbacks associated with the notifier must not
2846 * re-enter into the clk framework by calling any top-level clk APIs;
2847 * this will cause a nested prepare_lock mutex.
2848 *
198bb594
MY
2849 * In all notification cases (pre, post and abort rate change) the original
2850 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2851 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 2852 *
b2476490
MT
2853 * clk_notifier_register() must be called from non-atomic context.
2854 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2855 * allocation failure; otherwise, passes along the return value of
2856 * srcu_notifier_chain_register().
2857 */
2858int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2859{
2860 struct clk_notifier *cn;
2861 int ret = -ENOMEM;
2862
2863 if (!clk || !nb)
2864 return -EINVAL;
2865
eab89f69 2866 clk_prepare_lock();
b2476490
MT
2867
2868 /* search the list of notifiers for this clk */
2869 list_for_each_entry(cn, &clk_notifier_list, node)
2870 if (cn->clk == clk)
2871 break;
2872
2873 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2874 if (cn->clk != clk) {
2875 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2876 if (!cn)
2877 goto out;
2878
2879 cn->clk = clk;
2880 srcu_init_notifier_head(&cn->notifier_head);
2881
2882 list_add(&cn->node, &clk_notifier_list);
2883 }
2884
2885 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2886
035a61c3 2887 clk->core->notifier_count++;
b2476490
MT
2888
2889out:
eab89f69 2890 clk_prepare_unlock();
b2476490
MT
2891
2892 return ret;
2893}
2894EXPORT_SYMBOL_GPL(clk_notifier_register);
2895
2896/**
2897 * clk_notifier_unregister - remove a clk rate change notifier
2898 * @clk: struct clk *
2899 * @nb: struct notifier_block * with callback info
2900 *
2901 * Request no further notification for changes to 'clk' and frees memory
2902 * allocated in clk_notifier_register.
2903 *
2904 * Returns -EINVAL if called with null arguments; otherwise, passes
2905 * along the return value of srcu_notifier_chain_unregister().
2906 */
2907int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2908{
2909 struct clk_notifier *cn = NULL;
2910 int ret = -EINVAL;
2911
2912 if (!clk || !nb)
2913 return -EINVAL;
2914
eab89f69 2915 clk_prepare_lock();
b2476490
MT
2916
2917 list_for_each_entry(cn, &clk_notifier_list, node)
2918 if (cn->clk == clk)
2919 break;
2920
2921 if (cn->clk == clk) {
2922 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2923
035a61c3 2924 clk->core->notifier_count--;
b2476490
MT
2925
2926 /* XXX the notifier code should handle this better */
2927 if (!cn->notifier_head.head) {
2928 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2929 list_del(&cn->node);
b2476490
MT
2930 kfree(cn);
2931 }
2932
2933 } else {
2934 ret = -ENOENT;
2935 }
2936
eab89f69 2937 clk_prepare_unlock();
b2476490
MT
2938
2939 return ret;
2940}
2941EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2942
2943#ifdef CONFIG_OF
2944/**
2945 * struct of_clk_provider - Clock provider registration structure
2946 * @link: Entry in global list of clock providers
2947 * @node: Pointer to device tree node of clock provider
2948 * @get: Get clock callback. Returns NULL or a struct clk for the
2949 * given clock specifier
2950 * @data: context pointer to be passed into @get callback
2951 */
2952struct of_clk_provider {
2953 struct list_head link;
2954
2955 struct device_node *node;
2956 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 2957 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
2958 void *data;
2959};
2960
f2f6c255
PG
2961static const struct of_device_id __clk_of_table_sentinel
2962 __used __section(__clk_of_table_end);
2963
766e6a4e 2964static LIST_HEAD(of_clk_providers);
d6782c26
SN
2965static DEFINE_MUTEX(of_clk_mutex);
2966
766e6a4e
GL
2967struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2968 void *data)
2969{
2970 return data;
2971}
2972EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2973
0861e5b8
SB
2974struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
2975{
2976 return data;
2977}
2978EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
2979
494bfec9
SG
2980struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2981{
2982 struct clk_onecell_data *clk_data = data;
2983 unsigned int idx = clkspec->args[0];
2984
2985 if (idx >= clk_data->clk_num) {
7e96353c 2986 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
2987 return ERR_PTR(-EINVAL);
2988 }
2989
2990 return clk_data->clks[idx];
2991}
2992EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2993
0861e5b8
SB
2994struct clk_hw *
2995of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
2996{
2997 struct clk_hw_onecell_data *hw_data = data;
2998 unsigned int idx = clkspec->args[0];
2999
3000 if (idx >= hw_data->num) {
3001 pr_err("%s: invalid index %u\n", __func__, idx);
3002 return ERR_PTR(-EINVAL);
3003 }
3004
3005 return hw_data->hws[idx];
3006}
3007EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3008
766e6a4e
GL
3009/**
3010 * of_clk_add_provider() - Register a clock provider for a node
3011 * @np: Device node pointer associated with clock provider
3012 * @clk_src_get: callback for decoding clock
3013 * @data: context pointer for @clk_src_get callback.
3014 */
3015int of_clk_add_provider(struct device_node *np,
3016 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3017 void *data),
3018 void *data)
3019{
3020 struct of_clk_provider *cp;
86be408b 3021 int ret;
766e6a4e
GL
3022
3023 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
3024 if (!cp)
3025 return -ENOMEM;
3026
3027 cp->node = of_node_get(np);
3028 cp->data = data;
3029 cp->get = clk_src_get;
3030
d6782c26 3031 mutex_lock(&of_clk_mutex);
766e6a4e 3032 list_add(&cp->link, &of_clk_providers);
d6782c26 3033 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3034 pr_debug("Added clock from %s\n", np->full_name);
3035
86be408b
SN
3036 ret = of_clk_set_defaults(np, true);
3037 if (ret < 0)
3038 of_clk_del_provider(np);
3039
3040 return ret;
766e6a4e
GL
3041}
3042EXPORT_SYMBOL_GPL(of_clk_add_provider);
3043
0861e5b8
SB
3044/**
3045 * of_clk_add_hw_provider() - Register a clock provider for a node
3046 * @np: Device node pointer associated with clock provider
3047 * @get: callback for decoding clk_hw
3048 * @data: context pointer for @get callback.
3049 */
3050int of_clk_add_hw_provider(struct device_node *np,
3051 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3052 void *data),
3053 void *data)
3054{
3055 struct of_clk_provider *cp;
3056 int ret;
3057
3058 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3059 if (!cp)
3060 return -ENOMEM;
3061
3062 cp->node = of_node_get(np);
3063 cp->data = data;
3064 cp->get_hw = get;
3065
3066 mutex_lock(&of_clk_mutex);
3067 list_add(&cp->link, &of_clk_providers);
3068 mutex_unlock(&of_clk_mutex);
3069 pr_debug("Added clk_hw provider from %s\n", np->full_name);
3070
3071 ret = of_clk_set_defaults(np, true);
3072 if (ret < 0)
3073 of_clk_del_provider(np);
3074
3075 return ret;
3076}
3077EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3078
766e6a4e
GL
3079/**
3080 * of_clk_del_provider() - Remove a previously registered clock provider
3081 * @np: Device node pointer associated with clock provider
3082 */
3083void of_clk_del_provider(struct device_node *np)
3084{
3085 struct of_clk_provider *cp;
3086
d6782c26 3087 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3088 list_for_each_entry(cp, &of_clk_providers, link) {
3089 if (cp->node == np) {
3090 list_del(&cp->link);
3091 of_node_put(cp->node);
3092 kfree(cp);
3093 break;
3094 }
3095 }
d6782c26 3096 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3097}
3098EXPORT_SYMBOL_GPL(of_clk_del_provider);
3099
0861e5b8
SB
3100static struct clk_hw *
3101__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3102 struct of_phandle_args *clkspec)
3103{
3104 struct clk *clk;
3105 struct clk_hw *hw = ERR_PTR(-EPROBE_DEFER);
3106
3107 if (provider->get_hw) {
3108 hw = provider->get_hw(clkspec, provider->data);
3109 } else if (provider->get) {
3110 clk = provider->get(clkspec, provider->data);
3111 if (!IS_ERR(clk))
3112 hw = __clk_get_hw(clk);
3113 else
3114 hw = ERR_CAST(clk);
3115 }
3116
3117 return hw;
3118}
3119
73e0e496
SB
3120struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3121 const char *dev_id, const char *con_id)
766e6a4e
GL
3122{
3123 struct of_clk_provider *provider;
a34cd466 3124 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
0861e5b8 3125 struct clk_hw *hw = ERR_PTR(-EPROBE_DEFER);
766e6a4e 3126
306c342f
SB
3127 if (!clkspec)
3128 return ERR_PTR(-EINVAL);
3129
766e6a4e 3130 /* Check if we have such a provider in our array */
306c342f 3131 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3132 list_for_each_entry(provider, &of_clk_providers, link) {
3133 if (provider->node == clkspec->np)
0861e5b8
SB
3134 hw = __of_clk_get_hw_from_provider(provider, clkspec);
3135 if (!IS_ERR(hw)) {
3136 clk = __clk_create_clk(hw, dev_id, con_id);
73e0e496
SB
3137
3138 if (!IS_ERR(clk) && !__clk_get(clk)) {
3139 __clk_free_clk(clk);
3140 clk = ERR_PTR(-ENOENT);
3141 }
3142
766e6a4e 3143 break;
73e0e496 3144 }
766e6a4e 3145 }
306c342f 3146 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3147
3148 return clk;
3149}
3150
306c342f
SB
3151/**
3152 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3153 * @clkspec: pointer to a clock specifier data structure
3154 *
3155 * This function looks up a struct clk from the registered list of clock
3156 * providers, an input is a clock specifier data structure as returned
3157 * from the of_parse_phandle_with_args() function call.
3158 */
d6782c26
SN
3159struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3160{
306c342f 3161 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 3162}
fb4dd222 3163EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 3164
929e7f3b
SB
3165/**
3166 * of_clk_get_parent_count() - Count the number of clocks a device node has
3167 * @np: device node to count
3168 *
3169 * Returns: The number of clocks that are possible parents of this node
3170 */
3171unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 3172{
929e7f3b
SB
3173 int count;
3174
3175 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3176 if (count < 0)
3177 return 0;
3178
3179 return count;
f6102742
MT
3180}
3181EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3182
766e6a4e
GL
3183const char *of_clk_get_parent_name(struct device_node *np, int index)
3184{
3185 struct of_phandle_args clkspec;
7a0fc1a3 3186 struct property *prop;
766e6a4e 3187 const char *clk_name;
7a0fc1a3
BD
3188 const __be32 *vp;
3189 u32 pv;
766e6a4e 3190 int rc;
7a0fc1a3 3191 int count;
0a4807c2 3192 struct clk *clk;
766e6a4e 3193
766e6a4e
GL
3194 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3195 &clkspec);
3196 if (rc)
3197 return NULL;
3198
7a0fc1a3
BD
3199 index = clkspec.args_count ? clkspec.args[0] : 0;
3200 count = 0;
3201
3202 /* if there is an indices property, use it to transfer the index
3203 * specified into an array offset for the clock-output-names property.
3204 */
3205 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3206 if (index == pv) {
3207 index = count;
3208 break;
3209 }
3210 count++;
3211 }
8da411cc
MY
3212 /* We went off the end of 'clock-indices' without finding it */
3213 if (prop && !vp)
3214 return NULL;
7a0fc1a3 3215
766e6a4e 3216 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3217 index,
0a4807c2
SB
3218 &clk_name) < 0) {
3219 /*
3220 * Best effort to get the name if the clock has been
3221 * registered with the framework. If the clock isn't
3222 * registered, we return the node name as the name of
3223 * the clock as long as #clock-cells = 0.
3224 */
3225 clk = of_clk_get_from_provider(&clkspec);
3226 if (IS_ERR(clk)) {
3227 if (clkspec.args_count == 0)
3228 clk_name = clkspec.np->name;
3229 else
3230 clk_name = NULL;
3231 } else {
3232 clk_name = __clk_get_name(clk);
3233 clk_put(clk);
3234 }
3235 }
3236
766e6a4e
GL
3237
3238 of_node_put(clkspec.np);
3239 return clk_name;
3240}
3241EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3242
2e61dfb3
DN
3243/**
3244 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3245 * number of parents
3246 * @np: Device node pointer associated with clock provider
3247 * @parents: pointer to char array that hold the parents' names
3248 * @size: size of the @parents array
3249 *
3250 * Return: number of parents for the clock node.
3251 */
3252int of_clk_parent_fill(struct device_node *np, const char **parents,
3253 unsigned int size)
3254{
3255 unsigned int i = 0;
3256
3257 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3258 i++;
3259
3260 return i;
3261}
3262EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3263
1771b10d
GC
3264struct clock_provider {
3265 of_clk_init_cb_t clk_init_cb;
3266 struct device_node *np;
3267 struct list_head node;
3268};
3269
1771b10d
GC
3270/*
3271 * This function looks for a parent clock. If there is one, then it
3272 * checks that the provider for this parent clock was initialized, in
3273 * this case the parent clock will be ready.
3274 */
3275static int parent_ready(struct device_node *np)
3276{
3277 int i = 0;
3278
3279 while (true) {
3280 struct clk *clk = of_clk_get(np, i);
3281
3282 /* this parent is ready we can check the next one */
3283 if (!IS_ERR(clk)) {
3284 clk_put(clk);
3285 i++;
3286 continue;
3287 }
3288
3289 /* at least one parent is not ready, we exit now */
3290 if (PTR_ERR(clk) == -EPROBE_DEFER)
3291 return 0;
3292
3293 /*
3294 * Here we make assumption that the device tree is
3295 * written correctly. So an error means that there is
3296 * no more parent. As we didn't exit yet, then the
3297 * previous parent are ready. If there is no clock
3298 * parent, no need to wait for them, then we can
3299 * consider their absence as being ready
3300 */
3301 return 1;
3302 }
3303}
3304
d56f8994
LJ
3305/**
3306 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
3307 * @np: Device node pointer associated with clock provider
3308 * @index: clock index
3309 * @flags: pointer to clk_core->flags
3310 *
3311 * Detects if the clock-critical property exists and, if so, sets the
3312 * corresponding CLK_IS_CRITICAL flag.
3313 *
3314 * Do not use this function. It exists only for legacy Device Tree
3315 * bindings, such as the one-clock-per-node style that are outdated.
3316 * Those bindings typically put all clock data into .dts and the Linux
3317 * driver has no clock data, thus making it impossible to set this flag
3318 * correctly from the driver. Only those drivers may call
3319 * of_clk_detect_critical from their setup functions.
3320 *
3321 * Return: error code or zero on success
3322 */
3323int of_clk_detect_critical(struct device_node *np,
3324 int index, unsigned long *flags)
3325{
3326 struct property *prop;
3327 const __be32 *cur;
3328 uint32_t idx;
3329
3330 if (!np || !flags)
3331 return -EINVAL;
3332
3333 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
3334 if (index == idx)
3335 *flags |= CLK_IS_CRITICAL;
3336
3337 return 0;
3338}
3339
766e6a4e
GL
3340/**
3341 * of_clk_init() - Scan and init clock providers from the DT
3342 * @matches: array of compatible values and init functions for providers.
3343 *
1771b10d 3344 * This function scans the device tree for matching clock providers
e5ca8fb4 3345 * and calls their initialization functions. It also does it by trying
1771b10d 3346 * to follow the dependencies.
766e6a4e
GL
3347 */
3348void __init of_clk_init(const struct of_device_id *matches)
3349{
7f7ed584 3350 const struct of_device_id *match;
766e6a4e 3351 struct device_node *np;
1771b10d
GC
3352 struct clock_provider *clk_provider, *next;
3353 bool is_init_done;
3354 bool force = false;
2573a02a 3355 LIST_HEAD(clk_provider_list);
766e6a4e 3356
f2f6c255 3357 if (!matches)
819b4861 3358 matches = &__clk_of_table;
f2f6c255 3359
1771b10d 3360 /* First prepare the list of the clocks providers */
7f7ed584 3361 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3362 struct clock_provider *parent;
3363
3e5dd6f6
GU
3364 if (!of_device_is_available(np))
3365 continue;
3366
2e3b19f1
SB
3367 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3368 if (!parent) {
3369 list_for_each_entry_safe(clk_provider, next,
3370 &clk_provider_list, node) {
3371 list_del(&clk_provider->node);
6bc9d9d6 3372 of_node_put(clk_provider->np);
2e3b19f1
SB
3373 kfree(clk_provider);
3374 }
6bc9d9d6 3375 of_node_put(np);
2e3b19f1
SB
3376 return;
3377 }
1771b10d
GC
3378
3379 parent->clk_init_cb = match->data;
6bc9d9d6 3380 parent->np = of_node_get(np);
3f6d439f 3381 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3382 }
3383
3384 while (!list_empty(&clk_provider_list)) {
3385 is_init_done = false;
3386 list_for_each_entry_safe(clk_provider, next,
3387 &clk_provider_list, node) {
3388 if (force || parent_ready(clk_provider->np)) {
86be408b 3389
1771b10d 3390 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3391 of_clk_set_defaults(clk_provider->np, true);
3392
1771b10d 3393 list_del(&clk_provider->node);
6bc9d9d6 3394 of_node_put(clk_provider->np);
1771b10d
GC
3395 kfree(clk_provider);
3396 is_init_done = true;
3397 }
3398 }
3399
3400 /*
e5ca8fb4 3401 * We didn't manage to initialize any of the
1771b10d
GC
3402 * remaining providers during the last loop, so now we
3403 * initialize all the remaining ones unconditionally
3404 * in case the clock parent was not mandatory
3405 */
3406 if (!is_init_done)
3407 force = true;
766e6a4e
GL
3408 }
3409}
3410#endif