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clk: vc5: Configure the output buffer input mux on prepare
[linux-2.6-block.git] / drivers / clk / clk-versaclock5.c
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3e1aec4e
MV		 1/*
2 * Driver for IDT Versaclock 5
3 *
4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * Possible optimizations:
19 * - Use spread spectrum
20 * - Use integer divider in FOD if applicable
21 */
22
23#include <linux/clk.h>
24#include <linux/clk-provider.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/interrupt.h>
28#include <linux/mod_devicetable.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_platform.h>
32#include <linux/rational.h>
33#include <linux/regmap.h>
34#include <linux/slab.h>
35
36/* VersaClock5 registers */
37#define VC5_OTP_CONTROL 0x00
38
39/* Factory-reserved register block */
40#define VC5_RSVD_DEVICE_ID 0x01
41#define VC5_RSVD_ADC_GAIN_7_0 0x02
42#define VC5_RSVD_ADC_GAIN_15_8 0x03
43#define VC5_RSVD_ADC_OFFSET_7_0 0x04
44#define VC5_RSVD_ADC_OFFSET_15_8 0x05
45#define VC5_RSVD_TEMPY 0x06
46#define VC5_RSVD_OFFSET_TBIN 0x07
47#define VC5_RSVD_GAIN 0x08
48#define VC5_RSVD_TEST_NP 0x09
49#define VC5_RSVD_UNUSED 0x0a
50#define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
51#define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
52#define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
53#define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
54#define VC5_RSVD_CLK_AMP_123 0x0f
55
56/* Configuration register block */
57#define VC5_PRIM_SRC_SHDN 0x10
58#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
59#define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
60#define VC5_PRIM_SRC_SHDN_SP BIT(1)
61#define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
62
63#define VC5_VCO_BAND 0x11
64#define VC5_XTAL_X1_LOAD_CAP 0x12
65#define VC5_XTAL_X2_LOAD_CAP 0x13
66#define VC5_REF_DIVIDER 0x15
67#define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
68#define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
69
70#define VC5_VCO_CTRL_AND_PREDIV 0x16
71#define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
72
73#define VC5_FEEDBACK_INT_DIV 0x17
74#define VC5_FEEDBACK_INT_DIV_BITS 0x18
75#define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
76#define VC5_RC_CONTROL0 0x1e
77#define VC5_RC_CONTROL1 0x1f
78/* Register 0x20 is factory reserved */
79
80/* Output divider control for divider 1,2,3,4 */
81#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
82#define VC5_OUT_DIV_CONTROL_RESET BIT(7)
83#define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
84#define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
85#define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
86#define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
87
88#define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
89#define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
90
91#define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
92#define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
93#define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
94#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
95#define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
96/* Registers 0x30, 0x40, 0x50 are factory reserved */
97
98/* Clock control register for clock 1,2 */
99#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
100#define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
101
102#define VC5_CLK_OE_SHDN 0x68
103#define VC5_CLK_OS_SHDN 0x69
104
105#define VC5_GLOBAL_REGISTER 0x76
106#define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
107
108/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
109#define VC5_PLL_VCO_MIN 2500000000UL
110#define VC5_PLL_VCO_MAX 3000000000UL
111
112/* VC5 Input mux settings */
113#define VC5_MUX_IN_XIN BIT(0)
114#define VC5_MUX_IN_CLKIN BIT(1)
115
9adddb01 116/* Maximum number of clk_out supported by this driver */
1193e14f 117#define VC5_MAX_CLK_OUT_NUM 5
9adddb01
AF		 118
119/* Maximum number of FODs supported by this driver */
1193e14f 120#define VC5_MAX_FOD_NUM 4
9adddb01
AF		 121
122/* flags to describe chip features */
123/* chip has built-in oscilator */
124#define VC5_HAS_INTERNAL_XTAL BIT(0)
125
3e1aec4e
MV		 126/* Supported IDT VC5 models. */
127enum vc5_model {
128 IDT_VC5_5P49V5923,
129 IDT_VC5_5P49V5933,
1193e14f 130 IDT_VC5_5P49V5935,
3e1aec4e
MV		 131};
132
9adddb01
AF		 133/* Structure to describe features of a particular VC5 model */
134struct vc5_chip_info {
135 const enum vc5_model model;
136 const unsigned int clk_fod_cnt;
137 const unsigned int clk_out_cnt;
138 const u32 flags;
139};
140
3e1aec4e
MV		 141struct vc5_driver_data;
142
143struct vc5_hw_data {
144 struct clk_hw hw;
145 struct vc5_driver_data *vc5;
146 u32 div_int;
147 u32 div_frc;
148 unsigned int num;
149};
150
151struct vc5_driver_data {
152 struct i2c_client *client;
153 struct regmap *regmap;
9adddb01 154 const struct vc5_chip_info *chip_info;
3e1aec4e
MV		 155
156 struct clk *pin_xin;
157 struct clk *pin_clkin;
158 unsigned char clk_mux_ins;
159 struct clk_hw clk_mux;
160 struct vc5_hw_data clk_pll;
9adddb01
AF		 161 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
162 struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
3e1aec4e
MV		 163};
164
165static const char * const vc5_mux_names[] = {
166 "mux"
167};
168
169static const char * const vc5_pll_names[] = {
170 "pll"
171};
172
173static const char * const vc5_fod_names[] = {
174 "fod0", "fod1", "fod2", "fod3",
175};
176
177static const char * const vc5_clk_out_names[] = {
178 "out0_sel_i2cb", "out1", "out2", "out3", "out4",
179};
180
181/*
182 * VersaClock5 i2c regmap
183 */
184static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
185{
186 /* Factory reserved regs, make them read-only */
187 if (reg <= 0xf)
188 return false;
189
190 /* Factory reserved regs, make them read-only */
191 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
192 return false;
193
194 return true;
195}
196
197static const struct regmap_config vc5_regmap_config = {
198 .reg_bits = 8,
199 .val_bits = 8,
200 .cache_type = REGCACHE_RBTREE,
201 .max_register = 0x76,
202 .writeable_reg = vc5_regmap_is_writeable,
203};
204
205/*
206 * VersaClock5 input multiplexer between XTAL and CLKIN divider
207 */
208static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
209{
210 struct vc5_driver_data *vc5 =
211 container_of(hw, struct vc5_driver_data, clk_mux);
212 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
213 unsigned int src;
214
215 regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
216 src &= mask;
217
218 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
219 return 0;
220
221 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
222 return 1;
223
224 dev_warn(&vc5->client->dev,
225 "Invalid clock input configuration (%02x)\n", src);
226 return 0;
227}
228
229static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
230{
231 struct vc5_driver_data *vc5 =
232 container_of(hw, struct vc5_driver_data, clk_mux);
233 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
234 u8 src;
235
236 if ((index > 1) || !vc5->clk_mux_ins)
237 return -EINVAL;
238
239 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
240 if (index == 0)
241 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
242 if (index == 1)
243 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
244 } else {
245 if (index != 0)
246 return -EINVAL;
247
248 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
249 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
250 if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
251 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
252 }
253
254 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
255}
256
257static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw,
258 unsigned long parent_rate)
259{
260 struct vc5_driver_data *vc5 =
261 container_of(hw, struct vc5_driver_data, clk_mux);
262 unsigned int prediv, div;
263
264 regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
265
266 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
267 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
268 return parent_rate;
269
270 regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
271
272 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
273 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
274 return parent_rate / 2;
275 else
276 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
277}
278
279static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate,
280 unsigned long *parent_rate)
281{
282 unsigned long idiv;
283
284 /* PLL cannot operate with input clock above 50 MHz. */
285 if (rate > 50000000)
286 return -EINVAL;
287
288 /* CLKIN within range of PLL input, feed directly to PLL. */
289 if (*parent_rate <= 50000000)
290 return *parent_rate;
291
292 idiv = DIV_ROUND_UP(*parent_rate, rate);
293 if (idiv > 127)
294 return -EINVAL;
295
296 return *parent_rate / idiv;
297}
298
299static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate,
300 unsigned long parent_rate)
301{
302 struct vc5_driver_data *vc5 =
303 container_of(hw, struct vc5_driver_data, clk_mux);
304 unsigned long idiv;
305 u8 div;
306
307 /* CLKIN within range of PLL input, feed directly to PLL. */
308 if (parent_rate <= 50000000) {
309 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
310 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
311 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
312 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
313 return 0;
314 }
315
316 idiv = DIV_ROUND_UP(parent_rate, rate);
317
318 /* We have dedicated div-2 predivider. */
319 if (idiv == 2)
320 div = VC5_REF_DIVIDER_SEL_PREDIV2;
321 else
322 div = VC5_REF_DIVIDER_REF_DIV(idiv);
323
324 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
325 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
326 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
327
328 return 0;
329}
330
331static const struct clk_ops vc5_mux_ops = {
332 .set_parent = vc5_mux_set_parent,
333 .get_parent = vc5_mux_get_parent,
334 .recalc_rate = vc5_mux_recalc_rate,
335 .round_rate = vc5_mux_round_rate,
336 .set_rate = vc5_mux_set_rate,
337};
338
339/*
340 * VersaClock5 PLL/VCO
341 */
342static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
343 unsigned long parent_rate)
344{
345 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
346 struct vc5_driver_data *vc5 = hwdata->vc5;
347 u32 div_int, div_frc;
348 u8 fb[5];
349
350 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
351
352 div_int = (fb[0] << 4) | (fb[1] >> 4);
353 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
354
355 /* The PLL divider has 12 integer bits and 24 fractional bits */
356 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
357}
358
359static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
360 unsigned long *parent_rate)
361{
362 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
363 u32 div_int;
364 u64 div_frc;
365
366 if (rate < VC5_PLL_VCO_MIN)
367 rate = VC5_PLL_VCO_MIN;
368 if (rate > VC5_PLL_VCO_MAX)
369 rate = VC5_PLL_VCO_MAX;
370
371 /* Determine integer part, which is 12 bit wide */
372 div_int = rate / *parent_rate;
373 if (div_int > 0xfff)
374 rate = *parent_rate * 0xfff;
375
376 /* Determine best fractional part, which is 24 bit wide */
377 div_frc = rate % *parent_rate;
378 div_frc *= BIT(24) - 1;
379 do_div(div_frc, *parent_rate);
380
381 hwdata->div_int = div_int;
382 hwdata->div_frc = (u32)div_frc;
383
384 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
385}
386
387static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
388 unsigned long parent_rate)
389{
390 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
391 struct vc5_driver_data *vc5 = hwdata->vc5;
392 u8 fb[5];
393
394 fb[0] = hwdata->div_int >> 4;
395 fb[1] = hwdata->div_int << 4;
396 fb[2] = hwdata->div_frc >> 16;
397 fb[3] = hwdata->div_frc >> 8;
398 fb[4] = hwdata->div_frc;
399
400 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
401}
402
403static const struct clk_ops vc5_pll_ops = {
404 .recalc_rate = vc5_pll_recalc_rate,
405 .round_rate = vc5_pll_round_rate,
406 .set_rate = vc5_pll_set_rate,
407};
408
409static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
410 unsigned long parent_rate)
411{
412 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
413 struct vc5_driver_data *vc5 = hwdata->vc5;
414 /* VCO frequency is divided by two before entering FOD */
415 u32 f_in = parent_rate / 2;
416 u32 div_int, div_frc;
417 u8 od_int[2];
418 u8 od_frc[4];
419
420 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
421 od_int, 2);
422 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
423 od_frc, 4);
424
425 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
426 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
427 (od_frc[2] << 6) | (od_frc[3] >> 2);
428
3bded569
MV		 429 /* Avoid division by zero if the output is not configured. */
430 if (div_int == 0 && div_frc == 0)
431 return 0;
432
3e1aec4e
MV		 433 /* The PLL divider has 12 integer bits and 30 fractional bits */
434 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
435}
436
437static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
438 unsigned long *parent_rate)
439{
440 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
441 /* VCO frequency is divided by two before entering FOD */
442 u32 f_in = *parent_rate / 2;
443 u32 div_int;
444 u64 div_frc;
445
446 /* Determine integer part, which is 12 bit wide */
447 div_int = f_in / rate;
448 /*
449 * WARNING: The clock chip does not output signal if the integer part
450 * of the divider is 0xfff and fractional part is non-zero.
451 * Clamp the divider at 0xffe to keep the code simple.
452 */
453 if (div_int > 0xffe) {
454 div_int = 0xffe;
455 rate = f_in / div_int;
456 }
457
458 /* Determine best fractional part, which is 30 bit wide */
459 div_frc = f_in % rate;
460 div_frc <<= 24;
461 do_div(div_frc, rate);
462
463 hwdata->div_int = div_int;
464 hwdata->div_frc = (u32)div_frc;
465
466 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
467}
468
469static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
470 unsigned long parent_rate)
471{
472 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
473 struct vc5_driver_data *vc5 = hwdata->vc5;
474 u8 data[14] = {
475 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
476 hwdata->div_frc >> 6, hwdata->div_frc << 2,
477 0, 0, 0, 0, 0,
478 0, 0,
479 hwdata->div_int >> 4, hwdata->div_int << 4,
480 0
481 };
482
483 regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
484 data, 14);
485
486 /*
487 * Toggle magic bit in undocumented register for unknown reason.
488 * This is what the IDT timing commander tool does and the chip
489 * datasheet somewhat implies this is needed, but the register
490 * and the bit is not documented.
491 */
492 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
493 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
494 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
495 VC5_GLOBAL_REGISTER_GLOBAL_RESET,
496 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
497 return 0;
498}
499
500static const struct clk_ops vc5_fod_ops = {
501 .recalc_rate = vc5_fod_recalc_rate,
502 .round_rate = vc5_fod_round_rate,
503 .set_rate = vc5_fod_set_rate,
504};
505
506static int vc5_clk_out_prepare(struct clk_hw *hw)
507{
508 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
509 struct vc5_driver_data *vc5 = hwdata->vc5;
718f4694
MV		 510 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
511 VC5_OUT_DIV_CONTROL_SEL_EXT |
512 VC5_OUT_DIV_CONTROL_EN_FOD;
513 unsigned int src;
514 int ret;
515
516 /*
517 * If the input mux is disabled, enable it first and
518 * select source from matching FOD.
519 */
520 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
521 if ((src & mask) == 0) {
522 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
523 ret = regmap_update_bits(vc5->regmap,
524 VC5_OUT_DIV_CONTROL(hwdata->num),
525 mask | VC5_OUT_DIV_CONTROL_RESET, src);
526 if (ret)
527 return ret;
528 }
3e1aec4e
MV		 529
530 /* Enable the clock buffer */
531 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
532 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
533 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
534 return 0;
535}
536
537static void vc5_clk_out_unprepare(struct clk_hw *hw)
538{
539 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
540 struct vc5_driver_data *vc5 = hwdata->vc5;
541
a4decf58 542 /* Disable the clock buffer */
3e1aec4e
MV		 543 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
544 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
545}
546
547static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
548{
549 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
550 struct vc5_driver_data *vc5 = hwdata->vc5;
551 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
552 VC5_OUT_DIV_CONTROL_SEL_EXT |
553 VC5_OUT_DIV_CONTROL_EN_FOD;
554 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
555 VC5_OUT_DIV_CONTROL_EN_FOD;
556 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
557 VC5_OUT_DIV_CONTROL_SEL_EXT;
558 unsigned int src;
559
560 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
561 src &= mask;
562
325b7b90
MV		 563 if (src == 0) /* Input mux set to DISABLED */
564 return 0;
565
3e1aec4e
MV		 566 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
567 return 0;
568
569 if (src == extclk)
570 return 1;
571
572 dev_warn(&vc5->client->dev,
573 "Invalid clock output configuration (%02x)\n", src);
574 return 0;
575}
576
577static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
578{
579 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
580 struct vc5_driver_data *vc5 = hwdata->vc5;
581 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
582 VC5_OUT_DIV_CONTROL_SELB_NORM |
583 VC5_OUT_DIV_CONTROL_SEL_EXT |
584 VC5_OUT_DIV_CONTROL_EN_FOD;
585 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
586 VC5_OUT_DIV_CONTROL_SEL_EXT;
587 u8 src = VC5_OUT_DIV_CONTROL_RESET;
588
589 if (index == 0)
590 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
591 else
592 src |= extclk;
593
594 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
595 mask, src);
596}
597
598static const struct clk_ops vc5_clk_out_ops = {
599 .prepare = vc5_clk_out_prepare,
600 .unprepare = vc5_clk_out_unprepare,
601 .set_parent = vc5_clk_out_set_parent,
602 .get_parent = vc5_clk_out_get_parent,
603};
604
605static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
606 void *data)
607{
608 struct vc5_driver_data *vc5 = data;
609 unsigned int idx = clkspec->args[0];
610
9adddb01 611 if (idx >= vc5->chip_info->clk_out_cnt)
3e1aec4e
MV		 612 return ERR_PTR(-EINVAL);
613
614 return &vc5->clk_out[idx].hw;
615}
616
617static int vc5_map_index_to_output(const enum vc5_model model,
618 const unsigned int n)
619{
620 switch (model) {
621 case IDT_VC5_5P49V5933:
622 return (n == 0) ? 0 : 3;
623 case IDT_VC5_5P49V5923:
1193e14f 624 case IDT_VC5_5P49V5935:
3e1aec4e
MV		 625 default:
626 return n;
627 }
628}
629
630static const struct of_device_id clk_vc5_of_match[];
631
632static int vc5_probe(struct i2c_client *client,
633 const struct i2c_device_id *id)
634{
3e1aec4e
MV		 635 struct vc5_driver_data *vc5;
636 struct clk_init_data init;
637 const char *parent_names[2];
9adddb01 638 unsigned int n, idx = 0;
3e1aec4e
MV		 639 int ret;
640
641 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
642 if (vc5 == NULL)
643 return -ENOMEM;
644
645 i2c_set_clientdata(client, vc5);
646 vc5->client = client;
9adddb01 647 vc5->chip_info = of_device_get_match_data(&client->dev);
3e1aec4e
MV		 648
649 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
650 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
651 return -EPROBE_DEFER;
652
653 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
654 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
655 return -EPROBE_DEFER;
656
657 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
658 if (IS_ERR(vc5->regmap)) {
659 dev_err(&client->dev, "failed to allocate register map\n");
660 return PTR_ERR(vc5->regmap);
661 }
662
663 /* Register clock input mux */
664 memset(&init, 0, sizeof(init));
665
666 if (!IS_ERR(vc5->pin_xin)) {
667 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
668 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
9adddb01 669 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
3e1aec4e
MV		 670 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
671 "internal-xtal", NULL,
672 0, 25000000);
673 if (IS_ERR(vc5->pin_xin))
674 return PTR_ERR(vc5->pin_xin);
675 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
676 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
677 }
678
679 if (!IS_ERR(vc5->pin_clkin)) {
680 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
681 parent_names[init.num_parents++] =
682 __clk_get_name(vc5->pin_clkin);
683 }
684
685 if (!init.num_parents) {
686 dev_err(&client->dev, "no input clock specified!\n");
687 return -EINVAL;
688 }
689
690 init.name = vc5_mux_names[0];
691 init.ops = &vc5_mux_ops;
692 init.flags = 0;
693 init.parent_names = parent_names;
694 vc5->clk_mux.init = &init;
695 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
696 if (ret) {
697 dev_err(&client->dev, "unable to register %s\n", init.name);
698 goto err_clk;
699 }
700
701 /* Register PLL */
702 memset(&init, 0, sizeof(init));
703 init.name = vc5_pll_names[0];
704 init.ops = &vc5_pll_ops;
705 init.flags = CLK_SET_RATE_PARENT;
706 init.parent_names = vc5_mux_names;
707 init.num_parents = 1;
708 vc5->clk_pll.num = 0;
709 vc5->clk_pll.vc5 = vc5;
710 vc5->clk_pll.hw.init = &init;
711 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
712 if (ret) {
713 dev_err(&client->dev, "unable to register %s\n", init.name);
714 goto err_clk;
715 }
716
717 /* Register FODs */
9adddb01
AF		 718 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
719 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
3e1aec4e
MV		 720 memset(&init, 0, sizeof(init));
721 init.name = vc5_fod_names[idx];
722 init.ops = &vc5_fod_ops;
723 init.flags = CLK_SET_RATE_PARENT;
724 init.parent_names = vc5_pll_names;
725 init.num_parents = 1;
726 vc5->clk_fod[n].num = idx;
727 vc5->clk_fod[n].vc5 = vc5;
728 vc5->clk_fod[n].hw.init = &init;
729 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
730 if (ret) {
731 dev_err(&client->dev, "unable to register %s\n",
732 init.name);
733 goto err_clk;
734 }
735 }
736
737 /* Register MUX-connected OUT0_I2C_SELB output */
738 memset(&init, 0, sizeof(init));
739 init.name = vc5_clk_out_names[0];
740 init.ops = &vc5_clk_out_ops;
741 init.flags = CLK_SET_RATE_PARENT;
742 init.parent_names = vc5_mux_names;
743 init.num_parents = 1;
744 vc5->clk_out[0].num = idx;
745 vc5->clk_out[0].vc5 = vc5;
746 vc5->clk_out[0].hw.init = &init;
747 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
748 if (ret) {
749 dev_err(&client->dev, "unable to register %s\n",
750 init.name);
751 goto err_clk;
752 }
753
754 /* Register FOD-connected OUTx outputs */
9adddb01
AF		 755 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
756 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
3e1aec4e
MV		 757 parent_names[0] = vc5_fod_names[idx];
758 if (n == 1)
759 parent_names[1] = vc5_mux_names[0];
760 else
761 parent_names[1] = vc5_clk_out_names[n - 1];
762
763 memset(&init, 0, sizeof(init));
764 init.name = vc5_clk_out_names[idx + 1];
765 init.ops = &vc5_clk_out_ops;
766 init.flags = CLK_SET_RATE_PARENT;
767 init.parent_names = parent_names;
768 init.num_parents = 2;
769 vc5->clk_out[n].num = idx;
770 vc5->clk_out[n].vc5 = vc5;
771 vc5->clk_out[n].hw.init = &init;
772 ret = devm_clk_hw_register(&client->dev,
773 &vc5->clk_out[n].hw);
774 if (ret) {
775 dev_err(&client->dev, "unable to register %s\n",
776 init.name);
777 goto err_clk;
778 }
779 }
780
781 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
782 if (ret) {
783 dev_err(&client->dev, "unable to add clk provider\n");
784 goto err_clk;
785 }
786
787 return 0;
788
789err_clk:
9adddb01 790 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
3e1aec4e
MV		 791 clk_unregister_fixed_rate(vc5->pin_xin);
792 return ret;
793}
794
795static int vc5_remove(struct i2c_client *client)
796{
797 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
798
799 of_clk_del_provider(client->dev.of_node);
800
9adddb01 801 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
3e1aec4e
MV		 802 clk_unregister_fixed_rate(vc5->pin_xin);
803
804 return 0;
805}
806
9adddb01
AF		 807static const struct vc5_chip_info idt_5p49v5923_info = {
808 .model = IDT_VC5_5P49V5923,
809 .clk_fod_cnt = 2,
810 .clk_out_cnt = 3,
811 .flags = 0,
812};
813
814static const struct vc5_chip_info idt_5p49v5933_info = {
815 .model = IDT_VC5_5P49V5933,
816 .clk_fod_cnt = 2,
817 .clk_out_cnt = 3,
818 .flags = VC5_HAS_INTERNAL_XTAL,
819};
820
1193e14f
AF		 821static const struct vc5_chip_info idt_5p49v5935_info = {
822 .model = IDT_VC5_5P49V5935,
823 .clk_fod_cnt = 4,
824 .clk_out_cnt = 5,
825 .flags = VC5_HAS_INTERNAL_XTAL,
826};
827
3e1aec4e
MV		 828static const struct i2c_device_id vc5_id[] = {
829 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
830 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
1193e14f 831 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
3e1aec4e
MV		 832 { }
833};
834MODULE_DEVICE_TABLE(i2c, vc5_id);
835
836static const struct of_device_id clk_vc5_of_match[] = {
9adddb01
AF		 837 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
838 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1193e14f 839 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
3e1aec4e
MV		 840 { },
841};
842MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
843
844static struct i2c_driver vc5_driver = {
845 .driver = {
846 .name = "vc5",
847 .of_match_table = clk_vc5_of_match,
848 },
849 .probe = vc5_probe,
850 .remove = vc5_remove,
851 .id_table = vc5_id,
852};
853module_i2c_driver(vc5_driver);
854
855MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
856MODULE_DESCRIPTION("IDT VersaClock 5 driver");
857MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)