projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'xfs-6.2-merge-8' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
[linux-block.git] / drivers / clk / clk-versaclock5.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
3e1aec4e
MV		 2/*
3 * Driver for IDT Versaclock 5
4 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
3e1aec4e
MV		 6 */
7
8/*
9 * Possible optimizations:
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/mod_devicetable.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
3e1aec4e
MV		 23#include <linux/regmap.h>
24#include <linux/slab.h>
25
ba6165bc 26#include <dt-bindings/clock/versaclock.h>
260249f9 27
3e1aec4e
MV		 28/* VersaClock5 registers */
29#define VC5_OTP_CONTROL 0x00
30
31/* Factory-reserved register block */
32#define VC5_RSVD_DEVICE_ID 0x01
33#define VC5_RSVD_ADC_GAIN_7_0 0x02
34#define VC5_RSVD_ADC_GAIN_15_8 0x03
35#define VC5_RSVD_ADC_OFFSET_7_0 0x04
36#define VC5_RSVD_ADC_OFFSET_15_8 0x05
37#define VC5_RSVD_TEMPY 0x06
38#define VC5_RSVD_OFFSET_TBIN 0x07
39#define VC5_RSVD_GAIN 0x08
40#define VC5_RSVD_TEST_NP 0x09
41#define VC5_RSVD_UNUSED 0x0a
42#define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
43#define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
44#define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
45#define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
46#define VC5_RSVD_CLK_AMP_123 0x0f
47
48/* Configuration register block */
49#define VC5_PRIM_SRC_SHDN 0x10
50#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
51#define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
8c1ebe97 52#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
3e1aec4e
MV		 53#define VC5_PRIM_SRC_SHDN_SP BIT(1)
54#define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
55
56#define VC5_VCO_BAND 0x11
57#define VC5_XTAL_X1_LOAD_CAP 0x12
58#define VC5_XTAL_X2_LOAD_CAP 0x13
59#define VC5_REF_DIVIDER 0x15
60#define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
61#define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
62
63#define VC5_VCO_CTRL_AND_PREDIV 0x16
64#define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
65
66#define VC5_FEEDBACK_INT_DIV 0x17
67#define VC5_FEEDBACK_INT_DIV_BITS 0x18
68#define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
69#define VC5_RC_CONTROL0 0x1e
70#define VC5_RC_CONTROL1 0x1f
fc336ae6
LC		 71
72/* These registers are named "Unused Factory Reserved Registers" */
73#define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
74#define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
3e1aec4e
MV		 75
76/* Output divider control for divider 1,2,3,4 */
77#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
78#define VC5_OUT_DIV_CONTROL_RESET BIT(7)
79#define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
80#define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
81#define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
82#define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
83
84#define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
85#define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
86
87#define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
88#define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
89#define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
90#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
91#define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
3e1aec4e
MV		 92
93/* Clock control register for clock 1,2 */
94#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
260249f9
AF		 95#define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
96#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
97
98#define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
99#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
100#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
101#define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
102#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
103#define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
104#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
105
106#define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
107#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
108#define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
109#define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
110#define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
111#define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
112#define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
113#define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
114#define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
115#define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
116#define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
3e1aec4e
MV		 117#define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
118
119#define VC5_CLK_OE_SHDN 0x68
120#define VC5_CLK_OS_SHDN 0x69
121
122#define VC5_GLOBAL_REGISTER 0x76
123#define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
124
125/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
126#define VC5_PLL_VCO_MIN 2500000000UL
127#define VC5_PLL_VCO_MAX 3000000000UL
128
129/* VC5 Input mux settings */
130#define VC5_MUX_IN_XIN BIT(0)
131#define VC5_MUX_IN_CLKIN BIT(1)
132
9adddb01 133/* Maximum number of clk_out supported by this driver */
1193e14f 134#define VC5_MAX_CLK_OUT_NUM 5
9adddb01
AF		 135
136/* Maximum number of FODs supported by this driver */
1193e14f 137#define VC5_MAX_FOD_NUM 4
9adddb01
AF		 138
139/* flags to describe chip features */
140/* chip has built-in oscilator */
141#define VC5_HAS_INTERNAL_XTAL BIT(0)
8c1ebe97
MV		 142/* chip has PFD requency doubler */
143#define VC5_HAS_PFD_FREQ_DBL BIT(1)
fc336ae6
LC		 144/* chip has bits to disable FOD sync */
145#define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
9adddb01 146
3e1aec4e
MV		 147/* Supported IDT VC5 models. */
148enum vc5_model {
149 IDT_VC5_5P49V5923,
b1911555 150 IDT_VC5_5P49V5925,
3e1aec4e 151 IDT_VC5_5P49V5933,
1193e14f 152 IDT_VC5_5P49V5935,
dbf6b16f 153 IDT_VC6_5P49V6901,
2bda748e 154 IDT_VC6_5P49V6965,
d8473831 155 IDT_VC6_5P49V6975,
3e1aec4e
MV		 156};
157
9adddb01
AF		 158/* Structure to describe features of a particular VC5 model */
159struct vc5_chip_info {
160 const enum vc5_model model;
161 const unsigned int clk_fod_cnt;
162 const unsigned int clk_out_cnt;
163 const u32 flags;
164};
165
3e1aec4e
MV		 166struct vc5_driver_data;
167
168struct vc5_hw_data {
169 struct clk_hw hw;
170 struct vc5_driver_data *vc5;
171 u32 div_int;
172 u32 div_frc;
173 unsigned int num;
3bca66b0
LC		 174};
175
176struct vc5_out_data {
177 struct clk_hw hw;
178 struct vc5_driver_data *vc5;
179 unsigned int num;
260249f9
AF		 180 unsigned int clk_output_cfg0;
181 unsigned int clk_output_cfg0_mask;
3e1aec4e
MV		 182};
183
184struct vc5_driver_data {
185 struct i2c_client *client;
186 struct regmap *regmap;
9adddb01 187 const struct vc5_chip_info *chip_info;
3e1aec4e
MV		 188
189 struct clk *pin_xin;
190 struct clk *pin_clkin;
191 unsigned char clk_mux_ins;
192 struct clk_hw clk_mux;
8c1ebe97 193 struct clk_hw clk_mul;
55997db5 194 struct clk_hw clk_pfd;
3e1aec4e 195 struct vc5_hw_data clk_pll;
9adddb01 196 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
3bca66b0 197 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
3e1aec4e
MV		 198};
199
3e1aec4e
MV		 200/*
201 * VersaClock5 i2c regmap
202 */
203static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
204{
205 /* Factory reserved regs, make them read-only */
206 if (reg <= 0xf)
207 return false;
208
209 /* Factory reserved regs, make them read-only */
210 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
211 return false;
212
213 return true;
214}
215
216static const struct regmap_config vc5_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .cache_type = REGCACHE_RBTREE,
220 .max_register = 0x76,
221 .writeable_reg = vc5_regmap_is_writeable,
222};
223
224/*
225 * VersaClock5 input multiplexer between XTAL and CLKIN divider
226 */
227static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
228{
229 struct vc5_driver_data *vc5 =
230 container_of(hw, struct vc5_driver_data, clk_mux);
231 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
232 unsigned int src;
cc323782
LPC		 233 int ret;
234
235 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
236 if (ret)
237 return 0;
3e1aec4e 238
3e1aec4e
MV		 239 src &= mask;
240
241 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
242 return 0;
243
244 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
245 return 1;
246
247 dev_warn(&vc5->client->dev,
248 "Invalid clock input configuration (%02x)\n", src);
249 return 0;
250}
251
252static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
253{
254 struct vc5_driver_data *vc5 =
255 container_of(hw, struct vc5_driver_data, clk_mux);
256 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
257 u8 src;
258
259 if ((index > 1) || !vc5->clk_mux_ins)
260 return -EINVAL;
261
262 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
263 if (index == 0)
264 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
265 if (index == 1)
266 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
267 } else {
268 if (index != 0)
269 return -EINVAL;
270
271 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
272 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
2137a109 273 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
3e1aec4e 274 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
2137a109
MV		 275 else /* Invalid; should have been caught by vc5_probe() */
276 return -EINVAL;
3e1aec4e
MV		 277 }
278
279 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
280}
281
55997db5
MV		 282static const struct clk_ops vc5_mux_ops = {
283 .set_parent = vc5_mux_set_parent,
284 .get_parent = vc5_mux_get_parent,
285};
286
8c1ebe97
MV		 287static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
288 unsigned long parent_rate)
289{
290 struct vc5_driver_data *vc5 =
291 container_of(hw, struct vc5_driver_data, clk_mul);
292 unsigned int premul;
cc323782
LPC		 293 int ret;
294
295 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
296 if (ret)
297 return 0;
8c1ebe97 298
8c1ebe97
MV		 299 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
300 parent_rate *= 2;
301
302 return parent_rate;
303}
304
305static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
306 unsigned long *parent_rate)
307{
308 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
309 return rate;
310 else
311 return -EINVAL;
312}
313
314static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
315 unsigned long parent_rate)
316{
317 struct vc5_driver_data *vc5 =
318 container_of(hw, struct vc5_driver_data, clk_mul);
319 u32 mask;
320
321 if ((parent_rate * 2) == rate)
322 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
323 else
324 mask = 0;
325
cc323782
LPC		 326 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
327 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
328 mask);
8c1ebe97
MV		 329}
330
331static const struct clk_ops vc5_dbl_ops = {
332 .recalc_rate = vc5_dbl_recalc_rate,
333 .round_rate = vc5_dbl_round_rate,
334 .set_rate = vc5_dbl_set_rate,
335};
336
55997db5 337static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
3e1aec4e
MV		 338 unsigned long parent_rate)
339{
340 struct vc5_driver_data *vc5 =
55997db5 341 container_of(hw, struct vc5_driver_data, clk_pfd);
3e1aec4e 342 unsigned int prediv, div;
cc323782 343 int ret;
3e1aec4e 344
cc323782
LPC		 345 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
346 if (ret)
347 return 0;
3e1aec4e
MV		 348
349 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
350 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
351 return parent_rate;
352
cc323782
LPC		 353 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
354 if (ret)
355 return 0;
3e1aec4e
MV		 356
357 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
358 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
359 return parent_rate / 2;
360 else
361 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
362}
363
55997db5 364static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
3e1aec4e
MV		 365 unsigned long *parent_rate)
366{
367 unsigned long idiv;
368
369 /* PLL cannot operate with input clock above 50 MHz. */
370 if (rate > 50000000)
371 return -EINVAL;
372
373 /* CLKIN within range of PLL input, feed directly to PLL. */
374 if (*parent_rate <= 50000000)
375 return *parent_rate;
376
377 idiv = DIV_ROUND_UP(*parent_rate, rate);
378 if (idiv > 127)
379 return -EINVAL;
380
381 return *parent_rate / idiv;
382}
383
55997db5 384static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
3e1aec4e
MV		 385 unsigned long parent_rate)
386{
387 struct vc5_driver_data *vc5 =
55997db5 388 container_of(hw, struct vc5_driver_data, clk_pfd);
3e1aec4e 389 unsigned long idiv;
cc323782 390 int ret;
3e1aec4e
MV		 391 u8 div;
392
393 /* CLKIN within range of PLL input, feed directly to PLL. */
394 if (parent_rate <= 50000000) {
01874fb2
LPC		 395 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
396 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
cc323782
LPC		 397 if (ret)
398 return ret;
399
400 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
3e1aec4e
MV		 401 }
402
403 idiv = DIV_ROUND_UP(parent_rate, rate);
404
405 /* We have dedicated div-2 predivider. */
406 if (idiv == 2)
407 div = VC5_REF_DIVIDER_SEL_PREDIV2;
408 else
409 div = VC5_REF_DIVIDER_REF_DIV(idiv);
410
cc323782
LPC		 411 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
412 if (ret)
413 return ret;
3e1aec4e 414
01874fb2
LPC		 415 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
416 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
3e1aec4e
MV		 417}
418
55997db5
MV		 419static const struct clk_ops vc5_pfd_ops = {
420 .recalc_rate = vc5_pfd_recalc_rate,
421 .round_rate = vc5_pfd_round_rate,
422 .set_rate = vc5_pfd_set_rate,
3e1aec4e
MV		 423};
424
425/*
426 * VersaClock5 PLL/VCO
427 */
428static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
429 unsigned long parent_rate)
430{
431 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
432 struct vc5_driver_data *vc5 = hwdata->vc5;
433 u32 div_int, div_frc;
434 u8 fb[5];
435
436 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
437
438 div_int = (fb[0] << 4) | (fb[1] >> 4);
439 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
440
441 /* The PLL divider has 12 integer bits and 24 fractional bits */
442 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
443}
444
445static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
446 unsigned long *parent_rate)
447{
448 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
449 u32 div_int;
450 u64 div_frc;
451
452 if (rate < VC5_PLL_VCO_MIN)
453 rate = VC5_PLL_VCO_MIN;
454 if (rate > VC5_PLL_VCO_MAX)
455 rate = VC5_PLL_VCO_MAX;
456
457 /* Determine integer part, which is 12 bit wide */
458 div_int = rate / *parent_rate;
459 if (div_int > 0xfff)
460 rate = *parent_rate * 0xfff;
461
462 /* Determine best fractional part, which is 24 bit wide */
463 div_frc = rate % *parent_rate;
464 div_frc *= BIT(24) - 1;
465 do_div(div_frc, *parent_rate);
466
467 hwdata->div_int = div_int;
468 hwdata->div_frc = (u32)div_frc;
469
470 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
471}
472
473static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
474 unsigned long parent_rate)
475{
476 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
477 struct vc5_driver_data *vc5 = hwdata->vc5;
478 u8 fb[5];
479
480 fb[0] = hwdata->div_int >> 4;
481 fb[1] = hwdata->div_int << 4;
482 fb[2] = hwdata->div_frc >> 16;
483 fb[3] = hwdata->div_frc >> 8;
484 fb[4] = hwdata->div_frc;
485
486 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
487}
488
489static const struct clk_ops vc5_pll_ops = {
490 .recalc_rate = vc5_pll_recalc_rate,
491 .round_rate = vc5_pll_round_rate,
492 .set_rate = vc5_pll_set_rate,
493};
494
495static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
496 unsigned long parent_rate)
497{
498 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
499 struct vc5_driver_data *vc5 = hwdata->vc5;
500 /* VCO frequency is divided by two before entering FOD */
501 u32 f_in = parent_rate / 2;
502 u32 div_int, div_frc;
503 u8 od_int[2];
504 u8 od_frc[4];
505
506 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
507 od_int, 2);
508 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
509 od_frc, 4);
510
511 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
512 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
513 (od_frc[2] << 6) | (od_frc[3] >> 2);
514
3bded569
MV		 515 /* Avoid division by zero if the output is not configured. */
516 if (div_int == 0 && div_frc == 0)
517 return 0;
518
3e1aec4e
MV		 519 /* The PLL divider has 12 integer bits and 30 fractional bits */
520 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
521}
522
523static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
524 unsigned long *parent_rate)
525{
526 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
527 /* VCO frequency is divided by two before entering FOD */
528 u32 f_in = *parent_rate / 2;
529 u32 div_int;
530 u64 div_frc;
531
532 /* Determine integer part, which is 12 bit wide */
533 div_int = f_in / rate;
534 /*
535 * WARNING: The clock chip does not output signal if the integer part
536 * of the divider is 0xfff and fractional part is non-zero.
537 * Clamp the divider at 0xffe to keep the code simple.
538 */
539 if (div_int > 0xffe) {
540 div_int = 0xffe;
541 rate = f_in / div_int;
542 }
543
544 /* Determine best fractional part, which is 30 bit wide */
545 div_frc = f_in % rate;
546 div_frc <<= 24;
547 do_div(div_frc, rate);
548
549 hwdata->div_int = div_int;
550 hwdata->div_frc = (u32)div_frc;
551
552 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
553}
554
555static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
556 unsigned long parent_rate)
557{
558 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
559 struct vc5_driver_data *vc5 = hwdata->vc5;
560 u8 data[14] = {
561 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
562 hwdata->div_frc >> 6, hwdata->div_frc << 2,
563 0, 0, 0, 0, 0,
564 0, 0,
565 hwdata->div_int >> 4, hwdata->div_int << 4,
566 0
567 };
cc323782 568 int ret;
3e1aec4e 569
cc323782
LPC		 570 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
571 data, 14);
572 if (ret)
573 return ret;
3e1aec4e
MV		 574
575 /*
576 * Toggle magic bit in undocumented register for unknown reason.
577 * This is what the IDT timing commander tool does and the chip
578 * datasheet somewhat implies this is needed, but the register
579 * and the bit is not documented.
580 */
01874fb2
LPC		 581 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
582 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
cc323782
LPC		 583 if (ret)
584 return ret;
585
01874fb2
LPC		 586 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
587 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
3e1aec4e
MV		 588}
589
590static const struct clk_ops vc5_fod_ops = {
591 .recalc_rate = vc5_fod_recalc_rate,
592 .round_rate = vc5_fod_round_rate,
593 .set_rate = vc5_fod_set_rate,
594};
595
596static int vc5_clk_out_prepare(struct clk_hw *hw)
597{
3bca66b0 598 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
3e1aec4e 599 struct vc5_driver_data *vc5 = hwdata->vc5;
718f4694
MV		 600 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
601 VC5_OUT_DIV_CONTROL_SEL_EXT |
602 VC5_OUT_DIV_CONTROL_EN_FOD;
603 unsigned int src;
604 int ret;
605
fc336ae6
LC		 606 /*
607 * When enabling a FOD, all currently enabled FODs are briefly
608 * stopped in order to synchronize all of them. This causes a clock
609 * disruption to any unrelated chips that might be already using
610 * other clock outputs. Bypass the sync feature to avoid the issue,
611 * which is possible on the VersaClock 6E family via reserved
612 * registers.
613 */
614 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
01874fb2
LPC		 615 ret = regmap_set_bits(vc5->regmap,
616 VC5_RESERVED_X0(hwdata->num),
617 VC5_RESERVED_X0_BYPASS_SYNC);
fc336ae6
LC		 618 if (ret)
619 return ret;
620 }
621
718f4694
MV		 622 /*
623 * If the input mux is disabled, enable it first and
624 * select source from matching FOD.
625 */
cc323782
LPC		 626 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
627 if (ret)
628 return ret;
629
718f4694
MV		 630 if ((src & mask) == 0) {
631 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
632 ret = regmap_update_bits(vc5->regmap,
633 VC5_OUT_DIV_CONTROL(hwdata->num),
634 mask | VC5_OUT_DIV_CONTROL_RESET, src);
635 if (ret)
636 return ret;
637 }
3e1aec4e
MV		 638
639 /* Enable the clock buffer */
01874fb2
LPC		 640 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
641 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
cc323782
LPC		 642 if (ret)
643 return ret;
644
260249f9
AF		 645 if (hwdata->clk_output_cfg0_mask) {
646 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
647 hwdata->num, hwdata->clk_output_cfg0_mask,
648 hwdata->clk_output_cfg0);
649
cc323782
LPC		 650 ret = regmap_update_bits(vc5->regmap,
651 VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
652 hwdata->clk_output_cfg0_mask,
653 hwdata->clk_output_cfg0);
654 if (ret)
655 return ret;
260249f9
AF		 656 }
657
3e1aec4e
MV		 658 return 0;
659}
660
661static void vc5_clk_out_unprepare(struct clk_hw *hw)
662{
3bca66b0 663 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
3e1aec4e
MV		 664 struct vc5_driver_data *vc5 = hwdata->vc5;
665
a4decf58 666 /* Disable the clock buffer */
01874fb2
LPC		 667 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
668 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
3e1aec4e
MV		 669}
670
671static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
672{
3bca66b0 673 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
3e1aec4e
MV		 674 struct vc5_driver_data *vc5 = hwdata->vc5;
675 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
676 VC5_OUT_DIV_CONTROL_SEL_EXT |
677 VC5_OUT_DIV_CONTROL_EN_FOD;
678 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
679 VC5_OUT_DIV_CONTROL_EN_FOD;
680 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
681 VC5_OUT_DIV_CONTROL_SEL_EXT;
682 unsigned int src;
cc323782
LPC		 683 int ret;
684
685 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
686 if (ret)
687 return 0;
3e1aec4e 688
3e1aec4e
MV		 689 src &= mask;
690
325b7b90
MV		 691 if (src == 0) /* Input mux set to DISABLED */
692 return 0;
693
3e1aec4e
MV		 694 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
695 return 0;
696
697 if (src == extclk)
698 return 1;
699
700 dev_warn(&vc5->client->dev,
701 "Invalid clock output configuration (%02x)\n", src);
702 return 0;
703}
704
705static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
706{
3bca66b0 707 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
3e1aec4e
MV		 708 struct vc5_driver_data *vc5 = hwdata->vc5;
709 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
710 VC5_OUT_DIV_CONTROL_SELB_NORM |
711 VC5_OUT_DIV_CONTROL_SEL_EXT |
712 VC5_OUT_DIV_CONTROL_EN_FOD;
713 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
714 VC5_OUT_DIV_CONTROL_SEL_EXT;
715 u8 src = VC5_OUT_DIV_CONTROL_RESET;
716
717 if (index == 0)
718 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
719 else
720 src |= extclk;
721
722 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
723 mask, src);
724}
725
726static const struct clk_ops vc5_clk_out_ops = {
727 .prepare = vc5_clk_out_prepare,
728 .unprepare = vc5_clk_out_unprepare,
729 .set_parent = vc5_clk_out_set_parent,
730 .get_parent = vc5_clk_out_get_parent,
731};
732
733static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
734 void *data)
735{
736 struct vc5_driver_data *vc5 = data;
737 unsigned int idx = clkspec->args[0];
738
9adddb01 739 if (idx >= vc5->chip_info->clk_out_cnt)
3e1aec4e
MV		 740 return ERR_PTR(-EINVAL);
741
742 return &vc5->clk_out[idx].hw;
743}
744
745static int vc5_map_index_to_output(const enum vc5_model model,
746 const unsigned int n)
747{
748 switch (model) {
749 case IDT_VC5_5P49V5933:
750 return (n == 0) ? 0 : 3;
751 case IDT_VC5_5P49V5923:
b1911555 752 case IDT_VC5_5P49V5925:
1193e14f 753 case IDT_VC5_5P49V5935:
dbf6b16f 754 case IDT_VC6_5P49V6901:
2bda748e 755 case IDT_VC6_5P49V6965:
d8473831 756 case IDT_VC6_5P49V6975:
3e1aec4e
MV		 757 default:
758 return n;
759 }
760}
761
260249f9 762static int vc5_update_mode(struct device_node *np_output,
3bca66b0 763 struct vc5_out_data *clk_out)
260249f9
AF		 764{
765 u32 value;
766
767 if (!of_property_read_u32(np_output, "idt,mode", &value)) {
768 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
769 switch (value) {
770 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
771 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
772 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
773 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
774 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
775 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
776 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
777 clk_out->clk_output_cfg0 |=
778 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
779 break;
780 default:
781 return -EINVAL;
782 }
783 }
784 return 0;
785}
786
787static int vc5_update_power(struct device_node *np_output,
3bca66b0 788 struct vc5_out_data *clk_out)
260249f9
AF		 789{
790 u32 value;
791
4b003f5f
GU		 792 if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
793 &value)) {
260249f9
AF		 794 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
795 switch (value) {
796 case 1800000:
797 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
798 break;
799 case 2500000:
800 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
801 break;
802 case 3300000:
803 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
804 break;
805 default:
806 return -EINVAL;
807 }
808 }
809 return 0;
810}
811
f3d661d6
AF		 812static int vc5_map_cap_value(u32 femtofarads)
813{
814 int mapped_value;
815
816 /*
817 * The datasheet explicitly states 9000 - 25000 with 0.5pF
818 * steps, but the Programmer's guide shows the steps are 0.430pF.
819 * After getting feedback from Renesas, the .5pF steps were the
820 * goal, but 430nF was the actual values.
821 * Because of this, the actual range goes to 22760 instead of 25000
822 */
823 if (femtofarads < 9000 || femtofarads > 22760)
824 return -EINVAL;
825
826 /*
827 * The Programmer's guide shows XTAL[5:0] but in reality,
828 * XTAL[0] and XTAL[1] are both LSB which makes the math
829 * strange. With clarfication from Renesas, setting the
830 * values should be simpler by ignoring XTAL[0]
831 */
832 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
833
834 /*
835 * Since the calculation ignores XTAL[0], there is one
836 * special case where mapped_value = 32. In reality, this means
837 * the real mapped value should be 111111b. In other cases,
838 * the mapped_value needs to be shifted 1 to the left.
839 */
840 if (mapped_value > 31)
841 mapped_value = 0x3f;
842 else
843 mapped_value <<= 1;
844
845 return mapped_value;
846}
847static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
848{
849 u32 value;
850 int mapped_value;
cc323782 851 int ret;
f3d661d6 852
cc323782
LPC		 853 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value))
854 return 0;
f3d661d6 855
cc323782
LPC		 856 mapped_value = vc5_map_cap_value(value);
857 if (mapped_value < 0)
858 return mapped_value;
859
860 /*
861 * The mapped_value is really the high 6 bits of
862 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
863 * shift the value 2 places.
864 */
865 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
866 mapped_value << 2);
867 if (ret)
868 return ret;
869
870 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
871 mapped_value << 2);
f3d661d6
AF		 872}
873
260249f9 874static int vc5_update_slew(struct device_node *np_output,
3bca66b0 875 struct vc5_out_data *clk_out)
260249f9
AF		 876{
877 u32 value;
878
879 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
880 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
881 switch (value) {
882 case 80:
883 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
884 break;
885 case 85:
886 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
887 break;
888 case 90:
889 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
890 break;
891 case 100:
892 clk_out->clk_output_cfg0 |=
893 VC5_CLK_OUTPUT_CFG0_SLEW_100;
894 break;
895 default:
896 return -EINVAL;
897 }
898 }
899 return 0;
900}
901
902static int vc5_get_output_config(struct i2c_client *client,
3bca66b0 903 struct vc5_out_data *clk_out)
260249f9
AF		 904{
905 struct device_node *np_output;
906 char *child_name;
907 int ret = 0;
908
909 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
faf29338
AF		 910 if (!child_name)
911 return -ENOMEM;
912
260249f9
AF		 913 np_output = of_get_child_by_name(client->dev.of_node, child_name);
914 kfree(child_name);
915 if (!np_output)
faf29338 916 return 0;
260249f9
AF		 917
918 ret = vc5_update_mode(np_output, clk_out);
919 if (ret)
920 goto output_error;
921
922 ret = vc5_update_power(np_output, clk_out);
923 if (ret)
924 goto output_error;
925
926 ret = vc5_update_slew(np_output, clk_out);
927
928output_error:
929 if (ret) {
930 dev_err(&client->dev,
931 "Invalid clock output configuration OUT%d\n",
932 clk_out->num + 1);
933 }
934
935 of_node_put(np_output);
936
260249f9
AF		 937 return ret;
938}
939
3e1aec4e
MV		 940static const struct of_device_id clk_vc5_of_match[];
941
5bba6d37 942static int vc5_probe(struct i2c_client *client)
3e1aec4e 943{
d83e561d 944 unsigned int oe, sd, src_mask = 0, src_val = 0;
3e1aec4e
MV		 945 struct vc5_driver_data *vc5;
946 struct clk_init_data init;
947 const char *parent_names[2];
9adddb01 948 unsigned int n, idx = 0;
3e1aec4e
MV		 949 int ret;
950
951 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
faf29338 952 if (!vc5)
3e1aec4e
MV		 953 return -ENOMEM;
954
955 i2c_set_clientdata(client, vc5);
956 vc5->client = client;
9adddb01 957 vc5->chip_info = of_device_get_match_data(&client->dev);
3e1aec4e
MV		 958
959 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
960 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
961 return -EPROBE_DEFER;
962
963 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
964 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
965 return -EPROBE_DEFER;
966
967 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
2ef16254
SA		 968 if (IS_ERR(vc5->regmap))
969 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
970 "failed to allocate register map\n");
3e1aec4e 971
d83e561d
SA		 972 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd);
973 if (!ret) {
974 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
975 if (sd)
976 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
977 } else if (ret != -EINVAL) {
978 return dev_err_probe(&client->dev, ret,
979 "could not read idt,shutdown\n");
980 }
981
982 ret = of_property_read_u32(client->dev.of_node,
983 "idt,output-enable-active", &oe);
984 if (!ret) {
985 src_mask |= VC5_PRIM_SRC_SHDN_SP;
986 if (oe)
987 src_val |= VC5_PRIM_SRC_SHDN_SP;
988 } else if (ret != -EINVAL) {
989 return dev_err_probe(&client->dev, ret,
990 "could not read idt,output-enable-active\n");
991 }
992
cc323782
LPC		 993 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
994 src_val);
995 if (ret)
996 return ret;
d83e561d 997
3e1aec4e
MV		 998 /* Register clock input mux */
999 memset(&init, 0, sizeof(init));
1000
1001 if (!IS_ERR(vc5->pin_xin)) {
1002 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1003 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
9adddb01 1004 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
3e1aec4e
MV		 1005 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
1006 "internal-xtal", NULL,
1007 0, 25000000);
1008 if (IS_ERR(vc5->pin_xin))
1009 return PTR_ERR(vc5->pin_xin);
1010 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1011 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1012 }
1013
1014 if (!IS_ERR(vc5->pin_clkin)) {
1015 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
1016 parent_names[init.num_parents++] =
f491276a 1017 __clk_get_name(vc5->pin_clkin);
3e1aec4e
MV		 1018 }
1019
2ef16254
SA		 1020 if (!init.num_parents)
1021 return dev_err_probe(&client->dev, -EINVAL,
1022 "no input clock specified!\n");
3e1aec4e 1023
f3d661d6
AF		 1024 /* Configure Optional Loading Capacitance for external XTAL */
1025 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
1026 ret = vc5_update_cap_load(client->dev.of_node, vc5);
1027 if (ret)
1028 goto err_clk_register;
1029 }
1030
f491276a 1031 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
3e1aec4e
MV		 1032 init.ops = &vc5_mux_ops;
1033 init.flags = 0;
1034 init.parent_names = parent_names;
1035 vc5->clk_mux.init = &init;
1036 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
8200597f
CIK		 1037 if (ret)
1038 goto err_clk_register;
f491276a 1039 kfree(init.name); /* clock framework made a copy of the name */
3e1aec4e 1040
8c1ebe97
MV		 1041 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
1042 /* Register frequency doubler */
1043 memset(&init, 0, sizeof(init));
f491276a
AF		 1044 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
1045 client->dev.of_node);
8c1ebe97
MV		 1046 init.ops = &vc5_dbl_ops;
1047 init.flags = CLK_SET_RATE_PARENT;
f491276a
AF		 1048 init.parent_names = parent_names;
1049 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
8c1ebe97
MV		 1050 init.num_parents = 1;
1051 vc5->clk_mul.init = &init;
1052 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
8200597f
CIK		 1053 if (ret)
1054 goto err_clk_register;
f491276a 1055 kfree(init.name); /* clock framework made a copy of the name */
8c1ebe97
MV		 1056 }
1057
55997db5
MV		 1058 /* Register PFD */
1059 memset(&init, 0, sizeof(init));
f491276a 1060 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
55997db5
MV		 1061 init.ops = &vc5_pfd_ops;
1062 init.flags = CLK_SET_RATE_PARENT;
f491276a 1063 init.parent_names = parent_names;
8c1ebe97 1064 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
f491276a 1065 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
8c1ebe97 1066 else
f491276a 1067 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
55997db5
MV		 1068 init.num_parents = 1;
1069 vc5->clk_pfd.init = &init;
1070 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
8200597f
CIK		 1071 if (ret)
1072 goto err_clk_register;
f491276a 1073 kfree(init.name); /* clock framework made a copy of the name */
55997db5 1074
3e1aec4e
MV		 1075 /* Register PLL */
1076 memset(&init, 0, sizeof(init));
f491276a 1077 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
3e1aec4e
MV		 1078 init.ops = &vc5_pll_ops;
1079 init.flags = CLK_SET_RATE_PARENT;
f491276a
AF		 1080 init.parent_names = parent_names;
1081 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
3e1aec4e
MV		 1082 init.num_parents = 1;
1083 vc5->clk_pll.num = 0;
1084 vc5->clk_pll.vc5 = vc5;
1085 vc5->clk_pll.hw.init = &init;
1086 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
8200597f
CIK		 1087 if (ret)
1088 goto err_clk_register;
f491276a 1089 kfree(init.name); /* clock framework made a copy of the name */
3e1aec4e
MV		 1090
1091 /* Register FODs */
9adddb01
AF		 1092 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1093 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
3e1aec4e 1094 memset(&init, 0, sizeof(init));
f491276a
AF		 1095 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
1096 client->dev.of_node, idx);
3e1aec4e
MV		 1097 init.ops = &vc5_fod_ops;
1098 init.flags = CLK_SET_RATE_PARENT;
f491276a
AF		 1099 init.parent_names = parent_names;
1100 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
3e1aec4e
MV		 1101 init.num_parents = 1;
1102 vc5->clk_fod[n].num = idx;
1103 vc5->clk_fod[n].vc5 = vc5;
1104 vc5->clk_fod[n].hw.init = &init;
1105 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
8200597f
CIK		 1106 if (ret)
1107 goto err_clk_register;
f491276a 1108 kfree(init.name); /* clock framework made a copy of the name */
3e1aec4e
MV		 1109 }
1110
1111 /* Register MUX-connected OUT0_I2C_SELB output */
1112 memset(&init, 0, sizeof(init));
f491276a
AF		 1113 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
1114 client->dev.of_node);
3e1aec4e
MV		 1115 init.ops = &vc5_clk_out_ops;
1116 init.flags = CLK_SET_RATE_PARENT;
f491276a
AF		 1117 init.parent_names = parent_names;
1118 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
3e1aec4e
MV		 1119 init.num_parents = 1;
1120 vc5->clk_out[0].num = idx;
1121 vc5->clk_out[0].vc5 = vc5;
1122 vc5->clk_out[0].hw.init = &init;
1123 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
8200597f
CIK		 1124 if (ret)
1125 goto err_clk_register;
1126 kfree(init.name); /* clock framework made a copy of the name */
3e1aec4e
MV		 1127
1128 /* Register FOD-connected OUTx outputs */
9adddb01
AF		 1129 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1130 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
f491276a 1131 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
3e1aec4e 1132 if (n == 1)
f491276a 1133 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
3e1aec4e 1134 else
f491276a
AF		 1135 parent_names[1] =
1136 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
3e1aec4e
MV		 1137
1138 memset(&init, 0, sizeof(init));
f491276a
AF		 1139 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
1140 client->dev.of_node, idx + 1);
3e1aec4e
MV		 1141 init.ops = &vc5_clk_out_ops;
1142 init.flags = CLK_SET_RATE_PARENT;
1143 init.parent_names = parent_names;
1144 init.num_parents = 2;
1145 vc5->clk_out[n].num = idx;
1146 vc5->clk_out[n].vc5 = vc5;
1147 vc5->clk_out[n].hw.init = &init;
f491276a 1148 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
8200597f
CIK		 1149 if (ret)
1150 goto err_clk_register;
f491276a 1151 kfree(init.name); /* clock framework made a copy of the name */
260249f9
AF		 1152
1153 /* Fetch Clock Output configuration from DT (if specified) */
1154 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1155 if (ret)
1156 goto err_clk;
3e1aec4e
MV		 1157 }
1158
1159 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1160 if (ret) {
2ef16254
SA		 1161 dev_err_probe(&client->dev, ret,
1162 "unable to add clk provider\n");
3e1aec4e
MV		 1163 goto err_clk;
1164 }
1165
1166 return 0;
1167
8200597f 1168err_clk_register:
2ef16254
SA		 1169 dev_err_probe(&client->dev, ret,
1170 "unable to register %s\n", init.name);
8200597f 1171 kfree(init.name); /* clock framework made a copy of the name */
3e1aec4e 1172err_clk:
9adddb01 1173 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
3e1aec4e
MV		 1174 clk_unregister_fixed_rate(vc5->pin_xin);
1175 return ret;
1176}
1177
ed5c2f5f 1178static void vc5_remove(struct i2c_client *client)
3e1aec4e
MV		 1179{
1180 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1181
1182 of_clk_del_provider(client->dev.of_node);
1183
9adddb01 1184 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
3e1aec4e 1185 clk_unregister_fixed_rate(vc5->pin_xin);
3e1aec4e
MV		 1186}
1187
8cbdc1f0
MV		 1188static int __maybe_unused vc5_suspend(struct device *dev)
1189{
1190 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1191
1192 regcache_cache_only(vc5->regmap, true);
1193 regcache_mark_dirty(vc5->regmap);
1194
1195 return 0;
1196}
1197
1198static int __maybe_unused vc5_resume(struct device *dev)
1199{
1200 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1201 int ret;
1202
1203 regcache_cache_only(vc5->regmap, false);
1204 ret = regcache_sync(vc5->regmap);
1205 if (ret)
1206 dev_err(dev, "Failed to restore register map: %d\n", ret);
1207 return ret;
1208}
1209
9adddb01
AF		 1210static const struct vc5_chip_info idt_5p49v5923_info = {
1211 .model = IDT_VC5_5P49V5923,
1212 .clk_fod_cnt = 2,
1213 .clk_out_cnt = 3,
1214 .flags = 0,
1215};
1216
b1911555
VB		 1217static const struct vc5_chip_info idt_5p49v5925_info = {
1218 .model = IDT_VC5_5P49V5925,
1219 .clk_fod_cnt = 4,
1220 .clk_out_cnt = 5,
1221 .flags = 0,
1222};
1223
9adddb01
AF		 1224static const struct vc5_chip_info idt_5p49v5933_info = {
1225 .model = IDT_VC5_5P49V5933,
1226 .clk_fod_cnt = 2,
1227 .clk_out_cnt = 3,
1228 .flags = VC5_HAS_INTERNAL_XTAL,
1229};
1230
1193e14f
AF		 1231static const struct vc5_chip_info idt_5p49v5935_info = {
1232 .model = IDT_VC5_5P49V5935,
1233 .clk_fod_cnt = 4,
1234 .clk_out_cnt = 5,
1235 .flags = VC5_HAS_INTERNAL_XTAL,
1236};
1237
dbf6b16f
MV		 1238static const struct vc5_chip_info idt_5p49v6901_info = {
1239 .model = IDT_VC6_5P49V6901,
1240 .clk_fod_cnt = 4,
1241 .clk_out_cnt = 5,
c388cc80 1242 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
dbf6b16f
MV		 1243};
1244
2bda748e
AF		 1245static const struct vc5_chip_info idt_5p49v6965_info = {
1246 .model = IDT_VC6_5P49V6965,
1247 .clk_fod_cnt = 4,
1248 .clk_out_cnt = 5,
fc336ae6 1249 .flags = VC5_HAS_BYPASS_SYNC_BIT,
2bda748e
AF		 1250};
1251
d8473831
MF		 1252static const struct vc5_chip_info idt_5p49v6975_info = {
1253 .model = IDT_VC6_5P49V6975,
1254 .clk_fod_cnt = 4,
1255 .clk_out_cnt = 5,
1256 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
1257};
1258
3e1aec4e
MV		 1259static const struct i2c_device_id vc5_id[] = {
1260 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
b1911555 1261 { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
3e1aec4e 1262 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
1193e14f 1263 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
dbf6b16f 1264 { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
2bda748e 1265 { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
d8473831 1266 { "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
3e1aec4e
MV		 1267 { }
1268};
1269MODULE_DEVICE_TABLE(i2c, vc5_id);
1270
1271static const struct of_device_id clk_vc5_of_match[] = {
9adddb01 1272 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
b1911555 1273 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
9adddb01 1274 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1193e14f 1275 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
dbf6b16f 1276 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
2bda748e 1277 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
d8473831 1278 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
3e1aec4e
MV		 1279 { },
1280};
1281MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
1282
8cbdc1f0
MV		 1283static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
1284
3e1aec4e
MV		 1285static struct i2c_driver vc5_driver = {
1286 .driver = {
1287 .name = "vc5",
8cbdc1f0 1288 .pm = &vc5_pm_ops,
3e1aec4e
MV		 1289 .of_match_table = clk_vc5_of_match,
1290 },
5bba6d37 1291 .probe_new = vc5_probe,
3e1aec4e
MV		 1292 .remove = vc5_remove,
1293 .id_table = vc5_id,
1294};
1295module_i2c_driver(vc5_driver);
1296
1297MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
1298MODULE_DESCRIPTION("IDT VersaClock 5 driver");
1299MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)