Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3e1aec4e MV |
2 | /* |
3 | * Driver for IDT Versaclock 5 | |
4 | * | |
5 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> | |
3e1aec4e MV |
6 | */ |
7 | ||
8 | /* | |
9 | * Possible optimizations: | |
10 | * - Use spread spectrum | |
11 | * - Use integer divider in FOD if applicable | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/mod_devicetable.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/rational.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/slab.h> | |
26 | ||
260249f9 AF |
27 | #include <dt-bindings/clk/versaclock.h> |
28 | ||
3e1aec4e MV |
29 | /* VersaClock5 registers */ |
30 | #define VC5_OTP_CONTROL 0x00 | |
31 | ||
32 | /* Factory-reserved register block */ | |
33 | #define VC5_RSVD_DEVICE_ID 0x01 | |
34 | #define VC5_RSVD_ADC_GAIN_7_0 0x02 | |
35 | #define VC5_RSVD_ADC_GAIN_15_8 0x03 | |
36 | #define VC5_RSVD_ADC_OFFSET_7_0 0x04 | |
37 | #define VC5_RSVD_ADC_OFFSET_15_8 0x05 | |
38 | #define VC5_RSVD_TEMPY 0x06 | |
39 | #define VC5_RSVD_OFFSET_TBIN 0x07 | |
40 | #define VC5_RSVD_GAIN 0x08 | |
41 | #define VC5_RSVD_TEST_NP 0x09 | |
42 | #define VC5_RSVD_UNUSED 0x0a | |
43 | #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b | |
44 | #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c | |
45 | #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d | |
46 | #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e | |
47 | #define VC5_RSVD_CLK_AMP_123 0x0f | |
48 | ||
49 | /* Configuration register block */ | |
50 | #define VC5_PRIM_SRC_SHDN 0x10 | |
51 | #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) | |
52 | #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) | |
8c1ebe97 | 53 | #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) |
3e1aec4e MV |
54 | #define VC5_PRIM_SRC_SHDN_SP BIT(1) |
55 | #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) | |
56 | ||
57 | #define VC5_VCO_BAND 0x11 | |
58 | #define VC5_XTAL_X1_LOAD_CAP 0x12 | |
59 | #define VC5_XTAL_X2_LOAD_CAP 0x13 | |
60 | #define VC5_REF_DIVIDER 0x15 | |
61 | #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) | |
62 | #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) | |
63 | ||
64 | #define VC5_VCO_CTRL_AND_PREDIV 0x16 | |
65 | #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) | |
66 | ||
67 | #define VC5_FEEDBACK_INT_DIV 0x17 | |
68 | #define VC5_FEEDBACK_INT_DIV_BITS 0x18 | |
69 | #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) | |
70 | #define VC5_RC_CONTROL0 0x1e | |
71 | #define VC5_RC_CONTROL1 0x1f | |
fc336ae6 LC |
72 | |
73 | /* These registers are named "Unused Factory Reserved Registers" */ | |
74 | #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10)) | |
75 | #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */ | |
3e1aec4e MV |
76 | |
77 | /* Output divider control for divider 1,2,3,4 */ | |
78 | #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) | |
79 | #define VC5_OUT_DIV_CONTROL_RESET BIT(7) | |
80 | #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) | |
81 | #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) | |
82 | #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) | |
83 | #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) | |
84 | ||
85 | #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) | |
86 | #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) | |
87 | ||
88 | #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) | |
89 | #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) | |
90 | #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) | |
91 | #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) | |
92 | #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) | |
3e1aec4e MV |
93 | |
94 | /* Clock control register for clock 1,2 */ | |
95 | #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) | |
260249f9 AF |
96 | #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 |
97 | #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) | |
98 | ||
99 | #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL) | |
100 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) | |
101 | #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33) | |
102 | #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) | |
103 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) | |
104 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) | |
105 | #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25) | |
106 | ||
107 | #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 | |
108 | #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) | |
109 | #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) | |
110 | #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) | |
111 | #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) | |
112 | #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0 | |
113 | #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) | |
114 | #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) | |
115 | #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) | |
116 | #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) | |
117 | #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) | |
3e1aec4e MV |
118 | #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) |
119 | ||
120 | #define VC5_CLK_OE_SHDN 0x68 | |
121 | #define VC5_CLK_OS_SHDN 0x69 | |
122 | ||
123 | #define VC5_GLOBAL_REGISTER 0x76 | |
124 | #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) | |
125 | ||
126 | /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ | |
127 | #define VC5_PLL_VCO_MIN 2500000000UL | |
128 | #define VC5_PLL_VCO_MAX 3000000000UL | |
129 | ||
130 | /* VC5 Input mux settings */ | |
131 | #define VC5_MUX_IN_XIN BIT(0) | |
132 | #define VC5_MUX_IN_CLKIN BIT(1) | |
133 | ||
9adddb01 | 134 | /* Maximum number of clk_out supported by this driver */ |
1193e14f | 135 | #define VC5_MAX_CLK_OUT_NUM 5 |
9adddb01 AF |
136 | |
137 | /* Maximum number of FODs supported by this driver */ | |
1193e14f | 138 | #define VC5_MAX_FOD_NUM 4 |
9adddb01 AF |
139 | |
140 | /* flags to describe chip features */ | |
141 | /* chip has built-in oscilator */ | |
142 | #define VC5_HAS_INTERNAL_XTAL BIT(0) | |
8c1ebe97 MV |
143 | /* chip has PFD requency doubler */ |
144 | #define VC5_HAS_PFD_FREQ_DBL BIT(1) | |
fc336ae6 LC |
145 | /* chip has bits to disable FOD sync */ |
146 | #define VC5_HAS_BYPASS_SYNC_BIT BIT(2) | |
9adddb01 | 147 | |
3e1aec4e MV |
148 | /* Supported IDT VC5 models. */ |
149 | enum vc5_model { | |
150 | IDT_VC5_5P49V5923, | |
b1911555 | 151 | IDT_VC5_5P49V5925, |
3e1aec4e | 152 | IDT_VC5_5P49V5933, |
1193e14f | 153 | IDT_VC5_5P49V5935, |
dbf6b16f | 154 | IDT_VC6_5P49V6901, |
2bda748e | 155 | IDT_VC6_5P49V6965, |
3e1aec4e MV |
156 | }; |
157 | ||
9adddb01 AF |
158 | /* Structure to describe features of a particular VC5 model */ |
159 | struct vc5_chip_info { | |
160 | const enum vc5_model model; | |
161 | const unsigned int clk_fod_cnt; | |
162 | const unsigned int clk_out_cnt; | |
163 | const u32 flags; | |
164 | }; | |
165 | ||
3e1aec4e MV |
166 | struct vc5_driver_data; |
167 | ||
168 | struct vc5_hw_data { | |
169 | struct clk_hw hw; | |
170 | struct vc5_driver_data *vc5; | |
171 | u32 div_int; | |
172 | u32 div_frc; | |
173 | unsigned int num; | |
3bca66b0 LC |
174 | }; |
175 | ||
176 | struct vc5_out_data { | |
177 | struct clk_hw hw; | |
178 | struct vc5_driver_data *vc5; | |
179 | unsigned int num; | |
260249f9 AF |
180 | unsigned int clk_output_cfg0; |
181 | unsigned int clk_output_cfg0_mask; | |
3e1aec4e MV |
182 | }; |
183 | ||
184 | struct vc5_driver_data { | |
185 | struct i2c_client *client; | |
186 | struct regmap *regmap; | |
9adddb01 | 187 | const struct vc5_chip_info *chip_info; |
3e1aec4e MV |
188 | |
189 | struct clk *pin_xin; | |
190 | struct clk *pin_clkin; | |
191 | unsigned char clk_mux_ins; | |
192 | struct clk_hw clk_mux; | |
8c1ebe97 | 193 | struct clk_hw clk_mul; |
55997db5 | 194 | struct clk_hw clk_pfd; |
3e1aec4e | 195 | struct vc5_hw_data clk_pll; |
9adddb01 | 196 | struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; |
3bca66b0 | 197 | struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM]; |
3e1aec4e MV |
198 | }; |
199 | ||
3e1aec4e MV |
200 | /* |
201 | * VersaClock5 i2c regmap | |
202 | */ | |
203 | static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) | |
204 | { | |
205 | /* Factory reserved regs, make them read-only */ | |
206 | if (reg <= 0xf) | |
207 | return false; | |
208 | ||
209 | /* Factory reserved regs, make them read-only */ | |
210 | if (reg == 0x14 || reg == 0x1c || reg == 0x1d) | |
211 | return false; | |
212 | ||
213 | return true; | |
214 | } | |
215 | ||
216 | static const struct regmap_config vc5_regmap_config = { | |
217 | .reg_bits = 8, | |
218 | .val_bits = 8, | |
219 | .cache_type = REGCACHE_RBTREE, | |
220 | .max_register = 0x76, | |
221 | .writeable_reg = vc5_regmap_is_writeable, | |
222 | }; | |
223 | ||
224 | /* | |
225 | * VersaClock5 input multiplexer between XTAL and CLKIN divider | |
226 | */ | |
227 | static unsigned char vc5_mux_get_parent(struct clk_hw *hw) | |
228 | { | |
229 | struct vc5_driver_data *vc5 = | |
230 | container_of(hw, struct vc5_driver_data, clk_mux); | |
231 | const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; | |
232 | unsigned int src; | |
233 | ||
234 | regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); | |
235 | src &= mask; | |
236 | ||
237 | if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) | |
238 | return 0; | |
239 | ||
240 | if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) | |
241 | return 1; | |
242 | ||
243 | dev_warn(&vc5->client->dev, | |
244 | "Invalid clock input configuration (%02x)\n", src); | |
245 | return 0; | |
246 | } | |
247 | ||
248 | static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) | |
249 | { | |
250 | struct vc5_driver_data *vc5 = | |
251 | container_of(hw, struct vc5_driver_data, clk_mux); | |
252 | const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; | |
253 | u8 src; | |
254 | ||
255 | if ((index > 1) || !vc5->clk_mux_ins) | |
256 | return -EINVAL; | |
257 | ||
258 | if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { | |
259 | if (index == 0) | |
260 | src = VC5_PRIM_SRC_SHDN_EN_XTAL; | |
261 | if (index == 1) | |
262 | src = VC5_PRIM_SRC_SHDN_EN_CLKIN; | |
263 | } else { | |
264 | if (index != 0) | |
265 | return -EINVAL; | |
266 | ||
267 | if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) | |
268 | src = VC5_PRIM_SRC_SHDN_EN_XTAL; | |
2137a109 | 269 | else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) |
3e1aec4e | 270 | src = VC5_PRIM_SRC_SHDN_EN_CLKIN; |
2137a109 MV |
271 | else /* Invalid; should have been caught by vc5_probe() */ |
272 | return -EINVAL; | |
3e1aec4e MV |
273 | } |
274 | ||
275 | return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); | |
276 | } | |
277 | ||
55997db5 MV |
278 | static const struct clk_ops vc5_mux_ops = { |
279 | .set_parent = vc5_mux_set_parent, | |
280 | .get_parent = vc5_mux_get_parent, | |
281 | }; | |
282 | ||
8c1ebe97 MV |
283 | static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, |
284 | unsigned long parent_rate) | |
285 | { | |
286 | struct vc5_driver_data *vc5 = | |
287 | container_of(hw, struct vc5_driver_data, clk_mul); | |
288 | unsigned int premul; | |
289 | ||
290 | regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); | |
291 | if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) | |
292 | parent_rate *= 2; | |
293 | ||
294 | return parent_rate; | |
295 | } | |
296 | ||
297 | static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, | |
298 | unsigned long *parent_rate) | |
299 | { | |
300 | if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) | |
301 | return rate; | |
302 | else | |
303 | return -EINVAL; | |
304 | } | |
305 | ||
306 | static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, | |
307 | unsigned long parent_rate) | |
308 | { | |
309 | struct vc5_driver_data *vc5 = | |
310 | container_of(hw, struct vc5_driver_data, clk_mul); | |
311 | u32 mask; | |
312 | ||
313 | if ((parent_rate * 2) == rate) | |
314 | mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; | |
315 | else | |
316 | mask = 0; | |
317 | ||
318 | regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, | |
319 | VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, | |
320 | mask); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static const struct clk_ops vc5_dbl_ops = { | |
326 | .recalc_rate = vc5_dbl_recalc_rate, | |
327 | .round_rate = vc5_dbl_round_rate, | |
328 | .set_rate = vc5_dbl_set_rate, | |
329 | }; | |
330 | ||
55997db5 | 331 | static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, |
3e1aec4e MV |
332 | unsigned long parent_rate) |
333 | { | |
334 | struct vc5_driver_data *vc5 = | |
55997db5 | 335 | container_of(hw, struct vc5_driver_data, clk_pfd); |
3e1aec4e MV |
336 | unsigned int prediv, div; |
337 | ||
338 | regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); | |
339 | ||
340 | /* The bypass_prediv is set, PLL fed from Ref_in directly. */ | |
341 | if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) | |
342 | return parent_rate; | |
343 | ||
344 | regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); | |
345 | ||
346 | /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ | |
347 | if (div & VC5_REF_DIVIDER_SEL_PREDIV2) | |
348 | return parent_rate / 2; | |
349 | else | |
350 | return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); | |
351 | } | |
352 | ||
55997db5 | 353 | static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, |
3e1aec4e MV |
354 | unsigned long *parent_rate) |
355 | { | |
356 | unsigned long idiv; | |
357 | ||
358 | /* PLL cannot operate with input clock above 50 MHz. */ | |
359 | if (rate > 50000000) | |
360 | return -EINVAL; | |
361 | ||
362 | /* CLKIN within range of PLL input, feed directly to PLL. */ | |
363 | if (*parent_rate <= 50000000) | |
364 | return *parent_rate; | |
365 | ||
366 | idiv = DIV_ROUND_UP(*parent_rate, rate); | |
367 | if (idiv > 127) | |
368 | return -EINVAL; | |
369 | ||
370 | return *parent_rate / idiv; | |
371 | } | |
372 | ||
55997db5 | 373 | static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, |
3e1aec4e MV |
374 | unsigned long parent_rate) |
375 | { | |
376 | struct vc5_driver_data *vc5 = | |
55997db5 | 377 | container_of(hw, struct vc5_driver_data, clk_pfd); |
3e1aec4e MV |
378 | unsigned long idiv; |
379 | u8 div; | |
380 | ||
381 | /* CLKIN within range of PLL input, feed directly to PLL. */ | |
382 | if (parent_rate <= 50000000) { | |
383 | regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, | |
384 | VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, | |
385 | VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); | |
386 | regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); | |
387 | return 0; | |
388 | } | |
389 | ||
390 | idiv = DIV_ROUND_UP(parent_rate, rate); | |
391 | ||
392 | /* We have dedicated div-2 predivider. */ | |
393 | if (idiv == 2) | |
394 | div = VC5_REF_DIVIDER_SEL_PREDIV2; | |
395 | else | |
396 | div = VC5_REF_DIVIDER_REF_DIV(idiv); | |
397 | ||
398 | regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); | |
399 | regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, | |
400 | VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
55997db5 MV |
405 | static const struct clk_ops vc5_pfd_ops = { |
406 | .recalc_rate = vc5_pfd_recalc_rate, | |
407 | .round_rate = vc5_pfd_round_rate, | |
408 | .set_rate = vc5_pfd_set_rate, | |
3e1aec4e MV |
409 | }; |
410 | ||
411 | /* | |
412 | * VersaClock5 PLL/VCO | |
413 | */ | |
414 | static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, | |
415 | unsigned long parent_rate) | |
416 | { | |
417 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
418 | struct vc5_driver_data *vc5 = hwdata->vc5; | |
419 | u32 div_int, div_frc; | |
420 | u8 fb[5]; | |
421 | ||
422 | regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); | |
423 | ||
424 | div_int = (fb[0] << 4) | (fb[1] >> 4); | |
425 | div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; | |
426 | ||
427 | /* The PLL divider has 12 integer bits and 24 fractional bits */ | |
428 | return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); | |
429 | } | |
430 | ||
431 | static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
432 | unsigned long *parent_rate) | |
433 | { | |
434 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
435 | u32 div_int; | |
436 | u64 div_frc; | |
437 | ||
438 | if (rate < VC5_PLL_VCO_MIN) | |
439 | rate = VC5_PLL_VCO_MIN; | |
440 | if (rate > VC5_PLL_VCO_MAX) | |
441 | rate = VC5_PLL_VCO_MAX; | |
442 | ||
443 | /* Determine integer part, which is 12 bit wide */ | |
444 | div_int = rate / *parent_rate; | |
445 | if (div_int > 0xfff) | |
446 | rate = *parent_rate * 0xfff; | |
447 | ||
448 | /* Determine best fractional part, which is 24 bit wide */ | |
449 | div_frc = rate % *parent_rate; | |
450 | div_frc *= BIT(24) - 1; | |
451 | do_div(div_frc, *parent_rate); | |
452 | ||
453 | hwdata->div_int = div_int; | |
454 | hwdata->div_frc = (u32)div_frc; | |
455 | ||
456 | return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); | |
457 | } | |
458 | ||
459 | static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
460 | unsigned long parent_rate) | |
461 | { | |
462 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
463 | struct vc5_driver_data *vc5 = hwdata->vc5; | |
464 | u8 fb[5]; | |
465 | ||
466 | fb[0] = hwdata->div_int >> 4; | |
467 | fb[1] = hwdata->div_int << 4; | |
468 | fb[2] = hwdata->div_frc >> 16; | |
469 | fb[3] = hwdata->div_frc >> 8; | |
470 | fb[4] = hwdata->div_frc; | |
471 | ||
472 | return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); | |
473 | } | |
474 | ||
475 | static const struct clk_ops vc5_pll_ops = { | |
476 | .recalc_rate = vc5_pll_recalc_rate, | |
477 | .round_rate = vc5_pll_round_rate, | |
478 | .set_rate = vc5_pll_set_rate, | |
479 | }; | |
480 | ||
481 | static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, | |
482 | unsigned long parent_rate) | |
483 | { | |
484 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
485 | struct vc5_driver_data *vc5 = hwdata->vc5; | |
486 | /* VCO frequency is divided by two before entering FOD */ | |
487 | u32 f_in = parent_rate / 2; | |
488 | u32 div_int, div_frc; | |
489 | u8 od_int[2]; | |
490 | u8 od_frc[4]; | |
491 | ||
492 | regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), | |
493 | od_int, 2); | |
494 | regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), | |
495 | od_frc, 4); | |
496 | ||
497 | div_int = (od_int[0] << 4) | (od_int[1] >> 4); | |
498 | div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | | |
499 | (od_frc[2] << 6) | (od_frc[3] >> 2); | |
500 | ||
3bded569 MV |
501 | /* Avoid division by zero if the output is not configured. */ |
502 | if (div_int == 0 && div_frc == 0) | |
503 | return 0; | |
504 | ||
3e1aec4e MV |
505 | /* The PLL divider has 12 integer bits and 30 fractional bits */ |
506 | return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); | |
507 | } | |
508 | ||
509 | static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, | |
510 | unsigned long *parent_rate) | |
511 | { | |
512 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
513 | /* VCO frequency is divided by two before entering FOD */ | |
514 | u32 f_in = *parent_rate / 2; | |
515 | u32 div_int; | |
516 | u64 div_frc; | |
517 | ||
518 | /* Determine integer part, which is 12 bit wide */ | |
519 | div_int = f_in / rate; | |
520 | /* | |
521 | * WARNING: The clock chip does not output signal if the integer part | |
522 | * of the divider is 0xfff and fractional part is non-zero. | |
523 | * Clamp the divider at 0xffe to keep the code simple. | |
524 | */ | |
525 | if (div_int > 0xffe) { | |
526 | div_int = 0xffe; | |
527 | rate = f_in / div_int; | |
528 | } | |
529 | ||
530 | /* Determine best fractional part, which is 30 bit wide */ | |
531 | div_frc = f_in % rate; | |
532 | div_frc <<= 24; | |
533 | do_div(div_frc, rate); | |
534 | ||
535 | hwdata->div_int = div_int; | |
536 | hwdata->div_frc = (u32)div_frc; | |
537 | ||
538 | return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); | |
539 | } | |
540 | ||
541 | static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, | |
542 | unsigned long parent_rate) | |
543 | { | |
544 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); | |
545 | struct vc5_driver_data *vc5 = hwdata->vc5; | |
546 | u8 data[14] = { | |
547 | hwdata->div_frc >> 22, hwdata->div_frc >> 14, | |
548 | hwdata->div_frc >> 6, hwdata->div_frc << 2, | |
549 | 0, 0, 0, 0, 0, | |
550 | 0, 0, | |
551 | hwdata->div_int >> 4, hwdata->div_int << 4, | |
552 | 0 | |
553 | }; | |
554 | ||
555 | regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), | |
556 | data, 14); | |
557 | ||
558 | /* | |
559 | * Toggle magic bit in undocumented register for unknown reason. | |
560 | * This is what the IDT timing commander tool does and the chip | |
561 | * datasheet somewhat implies this is needed, but the register | |
562 | * and the bit is not documented. | |
563 | */ | |
564 | regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, | |
565 | VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0); | |
566 | regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, | |
567 | VC5_GLOBAL_REGISTER_GLOBAL_RESET, | |
568 | VC5_GLOBAL_REGISTER_GLOBAL_RESET); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static const struct clk_ops vc5_fod_ops = { | |
573 | .recalc_rate = vc5_fod_recalc_rate, | |
574 | .round_rate = vc5_fod_round_rate, | |
575 | .set_rate = vc5_fod_set_rate, | |
576 | }; | |
577 | ||
578 | static int vc5_clk_out_prepare(struct clk_hw *hw) | |
579 | { | |
3bca66b0 | 580 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
3e1aec4e | 581 | struct vc5_driver_data *vc5 = hwdata->vc5; |
718f4694 MV |
582 | const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | |
583 | VC5_OUT_DIV_CONTROL_SEL_EXT | | |
584 | VC5_OUT_DIV_CONTROL_EN_FOD; | |
585 | unsigned int src; | |
586 | int ret; | |
587 | ||
fc336ae6 LC |
588 | /* |
589 | * When enabling a FOD, all currently enabled FODs are briefly | |
590 | * stopped in order to synchronize all of them. This causes a clock | |
591 | * disruption to any unrelated chips that might be already using | |
592 | * other clock outputs. Bypass the sync feature to avoid the issue, | |
593 | * which is possible on the VersaClock 6E family via reserved | |
594 | * registers. | |
595 | */ | |
596 | if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { | |
597 | ret = regmap_update_bits(vc5->regmap, | |
598 | VC5_RESERVED_X0(hwdata->num), | |
599 | VC5_RESERVED_X0_BYPASS_SYNC, | |
600 | VC5_RESERVED_X0_BYPASS_SYNC); | |
601 | if (ret) | |
602 | return ret; | |
603 | } | |
604 | ||
718f4694 MV |
605 | /* |
606 | * If the input mux is disabled, enable it first and | |
607 | * select source from matching FOD. | |
608 | */ | |
609 | regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); | |
610 | if ((src & mask) == 0) { | |
611 | src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD; | |
612 | ret = regmap_update_bits(vc5->regmap, | |
613 | VC5_OUT_DIV_CONTROL(hwdata->num), | |
614 | mask | VC5_OUT_DIV_CONTROL_RESET, src); | |
615 | if (ret) | |
616 | return ret; | |
617 | } | |
3e1aec4e MV |
618 | |
619 | /* Enable the clock buffer */ | |
620 | regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), | |
621 | VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, | |
622 | VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); | |
260249f9 AF |
623 | if (hwdata->clk_output_cfg0_mask) { |
624 | dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n", | |
625 | hwdata->num, hwdata->clk_output_cfg0_mask, | |
626 | hwdata->clk_output_cfg0); | |
627 | ||
628 | regmap_update_bits(vc5->regmap, | |
629 | VC5_CLK_OUTPUT_CFG(hwdata->num, 0), | |
630 | hwdata->clk_output_cfg0_mask, | |
631 | hwdata->clk_output_cfg0); | |
632 | } | |
633 | ||
3e1aec4e MV |
634 | return 0; |
635 | } | |
636 | ||
637 | static void vc5_clk_out_unprepare(struct clk_hw *hw) | |
638 | { | |
3bca66b0 | 639 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
3e1aec4e MV |
640 | struct vc5_driver_data *vc5 = hwdata->vc5; |
641 | ||
a4decf58 | 642 | /* Disable the clock buffer */ |
3e1aec4e MV |
643 | regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), |
644 | VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0); | |
645 | } | |
646 | ||
647 | static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) | |
648 | { | |
3bca66b0 | 649 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
3e1aec4e MV |
650 | struct vc5_driver_data *vc5 = hwdata->vc5; |
651 | const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | | |
652 | VC5_OUT_DIV_CONTROL_SEL_EXT | | |
653 | VC5_OUT_DIV_CONTROL_EN_FOD; | |
654 | const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | | |
655 | VC5_OUT_DIV_CONTROL_EN_FOD; | |
656 | const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | | |
657 | VC5_OUT_DIV_CONTROL_SEL_EXT; | |
658 | unsigned int src; | |
659 | ||
660 | regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); | |
661 | src &= mask; | |
662 | ||
325b7b90 MV |
663 | if (src == 0) /* Input mux set to DISABLED */ |
664 | return 0; | |
665 | ||
3e1aec4e MV |
666 | if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) |
667 | return 0; | |
668 | ||
669 | if (src == extclk) | |
670 | return 1; | |
671 | ||
672 | dev_warn(&vc5->client->dev, | |
673 | "Invalid clock output configuration (%02x)\n", src); | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) | |
678 | { | |
3bca66b0 | 679 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
3e1aec4e MV |
680 | struct vc5_driver_data *vc5 = hwdata->vc5; |
681 | const u8 mask = VC5_OUT_DIV_CONTROL_RESET | | |
682 | VC5_OUT_DIV_CONTROL_SELB_NORM | | |
683 | VC5_OUT_DIV_CONTROL_SEL_EXT | | |
684 | VC5_OUT_DIV_CONTROL_EN_FOD; | |
685 | const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | | |
686 | VC5_OUT_DIV_CONTROL_SEL_EXT; | |
687 | u8 src = VC5_OUT_DIV_CONTROL_RESET; | |
688 | ||
689 | if (index == 0) | |
690 | src |= VC5_OUT_DIV_CONTROL_EN_FOD; | |
691 | else | |
692 | src |= extclk; | |
693 | ||
694 | return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), | |
695 | mask, src); | |
696 | } | |
697 | ||
698 | static const struct clk_ops vc5_clk_out_ops = { | |
699 | .prepare = vc5_clk_out_prepare, | |
700 | .unprepare = vc5_clk_out_unprepare, | |
701 | .set_parent = vc5_clk_out_set_parent, | |
702 | .get_parent = vc5_clk_out_get_parent, | |
703 | }; | |
704 | ||
705 | static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, | |
706 | void *data) | |
707 | { | |
708 | struct vc5_driver_data *vc5 = data; | |
709 | unsigned int idx = clkspec->args[0]; | |
710 | ||
9adddb01 | 711 | if (idx >= vc5->chip_info->clk_out_cnt) |
3e1aec4e MV |
712 | return ERR_PTR(-EINVAL); |
713 | ||
714 | return &vc5->clk_out[idx].hw; | |
715 | } | |
716 | ||
717 | static int vc5_map_index_to_output(const enum vc5_model model, | |
718 | const unsigned int n) | |
719 | { | |
720 | switch (model) { | |
721 | case IDT_VC5_5P49V5933: | |
722 | return (n == 0) ? 0 : 3; | |
723 | case IDT_VC5_5P49V5923: | |
b1911555 | 724 | case IDT_VC5_5P49V5925: |
1193e14f | 725 | case IDT_VC5_5P49V5935: |
dbf6b16f | 726 | case IDT_VC6_5P49V6901: |
2bda748e | 727 | case IDT_VC6_5P49V6965: |
3e1aec4e MV |
728 | default: |
729 | return n; | |
730 | } | |
731 | } | |
732 | ||
260249f9 | 733 | static int vc5_update_mode(struct device_node *np_output, |
3bca66b0 | 734 | struct vc5_out_data *clk_out) |
260249f9 AF |
735 | { |
736 | u32 value; | |
737 | ||
738 | if (!of_property_read_u32(np_output, "idt,mode", &value)) { | |
739 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK; | |
740 | switch (value) { | |
741 | case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL: | |
742 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOS: | |
743 | case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33: | |
744 | case VC5_CLK_OUTPUT_CFG0_CFG_LVDS: | |
745 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2: | |
746 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD: | |
747 | case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25: | |
748 | clk_out->clk_output_cfg0 |= | |
749 | value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT; | |
750 | break; | |
751 | default: | |
752 | return -EINVAL; | |
753 | } | |
754 | } | |
755 | return 0; | |
756 | } | |
757 | ||
758 | static int vc5_update_power(struct device_node *np_output, | |
3bca66b0 | 759 | struct vc5_out_data *clk_out) |
260249f9 AF |
760 | { |
761 | u32 value; | |
762 | ||
4b003f5f GU |
763 | if (!of_property_read_u32(np_output, "idt,voltage-microvolt", |
764 | &value)) { | |
260249f9 AF |
765 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK; |
766 | switch (value) { | |
767 | case 1800000: | |
768 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18; | |
769 | break; | |
770 | case 2500000: | |
771 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25; | |
772 | break; | |
773 | case 3300000: | |
774 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33; | |
775 | break; | |
776 | default: | |
777 | return -EINVAL; | |
778 | } | |
779 | } | |
780 | return 0; | |
781 | } | |
782 | ||
f3d661d6 AF |
783 | static int vc5_map_cap_value(u32 femtofarads) |
784 | { | |
785 | int mapped_value; | |
786 | ||
787 | /* | |
788 | * The datasheet explicitly states 9000 - 25000 with 0.5pF | |
789 | * steps, but the Programmer's guide shows the steps are 0.430pF. | |
790 | * After getting feedback from Renesas, the .5pF steps were the | |
791 | * goal, but 430nF was the actual values. | |
792 | * Because of this, the actual range goes to 22760 instead of 25000 | |
793 | */ | |
794 | if (femtofarads < 9000 || femtofarads > 22760) | |
795 | return -EINVAL; | |
796 | ||
797 | /* | |
798 | * The Programmer's guide shows XTAL[5:0] but in reality, | |
799 | * XTAL[0] and XTAL[1] are both LSB which makes the math | |
800 | * strange. With clarfication from Renesas, setting the | |
801 | * values should be simpler by ignoring XTAL[0] | |
802 | */ | |
803 | mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430); | |
804 | ||
805 | /* | |
806 | * Since the calculation ignores XTAL[0], there is one | |
807 | * special case where mapped_value = 32. In reality, this means | |
808 | * the real mapped value should be 111111b. In other cases, | |
809 | * the mapped_value needs to be shifted 1 to the left. | |
810 | */ | |
811 | if (mapped_value > 31) | |
812 | mapped_value = 0x3f; | |
813 | else | |
814 | mapped_value <<= 1; | |
815 | ||
816 | return mapped_value; | |
817 | } | |
818 | static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5) | |
819 | { | |
820 | u32 value; | |
821 | int mapped_value; | |
822 | ||
823 | if (!of_property_read_u32(node, "idt,xtal-load-femtofarads", &value)) { | |
824 | mapped_value = vc5_map_cap_value(value); | |
825 | if (mapped_value < 0) | |
826 | return mapped_value; | |
827 | ||
828 | /* | |
829 | * The mapped_value is really the high 6 bits of | |
830 | * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so | |
831 | * shift the value 2 places. | |
832 | */ | |
833 | regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, mapped_value << 2); | |
834 | regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, mapped_value << 2); | |
835 | } | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
260249f9 | 840 | static int vc5_update_slew(struct device_node *np_output, |
3bca66b0 | 841 | struct vc5_out_data *clk_out) |
260249f9 AF |
842 | { |
843 | u32 value; | |
844 | ||
845 | if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) { | |
846 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK; | |
847 | switch (value) { | |
848 | case 80: | |
849 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80; | |
850 | break; | |
851 | case 85: | |
852 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85; | |
853 | break; | |
854 | case 90: | |
855 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90; | |
856 | break; | |
857 | case 100: | |
858 | clk_out->clk_output_cfg0 |= | |
859 | VC5_CLK_OUTPUT_CFG0_SLEW_100; | |
860 | break; | |
861 | default: | |
862 | return -EINVAL; | |
863 | } | |
864 | } | |
865 | return 0; | |
866 | } | |
867 | ||
868 | static int vc5_get_output_config(struct i2c_client *client, | |
3bca66b0 | 869 | struct vc5_out_data *clk_out) |
260249f9 AF |
870 | { |
871 | struct device_node *np_output; | |
872 | char *child_name; | |
873 | int ret = 0; | |
874 | ||
875 | child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1); | |
faf29338 AF |
876 | if (!child_name) |
877 | return -ENOMEM; | |
878 | ||
260249f9 AF |
879 | np_output = of_get_child_by_name(client->dev.of_node, child_name); |
880 | kfree(child_name); | |
881 | if (!np_output) | |
faf29338 | 882 | return 0; |
260249f9 AF |
883 | |
884 | ret = vc5_update_mode(np_output, clk_out); | |
885 | if (ret) | |
886 | goto output_error; | |
887 | ||
888 | ret = vc5_update_power(np_output, clk_out); | |
889 | if (ret) | |
890 | goto output_error; | |
891 | ||
892 | ret = vc5_update_slew(np_output, clk_out); | |
893 | ||
894 | output_error: | |
895 | if (ret) { | |
896 | dev_err(&client->dev, | |
897 | "Invalid clock output configuration OUT%d\n", | |
898 | clk_out->num + 1); | |
899 | } | |
900 | ||
901 | of_node_put(np_output); | |
902 | ||
260249f9 AF |
903 | return ret; |
904 | } | |
905 | ||
3e1aec4e MV |
906 | static const struct of_device_id clk_vc5_of_match[]; |
907 | ||
5bba6d37 | 908 | static int vc5_probe(struct i2c_client *client) |
3e1aec4e | 909 | { |
d83e561d | 910 | unsigned int oe, sd, src_mask = 0, src_val = 0; |
3e1aec4e MV |
911 | struct vc5_driver_data *vc5; |
912 | struct clk_init_data init; | |
913 | const char *parent_names[2]; | |
9adddb01 | 914 | unsigned int n, idx = 0; |
3e1aec4e MV |
915 | int ret; |
916 | ||
917 | vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); | |
faf29338 | 918 | if (!vc5) |
3e1aec4e MV |
919 | return -ENOMEM; |
920 | ||
921 | i2c_set_clientdata(client, vc5); | |
922 | vc5->client = client; | |
9adddb01 | 923 | vc5->chip_info = of_device_get_match_data(&client->dev); |
3e1aec4e MV |
924 | |
925 | vc5->pin_xin = devm_clk_get(&client->dev, "xin"); | |
926 | if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) | |
927 | return -EPROBE_DEFER; | |
928 | ||
929 | vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); | |
930 | if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) | |
931 | return -EPROBE_DEFER; | |
932 | ||
933 | vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); | |
2ef16254 SA |
934 | if (IS_ERR(vc5->regmap)) |
935 | return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap), | |
936 | "failed to allocate register map\n"); | |
3e1aec4e | 937 | |
d83e561d SA |
938 | ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd); |
939 | if (!ret) { | |
940 | src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; | |
941 | if (sd) | |
942 | src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; | |
943 | } else if (ret != -EINVAL) { | |
944 | return dev_err_probe(&client->dev, ret, | |
945 | "could not read idt,shutdown\n"); | |
946 | } | |
947 | ||
948 | ret = of_property_read_u32(client->dev.of_node, | |
949 | "idt,output-enable-active", &oe); | |
950 | if (!ret) { | |
951 | src_mask |= VC5_PRIM_SRC_SHDN_SP; | |
952 | if (oe) | |
953 | src_val |= VC5_PRIM_SRC_SHDN_SP; | |
954 | } else if (ret != -EINVAL) { | |
955 | return dev_err_probe(&client->dev, ret, | |
956 | "could not read idt,output-enable-active\n"); | |
957 | } | |
958 | ||
959 | regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, src_val); | |
960 | ||
3e1aec4e MV |
961 | /* Register clock input mux */ |
962 | memset(&init, 0, sizeof(init)); | |
963 | ||
964 | if (!IS_ERR(vc5->pin_xin)) { | |
965 | vc5->clk_mux_ins |= VC5_MUX_IN_XIN; | |
966 | parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); | |
9adddb01 | 967 | } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { |
3e1aec4e MV |
968 | vc5->pin_xin = clk_register_fixed_rate(&client->dev, |
969 | "internal-xtal", NULL, | |
970 | 0, 25000000); | |
971 | if (IS_ERR(vc5->pin_xin)) | |
972 | return PTR_ERR(vc5->pin_xin); | |
973 | vc5->clk_mux_ins |= VC5_MUX_IN_XIN; | |
974 | parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); | |
975 | } | |
976 | ||
977 | if (!IS_ERR(vc5->pin_clkin)) { | |
978 | vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; | |
979 | parent_names[init.num_parents++] = | |
f491276a | 980 | __clk_get_name(vc5->pin_clkin); |
3e1aec4e MV |
981 | } |
982 | ||
2ef16254 SA |
983 | if (!init.num_parents) |
984 | return dev_err_probe(&client->dev, -EINVAL, | |
985 | "no input clock specified!\n"); | |
3e1aec4e | 986 | |
f3d661d6 AF |
987 | /* Configure Optional Loading Capacitance for external XTAL */ |
988 | if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) { | |
989 | ret = vc5_update_cap_load(client->dev.of_node, vc5); | |
990 | if (ret) | |
991 | goto err_clk_register; | |
992 | } | |
993 | ||
f491276a | 994 | init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node); |
3e1aec4e MV |
995 | init.ops = &vc5_mux_ops; |
996 | init.flags = 0; | |
997 | init.parent_names = parent_names; | |
998 | vc5->clk_mux.init = &init; | |
999 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); | |
8200597f CIK |
1000 | if (ret) |
1001 | goto err_clk_register; | |
f491276a | 1002 | kfree(init.name); /* clock framework made a copy of the name */ |
3e1aec4e | 1003 | |
8c1ebe97 MV |
1004 | if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { |
1005 | /* Register frequency doubler */ | |
1006 | memset(&init, 0, sizeof(init)); | |
f491276a AF |
1007 | init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl", |
1008 | client->dev.of_node); | |
8c1ebe97 MV |
1009 | init.ops = &vc5_dbl_ops; |
1010 | init.flags = CLK_SET_RATE_PARENT; | |
f491276a AF |
1011 | init.parent_names = parent_names; |
1012 | parent_names[0] = clk_hw_get_name(&vc5->clk_mux); | |
8c1ebe97 MV |
1013 | init.num_parents = 1; |
1014 | vc5->clk_mul.init = &init; | |
1015 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); | |
8200597f CIK |
1016 | if (ret) |
1017 | goto err_clk_register; | |
f491276a | 1018 | kfree(init.name); /* clock framework made a copy of the name */ |
8c1ebe97 MV |
1019 | } |
1020 | ||
55997db5 MV |
1021 | /* Register PFD */ |
1022 | memset(&init, 0, sizeof(init)); | |
f491276a | 1023 | init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node); |
55997db5 MV |
1024 | init.ops = &vc5_pfd_ops; |
1025 | init.flags = CLK_SET_RATE_PARENT; | |
f491276a | 1026 | init.parent_names = parent_names; |
8c1ebe97 | 1027 | if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) |
f491276a | 1028 | parent_names[0] = clk_hw_get_name(&vc5->clk_mul); |
8c1ebe97 | 1029 | else |
f491276a | 1030 | parent_names[0] = clk_hw_get_name(&vc5->clk_mux); |
55997db5 MV |
1031 | init.num_parents = 1; |
1032 | vc5->clk_pfd.init = &init; | |
1033 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd); | |
8200597f CIK |
1034 | if (ret) |
1035 | goto err_clk_register; | |
f491276a | 1036 | kfree(init.name); /* clock framework made a copy of the name */ |
55997db5 | 1037 | |
3e1aec4e MV |
1038 | /* Register PLL */ |
1039 | memset(&init, 0, sizeof(init)); | |
f491276a | 1040 | init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node); |
3e1aec4e MV |
1041 | init.ops = &vc5_pll_ops; |
1042 | init.flags = CLK_SET_RATE_PARENT; | |
f491276a AF |
1043 | init.parent_names = parent_names; |
1044 | parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); | |
3e1aec4e MV |
1045 | init.num_parents = 1; |
1046 | vc5->clk_pll.num = 0; | |
1047 | vc5->clk_pll.vc5 = vc5; | |
1048 | vc5->clk_pll.hw.init = &init; | |
1049 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); | |
8200597f CIK |
1050 | if (ret) |
1051 | goto err_clk_register; | |
f491276a | 1052 | kfree(init.name); /* clock framework made a copy of the name */ |
3e1aec4e MV |
1053 | |
1054 | /* Register FODs */ | |
9adddb01 AF |
1055 | for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { |
1056 | idx = vc5_map_index_to_output(vc5->chip_info->model, n); | |
3e1aec4e | 1057 | memset(&init, 0, sizeof(init)); |
f491276a AF |
1058 | init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d", |
1059 | client->dev.of_node, idx); | |
3e1aec4e MV |
1060 | init.ops = &vc5_fod_ops; |
1061 | init.flags = CLK_SET_RATE_PARENT; | |
f491276a AF |
1062 | init.parent_names = parent_names; |
1063 | parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); | |
3e1aec4e MV |
1064 | init.num_parents = 1; |
1065 | vc5->clk_fod[n].num = idx; | |
1066 | vc5->clk_fod[n].vc5 = vc5; | |
1067 | vc5->clk_fod[n].hw.init = &init; | |
1068 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); | |
8200597f CIK |
1069 | if (ret) |
1070 | goto err_clk_register; | |
f491276a | 1071 | kfree(init.name); /* clock framework made a copy of the name */ |
3e1aec4e MV |
1072 | } |
1073 | ||
1074 | /* Register MUX-connected OUT0_I2C_SELB output */ | |
1075 | memset(&init, 0, sizeof(init)); | |
f491276a AF |
1076 | init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb", |
1077 | client->dev.of_node); | |
3e1aec4e MV |
1078 | init.ops = &vc5_clk_out_ops; |
1079 | init.flags = CLK_SET_RATE_PARENT; | |
f491276a AF |
1080 | init.parent_names = parent_names; |
1081 | parent_names[0] = clk_hw_get_name(&vc5->clk_mux); | |
3e1aec4e MV |
1082 | init.num_parents = 1; |
1083 | vc5->clk_out[0].num = idx; | |
1084 | vc5->clk_out[0].vc5 = vc5; | |
1085 | vc5->clk_out[0].hw.init = &init; | |
1086 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); | |
8200597f CIK |
1087 | if (ret) |
1088 | goto err_clk_register; | |
1089 | kfree(init.name); /* clock framework made a copy of the name */ | |
3e1aec4e MV |
1090 | |
1091 | /* Register FOD-connected OUTx outputs */ | |
9adddb01 AF |
1092 | for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { |
1093 | idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1); | |
f491276a | 1094 | parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); |
3e1aec4e | 1095 | if (n == 1) |
f491276a | 1096 | parent_names[1] = clk_hw_get_name(&vc5->clk_mux); |
3e1aec4e | 1097 | else |
f491276a AF |
1098 | parent_names[1] = |
1099 | clk_hw_get_name(&vc5->clk_out[n - 1].hw); | |
3e1aec4e MV |
1100 | |
1101 | memset(&init, 0, sizeof(init)); | |
f491276a AF |
1102 | init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d", |
1103 | client->dev.of_node, idx + 1); | |
3e1aec4e MV |
1104 | init.ops = &vc5_clk_out_ops; |
1105 | init.flags = CLK_SET_RATE_PARENT; | |
1106 | init.parent_names = parent_names; | |
1107 | init.num_parents = 2; | |
1108 | vc5->clk_out[n].num = idx; | |
1109 | vc5->clk_out[n].vc5 = vc5; | |
1110 | vc5->clk_out[n].hw.init = &init; | |
f491276a | 1111 | ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw); |
8200597f CIK |
1112 | if (ret) |
1113 | goto err_clk_register; | |
f491276a | 1114 | kfree(init.name); /* clock framework made a copy of the name */ |
260249f9 AF |
1115 | |
1116 | /* Fetch Clock Output configuration from DT (if specified) */ | |
1117 | ret = vc5_get_output_config(client, &vc5->clk_out[n]); | |
1118 | if (ret) | |
1119 | goto err_clk; | |
3e1aec4e MV |
1120 | } |
1121 | ||
1122 | ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); | |
1123 | if (ret) { | |
2ef16254 SA |
1124 | dev_err_probe(&client->dev, ret, |
1125 | "unable to add clk provider\n"); | |
3e1aec4e MV |
1126 | goto err_clk; |
1127 | } | |
1128 | ||
1129 | return 0; | |
1130 | ||
8200597f | 1131 | err_clk_register: |
2ef16254 SA |
1132 | dev_err_probe(&client->dev, ret, |
1133 | "unable to register %s\n", init.name); | |
8200597f | 1134 | kfree(init.name); /* clock framework made a copy of the name */ |
3e1aec4e | 1135 | err_clk: |
9adddb01 | 1136 | if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) |
3e1aec4e MV |
1137 | clk_unregister_fixed_rate(vc5->pin_xin); |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | static int vc5_remove(struct i2c_client *client) | |
1142 | { | |
1143 | struct vc5_driver_data *vc5 = i2c_get_clientdata(client); | |
1144 | ||
1145 | of_clk_del_provider(client->dev.of_node); | |
1146 | ||
9adddb01 | 1147 | if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) |
3e1aec4e MV |
1148 | clk_unregister_fixed_rate(vc5->pin_xin); |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
8cbdc1f0 MV |
1153 | static int __maybe_unused vc5_suspend(struct device *dev) |
1154 | { | |
1155 | struct vc5_driver_data *vc5 = dev_get_drvdata(dev); | |
1156 | ||
1157 | regcache_cache_only(vc5->regmap, true); | |
1158 | regcache_mark_dirty(vc5->regmap); | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static int __maybe_unused vc5_resume(struct device *dev) | |
1164 | { | |
1165 | struct vc5_driver_data *vc5 = dev_get_drvdata(dev); | |
1166 | int ret; | |
1167 | ||
1168 | regcache_cache_only(vc5->regmap, false); | |
1169 | ret = regcache_sync(vc5->regmap); | |
1170 | if (ret) | |
1171 | dev_err(dev, "Failed to restore register map: %d\n", ret); | |
1172 | return ret; | |
1173 | } | |
1174 | ||
9adddb01 AF |
1175 | static const struct vc5_chip_info idt_5p49v5923_info = { |
1176 | .model = IDT_VC5_5P49V5923, | |
1177 | .clk_fod_cnt = 2, | |
1178 | .clk_out_cnt = 3, | |
1179 | .flags = 0, | |
1180 | }; | |
1181 | ||
b1911555 VB |
1182 | static const struct vc5_chip_info idt_5p49v5925_info = { |
1183 | .model = IDT_VC5_5P49V5925, | |
1184 | .clk_fod_cnt = 4, | |
1185 | .clk_out_cnt = 5, | |
1186 | .flags = 0, | |
1187 | }; | |
1188 | ||
9adddb01 AF |
1189 | static const struct vc5_chip_info idt_5p49v5933_info = { |
1190 | .model = IDT_VC5_5P49V5933, | |
1191 | .clk_fod_cnt = 2, | |
1192 | .clk_out_cnt = 3, | |
1193 | .flags = VC5_HAS_INTERNAL_XTAL, | |
1194 | }; | |
1195 | ||
1193e14f AF |
1196 | static const struct vc5_chip_info idt_5p49v5935_info = { |
1197 | .model = IDT_VC5_5P49V5935, | |
1198 | .clk_fod_cnt = 4, | |
1199 | .clk_out_cnt = 5, | |
1200 | .flags = VC5_HAS_INTERNAL_XTAL, | |
1201 | }; | |
1202 | ||
dbf6b16f MV |
1203 | static const struct vc5_chip_info idt_5p49v6901_info = { |
1204 | .model = IDT_VC6_5P49V6901, | |
1205 | .clk_fod_cnt = 4, | |
1206 | .clk_out_cnt = 5, | |
1207 | .flags = VC5_HAS_PFD_FREQ_DBL, | |
1208 | }; | |
1209 | ||
2bda748e AF |
1210 | static const struct vc5_chip_info idt_5p49v6965_info = { |
1211 | .model = IDT_VC6_5P49V6965, | |
1212 | .clk_fod_cnt = 4, | |
1213 | .clk_out_cnt = 5, | |
fc336ae6 | 1214 | .flags = VC5_HAS_BYPASS_SYNC_BIT, |
2bda748e AF |
1215 | }; |
1216 | ||
3e1aec4e MV |
1217 | static const struct i2c_device_id vc5_id[] = { |
1218 | { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 }, | |
b1911555 | 1219 | { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 }, |
3e1aec4e | 1220 | { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, |
1193e14f | 1221 | { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 }, |
dbf6b16f | 1222 | { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 }, |
2bda748e | 1223 | { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 }, |
3e1aec4e MV |
1224 | { } |
1225 | }; | |
1226 | MODULE_DEVICE_TABLE(i2c, vc5_id); | |
1227 | ||
1228 | static const struct of_device_id clk_vc5_of_match[] = { | |
9adddb01 | 1229 | { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info }, |
b1911555 | 1230 | { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info }, |
9adddb01 | 1231 | { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, |
1193e14f | 1232 | { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, |
dbf6b16f | 1233 | { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info }, |
2bda748e | 1234 | { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info }, |
3e1aec4e MV |
1235 | { }, |
1236 | }; | |
1237 | MODULE_DEVICE_TABLE(of, clk_vc5_of_match); | |
1238 | ||
8cbdc1f0 MV |
1239 | static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume); |
1240 | ||
3e1aec4e MV |
1241 | static struct i2c_driver vc5_driver = { |
1242 | .driver = { | |
1243 | .name = "vc5", | |
8cbdc1f0 | 1244 | .pm = &vc5_pm_ops, |
3e1aec4e MV |
1245 | .of_match_table = clk_vc5_of_match, |
1246 | }, | |
5bba6d37 | 1247 | .probe_new = vc5_probe, |
3e1aec4e MV |
1248 | .remove = vc5_remove, |
1249 | .id_table = vc5_id, | |
1250 | }; | |
1251 | module_i2c_driver(vc5_driver); | |
1252 | ||
1253 | MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); | |
1254 | MODULE_DESCRIPTION("IDT VersaClock 5 driver"); | |
1255 | MODULE_LICENSE("GPL"); |