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Merge branch 'clk-stm32f4' into clk-next
[linux-2.6-block.git] / drivers / clk / clk-stm32f4.c
CommitLineData
358bdf89
DT		 1/*
2 * Author: Daniel Thompson <daniel.thompson@linaro.org>
3 *
4 * Inspired by clk-asm9260.c .
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/err.h>
21#include <linux/io.h>
861adc44
GF		 22#include <linux/iopoll.h>
23#include <linux/ioport.h>
358bdf89
DT		 24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
861adc44
GF		 28#include <linux/regmap.h>
29#include <linux/mfd/syscon.h>
358bdf89 30
83135ad3
GF		 31/*
32 * Include list of clocks wich are not derived from system clock (SYSCLOCK)
33 * The index of these clocks is the secondary index of DT bindings
34 *
35 */
36#include <dt-bindings/clock/stm32fx-clock.h>
37
38#define STM32F4_RCC_CR 0x00
358bdf89
DT		 39#define STM32F4_RCC_PLLCFGR 0x04
40#define STM32F4_RCC_CFGR 0x08
41#define STM32F4_RCC_AHB1ENR 0x30
42#define STM32F4_RCC_AHB2ENR 0x34
43#define STM32F4_RCC_AHB3ENR 0x38
44#define STM32F4_RCC_APB1ENR 0x40
45#define STM32F4_RCC_APB2ENR 0x44
861adc44
GF		 46#define STM32F4_RCC_BDCR 0x70
47#define STM32F4_RCC_CSR 0x74
83135ad3
GF		 48#define STM32F4_RCC_PLLI2SCFGR 0x84
49#define STM32F4_RCC_PLLSAICFGR 0x88
517633ef
GF		 50#define STM32F4_RCC_DCKCFGR 0x8c
51
52#define NONE -1
53#define NO_IDX NONE
daf2d117
GF		 54#define NO_MUX NONE
55#define NO_GATE NONE
358bdf89
DT		 56
57struct stm32f4_gate_data {
58 u8 offset;
59 u8 bit_idx;
60 const char *name;
61 const char *parent_name;
62 unsigned long flags;
63};
64
a064a07f 65static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
358bdf89
DT		 66 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
67 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
68 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
69 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
70 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
71 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
72 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
73 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
74 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
75 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
76 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
77 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
78 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
79 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
80 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
81 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
82 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
83 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
84 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
85 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
86 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
87 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
88 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
89
90 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
91 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
92 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
93 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
94 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
95
96 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
97 CLK_IGNORE_UNUSED },
98
99 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
100 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
101 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
102 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
103 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
104 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
105 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
106 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
107 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
108 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
109 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
110 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
111 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
112 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
113 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
114 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
115 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
116 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
117 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
118 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
119 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
120 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
121 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
122 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
123 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
124
125 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
126 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
127 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
128 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
129 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
130 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
131 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
132 { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
133 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
134 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
135 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
136 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
137 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
138 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
139 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
140 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
141 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
142 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
143};
144
a064a07f
GF		 145static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
146 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
147 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
148 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
149 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
150 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
151 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
152 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
153 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
154 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
155 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
156 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
157 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
158 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
159 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
160 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
161 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
162 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
163 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
164 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
165 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
166 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
167 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
168 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
169
170 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
171 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
172 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
173 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
174 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
175
176 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
177 CLK_IGNORE_UNUSED },
178 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
179 CLK_IGNORE_UNUSED },
180
181 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
182 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
183 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
184 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
185 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
186 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
187 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
188 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
189 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
190 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
191 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
192 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
193 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
194 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
195 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
196 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
197 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
198 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
199 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
200 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
201 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
202 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
203 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
204 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
205 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
206
207 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
208 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
209 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
210 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
211 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
212 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
213 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
844ca23f 214 { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
a064a07f
GF		 215 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
216 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
217 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
218 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
219 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
220 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
221 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
222 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
223 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
224 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
225};
226
358bdf89
DT		 227/*
228 * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
229 * have gate bits associated with them. Its combined hweight is 71.
230 */
a064a07f
GF		 231#define MAX_GATE_MAP 3
232
233static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
234 0x0000000000000001ull,
235 0x04777f33f6fec9ffull };
236
237static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
238 0x0000000000000003ull,
239 0x0c777f33f6fec9ffull };
240
241static const u64 *stm32f4_gate_map;
242
243static struct clk_hw **clks;
358bdf89 244
358bdf89
DT		 245static DEFINE_SPINLOCK(stm32f4_clk_lock);
246static void __iomem *base;
247
861adc44
GF		 248static struct regmap *pdrm;
249
358bdf89
DT		 250/*
251 * "Multiplier" device for APBx clocks.
252 *
253 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
254 * mode, they also tap out the one of the low order state bits to run the
255 * timers. ST datasheets represent this feature as a (conditional) clock
256 * multiplier.
257 */
258struct clk_apb_mul {
259 struct clk_hw hw;
260 u8 bit_idx;
261};
262
263#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
264
265static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
266 unsigned long parent_rate)
267{
268 struct clk_apb_mul *am = to_clk_apb_mul(hw);
269
270 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
271 return parent_rate * 2;
272
273 return parent_rate;
274}
275
276static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
277 unsigned long *prate)
278{
279 struct clk_apb_mul *am = to_clk_apb_mul(hw);
280 unsigned long mult = 1;
281
282 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
283 mult = 2;
284
98d8a60e 285 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
358bdf89
DT		 286 unsigned long best_parent = rate / mult;
287
17ae4b40 288 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
358bdf89
DT		 289 }
290
291 return *prate * mult;
292}
293
294static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
295 unsigned long parent_rate)
296{
297 /*
298 * We must report success but we can do so unconditionally because
299 * clk_apb_mul_round_rate returns values that ensure this call is a
300 * nop.
301 */
302
303 return 0;
304}
305
306static const struct clk_ops clk_apb_mul_factor_ops = {
307 .round_rate = clk_apb_mul_round_rate,
308 .set_rate = clk_apb_mul_set_rate,
309 .recalc_rate = clk_apb_mul_recalc_rate,
310};
311
312static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
313 const char *parent_name,
314 unsigned long flags, u8 bit_idx)
315{
316 struct clk_apb_mul *am;
317 struct clk_init_data init;
318 struct clk *clk;
319
320 am = kzalloc(sizeof(*am), GFP_KERNEL);
321 if (!am)
322 return ERR_PTR(-ENOMEM);
323
324 am->bit_idx = bit_idx;
325 am->hw.init = &init;
326
327 init.name = name;
328 init.ops = &clk_apb_mul_factor_ops;
329 init.flags = flags;
330 init.parent_names = &parent_name;
331 init.num_parents = 1;
332
333 clk = clk_register(dev, &am->hw);
334
335 if (IS_ERR(clk))
336 kfree(am);
337
338 return clk;
339}
340
83135ad3
GF		 341enum {
342 PLL,
343 PLL_I2S,
344 PLL_SAI,
345};
346
347static const struct clk_div_table pll_divp_table[] = {
348 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
349};
350
351static const struct clk_div_table pll_divr_table[] = {
352 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
353};
354
355struct stm32f4_pll {
356 spinlock_t *lock;
357 struct clk_gate gate;
358 u8 offset;
359 u8 bit_rdy_idx;
360 u8 status;
361 u8 n_start;
362};
363
364#define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
365
517633ef
GF		 366struct stm32f4_pll_post_div_data {
367 int idx;
368 u8 pll_num;
369 const char *name;
370 const char *parent;
371 u8 flag;
372 u8 offset;
373 u8 shift;
374 u8 width;
375 u8 flag_div;
376 const struct clk_div_table *div_table;
377};
378
83135ad3
GF		 379struct stm32f4_vco_data {
380 const char *vco_name;
381 u8 offset;
382 u8 bit_idx;
383 u8 bit_rdy_idx;
384};
385
386static const struct stm32f4_vco_data vco_data[] = {
387 { "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
388 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
389 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
390};
391
517633ef
GF		 392
393static const struct clk_div_table post_divr_table[] = {
394 { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
395};
396
397#define MAX_POST_DIV 3
398static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
399 { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
400 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
401
402 { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
403 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
404
405 { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
406 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
407};
408
83135ad3
GF		 409struct stm32f4_div_data {
410 u8 shift;
411 u8 width;
412 u8 flag_div;
413 const struct clk_div_table *div_table;
414};
415
416#define MAX_PLL_DIV 3
417static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
418 { 16, 2, 0, pll_divp_table },
419 { 24, 4, CLK_DIVIDER_ONE_BASED, NULL },
420 { 28, 3, 0, pll_divr_table },
421};
422
423struct stm32f4_pll_data {
424 u8 pll_num;
425 u8 n_start;
426 const char *div_name[MAX_PLL_DIV];
427};
428
429static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
430 { PLL, 192, { "pll", "pll48", NULL } },
431 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
432 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
433};
434
435static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
436 { PLL, 50, { "pll", "pll-q", NULL } },
437 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
438 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
439};
440
441static int stm32f4_pll_is_enabled(struct clk_hw *hw)
442{
443 return clk_gate_ops.is_enabled(hw);
444}
445
446static int stm32f4_pll_enable(struct clk_hw *hw)
447{
448 struct clk_gate *gate = to_clk_gate(hw);
449 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
450 int ret = 0;
451 unsigned long reg;
452
453 ret = clk_gate_ops.enable(hw);
454
455 ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
456 reg & (1 << pll->bit_rdy_idx), 0, 10000);
457
458 return ret;
459}
460
461static void stm32f4_pll_disable(struct clk_hw *hw)
462{
463 clk_gate_ops.disable(hw);
464}
465
466static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
467 unsigned long parent_rate)
468{
469 struct clk_gate *gate = to_clk_gate(hw);
470 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
471 unsigned long n;
472
473 n = (readl(base + pll->offset) >> 6) & 0x1ff;
474
475 return parent_rate * n;
476}
477
478static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
479 unsigned long *prate)
358bdf89 480{
83135ad3
GF		 481 struct clk_gate *gate = to_clk_gate(hw);
482 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
483 unsigned long n;
358bdf89 484
83135ad3 485 n = rate / *prate;
358bdf89 486
83135ad3
GF		 487 if (n < pll->n_start)
488 n = pll->n_start;
489 else if (n > 432)
490 n = 432;
491
492 return *prate * n;
493}
494
495static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
496 unsigned long parent_rate)
497{
498 struct clk_gate *gate = to_clk_gate(hw);
499 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
500
501 unsigned long n;
502 unsigned long val;
503 int pll_state;
504
505 pll_state = stm32f4_pll_is_enabled(hw);
506
507 if (pll_state)
508 stm32f4_pll_disable(hw);
509
510 n = rate / parent_rate;
511
512 val = readl(base + pll->offset) & ~(0x1ff << 6);
513
514 writel(val | ((n & 0x1ff) << 6), base + pll->offset);
515
516 if (pll_state)
517 stm32f4_pll_enable(hw);
518
519 return 0;
520}
521
522static const struct clk_ops stm32f4_pll_gate_ops = {
523 .enable = stm32f4_pll_enable,
524 .disable = stm32f4_pll_disable,
525 .is_enabled = stm32f4_pll_is_enabled,
526 .recalc_rate = stm32f4_pll_recalc,
527 .round_rate = stm32f4_pll_round_rate,
528 .set_rate = stm32f4_pll_set_rate,
529};
530
531struct stm32f4_pll_div {
532 struct clk_divider div;
533 struct clk_hw *hw_pll;
534};
535
536#define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
537
538static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
539 unsigned long parent_rate)
540{
541 return clk_divider_ops.recalc_rate(hw, parent_rate);
542}
543
544static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
545 unsigned long *prate)
546{
547 return clk_divider_ops.round_rate(hw, rate, prate);
548}
549
550static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
551 unsigned long parent_rate)
358bdf89 552{
83135ad3
GF		 553 int pll_state, ret;
554
555 struct clk_divider *div = to_clk_divider(hw);
556 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
557
558 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
559
560 if (pll_state)
561 stm32f4_pll_disable(pll_div->hw_pll);
562
563 ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
358bdf89 564
83135ad3
GF		 565 if (pll_state)
566 stm32f4_pll_enable(pll_div->hw_pll);
358bdf89 567
83135ad3
GF		 568 return ret;
569}
570
571static const struct clk_ops stm32f4_pll_div_ops = {
572 .recalc_rate = stm32f4_pll_div_recalc_rate,
573 .round_rate = stm32f4_pll_div_round_rate,
574 .set_rate = stm32f4_pll_div_set_rate,
575};
576
577static struct clk_hw *clk_register_pll_div(const char *name,
578 const char *parent_name, unsigned long flags,
579 void __iomem *reg, u8 shift, u8 width,
580 u8 clk_divider_flags, const struct clk_div_table *table,
581 struct clk_hw *pll_hw, spinlock_t *lock)
582{
583 struct stm32f4_pll_div *pll_div;
584 struct clk_hw *hw;
585 struct clk_init_data init;
586 int ret;
587
588 /* allocate the divider */
589 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
590 if (!pll_div)
591 return ERR_PTR(-ENOMEM);
592
593 init.name = name;
594 init.ops = &stm32f4_pll_div_ops;
595 init.flags = flags;
596 init.parent_names = (parent_name ? &parent_name : NULL);
597 init.num_parents = (parent_name ? 1 : 0);
598
599 /* struct clk_divider assignments */
600 pll_div->div.reg = reg;
601 pll_div->div.shift = shift;
602 pll_div->div.width = width;
603 pll_div->div.flags = clk_divider_flags;
604 pll_div->div.lock = lock;
605 pll_div->div.table = table;
606 pll_div->div.hw.init = &init;
607
608 pll_div->hw_pll = pll_hw;
609
610 /* register the clock */
611 hw = &pll_div->div.hw;
612 ret = clk_hw_register(NULL, hw);
613 if (ret) {
614 kfree(pll_div);
615 hw = ERR_PTR(ret);
616 }
617
618 return hw;
619}
620
621static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
622 const struct stm32f4_pll_data *data, spinlock_t *lock)
623{
624 struct stm32f4_pll *pll;
625 struct clk_init_data init = { NULL };
626 void __iomem *reg;
627 struct clk_hw *pll_hw;
628 int ret;
629 int i;
630 const struct stm32f4_vco_data *vco;
631
632
633 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
634 if (!pll)
635 return ERR_PTR(-ENOMEM);
636
637 vco = &vco_data[data->pll_num];
638
639 init.name = vco->vco_name;
640 init.ops = &stm32f4_pll_gate_ops;
641 init.flags = CLK_SET_RATE_GATE;
642 init.parent_names = &pllsrc;
643 init.num_parents = 1;
644
645 pll->gate.lock = lock;
646 pll->gate.reg = base + STM32F4_RCC_CR;
647 pll->gate.bit_idx = vco->bit_idx;
648 pll->gate.hw.init = &init;
649
650 pll->offset = vco->offset;
651 pll->n_start = data->n_start;
652 pll->bit_rdy_idx = vco->bit_rdy_idx;
653 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
654
655 reg = base + pll->offset;
656
657 pll_hw = &pll->gate.hw;
658 ret = clk_hw_register(NULL, pll_hw);
659 if (ret) {
660 kfree(pll);
661 return ERR_PTR(ret);
662 }
663
664 for (i = 0; i < MAX_PLL_DIV; i++)
665 if (data->div_name[i])
666 clk_register_pll_div(data->div_name[i],
667 vco->vco_name,
668 0,
669 reg,
670 div_data[i].shift,
671 div_data[i].width,
672 div_data[i].flag_div,
673 div_data[i].div_table,
674 pll_hw,
675 lock);
676 return pll_hw;
358bdf89
DT		 677}
678
679/*
680 * Converts the primary and secondary indices (as they appear in DT) to an
681 * offset into our struct clock array.
682 */
683static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
684{
a064a07f 685 u64 table[MAX_GATE_MAP];
358bdf89
DT		 686
687 if (primary == 1) {
861adc44 688 if (WARN_ON(secondary >= END_PRIMARY_CLK))
358bdf89
DT		 689 return -EINVAL;
690 return secondary;
691 }
692
a064a07f 693 memcpy(table, stm32f4_gate_map, sizeof(table));
358bdf89
DT		 694
695 /* only bits set in table can be used as indices */
15ab3827 696 if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
358bdf89
DT		 697 0 == (table[BIT_ULL_WORD(secondary)] &
698 BIT_ULL_MASK(secondary))))
699 return -EINVAL;
700
701 /* mask out bits above our current index */
702 table[BIT_ULL_WORD(secondary)] &=
703 GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
704
861adc44 705 return END_PRIMARY_CLK - 1 + hweight64(table[0]) +
358bdf89
DT		 706 (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
707 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
708}
709
4e950d1e 710static struct clk_hw *
358bdf89
DT		 711stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
712{
713 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
714
715 if (i < 0)
716 return ERR_PTR(-EINVAL);
717
718 return clks[i];
719}
720
861adc44
GF		 721#define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
722
723static inline void disable_power_domain_write_protection(void)
724{
725 if (pdrm)
726 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
727}
728
729static inline void enable_power_domain_write_protection(void)
730{
731 if (pdrm)
732 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
733}
734
4261a881
GF		 735static inline void sofware_reset_backup_domain(void)
736{
737 unsigned long val;
738
739 val = readl(base + STM32F4_RCC_BDCR);
740 writel(val | BIT(16), base + STM32F4_RCC_BDCR);
741 writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
742}
743
861adc44
GF		 744struct stm32_rgate {
745 struct clk_gate gate;
746 u8 bit_rdy_idx;
747};
748
749#define RTC_TIMEOUT 1000000
750
751static int rgclk_enable(struct clk_hw *hw)
752{
753 struct clk_gate *gate = to_clk_gate(hw);
754 struct stm32_rgate *rgate = to_rgclk(gate);
755 u32 reg;
756 int ret;
757
758 disable_power_domain_write_protection();
759
760 clk_gate_ops.enable(hw);
761
762 ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
763 reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
764
765 enable_power_domain_write_protection();
766 return ret;
767}
768
769static void rgclk_disable(struct clk_hw *hw)
770{
771 clk_gate_ops.disable(hw);
772}
773
774static int rgclk_is_enabled(struct clk_hw *hw)
775{
776 return clk_gate_ops.is_enabled(hw);
777}
778
779static const struct clk_ops rgclk_ops = {
780 .enable = rgclk_enable,
781 .disable = rgclk_disable,
782 .is_enabled = rgclk_is_enabled,
783};
784
785static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
786 const char *parent_name, unsigned long flags,
787 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
788 u8 clk_gate_flags, spinlock_t *lock)
789{
790 struct stm32_rgate *rgate;
791 struct clk_init_data init = { NULL };
792 struct clk_hw *hw;
793 int ret;
794
795 rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
796 if (!rgate)
797 return ERR_PTR(-ENOMEM);
798
799 init.name = name;
800 init.ops = &rgclk_ops;
801 init.flags = flags;
802 init.parent_names = &parent_name;
803 init.num_parents = 1;
804
805 rgate->bit_rdy_idx = bit_rdy_idx;
806
807 rgate->gate.lock = lock;
808 rgate->gate.reg = reg;
809 rgate->gate.bit_idx = bit_idx;
810 rgate->gate.hw.init = &init;
811
812 hw = &rgate->gate.hw;
813 ret = clk_hw_register(dev, hw);
814 if (ret) {
815 kfree(rgate);
816 hw = ERR_PTR(ret);
817 }
818
819 return hw;
820}
821
4261a881
GF		 822static int cclk_gate_enable(struct clk_hw *hw)
823{
824 int ret;
825
826 disable_power_domain_write_protection();
827
828 ret = clk_gate_ops.enable(hw);
829
830 enable_power_domain_write_protection();
831
832 return ret;
833}
834
835static void cclk_gate_disable(struct clk_hw *hw)
836{
837 disable_power_domain_write_protection();
838
839 clk_gate_ops.disable(hw);
840
841 enable_power_domain_write_protection();
842}
843
844static int cclk_gate_is_enabled(struct clk_hw *hw)
845{
846 return clk_gate_ops.is_enabled(hw);
847}
848
849static const struct clk_ops cclk_gate_ops = {
850 .enable = cclk_gate_enable,
851 .disable = cclk_gate_disable,
852 .is_enabled = cclk_gate_is_enabled,
853};
854
855static u8 cclk_mux_get_parent(struct clk_hw *hw)
856{
857 return clk_mux_ops.get_parent(hw);
858}
859
860static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
861{
862 int ret;
863
864 disable_power_domain_write_protection();
865
866 sofware_reset_backup_domain();
867
868 ret = clk_mux_ops.set_parent(hw, index);
869
870 enable_power_domain_write_protection();
871
872 return ret;
873}
874
875static const struct clk_ops cclk_mux_ops = {
876 .get_parent = cclk_mux_get_parent,
877 .set_parent = cclk_mux_set_parent,
878};
879
880static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
881 const char * const *parent_names, int num_parents,
882 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
883 spinlock_t *lock)
884{
885 struct clk_hw *hw;
886 struct clk_gate *gate;
887 struct clk_mux *mux;
888
889 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
890 if (!gate) {
891 hw = ERR_PTR(-EINVAL);
892 goto fail;
893 }
894
895 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
896 if (!mux) {
897 kfree(gate);
898 hw = ERR_PTR(-EINVAL);
899 goto fail;
900 }
901
902 gate->reg = reg;
903 gate->bit_idx = bit_idx;
904 gate->flags = 0;
905 gate->lock = lock;
906
907 mux->reg = reg;
908 mux->shift = shift;
909 mux->mask = 3;
910 mux->flags = 0;
911
912 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
913 &mux->hw, &cclk_mux_ops,
914 NULL, NULL,
915 &gate->hw, &cclk_gate_ops,
916 flags);
917
918 if (IS_ERR(hw)) {
919 kfree(gate);
920 kfree(mux);
921 }
922
923fail:
924 return hw;
925}
926
358bdf89
DT		 927static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
928
929static const struct clk_div_table ahb_div_table[] = {
930 { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
931 { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
932 { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
933 { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
934 { 0 },
935};
936
937static const struct clk_div_table apb_div_table[] = {
938 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
939 { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
940 { 0 },
941};
942
4261a881
GF		 943static const char *rtc_parents[4] = {
944 "no-clock", "lse", "lsi", "hse-rtc"
945};
946
daf2d117
GF		 947static const char *lcd_parent[1] = { "pllsai-r-div" };
948
12696bac
GF		 949static const char *i2s_parents[2] = { "plli2s-r", NULL };
950
62710c12
GF		 951static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
952 "no-clock" };
953
844ca23f
GF		 954static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
955
956static const char *sdmux_parents[2] = { "pll48", "sys" };
957
daf2d117
GF		 958struct stm32_aux_clk {
959 int idx;
960 const char *name;
961 const char * const *parent_names;
962 int num_parents;
963 int offset_mux;
964 u8 shift;
965 u8 mask;
966 int offset_gate;
967 u8 bit_idx;
968 unsigned long flags;
969};
970
a064a07f
GF		 971struct stm32f4_clk_data {
972 const struct stm32f4_gate_data *gates_data;
973 const u64 *gates_map;
974 int gates_num;
83135ad3 975 const struct stm32f4_pll_data *pll_data;
daf2d117
GF		 976 const struct stm32_aux_clk *aux_clk;
977 int aux_clk_num;
978};
979
980static const struct stm32_aux_clk stm32f429_aux_clk[] = {
981 {
982 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
983 NO_MUX, 0, 0,
984 STM32F4_RCC_APB2ENR, 26,
985 CLK_SET_RATE_PARENT
986 },
12696bac
GF		 987 {
988 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
989 STM32F4_RCC_CFGR, 23, 1,
990 NO_GATE, 0,
991 CLK_SET_RATE_PARENT
992 },
62710c12
GF		 993 {
994 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
995 STM32F4_RCC_DCKCFGR, 20, 3,
996 STM32F4_RCC_APB2ENR, 22,
997 CLK_SET_RATE_PARENT
998 },
999 {
1000 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1001 STM32F4_RCC_DCKCFGR, 22, 3,
1002 STM32F4_RCC_APB2ENR, 22,
1003 CLK_SET_RATE_PARENT
1004 },
a064a07f
GF		 1005};
1006
844ca23f
GF		 1007static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1008 {
1009 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1010 NO_MUX, 0, 0,
1011 STM32F4_RCC_APB2ENR, 26,
1012 CLK_SET_RATE_PARENT
1013 },
1014 {
1015 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1016 STM32F4_RCC_CFGR, 23, 1,
1017 NO_GATE, 0,
1018 CLK_SET_RATE_PARENT
1019 },
1020 {
1021 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1022 STM32F4_RCC_DCKCFGR, 20, 3,
1023 STM32F4_RCC_APB2ENR, 22,
1024 CLK_SET_RATE_PARENT
1025 },
1026 {
1027 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1028 STM32F4_RCC_DCKCFGR, 22, 3,
1029 STM32F4_RCC_APB2ENR, 22,
1030 CLK_SET_RATE_PARENT
1031 },
1032 {
1033 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1034 STM32F4_RCC_DCKCFGR, 27, 1,
1035 NO_GATE, 0,
1036 0
1037 },
1038 {
1039 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1040 STM32F4_RCC_DCKCFGR, 28, 1,
1041 NO_GATE, 0,
1042 0
1043 },
a064a07f
GF		 1044};
1045
1046static const struct stm32f4_clk_data stm32f429_clk_data = {
1047 .gates_data = stm32f429_gates,
1048 .gates_map = stm32f42xx_gate_map,
1049 .gates_num = ARRAY_SIZE(stm32f429_gates),
83135ad3 1050 .pll_data = stm32f429_pll,
daf2d117
GF		 1051 .aux_clk = stm32f429_aux_clk,
1052 .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
a064a07f
GF		 1053};
1054
1055static const struct stm32f4_clk_data stm32f469_clk_data = {
1056 .gates_data = stm32f469_gates,
1057 .gates_map = stm32f46xx_gate_map,
1058 .gates_num = ARRAY_SIZE(stm32f469_gates),
83135ad3 1059 .pll_data = stm32f469_pll,
844ca23f
GF		 1060 .aux_clk = stm32f469_aux_clk,
1061 .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
a064a07f
GF		 1062};
1063
1064static const struct of_device_id stm32f4_of_match[] = {
1065 {
1066 .compatible = "st,stm32f42xx-rcc",
1067 .data = &stm32f429_clk_data
1068 },
1069 {
1070 .compatible = "st,stm32f469-rcc",
1071 .data = &stm32f469_clk_data
1072 },
1073 {}
1074};
1075
daf2d117
GF		 1076static struct clk_hw *stm32_register_aux_clk(const char *name,
1077 const char * const *parent_names, int num_parents,
1078 int offset_mux, u8 shift, u8 mask,
1079 int offset_gate, u8 bit_idx,
1080 unsigned long flags, spinlock_t *lock)
1081{
1082 struct clk_hw *hw;
89d5dcc4 1083 struct clk_gate *gate = NULL;
daf2d117
GF		 1084 struct clk_mux *mux = NULL;
1085 struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1086 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1087
1088 if (offset_gate != NO_GATE) {
1089 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1090 if (!gate) {
1091 hw = ERR_PTR(-EINVAL);
1092 goto fail;
1093 }
1094
1095 gate->reg = base + offset_gate;
1096 gate->bit_idx = bit_idx;
1097 gate->flags = 0;
1098 gate->lock = lock;
1099 gate_hw = &gate->hw;
1100 gate_ops = &clk_gate_ops;
1101 }
1102
1103 if (offset_mux != NO_MUX) {
1104 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1105 if (!mux) {
daf2d117
GF		 1106 hw = ERR_PTR(-EINVAL);
1107 goto fail;
1108 }
1109
1110 mux->reg = base + offset_mux;
1111 mux->shift = shift;
1112 mux->mask = mask;
1113 mux->flags = 0;
1114 mux_hw = &mux->hw;
1115 mux_ops = &clk_mux_ops;
1116 }
1117
89d5dcc4
AB		 1118 if (mux_hw == NULL && gate_hw == NULL) {
1119 hw = ERR_PTR(-EINVAL);
1120 goto fail;
1121 }
daf2d117
GF		 1122
1123 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1124 mux_hw, mux_ops,
1125 NULL, NULL,
1126 gate_hw, gate_ops,
1127 flags);
1128
89d5dcc4 1129fail:
daf2d117
GF		 1130 if (IS_ERR(hw)) {
1131 kfree(gate);
1132 kfree(mux);
1133 }
89d5dcc4 1134
daf2d117
GF		 1135 return hw;
1136}
1137
358bdf89
DT		 1138static void __init stm32f4_rcc_init(struct device_node *np)
1139{
12696bac 1140 const char *hse_clk, *i2s_in_clk;
358bdf89 1141 int n;
a064a07f
GF		 1142 const struct of_device_id *match;
1143 const struct stm32f4_clk_data *data;
83135ad3
GF		 1144 unsigned long pllcfgr;
1145 const char *pllsrc;
1146 unsigned long pllm;
358bdf89
DT		 1147
1148 base = of_iomap(np, 0);
1149 if (!base) {
1150 pr_err("%s: unable to map resource", np->name);
1151 return;
1152 }
1153
861adc44
GF		 1154 pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1155 if (IS_ERR(pdrm)) {
1156 pdrm = NULL;
1157 pr_warn("%s: Unable to get syscfg\n", __func__);
1158 }
1159
a064a07f
GF		 1160 match = of_match_node(stm32f4_of_match, np);
1161 if (WARN_ON(!match))
1162 return;
1163
1164 data = match->data;
1165
1166 clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
1167 sizeof(*clks), GFP_KERNEL);
1168 if (!clks)
1169 goto fail;
1170
1171 stm32f4_gate_map = data->gates_map;
1172
358bdf89
DT		 1173 hse_clk = of_clk_get_parent_name(np, 0);
1174
12696bac
GF		 1175 i2s_in_clk = of_clk_get_parent_name(np, 1);
1176
1177 i2s_parents[1] = i2s_in_clk;
62710c12 1178 sai_parents[2] = i2s_in_clk;
12696bac 1179
358bdf89
DT		 1180 clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
1181 16000000, 160000);
83135ad3
GF		 1182 pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
1183 pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
1184 pllm = pllcfgr & 0x3f;
1185
1186 clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
1187 0, 1, pllm);
1188
1189 stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1190 &stm32f4_clk_lock);
1191
1192 clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1193 &data->pll_data[1], &stm32f4_clk_lock);
1194
1195 clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1196 &data->pll_data[2], &stm32f4_clk_lock);
358bdf89 1197
517633ef
GF		 1198 for (n = 0; n < MAX_POST_DIV; n++) {
1199 const struct stm32f4_pll_post_div_data *post_div;
1200 struct clk_hw *hw;
1201
1202 post_div = &post_div_data[n];
1203
1204 hw = clk_register_pll_div(post_div->name,
1205 post_div->parent,
1206 post_div->flag,
1207 base + post_div->offset,
1208 post_div->shift,
1209 post_div->width,
1210 post_div->flag_div,
1211 post_div->div_table,
1212 clks[post_div->pll_num],
1213 &stm32f4_clk_lock);
1214
1215 if (post_div->idx != NO_IDX)
1216 clks[post_div->idx] = hw;
1217 }
358bdf89
DT		 1218
1219 sys_parents[1] = hse_clk;
1220 clk_register_mux_table(
1221 NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1222 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1223
1224 clk_register_divider_table(NULL, "ahb_div", "sys",
1225 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1226 4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1227
1228 clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1229 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1230 10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1231 clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1232 CLK_SET_RATE_PARENT, 12);
1233
1234 clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1235 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1236 13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1237 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1238 CLK_SET_RATE_PARENT, 15);
1239
4e950d1e 1240 clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
358bdf89 1241 0, 1, 8);
4e950d1e 1242 clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
358bdf89
DT		 1243 0, 1, 1);
1244
a064a07f
GF		 1245 for (n = 0; n < data->gates_num; n++) {
1246 const struct stm32f4_gate_data *gd;
1247 unsigned int secondary;
1248 int idx;
1249
1250 gd = &data->gates_data[n];
1251 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1252 gd->bit_idx;
1253 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
358bdf89
DT		 1254
1255 if (idx < 0)
1256 goto fail;
1257
4e950d1e 1258 clks[idx] = clk_hw_register_gate(
358bdf89
DT		 1259 NULL, gd->name, gd->parent_name, gd->flags,
1260 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1261
334e125b 1262 if (IS_ERR(clks[idx])) {
358bdf89
DT		 1263 pr_err("%s: Unable to register leaf clock %s\n",
1264 np->full_name, gd->name);
1265 goto fail;
1266 }
1267 }
1268
861adc44
GF		 1269 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1270 base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
1271
1272 if (IS_ERR(clks[CLK_LSI])) {
1273 pr_err("Unable to register lsi clock\n");
1274 goto fail;
1275 }
1276
1277 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1278 base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
1279
1280 if (IS_ERR(clks[CLK_LSE])) {
1281 pr_err("Unable to register lse clock\n");
1282 goto fail;
1283 }
1284
4261a881
GF		 1285 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1286 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1287 &stm32f4_clk_lock);
1288
1289 if (IS_ERR(clks[CLK_HSE_RTC])) {
1290 pr_err("Unable to register hse-rtc clock\n");
1291 goto fail;
1292 }
1293
1294 clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1295 base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1296
1297 if (IS_ERR(clks[CLK_RTC])) {
1298 pr_err("Unable to register rtc clock\n");
1299 goto fail;
1300 }
1301
daf2d117
GF		 1302 for (n = 0; n < data->aux_clk_num; n++) {
1303 const struct stm32_aux_clk *aux_clk;
1304 struct clk_hw *hw;
1305
1306 aux_clk = &data->aux_clk[n];
1307
1308 hw = stm32_register_aux_clk(aux_clk->name,
1309 aux_clk->parent_names, aux_clk->num_parents,
1310 aux_clk->offset_mux, aux_clk->shift,
1311 aux_clk->mask, aux_clk->offset_gate,
1312 aux_clk->bit_idx, aux_clk->flags,
1313 &stm32f4_clk_lock);
1314
1315 if (IS_ERR(hw)) {
1316 pr_warn("Unable to register %s clk\n", aux_clk->name);
1317 continue;
1318 }
1319
1320 if (aux_clk->idx != NO_IDX)
1321 clks[aux_clk->idx] = hw;
1322 }
1323
4e950d1e 1324 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
358bdf89
DT		 1325 return;
1326fail:
a064a07f 1327 kfree(clks);
358bdf89
DT		 1328 iounmap(base);
1329}
3868f132
GF		 1330CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1331CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
Linux 6.x block layer and io_uring tree(s)