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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
358bdf89 DT |
2 | /* |
3 | * Author: Daniel Thompson <daniel.thompson@linaro.org> | |
4 | * | |
5 | * Inspired by clk-asm9260.c . | |
358bdf89 DT |
6 | */ |
7 | ||
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/io.h> | |
861adc44 GF |
11 | #include <linux/iopoll.h> |
12 | #include <linux/ioport.h> | |
358bdf89 DT |
13 | #include <linux/slab.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
861adc44 GF |
17 | #include <linux/regmap.h> |
18 | #include <linux/mfd/syscon.h> | |
358bdf89 | 19 | |
83135ad3 GF |
20 | /* |
21 | * Include list of clocks wich are not derived from system clock (SYSCLOCK) | |
22 | * The index of these clocks is the secondary index of DT bindings | |
23 | * | |
24 | */ | |
25 | #include <dt-bindings/clock/stm32fx-clock.h> | |
26 | ||
27 | #define STM32F4_RCC_CR 0x00 | |
358bdf89 DT |
28 | #define STM32F4_RCC_PLLCFGR 0x04 |
29 | #define STM32F4_RCC_CFGR 0x08 | |
30 | #define STM32F4_RCC_AHB1ENR 0x30 | |
31 | #define STM32F4_RCC_AHB2ENR 0x34 | |
32 | #define STM32F4_RCC_AHB3ENR 0x38 | |
33 | #define STM32F4_RCC_APB1ENR 0x40 | |
34 | #define STM32F4_RCC_APB2ENR 0x44 | |
861adc44 GF |
35 | #define STM32F4_RCC_BDCR 0x70 |
36 | #define STM32F4_RCC_CSR 0x74 | |
83135ad3 GF |
37 | #define STM32F4_RCC_PLLI2SCFGR 0x84 |
38 | #define STM32F4_RCC_PLLSAICFGR 0x88 | |
517633ef | 39 | #define STM32F4_RCC_DCKCFGR 0x8c |
88c9b70b | 40 | #define STM32F7_RCC_DCKCFGR2 0x90 |
517633ef GF |
41 | |
42 | #define NONE -1 | |
43 | #define NO_IDX NONE | |
daf2d117 GF |
44 | #define NO_MUX NONE |
45 | #define NO_GATE NONE | |
358bdf89 DT |
46 | |
47 | struct stm32f4_gate_data { | |
48 | u8 offset; | |
49 | u8 bit_idx; | |
50 | const char *name; | |
51 | const char *parent_name; | |
52 | unsigned long flags; | |
53 | }; | |
54 | ||
a064a07f | 55 | static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { |
358bdf89 DT |
56 | { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, |
57 | { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, | |
58 | { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, | |
59 | { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, | |
60 | { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, | |
61 | { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, | |
62 | { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, | |
63 | { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, | |
64 | { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, | |
65 | { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, | |
66 | { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, | |
67 | { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, | |
68 | { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, | |
69 | { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, | |
70 | { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, | |
71 | { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, | |
72 | { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, | |
73 | { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, | |
74 | { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, | |
75 | { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, | |
76 | { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, | |
77 | { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, | |
78 | { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, | |
79 | ||
80 | { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, | |
81 | { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, | |
82 | { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, | |
83 | { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, | |
84 | { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, | |
85 | ||
86 | { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", | |
87 | CLK_IGNORE_UNUSED }, | |
88 | ||
89 | { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, | |
90 | { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, | |
91 | { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, | |
92 | { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, | |
93 | { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, | |
94 | { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, | |
95 | { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, | |
96 | { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, | |
97 | { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, | |
98 | { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, | |
99 | { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, | |
100 | { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, | |
101 | { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, | |
102 | { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, | |
103 | { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, | |
104 | { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, | |
105 | { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, | |
106 | { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, | |
107 | { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, | |
108 | { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, | |
109 | { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, | |
110 | { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, | |
111 | { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, | |
112 | { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, | |
113 | { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, | |
114 | ||
115 | { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, | |
116 | { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, | |
117 | { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, | |
118 | { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, | |
119 | { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, | |
120 | { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, | |
121 | { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, | |
122 | { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" }, | |
123 | { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, | |
124 | { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, | |
125 | { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, | |
126 | { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, | |
127 | { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, | |
128 | { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, | |
129 | { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, | |
130 | { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, | |
131 | { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, | |
358bdf89 DT |
132 | }; |
133 | ||
a064a07f GF |
134 | static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { |
135 | { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, | |
136 | { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, | |
137 | { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, | |
138 | { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, | |
139 | { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, | |
140 | { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, | |
141 | { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, | |
142 | { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, | |
143 | { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, | |
144 | { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, | |
145 | { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, | |
146 | { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, | |
147 | { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, | |
148 | { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, | |
149 | { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, | |
150 | { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, | |
151 | { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, | |
152 | { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, | |
153 | { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, | |
154 | { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, | |
155 | { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, | |
156 | { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, | |
157 | { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, | |
158 | ||
159 | { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, | |
160 | { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, | |
161 | { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, | |
162 | { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, | |
163 | { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, | |
164 | ||
165 | { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", | |
166 | CLK_IGNORE_UNUSED }, | |
167 | { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", | |
168 | CLK_IGNORE_UNUSED }, | |
169 | ||
170 | { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, | |
171 | { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, | |
172 | { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, | |
173 | { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, | |
174 | { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, | |
175 | { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, | |
176 | { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, | |
177 | { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, | |
178 | { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, | |
179 | { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, | |
180 | { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, | |
181 | { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, | |
182 | { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, | |
183 | { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, | |
184 | { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, | |
185 | { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, | |
186 | { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, | |
187 | { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, | |
188 | { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, | |
189 | { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, | |
190 | { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, | |
191 | { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, | |
192 | { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, | |
193 | { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, | |
194 | { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, | |
195 | ||
196 | { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, | |
197 | { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, | |
198 | { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, | |
199 | { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, | |
200 | { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, | |
201 | { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, | |
202 | { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, | |
844ca23f | 203 | { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" }, |
a064a07f GF |
204 | { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, |
205 | { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, | |
206 | { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, | |
207 | { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, | |
208 | { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, | |
209 | { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, | |
210 | { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, | |
211 | { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, | |
212 | { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, | |
a064a07f GF |
213 | }; |
214 | ||
88c9b70b GF |
215 | static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { |
216 | { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, | |
217 | { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, | |
218 | { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, | |
219 | { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, | |
220 | { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, | |
221 | { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, | |
222 | { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, | |
223 | { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, | |
224 | { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, | |
225 | { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, | |
226 | { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, | |
227 | { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, | |
228 | { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, | |
229 | { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" }, | |
230 | { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, | |
231 | { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, | |
232 | { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, | |
233 | { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, | |
234 | { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, | |
235 | { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, | |
236 | { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, | |
237 | { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, | |
238 | { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, | |
239 | ||
240 | { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, | |
241 | { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, | |
242 | { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, | |
243 | { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, | |
244 | { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, | |
245 | ||
246 | { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", | |
247 | CLK_IGNORE_UNUSED }, | |
248 | { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", | |
249 | CLK_IGNORE_UNUSED }, | |
250 | ||
251 | { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, | |
252 | { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, | |
253 | { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, | |
254 | { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, | |
255 | { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, | |
256 | { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, | |
257 | { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, | |
258 | { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, | |
259 | { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, | |
260 | { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, | |
261 | { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, | |
262 | { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, | |
263 | { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" }, | |
264 | { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, | |
265 | { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, | |
266 | { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" }, | |
267 | { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, | |
268 | { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, | |
269 | ||
270 | { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, | |
271 | { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, | |
f9acf105 | 272 | { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" }, |
88c9b70b GF |
273 | { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, |
274 | { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, | |
275 | { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, | |
276 | { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" }, | |
277 | { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, | |
278 | { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, | |
279 | { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, | |
280 | { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, | |
281 | { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, | |
282 | { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, | |
283 | { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, | |
284 | { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, | |
285 | { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, | |
286 | { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, | |
88c9b70b GF |
287 | }; |
288 | ||
936289f0 GF |
289 | static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { |
290 | { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, | |
291 | { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, | |
292 | { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, | |
293 | { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, | |
294 | { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, | |
295 | { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, | |
296 | { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, | |
297 | { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, | |
298 | { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, | |
299 | { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, | |
300 | { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, | |
301 | { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, | |
302 | { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, | |
303 | { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" }, | |
304 | { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, | |
305 | { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, | |
306 | { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, | |
307 | { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, | |
308 | { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, | |
309 | { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, | |
310 | { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, | |
311 | { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, | |
312 | { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, | |
313 | ||
314 | { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, | |
315 | { STM32F4_RCC_AHB2ENR, 1, "jpeg", "ahb_div" }, | |
316 | { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, | |
317 | { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, | |
318 | { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, | |
319 | { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, | |
320 | ||
321 | { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", | |
322 | CLK_IGNORE_UNUSED }, | |
323 | { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div", | |
324 | CLK_IGNORE_UNUSED }, | |
325 | ||
326 | { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, | |
327 | { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, | |
328 | { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, | |
329 | { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, | |
330 | { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, | |
331 | { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, | |
332 | { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, | |
333 | { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, | |
334 | { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, | |
335 | { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" }, | |
336 | { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, | |
337 | { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" }, | |
338 | { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, | |
339 | { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, | |
340 | { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" }, | |
341 | { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, | |
342 | { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, | |
343 | { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" }, | |
344 | { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, | |
345 | { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, | |
346 | ||
347 | { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, | |
348 | { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, | |
349 | { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux2" }, | |
350 | { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, | |
351 | { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, | |
352 | { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, | |
353 | { STM32F4_RCC_APB2ENR, 11, "sdmmc1", "sdmux1" }, | |
354 | { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, | |
355 | { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, | |
356 | { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, | |
357 | { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, | |
358 | { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, | |
359 | { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, | |
360 | { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, | |
361 | { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, | |
362 | { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, | |
363 | { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, | |
936289f0 GF |
364 | { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" }, |
365 | }; | |
366 | ||
358bdf89 DT |
367 | /* |
368 | * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx | |
369 | * have gate bits associated with them. Its combined hweight is 71. | |
370 | */ | |
a064a07f GF |
371 | #define MAX_GATE_MAP 3 |
372 | ||
373 | static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, | |
374 | 0x0000000000000001ull, | |
375 | 0x04777f33f6fec9ffull }; | |
376 | ||
377 | static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, | |
378 | 0x0000000000000003ull, | |
379 | 0x0c777f33f6fec9ffull }; | |
380 | ||
88c9b70b GF |
381 | static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, |
382 | 0x0000000000000003ull, | |
f9acf105 | 383 | 0x04f77f833e01c9ffull }; |
88c9b70b | 384 | |
936289f0 GF |
385 | static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull, |
386 | 0x0000000000000003ull, | |
387 | 0x44F77F833E01EDFFull }; | |
388 | ||
a064a07f GF |
389 | static const u64 *stm32f4_gate_map; |
390 | ||
391 | static struct clk_hw **clks; | |
358bdf89 | 392 | |
358bdf89 DT |
393 | static DEFINE_SPINLOCK(stm32f4_clk_lock); |
394 | static void __iomem *base; | |
395 | ||
861adc44 GF |
396 | static struct regmap *pdrm; |
397 | ||
88c9b70b GF |
398 | static int stm32fx_end_primary_clk; |
399 | ||
358bdf89 DT |
400 | /* |
401 | * "Multiplier" device for APBx clocks. | |
402 | * | |
403 | * The APBx dividers are power-of-two dividers and, if *not* running in 1:1 | |
404 | * mode, they also tap out the one of the low order state bits to run the | |
405 | * timers. ST datasheets represent this feature as a (conditional) clock | |
406 | * multiplier. | |
407 | */ | |
408 | struct clk_apb_mul { | |
409 | struct clk_hw hw; | |
410 | u8 bit_idx; | |
411 | }; | |
412 | ||
413 | #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw) | |
414 | ||
415 | static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw, | |
416 | unsigned long parent_rate) | |
417 | { | |
418 | struct clk_apb_mul *am = to_clk_apb_mul(hw); | |
419 | ||
420 | if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) | |
421 | return parent_rate * 2; | |
422 | ||
423 | return parent_rate; | |
424 | } | |
425 | ||
426 | static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, | |
427 | unsigned long *prate) | |
428 | { | |
429 | struct clk_apb_mul *am = to_clk_apb_mul(hw); | |
430 | unsigned long mult = 1; | |
431 | ||
432 | if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) | |
433 | mult = 2; | |
434 | ||
98d8a60e | 435 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
358bdf89 DT |
436 | unsigned long best_parent = rate / mult; |
437 | ||
17ae4b40 | 438 | *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); |
358bdf89 DT |
439 | } |
440 | ||
441 | return *prate * mult; | |
442 | } | |
443 | ||
444 | static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, | |
445 | unsigned long parent_rate) | |
446 | { | |
447 | /* | |
448 | * We must report success but we can do so unconditionally because | |
449 | * clk_apb_mul_round_rate returns values that ensure this call is a | |
450 | * nop. | |
451 | */ | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | static const struct clk_ops clk_apb_mul_factor_ops = { | |
457 | .round_rate = clk_apb_mul_round_rate, | |
458 | .set_rate = clk_apb_mul_set_rate, | |
459 | .recalc_rate = clk_apb_mul_recalc_rate, | |
460 | }; | |
461 | ||
462 | static struct clk *clk_register_apb_mul(struct device *dev, const char *name, | |
463 | const char *parent_name, | |
464 | unsigned long flags, u8 bit_idx) | |
465 | { | |
466 | struct clk_apb_mul *am; | |
467 | struct clk_init_data init; | |
468 | struct clk *clk; | |
469 | ||
470 | am = kzalloc(sizeof(*am), GFP_KERNEL); | |
471 | if (!am) | |
472 | return ERR_PTR(-ENOMEM); | |
473 | ||
474 | am->bit_idx = bit_idx; | |
475 | am->hw.init = &init; | |
476 | ||
477 | init.name = name; | |
478 | init.ops = &clk_apb_mul_factor_ops; | |
479 | init.flags = flags; | |
480 | init.parent_names = &parent_name; | |
481 | init.num_parents = 1; | |
482 | ||
483 | clk = clk_register(dev, &am->hw); | |
484 | ||
485 | if (IS_ERR(clk)) | |
486 | kfree(am); | |
487 | ||
488 | return clk; | |
489 | } | |
490 | ||
83135ad3 GF |
491 | enum { |
492 | PLL, | |
493 | PLL_I2S, | |
494 | PLL_SAI, | |
495 | }; | |
496 | ||
497 | static const struct clk_div_table pll_divp_table[] = { | |
498 | { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 } | |
499 | }; | |
500 | ||
ef189104 GF |
501 | static const struct clk_div_table pll_divq_table[] = { |
502 | { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, | |
503 | { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 }, | |
504 | { 14, 14 }, { 15, 15 }, | |
505 | { 0 } | |
506 | }; | |
507 | ||
83135ad3 GF |
508 | static const struct clk_div_table pll_divr_table[] = { |
509 | { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } | |
510 | }; | |
511 | ||
512 | struct stm32f4_pll { | |
513 | spinlock_t *lock; | |
514 | struct clk_gate gate; | |
515 | u8 offset; | |
516 | u8 bit_rdy_idx; | |
517 | u8 status; | |
518 | u8 n_start; | |
519 | }; | |
520 | ||
521 | #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) | |
522 | ||
517633ef GF |
523 | struct stm32f4_pll_post_div_data { |
524 | int idx; | |
24b5b197 | 525 | int pll_idx; |
517633ef GF |
526 | const char *name; |
527 | const char *parent; | |
528 | u8 flag; | |
529 | u8 offset; | |
530 | u8 shift; | |
531 | u8 width; | |
532 | u8 flag_div; | |
533 | const struct clk_div_table *div_table; | |
534 | }; | |
535 | ||
83135ad3 GF |
536 | struct stm32f4_vco_data { |
537 | const char *vco_name; | |
538 | u8 offset; | |
539 | u8 bit_idx; | |
540 | u8 bit_rdy_idx; | |
541 | }; | |
542 | ||
543 | static const struct stm32f4_vco_data vco_data[] = { | |
544 | { "vco", STM32F4_RCC_PLLCFGR, 24, 25 }, | |
545 | { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 }, | |
546 | { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 }, | |
547 | }; | |
548 | ||
517633ef GF |
549 | |
550 | static const struct clk_div_table post_divr_table[] = { | |
551 | { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 } | |
552 | }; | |
553 | ||
554 | #define MAX_POST_DIV 3 | |
555 | static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { | |
24b5b197 | 556 | { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", |
517633ef GF |
557 | CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, |
558 | ||
24b5b197 | 559 | { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", |
517633ef GF |
560 | CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, |
561 | ||
24b5b197 | 562 | { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, |
517633ef GF |
563 | STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, |
564 | }; | |
565 | ||
83135ad3 GF |
566 | struct stm32f4_div_data { |
567 | u8 shift; | |
568 | u8 width; | |
569 | u8 flag_div; | |
570 | const struct clk_div_table *div_table; | |
571 | }; | |
572 | ||
573 | #define MAX_PLL_DIV 3 | |
574 | static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { | |
ef189104 GF |
575 | { 16, 2, 0, pll_divp_table }, |
576 | { 24, 4, 0, pll_divq_table }, | |
577 | { 28, 3, 0, pll_divr_table }, | |
83135ad3 GF |
578 | }; |
579 | ||
580 | struct stm32f4_pll_data { | |
581 | u8 pll_num; | |
582 | u8 n_start; | |
583 | const char *div_name[MAX_PLL_DIV]; | |
584 | }; | |
585 | ||
586 | static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = { | |
587 | { PLL, 192, { "pll", "pll48", NULL } }, | |
588 | { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } }, | |
589 | { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } }, | |
590 | }; | |
591 | ||
592 | static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { | |
2f05b6b9 | 593 | { PLL, 50, { "pll", "pll-q", "pll-r" } }, |
83135ad3 GF |
594 | { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, |
595 | { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, | |
596 | }; | |
597 | ||
598 | static int stm32f4_pll_is_enabled(struct clk_hw *hw) | |
599 | { | |
600 | return clk_gate_ops.is_enabled(hw); | |
601 | } | |
602 | ||
ac03d8b3 GF |
603 | #define PLL_TIMEOUT 10000 |
604 | ||
83135ad3 GF |
605 | static int stm32f4_pll_enable(struct clk_hw *hw) |
606 | { | |
607 | struct clk_gate *gate = to_clk_gate(hw); | |
608 | struct stm32f4_pll *pll = to_stm32f4_pll(gate); | |
ac03d8b3 GF |
609 | int bit_status; |
610 | unsigned int timeout = PLL_TIMEOUT; | |
83135ad3 | 611 | |
ac03d8b3 GF |
612 | if (clk_gate_ops.is_enabled(hw)) |
613 | return 0; | |
614 | ||
615 | clk_gate_ops.enable(hw); | |
83135ad3 | 616 | |
ac03d8b3 GF |
617 | do { |
618 | bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); | |
83135ad3 | 619 | |
ac03d8b3 GF |
620 | } while (bit_status && --timeout); |
621 | ||
622 | return bit_status; | |
83135ad3 GF |
623 | } |
624 | ||
625 | static void stm32f4_pll_disable(struct clk_hw *hw) | |
626 | { | |
627 | clk_gate_ops.disable(hw); | |
628 | } | |
629 | ||
630 | static unsigned long stm32f4_pll_recalc(struct clk_hw *hw, | |
631 | unsigned long parent_rate) | |
632 | { | |
633 | struct clk_gate *gate = to_clk_gate(hw); | |
634 | struct stm32f4_pll *pll = to_stm32f4_pll(gate); | |
635 | unsigned long n; | |
636 | ||
637 | n = (readl(base + pll->offset) >> 6) & 0x1ff; | |
638 | ||
639 | return parent_rate * n; | |
640 | } | |
641 | ||
642 | static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
643 | unsigned long *prate) | |
358bdf89 | 644 | { |
83135ad3 GF |
645 | struct clk_gate *gate = to_clk_gate(hw); |
646 | struct stm32f4_pll *pll = to_stm32f4_pll(gate); | |
647 | unsigned long n; | |
358bdf89 | 648 | |
83135ad3 | 649 | n = rate / *prate; |
358bdf89 | 650 | |
83135ad3 GF |
651 | if (n < pll->n_start) |
652 | n = pll->n_start; | |
653 | else if (n > 432) | |
654 | n = 432; | |
655 | ||
656 | return *prate * n; | |
657 | } | |
658 | ||
659 | static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
660 | unsigned long parent_rate) | |
661 | { | |
662 | struct clk_gate *gate = to_clk_gate(hw); | |
663 | struct stm32f4_pll *pll = to_stm32f4_pll(gate); | |
664 | ||
665 | unsigned long n; | |
666 | unsigned long val; | |
667 | int pll_state; | |
668 | ||
669 | pll_state = stm32f4_pll_is_enabled(hw); | |
670 | ||
671 | if (pll_state) | |
672 | stm32f4_pll_disable(hw); | |
673 | ||
674 | n = rate / parent_rate; | |
675 | ||
676 | val = readl(base + pll->offset) & ~(0x1ff << 6); | |
677 | ||
678 | writel(val | ((n & 0x1ff) << 6), base + pll->offset); | |
679 | ||
680 | if (pll_state) | |
681 | stm32f4_pll_enable(hw); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | static const struct clk_ops stm32f4_pll_gate_ops = { | |
687 | .enable = stm32f4_pll_enable, | |
688 | .disable = stm32f4_pll_disable, | |
689 | .is_enabled = stm32f4_pll_is_enabled, | |
690 | .recalc_rate = stm32f4_pll_recalc, | |
691 | .round_rate = stm32f4_pll_round_rate, | |
692 | .set_rate = stm32f4_pll_set_rate, | |
693 | }; | |
694 | ||
695 | struct stm32f4_pll_div { | |
696 | struct clk_divider div; | |
697 | struct clk_hw *hw_pll; | |
698 | }; | |
699 | ||
700 | #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div) | |
701 | ||
702 | static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw, | |
703 | unsigned long parent_rate) | |
704 | { | |
705 | return clk_divider_ops.recalc_rate(hw, parent_rate); | |
706 | } | |
707 | ||
d1e40bc9 MB |
708 | static int stm32f4_pll_div_determine_rate(struct clk_hw *hw, |
709 | struct clk_rate_request *req) | |
83135ad3 | 710 | { |
d1e40bc9 | 711 | return clk_divider_ops.determine_rate(hw, req); |
83135ad3 GF |
712 | } |
713 | ||
714 | static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate, | |
715 | unsigned long parent_rate) | |
358bdf89 | 716 | { |
83135ad3 GF |
717 | int pll_state, ret; |
718 | ||
719 | struct clk_divider *div = to_clk_divider(hw); | |
720 | struct stm32f4_pll_div *pll_div = to_pll_div_clk(div); | |
721 | ||
722 | pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); | |
723 | ||
724 | if (pll_state) | |
725 | stm32f4_pll_disable(pll_div->hw_pll); | |
726 | ||
727 | ret = clk_divider_ops.set_rate(hw, rate, parent_rate); | |
358bdf89 | 728 | |
83135ad3 GF |
729 | if (pll_state) |
730 | stm32f4_pll_enable(pll_div->hw_pll); | |
358bdf89 | 731 | |
83135ad3 GF |
732 | return ret; |
733 | } | |
734 | ||
735 | static const struct clk_ops stm32f4_pll_div_ops = { | |
736 | .recalc_rate = stm32f4_pll_div_recalc_rate, | |
d1e40bc9 | 737 | .determine_rate = stm32f4_pll_div_determine_rate, |
83135ad3 GF |
738 | .set_rate = stm32f4_pll_div_set_rate, |
739 | }; | |
740 | ||
741 | static struct clk_hw *clk_register_pll_div(const char *name, | |
742 | const char *parent_name, unsigned long flags, | |
743 | void __iomem *reg, u8 shift, u8 width, | |
744 | u8 clk_divider_flags, const struct clk_div_table *table, | |
745 | struct clk_hw *pll_hw, spinlock_t *lock) | |
746 | { | |
747 | struct stm32f4_pll_div *pll_div; | |
748 | struct clk_hw *hw; | |
749 | struct clk_init_data init; | |
750 | int ret; | |
751 | ||
752 | /* allocate the divider */ | |
753 | pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL); | |
754 | if (!pll_div) | |
755 | return ERR_PTR(-ENOMEM); | |
756 | ||
757 | init.name = name; | |
758 | init.ops = &stm32f4_pll_div_ops; | |
759 | init.flags = flags; | |
760 | init.parent_names = (parent_name ? &parent_name : NULL); | |
761 | init.num_parents = (parent_name ? 1 : 0); | |
762 | ||
763 | /* struct clk_divider assignments */ | |
764 | pll_div->div.reg = reg; | |
765 | pll_div->div.shift = shift; | |
766 | pll_div->div.width = width; | |
767 | pll_div->div.flags = clk_divider_flags; | |
768 | pll_div->div.lock = lock; | |
769 | pll_div->div.table = table; | |
770 | pll_div->div.hw.init = &init; | |
771 | ||
772 | pll_div->hw_pll = pll_hw; | |
773 | ||
774 | /* register the clock */ | |
775 | hw = &pll_div->div.hw; | |
776 | ret = clk_hw_register(NULL, hw); | |
777 | if (ret) { | |
778 | kfree(pll_div); | |
779 | hw = ERR_PTR(ret); | |
780 | } | |
781 | ||
782 | return hw; | |
783 | } | |
784 | ||
785 | static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc, | |
786 | const struct stm32f4_pll_data *data, spinlock_t *lock) | |
787 | { | |
788 | struct stm32f4_pll *pll; | |
789 | struct clk_init_data init = { NULL }; | |
790 | void __iomem *reg; | |
791 | struct clk_hw *pll_hw; | |
792 | int ret; | |
793 | int i; | |
794 | const struct stm32f4_vco_data *vco; | |
795 | ||
796 | ||
797 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
798 | if (!pll) | |
799 | return ERR_PTR(-ENOMEM); | |
800 | ||
801 | vco = &vco_data[data->pll_num]; | |
802 | ||
803 | init.name = vco->vco_name; | |
804 | init.ops = &stm32f4_pll_gate_ops; | |
805 | init.flags = CLK_SET_RATE_GATE; | |
806 | init.parent_names = &pllsrc; | |
807 | init.num_parents = 1; | |
808 | ||
809 | pll->gate.lock = lock; | |
810 | pll->gate.reg = base + STM32F4_RCC_CR; | |
811 | pll->gate.bit_idx = vco->bit_idx; | |
812 | pll->gate.hw.init = &init; | |
813 | ||
814 | pll->offset = vco->offset; | |
815 | pll->n_start = data->n_start; | |
816 | pll->bit_rdy_idx = vco->bit_rdy_idx; | |
817 | pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; | |
818 | ||
819 | reg = base + pll->offset; | |
820 | ||
821 | pll_hw = &pll->gate.hw; | |
822 | ret = clk_hw_register(NULL, pll_hw); | |
823 | if (ret) { | |
824 | kfree(pll); | |
825 | return ERR_PTR(ret); | |
826 | } | |
827 | ||
828 | for (i = 0; i < MAX_PLL_DIV; i++) | |
829 | if (data->div_name[i]) | |
830 | clk_register_pll_div(data->div_name[i], | |
831 | vco->vco_name, | |
832 | 0, | |
833 | reg, | |
834 | div_data[i].shift, | |
835 | div_data[i].width, | |
836 | div_data[i].flag_div, | |
837 | div_data[i].div_table, | |
838 | pll_hw, | |
839 | lock); | |
840 | return pll_hw; | |
358bdf89 DT |
841 | } |
842 | ||
843 | /* | |
844 | * Converts the primary and secondary indices (as they appear in DT) to an | |
845 | * offset into our struct clock array. | |
846 | */ | |
847 | static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) | |
848 | { | |
a064a07f | 849 | u64 table[MAX_GATE_MAP]; |
358bdf89 DT |
850 | |
851 | if (primary == 1) { | |
88c9b70b | 852 | if (WARN_ON(secondary >= stm32fx_end_primary_clk)) |
358bdf89 DT |
853 | return -EINVAL; |
854 | return secondary; | |
855 | } | |
856 | ||
a064a07f | 857 | memcpy(table, stm32f4_gate_map, sizeof(table)); |
358bdf89 DT |
858 | |
859 | /* only bits set in table can be used as indices */ | |
15ab3827 | 860 | if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) || |
358bdf89 DT |
861 | 0 == (table[BIT_ULL_WORD(secondary)] & |
862 | BIT_ULL_MASK(secondary)))) | |
863 | return -EINVAL; | |
864 | ||
865 | /* mask out bits above our current index */ | |
866 | table[BIT_ULL_WORD(secondary)] &= | |
867 | GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); | |
868 | ||
88c9b70b | 869 | return stm32fx_end_primary_clk - 1 + hweight64(table[0]) + |
358bdf89 DT |
870 | (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) + |
871 | (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); | |
872 | } | |
873 | ||
4e950d1e | 874 | static struct clk_hw * |
358bdf89 DT |
875 | stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) |
876 | { | |
877 | int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]); | |
878 | ||
879 | if (i < 0) | |
880 | return ERR_PTR(-EINVAL); | |
881 | ||
882 | return clks[i]; | |
883 | } | |
884 | ||
861adc44 GF |
885 | #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate) |
886 | ||
887 | static inline void disable_power_domain_write_protection(void) | |
888 | { | |
889 | if (pdrm) | |
890 | regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8)); | |
891 | } | |
892 | ||
893 | static inline void enable_power_domain_write_protection(void) | |
894 | { | |
895 | if (pdrm) | |
896 | regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8)); | |
897 | } | |
898 | ||
4261a881 GF |
899 | static inline void sofware_reset_backup_domain(void) |
900 | { | |
901 | unsigned long val; | |
902 | ||
903 | val = readl(base + STM32F4_RCC_BDCR); | |
904 | writel(val | BIT(16), base + STM32F4_RCC_BDCR); | |
905 | writel(val & ~BIT(16), base + STM32F4_RCC_BDCR); | |
906 | } | |
907 | ||
861adc44 GF |
908 | struct stm32_rgate { |
909 | struct clk_gate gate; | |
910 | u8 bit_rdy_idx; | |
911 | }; | |
912 | ||
ac03d8b3 | 913 | #define RGATE_TIMEOUT 50000 |
861adc44 GF |
914 | |
915 | static int rgclk_enable(struct clk_hw *hw) | |
916 | { | |
917 | struct clk_gate *gate = to_clk_gate(hw); | |
918 | struct stm32_rgate *rgate = to_rgclk(gate); | |
ac03d8b3 GF |
919 | int bit_status; |
920 | unsigned int timeout = RGATE_TIMEOUT; | |
921 | ||
922 | if (clk_gate_ops.is_enabled(hw)) | |
923 | return 0; | |
861adc44 GF |
924 | |
925 | disable_power_domain_write_protection(); | |
926 | ||
927 | clk_gate_ops.enable(hw); | |
928 | ||
ac03d8b3 GF |
929 | do { |
930 | bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); | |
931 | if (bit_status) | |
932 | udelay(100); | |
933 | ||
934 | } while (bit_status && --timeout); | |
861adc44 GF |
935 | |
936 | enable_power_domain_write_protection(); | |
ac03d8b3 GF |
937 | |
938 | return bit_status; | |
861adc44 GF |
939 | } |
940 | ||
941 | static void rgclk_disable(struct clk_hw *hw) | |
942 | { | |
943 | clk_gate_ops.disable(hw); | |
944 | } | |
945 | ||
946 | static int rgclk_is_enabled(struct clk_hw *hw) | |
947 | { | |
948 | return clk_gate_ops.is_enabled(hw); | |
949 | } | |
950 | ||
951 | static const struct clk_ops rgclk_ops = { | |
952 | .enable = rgclk_enable, | |
953 | .disable = rgclk_disable, | |
954 | .is_enabled = rgclk_is_enabled, | |
955 | }; | |
956 | ||
957 | static struct clk_hw *clk_register_rgate(struct device *dev, const char *name, | |
958 | const char *parent_name, unsigned long flags, | |
959 | void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, | |
960 | u8 clk_gate_flags, spinlock_t *lock) | |
961 | { | |
962 | struct stm32_rgate *rgate; | |
963 | struct clk_init_data init = { NULL }; | |
964 | struct clk_hw *hw; | |
965 | int ret; | |
966 | ||
967 | rgate = kzalloc(sizeof(*rgate), GFP_KERNEL); | |
968 | if (!rgate) | |
969 | return ERR_PTR(-ENOMEM); | |
970 | ||
971 | init.name = name; | |
972 | init.ops = &rgclk_ops; | |
973 | init.flags = flags; | |
974 | init.parent_names = &parent_name; | |
975 | init.num_parents = 1; | |
976 | ||
977 | rgate->bit_rdy_idx = bit_rdy_idx; | |
978 | ||
979 | rgate->gate.lock = lock; | |
980 | rgate->gate.reg = reg; | |
981 | rgate->gate.bit_idx = bit_idx; | |
982 | rgate->gate.hw.init = &init; | |
983 | ||
984 | hw = &rgate->gate.hw; | |
985 | ret = clk_hw_register(dev, hw); | |
986 | if (ret) { | |
987 | kfree(rgate); | |
988 | hw = ERR_PTR(ret); | |
989 | } | |
990 | ||
991 | return hw; | |
992 | } | |
993 | ||
4261a881 GF |
994 | static int cclk_gate_enable(struct clk_hw *hw) |
995 | { | |
996 | int ret; | |
997 | ||
998 | disable_power_domain_write_protection(); | |
999 | ||
1000 | ret = clk_gate_ops.enable(hw); | |
1001 | ||
1002 | enable_power_domain_write_protection(); | |
1003 | ||
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | static void cclk_gate_disable(struct clk_hw *hw) | |
1008 | { | |
1009 | disable_power_domain_write_protection(); | |
1010 | ||
1011 | clk_gate_ops.disable(hw); | |
1012 | ||
1013 | enable_power_domain_write_protection(); | |
1014 | } | |
1015 | ||
1016 | static int cclk_gate_is_enabled(struct clk_hw *hw) | |
1017 | { | |
1018 | return clk_gate_ops.is_enabled(hw); | |
1019 | } | |
1020 | ||
1021 | static const struct clk_ops cclk_gate_ops = { | |
1022 | .enable = cclk_gate_enable, | |
1023 | .disable = cclk_gate_disable, | |
1024 | .is_enabled = cclk_gate_is_enabled, | |
1025 | }; | |
1026 | ||
1027 | static u8 cclk_mux_get_parent(struct clk_hw *hw) | |
1028 | { | |
1029 | return clk_mux_ops.get_parent(hw); | |
1030 | } | |
1031 | ||
1032 | static int cclk_mux_set_parent(struct clk_hw *hw, u8 index) | |
1033 | { | |
1034 | int ret; | |
1035 | ||
1036 | disable_power_domain_write_protection(); | |
1037 | ||
1038 | sofware_reset_backup_domain(); | |
1039 | ||
1040 | ret = clk_mux_ops.set_parent(hw, index); | |
1041 | ||
1042 | enable_power_domain_write_protection(); | |
1043 | ||
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | static const struct clk_ops cclk_mux_ops = { | |
5ce89dcc | 1048 | .determine_rate = clk_hw_determine_rate_no_reparent, |
4261a881 GF |
1049 | .get_parent = cclk_mux_get_parent, |
1050 | .set_parent = cclk_mux_set_parent, | |
1051 | }; | |
1052 | ||
1053 | static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, | |
1054 | const char * const *parent_names, int num_parents, | |
1055 | void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags, | |
1056 | spinlock_t *lock) | |
1057 | { | |
1058 | struct clk_hw *hw; | |
1059 | struct clk_gate *gate; | |
1060 | struct clk_mux *mux; | |
1061 | ||
1062 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
1063 | if (!gate) { | |
1064 | hw = ERR_PTR(-EINVAL); | |
1065 | goto fail; | |
1066 | } | |
1067 | ||
1068 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
1069 | if (!mux) { | |
1070 | kfree(gate); | |
1071 | hw = ERR_PTR(-EINVAL); | |
1072 | goto fail; | |
1073 | } | |
1074 | ||
1075 | gate->reg = reg; | |
1076 | gate->bit_idx = bit_idx; | |
1077 | gate->flags = 0; | |
1078 | gate->lock = lock; | |
1079 | ||
1080 | mux->reg = reg; | |
1081 | mux->shift = shift; | |
1082 | mux->mask = 3; | |
1083 | mux->flags = 0; | |
1084 | ||
1085 | hw = clk_hw_register_composite(dev, name, parent_names, num_parents, | |
1086 | &mux->hw, &cclk_mux_ops, | |
1087 | NULL, NULL, | |
1088 | &gate->hw, &cclk_gate_ops, | |
1089 | flags); | |
1090 | ||
1091 | if (IS_ERR(hw)) { | |
1092 | kfree(gate); | |
1093 | kfree(mux); | |
1094 | } | |
1095 | ||
1096 | fail: | |
1097 | return hw; | |
1098 | } | |
1099 | ||
358bdf89 DT |
1100 | static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" }; |
1101 | ||
1102 | static const struct clk_div_table ahb_div_table[] = { | |
1103 | { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, | |
1104 | { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 }, | |
1105 | { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 }, | |
1106 | { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 }, | |
1107 | { 0 }, | |
1108 | }; | |
1109 | ||
1110 | static const struct clk_div_table apb_div_table[] = { | |
1111 | { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, | |
1112 | { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 }, | |
1113 | { 0 }, | |
1114 | }; | |
1115 | ||
4261a881 GF |
1116 | static const char *rtc_parents[4] = { |
1117 | "no-clock", "lse", "lsi", "hse-rtc" | |
1118 | }; | |
1119 | ||
936289f0 GF |
1120 | static const char *pll_src = "pll-src"; |
1121 | ||
1122 | static const char *pllsrc_parent[2] = { "hsi", NULL }; | |
1123 | ||
2f05b6b9 GF |
1124 | static const char *dsi_parent[2] = { NULL, "pll-r" }; |
1125 | ||
daf2d117 GF |
1126 | static const char *lcd_parent[1] = { "pllsai-r-div" }; |
1127 | ||
12696bac GF |
1128 | static const char *i2s_parents[2] = { "plli2s-r", NULL }; |
1129 | ||
62710c12 GF |
1130 | static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL, |
1131 | "no-clock" }; | |
1132 | ||
844ca23f GF |
1133 | static const char *pll48_parents[2] = { "pll-q", "pllsai-p" }; |
1134 | ||
1135 | static const char *sdmux_parents[2] = { "pll48", "sys" }; | |
1136 | ||
88c9b70b GF |
1137 | static const char *hdmi_parents[2] = { "lse", "hsi_div488" }; |
1138 | ||
1139 | static const char *spdif_parent[1] = { "plli2s-p" }; | |
1140 | ||
1141 | static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" }; | |
1142 | ||
1143 | static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" }; | |
1144 | static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" }; | |
1145 | ||
1146 | static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" }; | |
1147 | ||
936289f0 GF |
1148 | static const char * const dfsdm1_src[] = { "apb2_div", "sys" }; |
1149 | static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" }; | |
1150 | ||
daf2d117 GF |
1151 | struct stm32_aux_clk { |
1152 | int idx; | |
1153 | const char *name; | |
1154 | const char * const *parent_names; | |
1155 | int num_parents; | |
1156 | int offset_mux; | |
1157 | u8 shift; | |
1158 | u8 mask; | |
1159 | int offset_gate; | |
1160 | u8 bit_idx; | |
1161 | unsigned long flags; | |
1162 | }; | |
1163 | ||
a064a07f GF |
1164 | struct stm32f4_clk_data { |
1165 | const struct stm32f4_gate_data *gates_data; | |
1166 | const u64 *gates_map; | |
1167 | int gates_num; | |
83135ad3 | 1168 | const struct stm32f4_pll_data *pll_data; |
daf2d117 GF |
1169 | const struct stm32_aux_clk *aux_clk; |
1170 | int aux_clk_num; | |
88c9b70b | 1171 | int end_primary; |
daf2d117 GF |
1172 | }; |
1173 | ||
1174 | static const struct stm32_aux_clk stm32f429_aux_clk[] = { | |
1175 | { | |
1176 | CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), | |
1177 | NO_MUX, 0, 0, | |
1178 | STM32F4_RCC_APB2ENR, 26, | |
1179 | CLK_SET_RATE_PARENT | |
1180 | }, | |
12696bac GF |
1181 | { |
1182 | CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), | |
1183 | STM32F4_RCC_CFGR, 23, 1, | |
1184 | NO_GATE, 0, | |
1185 | CLK_SET_RATE_PARENT | |
1186 | }, | |
62710c12 GF |
1187 | { |
1188 | CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), | |
1189 | STM32F4_RCC_DCKCFGR, 20, 3, | |
1190 | STM32F4_RCC_APB2ENR, 22, | |
1191 | CLK_SET_RATE_PARENT | |
1192 | }, | |
1193 | { | |
1194 | CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), | |
1195 | STM32F4_RCC_DCKCFGR, 22, 3, | |
1196 | STM32F4_RCC_APB2ENR, 22, | |
1197 | CLK_SET_RATE_PARENT | |
1198 | }, | |
a064a07f GF |
1199 | }; |
1200 | ||
844ca23f GF |
1201 | static const struct stm32_aux_clk stm32f469_aux_clk[] = { |
1202 | { | |
1203 | CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), | |
1204 | NO_MUX, 0, 0, | |
1205 | STM32F4_RCC_APB2ENR, 26, | |
1206 | CLK_SET_RATE_PARENT | |
1207 | }, | |
1208 | { | |
1209 | CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), | |
1210 | STM32F4_RCC_CFGR, 23, 1, | |
1211 | NO_GATE, 0, | |
1212 | CLK_SET_RATE_PARENT | |
1213 | }, | |
1214 | { | |
1215 | CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), | |
1216 | STM32F4_RCC_DCKCFGR, 20, 3, | |
1217 | STM32F4_RCC_APB2ENR, 22, | |
1218 | CLK_SET_RATE_PARENT | |
1219 | }, | |
1220 | { | |
1221 | CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), | |
1222 | STM32F4_RCC_DCKCFGR, 22, 3, | |
1223 | STM32F4_RCC_APB2ENR, 22, | |
1224 | CLK_SET_RATE_PARENT | |
1225 | }, | |
1226 | { | |
1227 | NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), | |
1228 | STM32F4_RCC_DCKCFGR, 27, 1, | |
1229 | NO_GATE, 0, | |
1230 | 0 | |
1231 | }, | |
1232 | { | |
1233 | NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents), | |
1234 | STM32F4_RCC_DCKCFGR, 28, 1, | |
1235 | NO_GATE, 0, | |
1236 | 0 | |
1237 | }, | |
2f05b6b9 GF |
1238 | { |
1239 | CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent), | |
1240 | STM32F4_RCC_DCKCFGR, 29, 1, | |
1241 | STM32F4_RCC_APB2ENR, 27, | |
1242 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | |
1243 | }, | |
a064a07f GF |
1244 | }; |
1245 | ||
88c9b70b GF |
1246 | static const struct stm32_aux_clk stm32f746_aux_clk[] = { |
1247 | { | |
1248 | CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), | |
1249 | NO_MUX, 0, 0, | |
1250 | STM32F4_RCC_APB2ENR, 26, | |
1251 | CLK_SET_RATE_PARENT | |
1252 | }, | |
1253 | { | |
1254 | CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), | |
1255 | STM32F4_RCC_CFGR, 23, 1, | |
1256 | NO_GATE, 0, | |
1257 | CLK_SET_RATE_PARENT | |
1258 | }, | |
1259 | { | |
1260 | CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents), | |
1261 | STM32F4_RCC_DCKCFGR, 20, 3, | |
1262 | STM32F4_RCC_APB2ENR, 22, | |
1263 | CLK_SET_RATE_PARENT | |
1264 | }, | |
1265 | { | |
1266 | CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents), | |
1267 | STM32F4_RCC_DCKCFGR, 22, 3, | |
1268 | STM32F4_RCC_APB2ENR, 23, | |
1269 | CLK_SET_RATE_PARENT | |
1270 | }, | |
1271 | { | |
1272 | NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), | |
1273 | STM32F7_RCC_DCKCFGR2, 27, 1, | |
1274 | NO_GATE, 0, | |
1275 | 0 | |
1276 | }, | |
1277 | { | |
1278 | NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents), | |
1279 | STM32F7_RCC_DCKCFGR2, 28, 1, | |
1280 | NO_GATE, 0, | |
1281 | 0 | |
1282 | }, | |
1283 | { | |
1284 | CLK_HDMI_CEC, "hdmi-cec", | |
1285 | hdmi_parents, ARRAY_SIZE(hdmi_parents), | |
1286 | STM32F7_RCC_DCKCFGR2, 26, 1, | |
1287 | NO_GATE, 0, | |
1288 | 0 | |
1289 | }, | |
1290 | { | |
1291 | CLK_SPDIF, "spdif-rx", | |
1292 | spdif_parent, ARRAY_SIZE(spdif_parent), | |
1293 | STM32F7_RCC_DCKCFGR2, 22, 3, | |
1294 | STM32F4_RCC_APB2ENR, 23, | |
1295 | CLK_SET_RATE_PARENT | |
1296 | }, | |
1297 | { | |
1298 | CLK_USART1, "usart1", | |
1299 | uart_parents1, ARRAY_SIZE(uart_parents1), | |
1300 | STM32F7_RCC_DCKCFGR2, 0, 3, | |
1301 | STM32F4_RCC_APB2ENR, 4, | |
1302 | CLK_SET_RATE_PARENT, | |
1303 | }, | |
1304 | { | |
1305 | CLK_USART2, "usart2", | |
1306 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1307 | STM32F7_RCC_DCKCFGR2, 2, 3, | |
1308 | STM32F4_RCC_APB1ENR, 17, | |
1309 | CLK_SET_RATE_PARENT, | |
1310 | }, | |
1311 | { | |
1312 | CLK_USART3, "usart3", | |
1313 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1314 | STM32F7_RCC_DCKCFGR2, 4, 3, | |
1315 | STM32F4_RCC_APB1ENR, 18, | |
1316 | CLK_SET_RATE_PARENT, | |
1317 | }, | |
1318 | { | |
1319 | CLK_UART4, "uart4", | |
1320 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1321 | STM32F7_RCC_DCKCFGR2, 6, 3, | |
1322 | STM32F4_RCC_APB1ENR, 19, | |
1323 | CLK_SET_RATE_PARENT, | |
1324 | }, | |
1325 | { | |
1326 | CLK_UART5, "uart5", | |
1327 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1328 | STM32F7_RCC_DCKCFGR2, 8, 3, | |
1329 | STM32F4_RCC_APB1ENR, 20, | |
1330 | CLK_SET_RATE_PARENT, | |
1331 | }, | |
1332 | { | |
1333 | CLK_USART6, "usart6", | |
1334 | uart_parents1, ARRAY_SIZE(uart_parents1), | |
1335 | STM32F7_RCC_DCKCFGR2, 10, 3, | |
1336 | STM32F4_RCC_APB2ENR, 5, | |
1337 | CLK_SET_RATE_PARENT, | |
1338 | }, | |
1339 | ||
1340 | { | |
1341 | CLK_UART7, "uart7", | |
1342 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1343 | STM32F7_RCC_DCKCFGR2, 12, 3, | |
1344 | STM32F4_RCC_APB1ENR, 30, | |
1345 | CLK_SET_RATE_PARENT, | |
1346 | }, | |
1347 | { | |
1348 | CLK_UART8, "uart8", | |
1349 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1350 | STM32F7_RCC_DCKCFGR2, 14, 3, | |
1351 | STM32F4_RCC_APB1ENR, 31, | |
1352 | CLK_SET_RATE_PARENT, | |
1353 | }, | |
1354 | { | |
1355 | CLK_I2C1, "i2c1", | |
1356 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1357 | STM32F7_RCC_DCKCFGR2, 16, 3, | |
1358 | STM32F4_RCC_APB1ENR, 21, | |
1359 | CLK_SET_RATE_PARENT, | |
1360 | }, | |
1361 | { | |
1362 | CLK_I2C2, "i2c2", | |
1363 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1364 | STM32F7_RCC_DCKCFGR2, 18, 3, | |
1365 | STM32F4_RCC_APB1ENR, 22, | |
1366 | CLK_SET_RATE_PARENT, | |
1367 | }, | |
1368 | { | |
1369 | CLK_I2C3, "i2c3", | |
1370 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1371 | STM32F7_RCC_DCKCFGR2, 20, 3, | |
1372 | STM32F4_RCC_APB1ENR, 23, | |
1373 | CLK_SET_RATE_PARENT, | |
1374 | }, | |
1375 | { | |
1376 | CLK_I2C4, "i2c4", | |
1377 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1378 | STM32F7_RCC_DCKCFGR2, 22, 3, | |
1379 | STM32F4_RCC_APB1ENR, 24, | |
1380 | CLK_SET_RATE_PARENT, | |
1381 | }, | |
1382 | ||
1383 | { | |
1384 | CLK_LPTIMER, "lptim1", | |
1385 | lptim_parent, ARRAY_SIZE(lptim_parent), | |
1386 | STM32F7_RCC_DCKCFGR2, 24, 3, | |
1387 | STM32F4_RCC_APB1ENR, 9, | |
1388 | CLK_SET_RATE_PARENT | |
1389 | }, | |
1390 | }; | |
1391 | ||
936289f0 GF |
1392 | static const struct stm32_aux_clk stm32f769_aux_clk[] = { |
1393 | { | |
1394 | CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent), | |
1395 | NO_MUX, 0, 0, | |
1396 | STM32F4_RCC_APB2ENR, 26, | |
1397 | CLK_SET_RATE_PARENT | |
1398 | }, | |
1399 | { | |
1400 | CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), | |
1401 | STM32F4_RCC_CFGR, 23, 1, | |
1402 | NO_GATE, 0, | |
1403 | CLK_SET_RATE_PARENT | |
1404 | }, | |
1405 | { | |
1406 | CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents), | |
1407 | STM32F4_RCC_DCKCFGR, 20, 3, | |
1408 | STM32F4_RCC_APB2ENR, 22, | |
1409 | CLK_SET_RATE_PARENT | |
1410 | }, | |
1411 | { | |
1412 | CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents), | |
1413 | STM32F4_RCC_DCKCFGR, 22, 3, | |
1414 | STM32F4_RCC_APB2ENR, 23, | |
1415 | CLK_SET_RATE_PARENT | |
1416 | }, | |
1417 | { | |
1418 | NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents), | |
1419 | STM32F7_RCC_DCKCFGR2, 27, 1, | |
1420 | NO_GATE, 0, | |
1421 | 0 | |
1422 | }, | |
1423 | { | |
1424 | NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents), | |
1425 | STM32F7_RCC_DCKCFGR2, 28, 1, | |
1426 | NO_GATE, 0, | |
1427 | 0 | |
1428 | }, | |
1429 | { | |
1430 | NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents), | |
1431 | STM32F7_RCC_DCKCFGR2, 29, 1, | |
1432 | NO_GATE, 0, | |
1433 | 0 | |
1434 | }, | |
1435 | { | |
1436 | CLK_HDMI_CEC, "hdmi-cec", | |
1437 | hdmi_parents, ARRAY_SIZE(hdmi_parents), | |
1438 | STM32F7_RCC_DCKCFGR2, 26, 1, | |
1439 | NO_GATE, 0, | |
1440 | 0 | |
1441 | }, | |
1442 | { | |
1443 | CLK_SPDIF, "spdif-rx", | |
1444 | spdif_parent, ARRAY_SIZE(spdif_parent), | |
1445 | STM32F7_RCC_DCKCFGR2, 22, 3, | |
1446 | STM32F4_RCC_APB2ENR, 23, | |
1447 | CLK_SET_RATE_PARENT | |
1448 | }, | |
1449 | { | |
1450 | CLK_USART1, "usart1", | |
1451 | uart_parents1, ARRAY_SIZE(uart_parents1), | |
1452 | STM32F7_RCC_DCKCFGR2, 0, 3, | |
1453 | STM32F4_RCC_APB2ENR, 4, | |
1454 | CLK_SET_RATE_PARENT, | |
1455 | }, | |
1456 | { | |
1457 | CLK_USART2, "usart2", | |
1458 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1459 | STM32F7_RCC_DCKCFGR2, 2, 3, | |
1460 | STM32F4_RCC_APB1ENR, 17, | |
1461 | CLK_SET_RATE_PARENT, | |
1462 | }, | |
1463 | { | |
1464 | CLK_USART3, "usart3", | |
1465 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1466 | STM32F7_RCC_DCKCFGR2, 4, 3, | |
1467 | STM32F4_RCC_APB1ENR, 18, | |
1468 | CLK_SET_RATE_PARENT, | |
1469 | }, | |
1470 | { | |
1471 | CLK_UART4, "uart4", | |
1472 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1473 | STM32F7_RCC_DCKCFGR2, 6, 3, | |
1474 | STM32F4_RCC_APB1ENR, 19, | |
1475 | CLK_SET_RATE_PARENT, | |
1476 | }, | |
1477 | { | |
1478 | CLK_UART5, "uart5", | |
1479 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1480 | STM32F7_RCC_DCKCFGR2, 8, 3, | |
1481 | STM32F4_RCC_APB1ENR, 20, | |
1482 | CLK_SET_RATE_PARENT, | |
1483 | }, | |
1484 | { | |
1485 | CLK_USART6, "usart6", | |
1486 | uart_parents1, ARRAY_SIZE(uart_parents1), | |
1487 | STM32F7_RCC_DCKCFGR2, 10, 3, | |
1488 | STM32F4_RCC_APB2ENR, 5, | |
1489 | CLK_SET_RATE_PARENT, | |
1490 | }, | |
1491 | { | |
1492 | CLK_UART7, "uart7", | |
1493 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1494 | STM32F7_RCC_DCKCFGR2, 12, 3, | |
1495 | STM32F4_RCC_APB1ENR, 30, | |
1496 | CLK_SET_RATE_PARENT, | |
1497 | }, | |
1498 | { | |
1499 | CLK_UART8, "uart8", | |
1500 | uart_parents2, ARRAY_SIZE(uart_parents1), | |
1501 | STM32F7_RCC_DCKCFGR2, 14, 3, | |
1502 | STM32F4_RCC_APB1ENR, 31, | |
1503 | CLK_SET_RATE_PARENT, | |
1504 | }, | |
1505 | { | |
1506 | CLK_I2C1, "i2c1", | |
1507 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1508 | STM32F7_RCC_DCKCFGR2, 16, 3, | |
1509 | STM32F4_RCC_APB1ENR, 21, | |
1510 | CLK_SET_RATE_PARENT, | |
1511 | }, | |
1512 | { | |
1513 | CLK_I2C2, "i2c2", | |
1514 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1515 | STM32F7_RCC_DCKCFGR2, 18, 3, | |
1516 | STM32F4_RCC_APB1ENR, 22, | |
1517 | CLK_SET_RATE_PARENT, | |
1518 | }, | |
1519 | { | |
1520 | CLK_I2C3, "i2c3", | |
1521 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1522 | STM32F7_RCC_DCKCFGR2, 20, 3, | |
1523 | STM32F4_RCC_APB1ENR, 23, | |
1524 | CLK_SET_RATE_PARENT, | |
1525 | }, | |
1526 | { | |
1527 | CLK_I2C4, "i2c4", | |
1528 | i2c_parents, ARRAY_SIZE(i2c_parents), | |
1529 | STM32F7_RCC_DCKCFGR2, 22, 3, | |
1530 | STM32F4_RCC_APB1ENR, 24, | |
1531 | CLK_SET_RATE_PARENT, | |
1532 | }, | |
1533 | { | |
1534 | CLK_LPTIMER, "lptim1", | |
1535 | lptim_parent, ARRAY_SIZE(lptim_parent), | |
1536 | STM32F7_RCC_DCKCFGR2, 24, 3, | |
1537 | STM32F4_RCC_APB1ENR, 9, | |
1538 | CLK_SET_RATE_PARENT | |
1539 | }, | |
1540 | { | |
1541 | CLK_F769_DSI, "dsi", | |
1542 | dsi_parent, ARRAY_SIZE(dsi_parent), | |
1543 | STM32F7_RCC_DCKCFGR2, 0, 1, | |
1544 | STM32F4_RCC_APB2ENR, 27, | |
1545 | CLK_SET_RATE_PARENT | |
1546 | }, | |
1547 | { | |
1548 | CLK_DFSDM1, "dfsdm1", | |
1549 | dfsdm1_src, ARRAY_SIZE(dfsdm1_src), | |
1550 | STM32F4_RCC_DCKCFGR, 25, 1, | |
1551 | STM32F4_RCC_APB2ENR, 29, | |
1552 | CLK_SET_RATE_PARENT | |
1553 | }, | |
1554 | { | |
1555 | CLK_ADFSDM1, "adfsdm1", | |
1556 | adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent), | |
1557 | STM32F4_RCC_DCKCFGR, 26, 1, | |
1558 | STM32F4_RCC_APB2ENR, 29, | |
1559 | CLK_SET_RATE_PARENT | |
1560 | }, | |
1561 | }; | |
1562 | ||
a064a07f | 1563 | static const struct stm32f4_clk_data stm32f429_clk_data = { |
88c9b70b | 1564 | .end_primary = END_PRIMARY_CLK, |
a064a07f GF |
1565 | .gates_data = stm32f429_gates, |
1566 | .gates_map = stm32f42xx_gate_map, | |
1567 | .gates_num = ARRAY_SIZE(stm32f429_gates), | |
83135ad3 | 1568 | .pll_data = stm32f429_pll, |
daf2d117 GF |
1569 | .aux_clk = stm32f429_aux_clk, |
1570 | .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk), | |
a064a07f GF |
1571 | }; |
1572 | ||
1573 | static const struct stm32f4_clk_data stm32f469_clk_data = { | |
88c9b70b | 1574 | .end_primary = END_PRIMARY_CLK, |
a064a07f GF |
1575 | .gates_data = stm32f469_gates, |
1576 | .gates_map = stm32f46xx_gate_map, | |
1577 | .gates_num = ARRAY_SIZE(stm32f469_gates), | |
83135ad3 | 1578 | .pll_data = stm32f469_pll, |
844ca23f GF |
1579 | .aux_clk = stm32f469_aux_clk, |
1580 | .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk), | |
a064a07f GF |
1581 | }; |
1582 | ||
88c9b70b GF |
1583 | static const struct stm32f4_clk_data stm32f746_clk_data = { |
1584 | .end_primary = END_PRIMARY_CLK_F7, | |
1585 | .gates_data = stm32f746_gates, | |
1586 | .gates_map = stm32f746_gate_map, | |
1587 | .gates_num = ARRAY_SIZE(stm32f746_gates), | |
1588 | .pll_data = stm32f469_pll, | |
1589 | .aux_clk = stm32f746_aux_clk, | |
1590 | .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk), | |
1591 | }; | |
1592 | ||
936289f0 GF |
1593 | static const struct stm32f4_clk_data stm32f769_clk_data = { |
1594 | .end_primary = END_PRIMARY_CLK_F7, | |
1595 | .gates_data = stm32f769_gates, | |
1596 | .gates_map = stm32f769_gate_map, | |
1597 | .gates_num = ARRAY_SIZE(stm32f769_gates), | |
1598 | .pll_data = stm32f469_pll, | |
1599 | .aux_clk = stm32f769_aux_clk, | |
1600 | .aux_clk_num = ARRAY_SIZE(stm32f769_aux_clk), | |
1601 | }; | |
1602 | ||
a064a07f GF |
1603 | static const struct of_device_id stm32f4_of_match[] = { |
1604 | { | |
1605 | .compatible = "st,stm32f42xx-rcc", | |
1606 | .data = &stm32f429_clk_data | |
1607 | }, | |
1608 | { | |
1609 | .compatible = "st,stm32f469-rcc", | |
1610 | .data = &stm32f469_clk_data | |
1611 | }, | |
88c9b70b GF |
1612 | { |
1613 | .compatible = "st,stm32f746-rcc", | |
1614 | .data = &stm32f746_clk_data | |
1615 | }, | |
936289f0 GF |
1616 | { |
1617 | .compatible = "st,stm32f769-rcc", | |
1618 | .data = &stm32f769_clk_data | |
1619 | }, | |
a064a07f GF |
1620 | {} |
1621 | }; | |
1622 | ||
daf2d117 GF |
1623 | static struct clk_hw *stm32_register_aux_clk(const char *name, |
1624 | const char * const *parent_names, int num_parents, | |
1625 | int offset_mux, u8 shift, u8 mask, | |
1626 | int offset_gate, u8 bit_idx, | |
1627 | unsigned long flags, spinlock_t *lock) | |
1628 | { | |
1629 | struct clk_hw *hw; | |
89d5dcc4 | 1630 | struct clk_gate *gate = NULL; |
daf2d117 GF |
1631 | struct clk_mux *mux = NULL; |
1632 | struct clk_hw *mux_hw = NULL, *gate_hw = NULL; | |
1633 | const struct clk_ops *mux_ops = NULL, *gate_ops = NULL; | |
1634 | ||
1635 | if (offset_gate != NO_GATE) { | |
1636 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
1637 | if (!gate) { | |
1638 | hw = ERR_PTR(-EINVAL); | |
1639 | goto fail; | |
1640 | } | |
1641 | ||
1642 | gate->reg = base + offset_gate; | |
1643 | gate->bit_idx = bit_idx; | |
1644 | gate->flags = 0; | |
1645 | gate->lock = lock; | |
1646 | gate_hw = &gate->hw; | |
1647 | gate_ops = &clk_gate_ops; | |
1648 | } | |
1649 | ||
1650 | if (offset_mux != NO_MUX) { | |
1651 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
1652 | if (!mux) { | |
daf2d117 GF |
1653 | hw = ERR_PTR(-EINVAL); |
1654 | goto fail; | |
1655 | } | |
1656 | ||
1657 | mux->reg = base + offset_mux; | |
1658 | mux->shift = shift; | |
1659 | mux->mask = mask; | |
1660 | mux->flags = 0; | |
1661 | mux_hw = &mux->hw; | |
1662 | mux_ops = &clk_mux_ops; | |
1663 | } | |
1664 | ||
89d5dcc4 AB |
1665 | if (mux_hw == NULL && gate_hw == NULL) { |
1666 | hw = ERR_PTR(-EINVAL); | |
1667 | goto fail; | |
1668 | } | |
daf2d117 GF |
1669 | |
1670 | hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, | |
1671 | mux_hw, mux_ops, | |
1672 | NULL, NULL, | |
1673 | gate_hw, gate_ops, | |
1674 | flags); | |
1675 | ||
89d5dcc4 | 1676 | fail: |
daf2d117 GF |
1677 | if (IS_ERR(hw)) { |
1678 | kfree(gate); | |
1679 | kfree(mux); | |
1680 | } | |
89d5dcc4 | 1681 | |
daf2d117 GF |
1682 | return hw; |
1683 | } | |
1684 | ||
358bdf89 DT |
1685 | static void __init stm32f4_rcc_init(struct device_node *np) |
1686 | { | |
12696bac | 1687 | const char *hse_clk, *i2s_in_clk; |
358bdf89 | 1688 | int n; |
a064a07f GF |
1689 | const struct of_device_id *match; |
1690 | const struct stm32f4_clk_data *data; | |
83135ad3 | 1691 | unsigned long pllm; |
936289f0 | 1692 | struct clk_hw *pll_src_hw; |
358bdf89 DT |
1693 | |
1694 | base = of_iomap(np, 0); | |
1695 | if (!base) { | |
e665f029 | 1696 | pr_err("%pOFn: unable to map resource\n", np); |
358bdf89 DT |
1697 | return; |
1698 | } | |
1699 | ||
861adc44 GF |
1700 | pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); |
1701 | if (IS_ERR(pdrm)) { | |
1702 | pdrm = NULL; | |
1703 | pr_warn("%s: Unable to get syscfg\n", __func__); | |
1704 | } | |
1705 | ||
a064a07f GF |
1706 | match = of_match_node(stm32f4_of_match, np); |
1707 | if (WARN_ON(!match)) | |
1708 | return; | |
1709 | ||
1710 | data = match->data; | |
1711 | ||
88c9b70b GF |
1712 | stm32fx_end_primary_clk = data->end_primary; |
1713 | ||
1714 | clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk, | |
a064a07f GF |
1715 | sizeof(*clks), GFP_KERNEL); |
1716 | if (!clks) | |
1717 | goto fail; | |
1718 | ||
1719 | stm32f4_gate_map = data->gates_map; | |
1720 | ||
358bdf89 | 1721 | hse_clk = of_clk_get_parent_name(np, 0); |
2f05b6b9 | 1722 | dsi_parent[0] = hse_clk; |
936289f0 | 1723 | pllsrc_parent[1] = hse_clk; |
358bdf89 | 1724 | |
12696bac GF |
1725 | i2s_in_clk = of_clk_get_parent_name(np, 1); |
1726 | ||
1727 | i2s_parents[1] = i2s_in_clk; | |
62710c12 | 1728 | sai_parents[2] = i2s_in_clk; |
12696bac | 1729 | |
936289f0 GF |
1730 | if (of_device_is_compatible(np, "st,stm32f769-rcc")) { |
1731 | clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0, | |
1732 | base + STM32F4_RCC_APB2ENR, 29, | |
1733 | CLK_IGNORE_UNUSED, &stm32f4_clk_lock); | |
1734 | dsi_parent[0] = pll_src; | |
1735 | sai_parents[3] = pll_src; | |
1736 | } | |
1737 | ||
88c9b70b GF |
1738 | clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi", |
1739 | NULL, 0, 16000000, 160000); | |
1740 | ||
936289f0 GF |
1741 | pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent, |
1742 | ARRAY_SIZE(pllsrc_parent), 0, | |
1743 | base + STM32F4_RCC_PLLCFGR, 22, 1, 0, | |
1744 | &stm32f4_clk_lock); | |
1745 | ||
1746 | pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f; | |
83135ad3 | 1747 | |
936289f0 GF |
1748 | clk_hw_register_fixed_factor(NULL, "vco_in", pll_src, |
1749 | 0, 1, pllm); | |
83135ad3 GF |
1750 | |
1751 | stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], | |
1752 | &stm32f4_clk_lock); | |
1753 | ||
1754 | clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in", | |
1755 | &data->pll_data[1], &stm32f4_clk_lock); | |
1756 | ||
1757 | clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in", | |
1758 | &data->pll_data[2], &stm32f4_clk_lock); | |
358bdf89 | 1759 | |
517633ef GF |
1760 | for (n = 0; n < MAX_POST_DIV; n++) { |
1761 | const struct stm32f4_pll_post_div_data *post_div; | |
1762 | struct clk_hw *hw; | |
1763 | ||
1764 | post_div = &post_div_data[n]; | |
1765 | ||
1766 | hw = clk_register_pll_div(post_div->name, | |
1767 | post_div->parent, | |
1768 | post_div->flag, | |
1769 | base + post_div->offset, | |
1770 | post_div->shift, | |
1771 | post_div->width, | |
1772 | post_div->flag_div, | |
1773 | post_div->div_table, | |
24b5b197 | 1774 | clks[post_div->pll_idx], |
517633ef GF |
1775 | &stm32f4_clk_lock); |
1776 | ||
1777 | if (post_div->idx != NO_IDX) | |
1778 | clks[post_div->idx] = hw; | |
1779 | } | |
358bdf89 DT |
1780 | |
1781 | sys_parents[1] = hse_clk; | |
88c9b70b GF |
1782 | |
1783 | clks[CLK_SYSCLK] = clk_hw_register_mux_table( | |
358bdf89 DT |
1784 | NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, |
1785 | base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); | |
1786 | ||
1787 | clk_register_divider_table(NULL, "ahb_div", "sys", | |
1788 | CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, | |
1789 | 4, 4, 0, ahb_div_table, &stm32f4_clk_lock); | |
1790 | ||
1791 | clk_register_divider_table(NULL, "apb1_div", "ahb_div", | |
1792 | CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, | |
1793 | 10, 3, 0, apb_div_table, &stm32f4_clk_lock); | |
1794 | clk_register_apb_mul(NULL, "apb1_mul", "apb1_div", | |
1795 | CLK_SET_RATE_PARENT, 12); | |
1796 | ||
1797 | clk_register_divider_table(NULL, "apb2_div", "ahb_div", | |
1798 | CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, | |
1799 | 13, 3, 0, apb_div_table, &stm32f4_clk_lock); | |
1800 | clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", | |
1801 | CLK_SET_RATE_PARENT, 15); | |
1802 | ||
4e950d1e | 1803 | clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div", |
358bdf89 | 1804 | 0, 1, 8); |
4e950d1e | 1805 | clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div", |
358bdf89 DT |
1806 | 0, 1, 1); |
1807 | ||
a064a07f GF |
1808 | for (n = 0; n < data->gates_num; n++) { |
1809 | const struct stm32f4_gate_data *gd; | |
1810 | unsigned int secondary; | |
1811 | int idx; | |
1812 | ||
1813 | gd = &data->gates_data[n]; | |
1814 | secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + | |
1815 | gd->bit_idx; | |
1816 | idx = stm32f4_rcc_lookup_clk_idx(0, secondary); | |
358bdf89 DT |
1817 | |
1818 | if (idx < 0) | |
1819 | goto fail; | |
1820 | ||
4e950d1e | 1821 | clks[idx] = clk_hw_register_gate( |
358bdf89 DT |
1822 | NULL, gd->name, gd->parent_name, gd->flags, |
1823 | base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); | |
1824 | ||
334e125b | 1825 | if (IS_ERR(clks[idx])) { |
16673931 RH |
1826 | pr_err("%pOF: Unable to register leaf clock %s\n", |
1827 | np, gd->name); | |
358bdf89 DT |
1828 | goto fail; |
1829 | } | |
1830 | } | |
1831 | ||
861adc44 | 1832 | clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, |
ac03d8b3 | 1833 | base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); |
861adc44 GF |
1834 | |
1835 | if (IS_ERR(clks[CLK_LSI])) { | |
1836 | pr_err("Unable to register lsi clock\n"); | |
1837 | goto fail; | |
1838 | } | |
1839 | ||
1840 | clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, | |
ac03d8b3 | 1841 | base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); |
861adc44 GF |
1842 | |
1843 | if (IS_ERR(clks[CLK_LSE])) { | |
1844 | pr_err("Unable to register lse clock\n"); | |
1845 | goto fail; | |
1846 | } | |
1847 | ||
4261a881 GF |
1848 | clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse", |
1849 | 0, base + STM32F4_RCC_CFGR, 16, 5, 0, | |
1850 | &stm32f4_clk_lock); | |
1851 | ||
1852 | if (IS_ERR(clks[CLK_HSE_RTC])) { | |
1853 | pr_err("Unable to register hse-rtc clock\n"); | |
1854 | goto fail; | |
1855 | } | |
1856 | ||
1857 | clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4, | |
1858 | base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock); | |
1859 | ||
1860 | if (IS_ERR(clks[CLK_RTC])) { | |
1861 | pr_err("Unable to register rtc clock\n"); | |
1862 | goto fail; | |
1863 | } | |
1864 | ||
daf2d117 GF |
1865 | for (n = 0; n < data->aux_clk_num; n++) { |
1866 | const struct stm32_aux_clk *aux_clk; | |
1867 | struct clk_hw *hw; | |
1868 | ||
1869 | aux_clk = &data->aux_clk[n]; | |
1870 | ||
1871 | hw = stm32_register_aux_clk(aux_clk->name, | |
1872 | aux_clk->parent_names, aux_clk->num_parents, | |
1873 | aux_clk->offset_mux, aux_clk->shift, | |
1874 | aux_clk->mask, aux_clk->offset_gate, | |
1875 | aux_clk->bit_idx, aux_clk->flags, | |
1876 | &stm32f4_clk_lock); | |
1877 | ||
1878 | if (IS_ERR(hw)) { | |
1879 | pr_warn("Unable to register %s clk\n", aux_clk->name); | |
1880 | continue; | |
1881 | } | |
1882 | ||
1883 | if (aux_clk->idx != NO_IDX) | |
1884 | clks[aux_clk->idx] = hw; | |
1885 | } | |
1886 | ||
936289f0 | 1887 | if (of_device_is_compatible(np, "st,stm32f746-rcc")) { |
88c9b70b GF |
1888 | |
1889 | clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0, | |
1890 | 1, 488); | |
1891 | ||
936289f0 GF |
1892 | clks[CLK_PLL_SRC] = pll_src_hw; |
1893 | } | |
1894 | ||
4e950d1e | 1895 | of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL); |
936289f0 | 1896 | |
358bdf89 DT |
1897 | return; |
1898 | fail: | |
a064a07f | 1899 | kfree(clks); |
358bdf89 DT |
1900 | iounmap(base); |
1901 | } | |
3868f132 GF |
1902 | CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init); |
1903 | CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init); | |
88c9b70b | 1904 | CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init); |
936289f0 | 1905 | CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init); |