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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9abd5f05 | 2 | /* |
dd5e1280 | 3 | * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator |
9abd5f05 SH |
4 | * |
5 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
6 | * Rabeeh Khoury <rabeeh@solid-run.com> | |
7 | * | |
8 | * References: | |
9 | * [1] "Si5351A/B/C Data Sheet" | |
dd5e1280 JR |
10 | * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf |
11 | * [2] "AN619: Manually Generating an Si5351 Register Map" | |
12 | * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf | |
9abd5f05 SH |
13 | */ |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
608f9b6e | 17 | #include <linux/clk.h> |
9abd5f05 SH |
18 | #include <linux/clk-provider.h> |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/rational.h> | |
23 | #include <linux/i2c.h> | |
a96cbb14 | 24 | #include <linux/of.h> |
9abd5f05 SH |
25 | #include <linux/platform_data/si5351.h> |
26 | #include <linux/regmap.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/string.h> | |
29 | #include <asm/div64.h> | |
30 | ||
31 | #include "clk-si5351.h" | |
32 | ||
33 | struct si5351_driver_data; | |
34 | ||
35 | struct si5351_parameters { | |
36 | unsigned long p1; | |
37 | unsigned long p2; | |
38 | unsigned long p3; | |
39 | int valid; | |
40 | }; | |
41 | ||
42 | struct si5351_hw_data { | |
43 | struct clk_hw hw; | |
44 | struct si5351_driver_data *drvdata; | |
45 | struct si5351_parameters params; | |
46 | unsigned char num; | |
47 | }; | |
48 | ||
49 | struct si5351_driver_data { | |
50 | enum si5351_variant variant; | |
51 | struct i2c_client *client; | |
52 | struct regmap *regmap; | |
9abd5f05 SH |
53 | |
54 | struct clk *pxtal; | |
55 | const char *pxtal_name; | |
56 | struct clk_hw xtal; | |
57 | struct clk *pclkin; | |
58 | const char *pclkin_name; | |
59 | struct clk_hw clkin; | |
60 | ||
61 | struct si5351_hw_data pll[2]; | |
62 | struct si5351_hw_data *msynth; | |
63 | struct si5351_hw_data *clkout; | |
4d89c3d5 | 64 | size_t num_clkout; |
9abd5f05 SH |
65 | }; |
66 | ||
8234caed | 67 | static const char * const si5351_input_names[] = { |
9abd5f05 SH |
68 | "xtal", "clkin" |
69 | }; | |
8234caed | 70 | static const char * const si5351_pll_names[] = { |
cdba9a4f | 71 | "si5351_plla", "si5351_pllb", "si5351_vxco" |
9abd5f05 | 72 | }; |
8234caed | 73 | static const char * const si5351_msynth_names[] = { |
9abd5f05 SH |
74 | "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7" |
75 | }; | |
8234caed | 76 | static const char * const si5351_clkout_names[] = { |
9abd5f05 SH |
77 | "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7" |
78 | }; | |
79 | ||
80 | /* | |
81 | * Si5351 i2c regmap | |
82 | */ | |
83 | static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg) | |
84 | { | |
85 | u32 val; | |
86 | int ret; | |
87 | ||
88 | ret = regmap_read(drvdata->regmap, reg, &val); | |
89 | if (ret) { | |
90 | dev_err(&drvdata->client->dev, | |
91 | "unable to read from reg%02x\n", reg); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | return (u8)val; | |
96 | } | |
97 | ||
98 | static inline int si5351_bulk_read(struct si5351_driver_data *drvdata, | |
99 | u8 reg, u8 count, u8 *buf) | |
100 | { | |
101 | return regmap_bulk_read(drvdata->regmap, reg, buf, count); | |
102 | } | |
103 | ||
104 | static inline int si5351_reg_write(struct si5351_driver_data *drvdata, | |
105 | u8 reg, u8 val) | |
106 | { | |
107 | return regmap_write(drvdata->regmap, reg, val); | |
108 | } | |
109 | ||
110 | static inline int si5351_bulk_write(struct si5351_driver_data *drvdata, | |
111 | u8 reg, u8 count, const u8 *buf) | |
112 | { | |
113 | return regmap_raw_write(drvdata->regmap, reg, buf, count); | |
114 | } | |
115 | ||
116 | static inline int si5351_set_bits(struct si5351_driver_data *drvdata, | |
117 | u8 reg, u8 mask, u8 val) | |
118 | { | |
119 | return regmap_update_bits(drvdata->regmap, reg, mask, val); | |
120 | } | |
121 | ||
122 | static inline u8 si5351_msynth_params_address(int num) | |
123 | { | |
124 | if (num > 5) | |
125 | return SI5351_CLK6_PARAMETERS + (num - 6); | |
126 | return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num); | |
127 | } | |
128 | ||
129 | static void si5351_read_parameters(struct si5351_driver_data *drvdata, | |
130 | u8 reg, struct si5351_parameters *params) | |
131 | { | |
132 | u8 buf[SI5351_PARAMETERS_LENGTH]; | |
133 | ||
134 | switch (reg) { | |
135 | case SI5351_CLK6_PARAMETERS: | |
136 | case SI5351_CLK7_PARAMETERS: | |
137 | buf[0] = si5351_reg_read(drvdata, reg); | |
138 | params->p1 = buf[0]; | |
139 | params->p2 = 0; | |
140 | params->p3 = 1; | |
141 | break; | |
142 | default: | |
143 | si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); | |
144 | params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; | |
145 | params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7]; | |
146 | params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1]; | |
147 | } | |
148 | params->valid = 1; | |
149 | } | |
150 | ||
151 | static void si5351_write_parameters(struct si5351_driver_data *drvdata, | |
152 | u8 reg, struct si5351_parameters *params) | |
153 | { | |
154 | u8 buf[SI5351_PARAMETERS_LENGTH]; | |
155 | ||
156 | switch (reg) { | |
157 | case SI5351_CLK6_PARAMETERS: | |
158 | case SI5351_CLK7_PARAMETERS: | |
159 | buf[0] = params->p1 & 0xff; | |
160 | si5351_reg_write(drvdata, reg, buf[0]); | |
161 | break; | |
162 | default: | |
163 | buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff; | |
164 | buf[1] = params->p3 & 0xff; | |
165 | /* save rdiv and divby4 */ | |
166 | buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03; | |
167 | buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; | |
168 | buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; | |
169 | buf[4] = params->p1 & 0xff; | |
170 | buf[5] = ((params->p3 & 0xf0000) >> 12) | | |
171 | ((params->p2 & 0xf0000) >> 16); | |
172 | buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff; | |
173 | buf[7] = params->p2 & 0xff; | |
174 | si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); | |
175 | } | |
176 | } | |
177 | ||
178 | static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg) | |
179 | { | |
180 | switch (reg) { | |
181 | case SI5351_DEVICE_STATUS: | |
182 | case SI5351_INTERRUPT_STATUS: | |
183 | case SI5351_PLL_RESET: | |
184 | return true; | |
185 | } | |
186 | return false; | |
187 | } | |
188 | ||
189 | static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg) | |
190 | { | |
191 | /* reserved registers */ | |
192 | if (reg >= 4 && reg <= 8) | |
193 | return false; | |
194 | if (reg >= 10 && reg <= 14) | |
195 | return false; | |
196 | if (reg >= 173 && reg <= 176) | |
197 | return false; | |
198 | if (reg >= 178 && reg <= 182) | |
199 | return false; | |
200 | /* read-only */ | |
201 | if (reg == SI5351_DEVICE_STATUS) | |
202 | return false; | |
203 | return true; | |
204 | } | |
205 | ||
8234caed | 206 | static const struct regmap_config si5351_regmap_config = { |
9abd5f05 SH |
207 | .reg_bits = 8, |
208 | .val_bits = 8, | |
41d22886 | 209 | .cache_type = REGCACHE_MAPLE, |
9abd5f05 SH |
210 | .max_register = 187, |
211 | .writeable_reg = si5351_regmap_is_writeable, | |
212 | .volatile_reg = si5351_regmap_is_volatile, | |
213 | }; | |
214 | ||
215 | /* | |
216 | * Si5351 xtal clock input | |
217 | */ | |
218 | static int si5351_xtal_prepare(struct clk_hw *hw) | |
219 | { | |
220 | struct si5351_driver_data *drvdata = | |
221 | container_of(hw, struct si5351_driver_data, xtal); | |
222 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, | |
223 | SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE); | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static void si5351_xtal_unprepare(struct clk_hw *hw) | |
228 | { | |
229 | struct si5351_driver_data *drvdata = | |
230 | container_of(hw, struct si5351_driver_data, xtal); | |
231 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, | |
232 | SI5351_XTAL_ENABLE, 0); | |
233 | } | |
234 | ||
235 | static const struct clk_ops si5351_xtal_ops = { | |
236 | .prepare = si5351_xtal_prepare, | |
237 | .unprepare = si5351_xtal_unprepare, | |
238 | }; | |
239 | ||
240 | /* | |
241 | * Si5351 clkin clock input (Si5351C only) | |
242 | */ | |
243 | static int si5351_clkin_prepare(struct clk_hw *hw) | |
244 | { | |
245 | struct si5351_driver_data *drvdata = | |
246 | container_of(hw, struct si5351_driver_data, clkin); | |
247 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, | |
248 | SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE); | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static void si5351_clkin_unprepare(struct clk_hw *hw) | |
253 | { | |
254 | struct si5351_driver_data *drvdata = | |
255 | container_of(hw, struct si5351_driver_data, clkin); | |
256 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, | |
257 | SI5351_CLKIN_ENABLE, 0); | |
258 | } | |
259 | ||
260 | /* | |
261 | * CMOS clock source constraints: | |
262 | * The input frequency range of the PLL is 10Mhz to 40MHz. | |
263 | * If CLKIN is >40MHz, the input divider must be used. | |
264 | */ | |
265 | static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw, | |
266 | unsigned long parent_rate) | |
267 | { | |
268 | struct si5351_driver_data *drvdata = | |
269 | container_of(hw, struct si5351_driver_data, clkin); | |
270 | unsigned long rate; | |
271 | unsigned char idiv; | |
272 | ||
273 | rate = parent_rate; | |
274 | if (parent_rate > 160000000) { | |
275 | idiv = SI5351_CLKIN_DIV_8; | |
276 | rate /= 8; | |
277 | } else if (parent_rate > 80000000) { | |
278 | idiv = SI5351_CLKIN_DIV_4; | |
279 | rate /= 4; | |
280 | } else if (parent_rate > 40000000) { | |
281 | idiv = SI5351_CLKIN_DIV_2; | |
282 | rate /= 2; | |
283 | } else { | |
284 | idiv = SI5351_CLKIN_DIV_1; | |
285 | } | |
286 | ||
287 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, | |
288 | SI5351_CLKIN_DIV_MASK, idiv); | |
289 | ||
290 | dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n", | |
291 | __func__, (1 << (idiv >> 6)), rate); | |
292 | ||
293 | return rate; | |
294 | } | |
295 | ||
296 | static const struct clk_ops si5351_clkin_ops = { | |
297 | .prepare = si5351_clkin_prepare, | |
298 | .unprepare = si5351_clkin_unprepare, | |
299 | .recalc_rate = si5351_clkin_recalc_rate, | |
300 | }; | |
301 | ||
302 | /* | |
303 | * Si5351 vxco clock input (Si5351B only) | |
304 | */ | |
305 | ||
306 | static int si5351_vxco_prepare(struct clk_hw *hw) | |
307 | { | |
308 | struct si5351_hw_data *hwdata = | |
309 | container_of(hw, struct si5351_hw_data, hw); | |
310 | ||
311 | dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n"); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static void si5351_vxco_unprepare(struct clk_hw *hw) | |
317 | { | |
318 | } | |
319 | ||
320 | static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw, | |
321 | unsigned long parent_rate) | |
322 | { | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate, | |
327 | unsigned long parent) | |
328 | { | |
329 | return 0; | |
330 | } | |
331 | ||
332 | static const struct clk_ops si5351_vxco_ops = { | |
333 | .prepare = si5351_vxco_prepare, | |
334 | .unprepare = si5351_vxco_unprepare, | |
335 | .recalc_rate = si5351_vxco_recalc_rate, | |
336 | .set_rate = si5351_vxco_set_rate, | |
337 | }; | |
338 | ||
339 | /* | |
340 | * Si5351 pll a/b | |
341 | * | |
342 | * Feedback Multisynth Divider Equations [2] | |
343 | * | |
344 | * fVCO = fIN * (a + b/c) | |
345 | * | |
346 | * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and | |
347 | * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV | |
348 | * | |
349 | * Feedback Multisynth Register Equations | |
350 | * | |
351 | * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 | |
352 | * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c | |
353 | * (3) MSNx_P3[19:0] = c | |
354 | * | |
355 | * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c | |
356 | * | |
357 | * Using (4) on (1) yields: | |
358 | * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512 | |
359 | * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c | |
360 | * | |
361 | * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128 | |
362 | * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3) | |
363 | * | |
364 | */ | |
365 | static int _si5351_pll_reparent(struct si5351_driver_data *drvdata, | |
366 | int num, enum si5351_pll_src parent) | |
367 | { | |
368 | u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; | |
369 | ||
370 | if (parent == SI5351_PLL_SRC_DEFAULT) | |
371 | return 0; | |
372 | ||
373 | if (num > 2) | |
374 | return -EINVAL; | |
375 | ||
376 | if (drvdata->variant != SI5351_VARIANT_C && | |
377 | parent != SI5351_PLL_SRC_XTAL) | |
378 | return -EINVAL; | |
379 | ||
380 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask, | |
381 | (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask); | |
382 | return 0; | |
383 | } | |
384 | ||
385 | static unsigned char si5351_pll_get_parent(struct clk_hw *hw) | |
386 | { | |
387 | struct si5351_hw_data *hwdata = | |
388 | container_of(hw, struct si5351_hw_data, hw); | |
389 | u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; | |
390 | u8 val; | |
391 | ||
392 | val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); | |
393 | ||
394 | return (val & mask) ? 1 : 0; | |
395 | } | |
396 | ||
397 | static int si5351_pll_set_parent(struct clk_hw *hw, u8 index) | |
398 | { | |
399 | struct si5351_hw_data *hwdata = | |
400 | container_of(hw, struct si5351_hw_data, hw); | |
401 | ||
402 | if (hwdata->drvdata->variant != SI5351_VARIANT_C && | |
403 | index > 0) | |
404 | return -EPERM; | |
405 | ||
406 | if (index > 1) | |
407 | return -EINVAL; | |
408 | ||
409 | return _si5351_pll_reparent(hwdata->drvdata, hwdata->num, | |
410 | (index == 0) ? SI5351_PLL_SRC_XTAL : | |
411 | SI5351_PLL_SRC_CLKIN); | |
412 | } | |
413 | ||
414 | static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw, | |
415 | unsigned long parent_rate) | |
416 | { | |
417 | struct si5351_hw_data *hwdata = | |
418 | container_of(hw, struct si5351_hw_data, hw); | |
419 | u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : | |
420 | SI5351_PLLB_PARAMETERS; | |
421 | unsigned long long rate; | |
422 | ||
423 | if (!hwdata->params.valid) | |
424 | si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); | |
425 | ||
426 | if (hwdata->params.p3 == 0) | |
427 | return parent_rate; | |
428 | ||
429 | /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */ | |
430 | rate = hwdata->params.p1 * hwdata->params.p3; | |
431 | rate += 512 * hwdata->params.p3; | |
432 | rate += hwdata->params.p2; | |
433 | rate *= parent_rate; | |
434 | do_div(rate, 128 * hwdata->params.p3); | |
435 | ||
436 | dev_dbg(&hwdata->drvdata->client->dev, | |
437 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 438 | __func__, clk_hw_get_name(hw), |
9abd5f05 SH |
439 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
440 | parent_rate, (unsigned long)rate); | |
441 | ||
442 | return (unsigned long)rate; | |
443 | } | |
444 | ||
08add3c1 MR |
445 | static int si5351_pll_determine_rate(struct clk_hw *hw, |
446 | struct clk_rate_request *req) | |
9abd5f05 SH |
447 | { |
448 | struct si5351_hw_data *hwdata = | |
449 | container_of(hw, struct si5351_hw_data, hw); | |
08add3c1 | 450 | unsigned long rate = req->rate; |
9abd5f05 SH |
451 | unsigned long rfrac, denom, a, b, c; |
452 | unsigned long long lltmp; | |
453 | ||
454 | if (rate < SI5351_PLL_VCO_MIN) | |
455 | rate = SI5351_PLL_VCO_MIN; | |
456 | if (rate > SI5351_PLL_VCO_MAX) | |
457 | rate = SI5351_PLL_VCO_MAX; | |
458 | ||
459 | /* determine integer part of feedback equation */ | |
08add3c1 | 460 | a = rate / req->best_parent_rate; |
9abd5f05 SH |
461 | |
462 | if (a < SI5351_PLL_A_MIN) | |
08add3c1 | 463 | rate = req->best_parent_rate * SI5351_PLL_A_MIN; |
9abd5f05 | 464 | if (a > SI5351_PLL_A_MAX) |
08add3c1 | 465 | rate = req->best_parent_rate * SI5351_PLL_A_MAX; |
9abd5f05 SH |
466 | |
467 | /* find best approximation for b/c = fVCO mod fIN */ | |
468 | denom = 1000 * 1000; | |
08add3c1 | 469 | lltmp = rate % (req->best_parent_rate); |
9abd5f05 | 470 | lltmp *= denom; |
08add3c1 | 471 | do_div(lltmp, req->best_parent_rate); |
9abd5f05 SH |
472 | rfrac = (unsigned long)lltmp; |
473 | ||
474 | b = 0; | |
475 | c = 1; | |
476 | if (rfrac) | |
477 | rational_best_approximation(rfrac, denom, | |
478 | SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c); | |
479 | ||
480 | /* calculate parameters */ | |
481 | hwdata->params.p3 = c; | |
482 | hwdata->params.p2 = (128 * b) % c; | |
483 | hwdata->params.p1 = 128 * a; | |
484 | hwdata->params.p1 += (128 * b / c); | |
485 | hwdata->params.p1 -= 512; | |
486 | ||
487 | /* recalculate rate by fIN * (a + b/c) */ | |
08add3c1 | 488 | lltmp = req->best_parent_rate; |
9abd5f05 SH |
489 | lltmp *= b; |
490 | do_div(lltmp, c); | |
491 | ||
492 | rate = (unsigned long)lltmp; | |
08add3c1 | 493 | rate += req->best_parent_rate * a; |
9abd5f05 SH |
494 | |
495 | dev_dbg(&hwdata->drvdata->client->dev, | |
496 | "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 497 | __func__, clk_hw_get_name(hw), a, b, c, |
08add3c1 | 498 | req->best_parent_rate, rate); |
9abd5f05 | 499 | |
08add3c1 MR |
500 | req->rate = rate; |
501 | return 0; | |
9abd5f05 SH |
502 | } |
503 | ||
504 | static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
505 | unsigned long parent_rate) | |
506 | { | |
507 | struct si5351_hw_data *hwdata = | |
508 | container_of(hw, struct si5351_hw_data, hw); | |
b2adbc9c AŠ |
509 | struct si5351_platform_data *pdata = |
510 | hwdata->drvdata->client->dev.platform_data; | |
9abd5f05 SH |
511 | u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : |
512 | SI5351_PLLB_PARAMETERS; | |
513 | ||
514 | /* write multisynth parameters */ | |
515 | si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); | |
516 | ||
517 | /* plla/pllb ctrl is in clk6/clk7 ctrl registers */ | |
518 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num, | |
519 | SI5351_CLK_INTEGER_MODE, | |
520 | (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); | |
521 | ||
73c950da | 522 | /* Do a pll soft reset on the affected pll */ |
b2adbc9c AŠ |
523 | if (pdata->pll_reset[hwdata->num]) |
524 | si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, | |
525 | hwdata->num == 0 ? SI5351_PLL_RESET_A : | |
526 | SI5351_PLL_RESET_B); | |
73c950da | 527 | |
9abd5f05 SH |
528 | dev_dbg(&hwdata->drvdata->client->dev, |
529 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 530 | __func__, clk_hw_get_name(hw), |
9abd5f05 SH |
531 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
532 | parent_rate, rate); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static const struct clk_ops si5351_pll_ops = { | |
538 | .set_parent = si5351_pll_set_parent, | |
539 | .get_parent = si5351_pll_get_parent, | |
540 | .recalc_rate = si5351_pll_recalc_rate, | |
08add3c1 | 541 | .determine_rate = si5351_pll_determine_rate, |
9abd5f05 SH |
542 | .set_rate = si5351_pll_set_rate, |
543 | }; | |
544 | ||
545 | /* | |
546 | * Si5351 multisync divider | |
547 | * | |
548 | * for fOUT <= 150 MHz: | |
549 | * | |
550 | * fOUT = (fIN * (a + b/c)) / CLKOUTDIV | |
551 | * | |
552 | * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and | |
553 | * fIN = fVCO0, fVCO1 | |
554 | * | |
555 | * Output Clock Multisynth Register Equations | |
556 | * | |
557 | * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 | |
558 | * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c | |
559 | * MSx_P3[19:0] = c | |
560 | * | |
2073b5e9 SS |
561 | * MS[6,7] are integer (P1) divide only, P1 = divide value, |
562 | * P2 and P3 are not applicable | |
9abd5f05 SH |
563 | * |
564 | * for 150MHz < fOUT <= 160MHz: | |
565 | * | |
566 | * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b | |
567 | */ | |
568 | static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata, | |
569 | int num, enum si5351_multisynth_src parent) | |
570 | { | |
571 | if (parent == SI5351_MULTISYNTH_SRC_DEFAULT) | |
572 | return 0; | |
573 | ||
574 | if (num > 8) | |
575 | return -EINVAL; | |
576 | ||
577 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT, | |
578 | (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 : | |
579 | SI5351_CLK_PLL_SELECT); | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static unsigned char si5351_msynth_get_parent(struct clk_hw *hw) | |
584 | { | |
585 | struct si5351_hw_data *hwdata = | |
586 | container_of(hw, struct si5351_hw_data, hw); | |
587 | u8 val; | |
588 | ||
589 | val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); | |
590 | ||
591 | return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0; | |
592 | } | |
593 | ||
594 | static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index) | |
595 | { | |
596 | struct si5351_hw_data *hwdata = | |
597 | container_of(hw, struct si5351_hw_data, hw); | |
598 | ||
599 | return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num, | |
600 | (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 : | |
601 | SI5351_MULTISYNTH_SRC_VCO1); | |
602 | } | |
603 | ||
604 | static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw, | |
605 | unsigned long parent_rate) | |
606 | { | |
607 | struct si5351_hw_data *hwdata = | |
608 | container_of(hw, struct si5351_hw_data, hw); | |
609 | u8 reg = si5351_msynth_params_address(hwdata->num); | |
610 | unsigned long long rate; | |
611 | unsigned long m; | |
612 | ||
613 | if (!hwdata->params.valid) | |
614 | si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); | |
615 | ||
9abd5f05 SH |
616 | /* |
617 | * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3) | |
618 | * multisync6-7: fOUT = fIN / P1 | |
619 | */ | |
620 | rate = parent_rate; | |
621 | if (hwdata->num > 5) { | |
622 | m = hwdata->params.p1; | |
45b03d3e SS |
623 | } else if (hwdata->params.p3 == 0) { |
624 | return parent_rate; | |
9abd5f05 SH |
625 | } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & |
626 | SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) { | |
627 | m = 4; | |
628 | } else { | |
629 | rate *= 128 * hwdata->params.p3; | |
630 | m = hwdata->params.p1 * hwdata->params.p3; | |
631 | m += hwdata->params.p2; | |
632 | m += 512 * hwdata->params.p3; | |
633 | } | |
634 | ||
635 | if (m == 0) | |
636 | return 0; | |
637 | do_div(rate, m); | |
638 | ||
639 | dev_dbg(&hwdata->drvdata->client->dev, | |
640 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 641 | __func__, clk_hw_get_name(hw), |
9abd5f05 SH |
642 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
643 | m, parent_rate, (unsigned long)rate); | |
644 | ||
645 | return (unsigned long)rate; | |
646 | } | |
647 | ||
4ab2bf81 MR |
648 | static int si5351_msynth_determine_rate(struct clk_hw *hw, |
649 | struct clk_rate_request *req) | |
9abd5f05 SH |
650 | { |
651 | struct si5351_hw_data *hwdata = | |
652 | container_of(hw, struct si5351_hw_data, hw); | |
4ab2bf81 | 653 | unsigned long rate = req->rate; |
9abd5f05 SH |
654 | unsigned long long lltmp; |
655 | unsigned long a, b, c; | |
656 | int divby4; | |
657 | ||
658 | /* multisync6-7 can only handle freqencies < 150MHz */ | |
659 | if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ) | |
660 | rate = SI5351_MULTISYNTH67_MAX_FREQ; | |
661 | ||
662 | /* multisync frequency is 1MHz .. 160MHz */ | |
663 | if (rate > SI5351_MULTISYNTH_MAX_FREQ) | |
664 | rate = SI5351_MULTISYNTH_MAX_FREQ; | |
665 | if (rate < SI5351_MULTISYNTH_MIN_FREQ) | |
666 | rate = SI5351_MULTISYNTH_MIN_FREQ; | |
667 | ||
668 | divby4 = 0; | |
669 | if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) | |
670 | divby4 = 1; | |
671 | ||
672 | /* multisync can set pll */ | |
98d8a60e | 673 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
9abd5f05 SH |
674 | /* |
675 | * find largest integer divider for max | |
676 | * vco frequency and given target rate | |
677 | */ | |
678 | if (divby4 == 0) { | |
679 | lltmp = SI5351_PLL_VCO_MAX; | |
680 | do_div(lltmp, rate); | |
681 | a = (unsigned long)lltmp; | |
682 | } else | |
683 | a = 4; | |
684 | ||
685 | b = 0; | |
686 | c = 1; | |
687 | ||
4ab2bf81 | 688 | req->best_parent_rate = a * rate; |
2073b5e9 SS |
689 | } else if (hwdata->num >= 6) { |
690 | /* determine the closest integer divider */ | |
4ab2bf81 | 691 | a = DIV_ROUND_CLOSEST(req->best_parent_rate, rate); |
2073b5e9 SS |
692 | if (a < SI5351_MULTISYNTH_A_MIN) |
693 | a = SI5351_MULTISYNTH_A_MIN; | |
694 | if (a > SI5351_MULTISYNTH67_A_MAX) | |
695 | a = SI5351_MULTISYNTH67_A_MAX; | |
696 | ||
697 | b = 0; | |
698 | c = 1; | |
9abd5f05 SH |
699 | } else { |
700 | unsigned long rfrac, denom; | |
701 | ||
702 | /* disable divby4 */ | |
703 | if (divby4) { | |
704 | rate = SI5351_MULTISYNTH_DIVBY4_FREQ; | |
705 | divby4 = 0; | |
706 | } | |
707 | ||
708 | /* determine integer part of divider equation */ | |
4ab2bf81 | 709 | a = req->best_parent_rate / rate; |
9abd5f05 SH |
710 | if (a < SI5351_MULTISYNTH_A_MIN) |
711 | a = SI5351_MULTISYNTH_A_MIN; | |
2073b5e9 | 712 | if (a > SI5351_MULTISYNTH_A_MAX) |
9abd5f05 SH |
713 | a = SI5351_MULTISYNTH_A_MAX; |
714 | ||
715 | /* find best approximation for b/c = fVCO mod fOUT */ | |
716 | denom = 1000 * 1000; | |
4ab2bf81 | 717 | lltmp = req->best_parent_rate % rate; |
9abd5f05 SH |
718 | lltmp *= denom; |
719 | do_div(lltmp, rate); | |
720 | rfrac = (unsigned long)lltmp; | |
721 | ||
722 | b = 0; | |
723 | c = 1; | |
724 | if (rfrac) | |
725 | rational_best_approximation(rfrac, denom, | |
726 | SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX, | |
727 | &b, &c); | |
728 | } | |
729 | ||
730 | /* recalculate rate by fOUT = fIN / (a + b/c) */ | |
4ab2bf81 | 731 | lltmp = req->best_parent_rate; |
9abd5f05 SH |
732 | lltmp *= c; |
733 | do_div(lltmp, a * c + b); | |
734 | rate = (unsigned long)lltmp; | |
735 | ||
736 | /* calculate parameters */ | |
737 | if (divby4) { | |
738 | hwdata->params.p3 = 1; | |
739 | hwdata->params.p2 = 0; | |
740 | hwdata->params.p1 = 0; | |
2073b5e9 SS |
741 | } else if (hwdata->num >= 6) { |
742 | hwdata->params.p3 = 0; | |
743 | hwdata->params.p2 = 0; | |
744 | hwdata->params.p1 = a; | |
9abd5f05 SH |
745 | } else { |
746 | hwdata->params.p3 = c; | |
747 | hwdata->params.p2 = (128 * b) % c; | |
748 | hwdata->params.p1 = 128 * a; | |
749 | hwdata->params.p1 += (128 * b / c); | |
750 | hwdata->params.p1 -= 512; | |
751 | } | |
752 | ||
753 | dev_dbg(&hwdata->drvdata->client->dev, | |
754 | "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 755 | __func__, clk_hw_get_name(hw), a, b, c, divby4, |
4ab2bf81 | 756 | req->best_parent_rate, rate); |
9abd5f05 | 757 | |
4ab2bf81 MR |
758 | req->rate = rate; |
759 | ||
760 | return 0; | |
9abd5f05 SH |
761 | } |
762 | ||
763 | static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate, | |
764 | unsigned long parent_rate) | |
765 | { | |
766 | struct si5351_hw_data *hwdata = | |
767 | container_of(hw, struct si5351_hw_data, hw); | |
768 | u8 reg = si5351_msynth_params_address(hwdata->num); | |
769 | int divby4 = 0; | |
770 | ||
771 | /* write multisynth parameters */ | |
772 | si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); | |
773 | ||
774 | if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) | |
775 | divby4 = 1; | |
776 | ||
777 | /* enable/disable integer mode and divby4 on multisynth0-5 */ | |
778 | if (hwdata->num < 6) { | |
779 | si5351_set_bits(hwdata->drvdata, reg + 2, | |
780 | SI5351_OUTPUT_CLK_DIVBY4, | |
781 | (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); | |
782 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, | |
783 | SI5351_CLK_INTEGER_MODE, | |
784 | (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); | |
785 | } | |
786 | ||
787 | dev_dbg(&hwdata->drvdata->client->dev, | |
788 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 789 | __func__, clk_hw_get_name(hw), |
9abd5f05 SH |
790 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
791 | divby4, parent_rate, rate); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static const struct clk_ops si5351_msynth_ops = { | |
797 | .set_parent = si5351_msynth_set_parent, | |
798 | .get_parent = si5351_msynth_get_parent, | |
799 | .recalc_rate = si5351_msynth_recalc_rate, | |
4ab2bf81 | 800 | .determine_rate = si5351_msynth_determine_rate, |
9abd5f05 SH |
801 | .set_rate = si5351_msynth_set_rate, |
802 | }; | |
803 | ||
804 | /* | |
805 | * Si5351 clkout divider | |
806 | */ | |
807 | static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata, | |
808 | int num, enum si5351_clkout_src parent) | |
809 | { | |
810 | u8 val; | |
811 | ||
812 | if (num > 8) | |
813 | return -EINVAL; | |
814 | ||
815 | switch (parent) { | |
816 | case SI5351_CLKOUT_SRC_MSYNTH_N: | |
817 | val = SI5351_CLK_INPUT_MULTISYNTH_N; | |
818 | break; | |
819 | case SI5351_CLKOUT_SRC_MSYNTH_0_4: | |
820 | /* clk0/clk4 can only connect to its own multisync */ | |
821 | if (num == 0 || num == 4) | |
822 | val = SI5351_CLK_INPUT_MULTISYNTH_N; | |
823 | else | |
824 | val = SI5351_CLK_INPUT_MULTISYNTH_0_4; | |
825 | break; | |
826 | case SI5351_CLKOUT_SRC_XTAL: | |
827 | val = SI5351_CLK_INPUT_XTAL; | |
828 | break; | |
829 | case SI5351_CLKOUT_SRC_CLKIN: | |
830 | if (drvdata->variant != SI5351_VARIANT_C) | |
831 | return -EINVAL; | |
832 | ||
833 | val = SI5351_CLK_INPUT_CLKIN; | |
834 | break; | |
835 | default: | |
836 | return 0; | |
837 | } | |
838 | ||
839 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, | |
840 | SI5351_CLK_INPUT_MASK, val); | |
841 | return 0; | |
842 | } | |
843 | ||
844 | static int _si5351_clkout_set_drive_strength( | |
845 | struct si5351_driver_data *drvdata, int num, | |
846 | enum si5351_drive_strength drive) | |
847 | { | |
848 | u8 mask; | |
849 | ||
850 | if (num > 8) | |
851 | return -EINVAL; | |
852 | ||
853 | switch (drive) { | |
854 | case SI5351_DRIVE_2MA: | |
855 | mask = SI5351_CLK_DRIVE_STRENGTH_2MA; | |
856 | break; | |
857 | case SI5351_DRIVE_4MA: | |
858 | mask = SI5351_CLK_DRIVE_STRENGTH_4MA; | |
859 | break; | |
860 | case SI5351_DRIVE_6MA: | |
861 | mask = SI5351_CLK_DRIVE_STRENGTH_6MA; | |
862 | break; | |
863 | case SI5351_DRIVE_8MA: | |
864 | mask = SI5351_CLK_DRIVE_STRENGTH_8MA; | |
865 | break; | |
866 | default: | |
867 | return 0; | |
868 | } | |
869 | ||
870 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, | |
871 | SI5351_CLK_DRIVE_STRENGTH_MASK, mask); | |
872 | return 0; | |
873 | } | |
874 | ||
1a0483d2 SH |
875 | static int _si5351_clkout_set_disable_state( |
876 | struct si5351_driver_data *drvdata, int num, | |
877 | enum si5351_disable_state state) | |
878 | { | |
879 | u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE : | |
880 | SI5351_CLK7_4_DISABLE_STATE; | |
881 | u8 shift = (num < 4) ? (2 * num) : (2 * (num-4)); | |
882 | u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift; | |
883 | u8 val; | |
884 | ||
885 | if (num > 8) | |
886 | return -EINVAL; | |
887 | ||
888 | switch (state) { | |
889 | case SI5351_DISABLE_LOW: | |
890 | val = SI5351_CLK_DISABLE_STATE_LOW; | |
891 | break; | |
892 | case SI5351_DISABLE_HIGH: | |
893 | val = SI5351_CLK_DISABLE_STATE_HIGH; | |
894 | break; | |
895 | case SI5351_DISABLE_FLOATING: | |
896 | val = SI5351_CLK_DISABLE_STATE_FLOAT; | |
897 | break; | |
898 | case SI5351_DISABLE_NEVER: | |
899 | val = SI5351_CLK_DISABLE_STATE_NEVER; | |
900 | break; | |
901 | default: | |
902 | return 0; | |
903 | } | |
904 | ||
905 | si5351_set_bits(drvdata, reg, mask, val << shift); | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
0136f852 | 910 | static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num) |
b26ff127 SS |
911 | { |
912 | u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num); | |
5142cbce SH |
913 | u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B : |
914 | SI5351_PLL_RESET_A; | |
915 | unsigned int v; | |
916 | int err; | |
b26ff127 SS |
917 | |
918 | switch (val & SI5351_CLK_INPUT_MASK) { | |
919 | case SI5351_CLK_INPUT_XTAL: | |
920 | case SI5351_CLK_INPUT_CLKIN: | |
921 | return; /* pll not used, no need to reset */ | |
922 | } | |
923 | ||
5142cbce SH |
924 | si5351_reg_write(drvdata, SI5351_PLL_RESET, mask); |
925 | ||
926 | err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v, | |
927 | !(v & mask), 0, 20000); | |
928 | if (err < 0) | |
929 | dev_err(&drvdata->client->dev, "Reset bit didn't clear\n"); | |
b26ff127 SS |
930 | |
931 | dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n", | |
932 | __func__, clk_hw_get_name(&drvdata->clkout[num].hw), | |
933 | (val & SI5351_CLK_PLL_SELECT) ? 1 : 0); | |
934 | } | |
935 | ||
9abd5f05 SH |
936 | static int si5351_clkout_prepare(struct clk_hw *hw) |
937 | { | |
938 | struct si5351_hw_data *hwdata = | |
939 | container_of(hw, struct si5351_hw_data, hw); | |
b26ff127 SS |
940 | struct si5351_platform_data *pdata = |
941 | hwdata->drvdata->client->dev.platform_data; | |
9abd5f05 SH |
942 | |
943 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, | |
944 | SI5351_CLK_POWERDOWN, 0); | |
b26ff127 SS |
945 | |
946 | /* | |
947 | * Do a pll soft reset on the parent pll -- needed to get a | |
948 | * deterministic phase relationship between the output clocks. | |
949 | */ | |
950 | if (pdata->clkout[hwdata->num].pll_reset) | |
951 | _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num); | |
952 | ||
9abd5f05 SH |
953 | si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, |
954 | (1 << hwdata->num), 0); | |
955 | return 0; | |
956 | } | |
957 | ||
958 | static void si5351_clkout_unprepare(struct clk_hw *hw) | |
959 | { | |
960 | struct si5351_hw_data *hwdata = | |
961 | container_of(hw, struct si5351_hw_data, hw); | |
962 | ||
963 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, | |
964 | SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN); | |
965 | si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, | |
966 | (1 << hwdata->num), (1 << hwdata->num)); | |
967 | } | |
968 | ||
969 | static u8 si5351_clkout_get_parent(struct clk_hw *hw) | |
970 | { | |
971 | struct si5351_hw_data *hwdata = | |
972 | container_of(hw, struct si5351_hw_data, hw); | |
973 | int index = 0; | |
974 | unsigned char val; | |
975 | ||
976 | val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); | |
977 | switch (val & SI5351_CLK_INPUT_MASK) { | |
978 | case SI5351_CLK_INPUT_MULTISYNTH_N: | |
979 | index = 0; | |
980 | break; | |
981 | case SI5351_CLK_INPUT_MULTISYNTH_0_4: | |
982 | index = 1; | |
983 | break; | |
984 | case SI5351_CLK_INPUT_XTAL: | |
985 | index = 2; | |
986 | break; | |
987 | case SI5351_CLK_INPUT_CLKIN: | |
988 | index = 3; | |
989 | break; | |
990 | } | |
991 | ||
992 | return index; | |
993 | } | |
994 | ||
995 | static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index) | |
996 | { | |
997 | struct si5351_hw_data *hwdata = | |
998 | container_of(hw, struct si5351_hw_data, hw); | |
999 | enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT; | |
1000 | ||
1001 | switch (index) { | |
1002 | case 0: | |
1003 | parent = SI5351_CLKOUT_SRC_MSYNTH_N; | |
1004 | break; | |
1005 | case 1: | |
1006 | parent = SI5351_CLKOUT_SRC_MSYNTH_0_4; | |
1007 | break; | |
1008 | case 2: | |
1009 | parent = SI5351_CLKOUT_SRC_XTAL; | |
1010 | break; | |
1011 | case 3: | |
1012 | parent = SI5351_CLKOUT_SRC_CLKIN; | |
1013 | break; | |
1014 | } | |
1015 | ||
1016 | return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent); | |
1017 | } | |
1018 | ||
1019 | static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, | |
1020 | unsigned long parent_rate) | |
1021 | { | |
1022 | struct si5351_hw_data *hwdata = | |
1023 | container_of(hw, struct si5351_hw_data, hw); | |
1024 | unsigned char reg; | |
1025 | unsigned char rdiv; | |
1026 | ||
67e1e226 | 1027 | if (hwdata->num <= 5) |
9abd5f05 SH |
1028 | reg = si5351_msynth_params_address(hwdata->num) + 2; |
1029 | else | |
1030 | reg = SI5351_CLK6_7_OUTPUT_DIVIDER; | |
1031 | ||
1032 | rdiv = si5351_reg_read(hwdata->drvdata, reg); | |
1033 | if (hwdata->num == 6) { | |
1034 | rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; | |
1035 | } else { | |
1036 | rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; | |
1037 | rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; | |
1038 | } | |
1039 | ||
1040 | return parent_rate >> rdiv; | |
1041 | } | |
1042 | ||
c8bfcfcb MR |
1043 | static int si5351_clkout_determine_rate(struct clk_hw *hw, |
1044 | struct clk_rate_request *req) | |
9abd5f05 SH |
1045 | { |
1046 | struct si5351_hw_data *hwdata = | |
1047 | container_of(hw, struct si5351_hw_data, hw); | |
c8bfcfcb | 1048 | unsigned long rate = req->rate; |
9abd5f05 SH |
1049 | unsigned char rdiv; |
1050 | ||
1051 | /* clkout6/7 can only handle output freqencies < 150MHz */ | |
1052 | if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ) | |
1053 | rate = SI5351_CLKOUT67_MAX_FREQ; | |
1054 | ||
1055 | /* clkout freqency is 8kHz - 160MHz */ | |
1056 | if (rate > SI5351_CLKOUT_MAX_FREQ) | |
1057 | rate = SI5351_CLKOUT_MAX_FREQ; | |
1058 | if (rate < SI5351_CLKOUT_MIN_FREQ) | |
1059 | rate = SI5351_CLKOUT_MIN_FREQ; | |
1060 | ||
1061 | /* request frequency if multisync master */ | |
98d8a60e | 1062 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
9abd5f05 SH |
1063 | /* use r divider for frequencies below 1MHz */ |
1064 | rdiv = SI5351_OUTPUT_CLK_DIV_1; | |
1065 | while (rate < SI5351_MULTISYNTH_MIN_FREQ && | |
1066 | rdiv < SI5351_OUTPUT_CLK_DIV_128) { | |
1067 | rdiv += 1; | |
1068 | rate *= 2; | |
1069 | } | |
c8bfcfcb | 1070 | req->best_parent_rate = rate; |
9abd5f05 SH |
1071 | } else { |
1072 | unsigned long new_rate, new_err, err; | |
1073 | ||
1074 | /* round to closed rdiv */ | |
1075 | rdiv = SI5351_OUTPUT_CLK_DIV_1; | |
c8bfcfcb | 1076 | new_rate = req->best_parent_rate; |
9abd5f05 SH |
1077 | err = abs(new_rate - rate); |
1078 | do { | |
1079 | new_rate >>= 1; | |
1080 | new_err = abs(new_rate - rate); | |
1081 | if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) | |
1082 | break; | |
1083 | rdiv++; | |
1084 | err = new_err; | |
1085 | } while (1); | |
1086 | } | |
c8bfcfcb | 1087 | rate = req->best_parent_rate >> rdiv; |
9abd5f05 SH |
1088 | |
1089 | dev_dbg(&hwdata->drvdata->client->dev, | |
1090 | "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 1091 | __func__, clk_hw_get_name(hw), (1 << rdiv), |
c8bfcfcb | 1092 | req->best_parent_rate, rate); |
9abd5f05 | 1093 | |
c8bfcfcb MR |
1094 | req->rate = rate; |
1095 | return 0; | |
9abd5f05 SH |
1096 | } |
1097 | ||
1098 | static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, | |
1099 | unsigned long parent_rate) | |
1100 | { | |
1101 | struct si5351_hw_data *hwdata = | |
1102 | container_of(hw, struct si5351_hw_data, hw); | |
1103 | unsigned long new_rate, new_err, err; | |
1104 | unsigned char rdiv; | |
1105 | ||
1106 | /* round to closed rdiv */ | |
1107 | rdiv = SI5351_OUTPUT_CLK_DIV_1; | |
1108 | new_rate = parent_rate; | |
1109 | err = abs(new_rate - rate); | |
1110 | do { | |
1111 | new_rate >>= 1; | |
1112 | new_err = abs(new_rate - rate); | |
1113 | if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) | |
1114 | break; | |
1115 | rdiv++; | |
1116 | err = new_err; | |
1117 | } while (1); | |
1118 | ||
1119 | /* write output divider */ | |
1120 | switch (hwdata->num) { | |
1121 | case 6: | |
1122 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, | |
1123 | SI5351_OUTPUT_CLK6_DIV_MASK, rdiv); | |
1124 | break; | |
1125 | case 7: | |
1126 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, | |
1127 | SI5351_OUTPUT_CLK_DIV_MASK, | |
1128 | rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); | |
1129 | break; | |
1130 | default: | |
1131 | si5351_set_bits(hwdata->drvdata, | |
1132 | si5351_msynth_params_address(hwdata->num) + 2, | |
1133 | SI5351_OUTPUT_CLK_DIV_MASK, | |
1134 | rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); | |
1135 | } | |
1136 | ||
1137 | /* powerup clkout */ | |
1138 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, | |
1139 | SI5351_CLK_POWERDOWN, 0); | |
1140 | ||
1141 | dev_dbg(&hwdata->drvdata->client->dev, | |
1142 | "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", | |
44f22a5d | 1143 | __func__, clk_hw_get_name(hw), (1 << rdiv), |
9abd5f05 SH |
1144 | parent_rate, rate); |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | static const struct clk_ops si5351_clkout_ops = { | |
1150 | .prepare = si5351_clkout_prepare, | |
1151 | .unprepare = si5351_clkout_unprepare, | |
1152 | .set_parent = si5351_clkout_set_parent, | |
1153 | .get_parent = si5351_clkout_get_parent, | |
1154 | .recalc_rate = si5351_clkout_recalc_rate, | |
c8bfcfcb | 1155 | .determine_rate = si5351_clkout_determine_rate, |
9abd5f05 SH |
1156 | .set_rate = si5351_clkout_set_rate, |
1157 | }; | |
1158 | ||
1159 | /* | |
1160 | * Si5351 i2c probe and DT | |
1161 | */ | |
1162 | #ifdef CONFIG_OF | |
1163 | static const struct of_device_id si5351_dt_ids[] = { | |
1164 | { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, }, | |
1165 | { .compatible = "silabs,si5351a-msop", | |
1166 | .data = (void *)SI5351_VARIANT_A3, }, | |
1167 | { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, }, | |
1168 | { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, }, | |
1169 | { } | |
1170 | }; | |
1171 | MODULE_DEVICE_TABLE(of, si5351_dt_ids); | |
1172 | ||
9d43dc7f SH |
1173 | static int si5351_dt_parse(struct i2c_client *client, |
1174 | enum si5351_variant variant) | |
9abd5f05 SH |
1175 | { |
1176 | struct device_node *child, *np = client->dev.of_node; | |
1177 | struct si5351_platform_data *pdata; | |
9abd5f05 SH |
1178 | struct property *prop; |
1179 | const __be32 *p; | |
1180 | int num = 0; | |
1181 | u32 val; | |
1182 | ||
1183 | if (np == NULL) | |
1184 | return 0; | |
1185 | ||
9abd5f05 SH |
1186 | pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); |
1187 | if (!pdata) | |
1188 | return -ENOMEM; | |
1189 | ||
9abd5f05 SH |
1190 | /* |
1191 | * property silabs,pll-source : <num src>, [<..>] | |
1192 | * allow to selectively set pll source | |
1193 | */ | |
1194 | of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) { | |
1195 | if (num >= 2) { | |
1196 | dev_err(&client->dev, | |
1197 | "invalid pll %d on pll-source prop\n", num); | |
1198 | return -EINVAL; | |
1199 | } | |
1200 | ||
1201 | p = of_prop_next_u32(prop, p, &val); | |
1202 | if (!p) { | |
1203 | dev_err(&client->dev, | |
1204 | "missing pll-source for pll %d\n", num); | |
1205 | return -EINVAL; | |
1206 | } | |
1207 | ||
1208 | switch (val) { | |
1209 | case 0: | |
1210 | pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; | |
1211 | break; | |
1212 | case 1: | |
9d43dc7f | 1213 | if (variant != SI5351_VARIANT_C) { |
9abd5f05 SH |
1214 | dev_err(&client->dev, |
1215 | "invalid parent %d for pll %d\n", | |
1216 | val, num); | |
1217 | return -EINVAL; | |
1218 | } | |
1219 | pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN; | |
1220 | break; | |
1221 | default: | |
1222 | dev_err(&client->dev, | |
1223 | "invalid parent %d for pll %d\n", val, num); | |
1224 | return -EINVAL; | |
1225 | } | |
1226 | } | |
1227 | ||
b2adbc9c AŠ |
1228 | /* |
1229 | * Parse PLL reset mode. For compatibility with older device trees, the | |
1230 | * default is to always reset a PLL after setting its rate. | |
1231 | */ | |
1232 | pdata->pll_reset[0] = true; | |
1233 | pdata->pll_reset[1] = true; | |
1234 | ||
1235 | of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { | |
1236 | if (num >= 2) { | |
1237 | dev_err(&client->dev, | |
1238 | "invalid pll %d on pll-reset-mode prop\n", num); | |
1239 | return -EINVAL; | |
1240 | } | |
1241 | ||
1242 | p = of_prop_next_u32(prop, p, &val); | |
1243 | if (!p) { | |
1244 | dev_err(&client->dev, | |
1245 | "missing pll-reset-mode for pll %d\n", num); | |
1246 | return -EINVAL; | |
1247 | } | |
1248 | ||
1249 | switch (val) { | |
1250 | case 0: | |
1251 | /* Reset PLL whenever its rate is adjusted */ | |
1252 | pdata->pll_reset[num] = true; | |
1253 | break; | |
1254 | case 1: | |
1255 | /* Don't reset PLL whenever its rate is adjusted */ | |
1256 | pdata->pll_reset[num] = false; | |
1257 | break; | |
1258 | default: | |
1259 | dev_err(&client->dev, | |
1260 | "invalid pll-reset-mode %d for pll %d\n", val, | |
1261 | num); | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | } | |
1265 | ||
9abd5f05 SH |
1266 | /* per clkout properties */ |
1267 | for_each_child_of_node(np, child) { | |
1268 | if (of_property_read_u32(child, "reg", &num)) { | |
e665f029 RH |
1269 | dev_err(&client->dev, "missing reg property of %pOFn\n", |
1270 | child); | |
a1bdfbaf | 1271 | goto put_child; |
9abd5f05 SH |
1272 | } |
1273 | ||
1274 | if (num >= 8 || | |
9d43dc7f | 1275 | (variant == SI5351_VARIANT_A3 && num >= 3)) { |
9abd5f05 | 1276 | dev_err(&client->dev, "invalid clkout %d\n", num); |
a1bdfbaf | 1277 | goto put_child; |
9abd5f05 SH |
1278 | } |
1279 | ||
1280 | if (!of_property_read_u32(child, "silabs,multisynth-source", | |
1281 | &val)) { | |
1282 | switch (val) { | |
1283 | case 0: | |
1284 | pdata->clkout[num].multisynth_src = | |
1285 | SI5351_MULTISYNTH_SRC_VCO0; | |
1286 | break; | |
1287 | case 1: | |
1288 | pdata->clkout[num].multisynth_src = | |
1289 | SI5351_MULTISYNTH_SRC_VCO1; | |
1290 | break; | |
1291 | default: | |
1292 | dev_err(&client->dev, | |
1293 | "invalid parent %d for multisynth %d\n", | |
1294 | val, num); | |
a1bdfbaf | 1295 | goto put_child; |
9abd5f05 SH |
1296 | } |
1297 | } | |
1298 | ||
1299 | if (!of_property_read_u32(child, "silabs,clock-source", &val)) { | |
1300 | switch (val) { | |
1301 | case 0: | |
1302 | pdata->clkout[num].clkout_src = | |
1303 | SI5351_CLKOUT_SRC_MSYNTH_N; | |
1304 | break; | |
1305 | case 1: | |
1306 | pdata->clkout[num].clkout_src = | |
1307 | SI5351_CLKOUT_SRC_MSYNTH_0_4; | |
1308 | break; | |
1309 | case 2: | |
1310 | pdata->clkout[num].clkout_src = | |
1311 | SI5351_CLKOUT_SRC_XTAL; | |
1312 | break; | |
1313 | case 3: | |
9d43dc7f | 1314 | if (variant != SI5351_VARIANT_C) { |
9abd5f05 SH |
1315 | dev_err(&client->dev, |
1316 | "invalid parent %d for clkout %d\n", | |
1317 | val, num); | |
a1bdfbaf | 1318 | goto put_child; |
9abd5f05 SH |
1319 | } |
1320 | pdata->clkout[num].clkout_src = | |
1321 | SI5351_CLKOUT_SRC_CLKIN; | |
1322 | break; | |
1323 | default: | |
1324 | dev_err(&client->dev, | |
1325 | "invalid parent %d for clkout %d\n", | |
1326 | val, num); | |
a1bdfbaf | 1327 | goto put_child; |
9abd5f05 SH |
1328 | } |
1329 | } | |
1330 | ||
1331 | if (!of_property_read_u32(child, "silabs,drive-strength", | |
1332 | &val)) { | |
1333 | switch (val) { | |
1334 | case SI5351_DRIVE_2MA: | |
1335 | case SI5351_DRIVE_4MA: | |
1336 | case SI5351_DRIVE_6MA: | |
1337 | case SI5351_DRIVE_8MA: | |
1338 | pdata->clkout[num].drive = val; | |
1339 | break; | |
1340 | default: | |
1341 | dev_err(&client->dev, | |
1342 | "invalid drive strength %d for clkout %d\n", | |
1343 | val, num); | |
a1bdfbaf | 1344 | goto put_child; |
9abd5f05 SH |
1345 | } |
1346 | } | |
1347 | ||
1a0483d2 SH |
1348 | if (!of_property_read_u32(child, "silabs,disable-state", |
1349 | &val)) { | |
1350 | switch (val) { | |
1351 | case 0: | |
1352 | pdata->clkout[num].disable_state = | |
1353 | SI5351_DISABLE_LOW; | |
1354 | break; | |
1355 | case 1: | |
1356 | pdata->clkout[num].disable_state = | |
1357 | SI5351_DISABLE_HIGH; | |
1358 | break; | |
1359 | case 2: | |
1360 | pdata->clkout[num].disable_state = | |
1361 | SI5351_DISABLE_FLOATING; | |
1362 | break; | |
1363 | case 3: | |
1364 | pdata->clkout[num].disable_state = | |
1365 | SI5351_DISABLE_NEVER; | |
1366 | break; | |
1367 | default: | |
1368 | dev_err(&client->dev, | |
1369 | "invalid disable state %d for clkout %d\n", | |
1370 | val, num); | |
a1bdfbaf | 1371 | goto put_child; |
1a0483d2 SH |
1372 | } |
1373 | } | |
1374 | ||
9abd5f05 SH |
1375 | if (!of_property_read_u32(child, "clock-frequency", &val)) |
1376 | pdata->clkout[num].rate = val; | |
1377 | ||
1378 | pdata->clkout[num].pll_master = | |
1379 | of_property_read_bool(child, "silabs,pll-master"); | |
51279ef9 SS |
1380 | |
1381 | pdata->clkout[num].pll_reset = | |
1382 | of_property_read_bool(child, "silabs,pll-reset"); | |
9abd5f05 SH |
1383 | } |
1384 | client->dev.platform_data = pdata; | |
1385 | ||
1386 | return 0; | |
a1bdfbaf JL |
1387 | put_child: |
1388 | of_node_put(child); | |
1389 | return -EINVAL; | |
9abd5f05 | 1390 | } |
4d89c3d5 SB |
1391 | |
1392 | static struct clk_hw * | |
1393 | si53351_of_clk_get(struct of_phandle_args *clkspec, void *data) | |
1394 | { | |
1395 | struct si5351_driver_data *drvdata = data; | |
1396 | unsigned int idx = clkspec->args[0]; | |
1397 | ||
1398 | if (idx >= drvdata->num_clkout) { | |
1399 | pr_err("%s: invalid index %u\n", __func__, idx); | |
1400 | return ERR_PTR(-EINVAL); | |
1401 | } | |
1402 | ||
1403 | return &drvdata->clkout[idx].hw; | |
1404 | } | |
9abd5f05 | 1405 | #else |
d30492ad | 1406 | static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant) |
9abd5f05 SH |
1407 | { |
1408 | return 0; | |
1409 | } | |
4d89c3d5 SB |
1410 | |
1411 | static struct clk_hw * | |
1412 | si53351_of_clk_get(struct of_phandle_args *clkspec, void *data) | |
1413 | { | |
1414 | return NULL; | |
1415 | } | |
9abd5f05 SH |
1416 | #endif /* CONFIG_OF */ |
1417 | ||
ca3ebd20 SK |
1418 | static const struct i2c_device_id si5351_i2c_ids[] = { |
1419 | { "si5351a", SI5351_VARIANT_A }, | |
1420 | { "si5351a-msop", SI5351_VARIANT_A3 }, | |
1421 | { "si5351b", SI5351_VARIANT_B }, | |
1422 | { "si5351c", SI5351_VARIANT_C }, | |
1423 | { } | |
1424 | }; | |
1425 | MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); | |
1426 | ||
1427 | static int si5351_i2c_probe(struct i2c_client *client) | |
9abd5f05 | 1428 | { |
f234f028 | 1429 | enum si5351_variant variant; |
9abd5f05 SH |
1430 | struct si5351_platform_data *pdata; |
1431 | struct si5351_driver_data *drvdata; | |
1432 | struct clk_init_data init; | |
9abd5f05 SH |
1433 | const char *parent_names[4]; |
1434 | u8 num_parents, num_clocks; | |
1435 | int ret, n; | |
1436 | ||
f234f028 | 1437 | variant = (enum si5351_variant)(uintptr_t)i2c_get_match_data(client); |
9d43dc7f | 1438 | ret = si5351_dt_parse(client, variant); |
9abd5f05 SH |
1439 | if (ret) |
1440 | return ret; | |
1441 | ||
1442 | pdata = client->dev.platform_data; | |
1443 | if (!pdata) | |
1444 | return -EINVAL; | |
1445 | ||
1446 | drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL); | |
56f2150a | 1447 | if (!drvdata) |
9abd5f05 | 1448 | return -ENOMEM; |
9abd5f05 SH |
1449 | |
1450 | i2c_set_clientdata(client, drvdata); | |
1451 | drvdata->client = client; | |
9d43dc7f | 1452 | drvdata->variant = variant; |
0cd3be6e SH |
1453 | drvdata->pxtal = devm_clk_get(&client->dev, "xtal"); |
1454 | drvdata->pclkin = devm_clk_get(&client->dev, "clkin"); | |
1455 | ||
1456 | if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER || | |
1457 | PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER) | |
1458 | return -EPROBE_DEFER; | |
1459 | ||
1460 | /* | |
1461 | * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL, | |
1462 | * VARIANT_C can have CLKIN instead. | |
1463 | */ | |
1464 | if (IS_ERR(drvdata->pxtal) && | |
1465 | (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) { | |
1466 | dev_err(&client->dev, "missing parent clock\n"); | |
1467 | return -EINVAL; | |
1468 | } | |
9abd5f05 SH |
1469 | |
1470 | drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); | |
1471 | if (IS_ERR(drvdata->regmap)) { | |
1472 | dev_err(&client->dev, "failed to allocate register map\n"); | |
1473 | return PTR_ERR(drvdata->regmap); | |
1474 | } | |
1475 | ||
1476 | /* Disable interrupts */ | |
1477 | si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0); | |
9abd5f05 SH |
1478 | /* Ensure pll select is on XTAL for Si5351A/B */ |
1479 | if (drvdata->variant != SI5351_VARIANT_C) | |
1480 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, | |
1481 | SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0); | |
1482 | ||
1483 | /* setup clock configuration */ | |
1484 | for (n = 0; n < 2; n++) { | |
1485 | ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]); | |
1486 | if (ret) { | |
1487 | dev_err(&client->dev, | |
1488 | "failed to reparent pll %d to %d\n", | |
1489 | n, pdata->pll_src[n]); | |
1490 | return ret; | |
1491 | } | |
1492 | } | |
1493 | ||
1494 | for (n = 0; n < 8; n++) { | |
1495 | ret = _si5351_msynth_reparent(drvdata, n, | |
1496 | pdata->clkout[n].multisynth_src); | |
1497 | if (ret) { | |
1498 | dev_err(&client->dev, | |
1499 | "failed to reparent multisynth %d to %d\n", | |
1500 | n, pdata->clkout[n].multisynth_src); | |
1501 | return ret; | |
1502 | } | |
1503 | ||
1504 | ret = _si5351_clkout_reparent(drvdata, n, | |
1505 | pdata->clkout[n].clkout_src); | |
1506 | if (ret) { | |
1507 | dev_err(&client->dev, | |
1508 | "failed to reparent clkout %d to %d\n", | |
1509 | n, pdata->clkout[n].clkout_src); | |
1510 | return ret; | |
1511 | } | |
1512 | ||
1513 | ret = _si5351_clkout_set_drive_strength(drvdata, n, | |
1514 | pdata->clkout[n].drive); | |
1515 | if (ret) { | |
1516 | dev_err(&client->dev, | |
1517 | "failed set drive strength of clkout%d to %d\n", | |
1518 | n, pdata->clkout[n].drive); | |
1519 | return ret; | |
1520 | } | |
1a0483d2 SH |
1521 | |
1522 | ret = _si5351_clkout_set_disable_state(drvdata, n, | |
1523 | pdata->clkout[n].disable_state); | |
1524 | if (ret) { | |
1525 | dev_err(&client->dev, | |
1526 | "failed set disable state of clkout%d to %d\n", | |
1527 | n, pdata->clkout[n].disable_state); | |
1528 | return ret; | |
1529 | } | |
9abd5f05 SH |
1530 | } |
1531 | ||
1532 | /* register xtal input clock gate */ | |
1533 | memset(&init, 0, sizeof(init)); | |
1534 | init.name = si5351_input_names[0]; | |
1535 | init.ops = &si5351_xtal_ops; | |
1536 | init.flags = 0; | |
1537 | if (!IS_ERR(drvdata->pxtal)) { | |
1538 | drvdata->pxtal_name = __clk_get_name(drvdata->pxtal); | |
1539 | init.parent_names = &drvdata->pxtal_name; | |
1540 | init.num_parents = 1; | |
1541 | } | |
1542 | drvdata->xtal.init = &init; | |
4d89c3d5 SB |
1543 | ret = devm_clk_hw_register(&client->dev, &drvdata->xtal); |
1544 | if (ret) { | |
9abd5f05 | 1545 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1fffaf6a | 1546 | return ret; |
9abd5f05 SH |
1547 | } |
1548 | ||
1549 | /* register clkin input clock gate */ | |
1550 | if (drvdata->variant == SI5351_VARIANT_C) { | |
1551 | memset(&init, 0, sizeof(init)); | |
1552 | init.name = si5351_input_names[1]; | |
1553 | init.ops = &si5351_clkin_ops; | |
1554 | if (!IS_ERR(drvdata->pclkin)) { | |
1555 | drvdata->pclkin_name = __clk_get_name(drvdata->pclkin); | |
1556 | init.parent_names = &drvdata->pclkin_name; | |
1557 | init.num_parents = 1; | |
1558 | } | |
1559 | drvdata->clkin.init = &init; | |
4d89c3d5 SB |
1560 | ret = devm_clk_hw_register(&client->dev, &drvdata->clkin); |
1561 | if (ret) { | |
9abd5f05 SH |
1562 | dev_err(&client->dev, "unable to register %s\n", |
1563 | init.name); | |
1fffaf6a | 1564 | return ret; |
9abd5f05 SH |
1565 | } |
1566 | } | |
1567 | ||
1568 | /* Si5351C allows to mux either xtal or clkin to PLL input */ | |
1569 | num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1; | |
1570 | parent_names[0] = si5351_input_names[0]; | |
1571 | parent_names[1] = si5351_input_names[1]; | |
1572 | ||
1573 | /* register PLLA */ | |
1574 | drvdata->pll[0].num = 0; | |
1575 | drvdata->pll[0].drvdata = drvdata; | |
1576 | drvdata->pll[0].hw.init = &init; | |
1577 | memset(&init, 0, sizeof(init)); | |
1578 | init.name = si5351_pll_names[0]; | |
1579 | init.ops = &si5351_pll_ops; | |
1580 | init.flags = 0; | |
1581 | init.parent_names = parent_names; | |
1582 | init.num_parents = num_parents; | |
4d89c3d5 SB |
1583 | ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw); |
1584 | if (ret) { | |
9abd5f05 | 1585 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1fffaf6a | 1586 | return ret; |
9abd5f05 SH |
1587 | } |
1588 | ||
1589 | /* register PLLB or VXCO (Si5351B) */ | |
1590 | drvdata->pll[1].num = 1; | |
1591 | drvdata->pll[1].drvdata = drvdata; | |
1592 | drvdata->pll[1].hw.init = &init; | |
1593 | memset(&init, 0, sizeof(init)); | |
1594 | if (drvdata->variant == SI5351_VARIANT_B) { | |
1595 | init.name = si5351_pll_names[2]; | |
1596 | init.ops = &si5351_vxco_ops; | |
803c4331 | 1597 | init.flags = 0; |
9abd5f05 SH |
1598 | init.parent_names = NULL; |
1599 | init.num_parents = 0; | |
1600 | } else { | |
1601 | init.name = si5351_pll_names[1]; | |
1602 | init.ops = &si5351_pll_ops; | |
1603 | init.flags = 0; | |
1604 | init.parent_names = parent_names; | |
1605 | init.num_parents = num_parents; | |
1606 | } | |
4d89c3d5 SB |
1607 | ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw); |
1608 | if (ret) { | |
9abd5f05 | 1609 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1fffaf6a | 1610 | return ret; |
9abd5f05 SH |
1611 | } |
1612 | ||
1613 | /* register clk multisync and clk out divider */ | |
1614 | num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8; | |
1615 | parent_names[0] = si5351_pll_names[0]; | |
1616 | if (drvdata->variant == SI5351_VARIANT_B) | |
1617 | parent_names[1] = si5351_pll_names[2]; | |
1618 | else | |
1619 | parent_names[1] = si5351_pll_names[1]; | |
1620 | ||
9a78b169 | 1621 | drvdata->msynth = devm_kcalloc(&client->dev, num_clocks, |
9abd5f05 | 1622 | sizeof(*drvdata->msynth), GFP_KERNEL); |
9a78b169 | 1623 | drvdata->clkout = devm_kcalloc(&client->dev, num_clocks, |
9abd5f05 | 1624 | sizeof(*drvdata->clkout), GFP_KERNEL); |
4d89c3d5 | 1625 | drvdata->num_clkout = num_clocks; |
9abd5f05 | 1626 | |
4d89c3d5 | 1627 | if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) { |
0cd3be6e | 1628 | ret = -ENOMEM; |
1fffaf6a | 1629 | return ret; |
0cd3be6e | 1630 | } |
9abd5f05 SH |
1631 | |
1632 | for (n = 0; n < num_clocks; n++) { | |
1633 | drvdata->msynth[n].num = n; | |
1634 | drvdata->msynth[n].drvdata = drvdata; | |
1635 | drvdata->msynth[n].hw.init = &init; | |
1636 | memset(&init, 0, sizeof(init)); | |
1637 | init.name = si5351_msynth_names[n]; | |
1638 | init.ops = &si5351_msynth_ops; | |
1639 | init.flags = 0; | |
1640 | if (pdata->clkout[n].pll_master) | |
1641 | init.flags |= CLK_SET_RATE_PARENT; | |
1642 | init.parent_names = parent_names; | |
1643 | init.num_parents = 2; | |
4d89c3d5 SB |
1644 | ret = devm_clk_hw_register(&client->dev, |
1645 | &drvdata->msynth[n].hw); | |
1646 | if (ret) { | |
9abd5f05 SH |
1647 | dev_err(&client->dev, "unable to register %s\n", |
1648 | init.name); | |
1fffaf6a | 1649 | return ret; |
9abd5f05 SH |
1650 | } |
1651 | } | |
1652 | ||
1653 | num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3; | |
1654 | parent_names[2] = si5351_input_names[0]; | |
1655 | parent_names[3] = si5351_input_names[1]; | |
1656 | for (n = 0; n < num_clocks; n++) { | |
1657 | parent_names[0] = si5351_msynth_names[n]; | |
1658 | parent_names[1] = (n < 4) ? si5351_msynth_names[0] : | |
1659 | si5351_msynth_names[4]; | |
1660 | ||
1661 | drvdata->clkout[n].num = n; | |
1662 | drvdata->clkout[n].drvdata = drvdata; | |
1663 | drvdata->clkout[n].hw.init = &init; | |
1664 | memset(&init, 0, sizeof(init)); | |
1665 | init.name = si5351_clkout_names[n]; | |
1666 | init.ops = &si5351_clkout_ops; | |
1667 | init.flags = 0; | |
1668 | if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N) | |
1669 | init.flags |= CLK_SET_RATE_PARENT; | |
1670 | init.parent_names = parent_names; | |
1671 | init.num_parents = num_parents; | |
4d89c3d5 SB |
1672 | ret = devm_clk_hw_register(&client->dev, |
1673 | &drvdata->clkout[n].hw); | |
1674 | if (ret) { | |
9abd5f05 SH |
1675 | dev_err(&client->dev, "unable to register %s\n", |
1676 | init.name); | |
1fffaf6a | 1677 | return ret; |
9abd5f05 | 1678 | } |
6532cb71 MB |
1679 | |
1680 | /* set initial clkout rate */ | |
1681 | if (pdata->clkout[n].rate != 0) { | |
1682 | int ret; | |
4d89c3d5 SB |
1683 | ret = clk_set_rate(drvdata->clkout[n].hw.clk, |
1684 | pdata->clkout[n].rate); | |
6532cb71 MB |
1685 | if (ret != 0) { |
1686 | dev_err(&client->dev, "Cannot set rate : %d\n", | |
1687 | ret); | |
1688 | } | |
1689 | } | |
9abd5f05 SH |
1690 | } |
1691 | ||
361dde3c LPC |
1692 | ret = devm_of_clk_add_hw_provider(&client->dev, si53351_of_clk_get, |
1693 | drvdata); | |
9abd5f05 SH |
1694 | if (ret) { |
1695 | dev_err(&client->dev, "unable to add clk provider\n"); | |
1fffaf6a | 1696 | return ret; |
9abd5f05 SH |
1697 | } |
1698 | ||
1699 | return 0; | |
1700 | } | |
1701 | ||
9abd5f05 SH |
1702 | static struct i2c_driver si5351_driver = { |
1703 | .driver = { | |
1704 | .name = "si5351", | |
1705 | .of_match_table = of_match_ptr(si5351_dt_ids), | |
1706 | }, | |
62279db5 | 1707 | .probe = si5351_i2c_probe, |
9abd5f05 SH |
1708 | .id_table = si5351_i2c_ids, |
1709 | }; | |
1710 | module_i2c_driver(si5351_driver); | |
1711 | ||
1712 | MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com"); | |
1713 | MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver"); | |
1714 | MODULE_LICENSE("GPL"); |