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Merge tag 'amd-drm-next-5.14-2021-05-19' of https://gitlab.freedesktop.org/agd5f...
[linux-block.git] / drivers / clk / clk-si5341.c
CommitLineData
3044a860
ML		 1// SPDX-License-Identifier: GPL-2.0
2/*
f9eec2ea 3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
3044a860
ML		 4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
f9eec2ea
ML		 6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
3044a860
ML		 12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/gcd.h>
18#include <linux/math64.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23#include <asm/unaligned.h>
24
69275187
ML		 25#define SI5341_NUM_INPUTS 4
26
3044a860 27#define SI5340_MAX_NUM_OUTPUTS 4
f9eec2ea
ML		 28#define SI5341_MAX_NUM_OUTPUTS 10
29#define SI5342_MAX_NUM_OUTPUTS 2
30#define SI5344_MAX_NUM_OUTPUTS 4
31#define SI5345_MAX_NUM_OUTPUTS 10
3044a860 32
3044a860 33#define SI5340_NUM_SYNTH 4
f9eec2ea
ML		 34#define SI5341_NUM_SYNTH 5
35#define SI5342_NUM_SYNTH 2
36#define SI5344_NUM_SYNTH 4
37#define SI5345_NUM_SYNTH 5
3044a860
ML		 38
39/* Range of the synthesizer fractional divider */
40#define SI5341_SYNTH_N_MIN 10
41#define SI5341_SYNTH_N_MAX 4095
42
43/* The chip can get its input clock from 3 input pins or an XTAL */
44
45/* There is one PLL running at 13500–14256 MHz */
46#define SI5341_PLL_VCO_MIN 13500000000ull
47#define SI5341_PLL_VCO_MAX 14256000000ull
48
49/* The 5 frequency synthesizers obtain their input from the PLL */
50struct clk_si5341_synth {
51 struct clk_hw hw;
52 struct clk_si5341 *data;
53 u8 index;
54};
55#define to_clk_si5341_synth(_hw) \
56 container_of(_hw, struct clk_si5341_synth, hw)
57
58/* The output stages can be connected to any synth (full mux) */
59struct clk_si5341_output {
60 struct clk_hw hw;
61 struct clk_si5341 *data;
62 u8 index;
63};
64#define to_clk_si5341_output(_hw) \
65 container_of(_hw, struct clk_si5341_output, hw)
66
67struct clk_si5341 {
68 struct clk_hw hw;
69 struct regmap *regmap;
70 struct i2c_client *i2c_client;
71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
69275187
ML		 73 struct clk *input_clk[SI5341_NUM_INPUTS];
74 const char *input_clk_name[SI5341_NUM_INPUTS];
3044a860
ML		 75 const u16 *reg_output_offset;
76 const u16 *reg_rdiv_offset;
77 u64 freq_vco; /* 13500–14256 MHz */
78 u8 num_outputs;
79 u8 num_synth;
f9eec2ea 80 u16 chip_id;
3044a860
ML		 81};
82#define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
83
84struct clk_si5341_output_config {
85 u8 out_format_drv_bits;
86 u8 out_cm_ampl_bits;
87 bool synth_master;
88 bool always_on;
89};
90
91#define SI5341_PAGE 0x0001
92#define SI5341_PN_BASE 0x0002
93#define SI5341_DEVICE_REV 0x0005
94#define SI5341_STATUS 0x000C
95#define SI5341_SOFT_RST 0x001C
69275187
ML		 96#define SI5341_IN_SEL 0x0021
97#define SI5341_XAXB_CFG 0x090E
98#define SI5341_IN_EN 0x0949
99#define SI5341_INX_TO_PFD_EN 0x094A
100
101/* Input selection */
102#define SI5341_IN_SEL_MASK 0x06
103#define SI5341_IN_SEL_SHIFT 1
104#define SI5341_IN_SEL_REGCTRL 0x01
105#define SI5341_INX_TO_PFD_SHIFT 4
106
107/* XTAL config bits */
108#define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
109#define SI5341_XAXB_CFG_PDNB BIT(1)
3044a860
ML		 110
111/* Input dividers (48-bit) */
112#define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
113#define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
69275187 114#define SI5341_PX_UPD 0x0230
3044a860
ML		 115
116/* PLL configuration */
117#define SI5341_PLL_M_NUM 0x0235
118#define SI5341_PLL_M_DEN 0x023B
119
120/* Output configuration */
121#define SI5341_OUT_CONFIG(output) \
122 ((output)->data->reg_output_offset[(output)->index])
123#define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
124#define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
125#define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
126#define SI5341_OUT_R_REG(output) \
127 ((output)->data->reg_rdiv_offset[(output)->index])
128
129/* Synthesize N divider */
130#define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
131#define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
132#define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
133
134/* Synthesizer output enable, phase bypass, power mode */
135#define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
136#define SI5341_SYNTH_N_PIBYP 0x0A04
137#define SI5341_SYNTH_N_PDNB 0x0A05
138#define SI5341_SYNTH_N_CLK_DIS 0x0B4A
139
140#define SI5341_REGISTER_MAX 0xBFF
141
142/* SI5341_OUT_CONFIG bits */
143#define SI5341_OUT_CFG_PDN BIT(0)
144#define SI5341_OUT_CFG_OE BIT(1)
145#define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
146
147/* Static configuration (to be moved to firmware) */
148struct si5341_reg_default {
149 u16 address;
150 u8 value;
151};
152
69275187
ML		 153static const char * const si5341_input_clock_names[] = {
154 "in0", "in1", "in2", "xtal"
155};
156
3044a860 157/* Output configuration registers 0..9 are not quite logically organized */
f9eec2ea 158/* Also for si5345 */
3044a860
ML		 159static const u16 si5341_reg_output_offset[] = {
160 0x0108,
161 0x010D,
162 0x0112,
163 0x0117,
164 0x011C,
165 0x0121,
166 0x0126,
167 0x012B,
168 0x0130,
169 0x013A,
170};
171
f9eec2ea 172/* for si5340, si5342 and si5344 */
3044a860
ML		 173static const u16 si5340_reg_output_offset[] = {
174 0x0112,
175 0x0117,
176 0x0126,
177 0x012B,
178};
179
180/* The location of the R divider registers */
181static const u16 si5341_reg_rdiv_offset[] = {
182 0x024A,
183 0x024D,
184 0x0250,
185 0x0253,
186 0x0256,
187 0x0259,
188 0x025C,
189 0x025F,
190 0x0262,
191 0x0268,
192};
193static const u16 si5340_reg_rdiv_offset[] = {
194 0x0250,
195 0x0253,
196 0x025C,
197 0x025F,
198};
199
200/*
201 * Programming sequence from ClockBuilder, settings to initialize the system
202 * using only the XTAL input, without pre-divider.
203 * This also contains settings that aren't mentioned anywhere in the datasheet.
204 * The "known" settings like synth and output configuration are done later.
205 */
206static const struct si5341_reg_default si5341_reg_defaults[] = {
207 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
208 { 0x0018, 0xFF }, /* INT mask */
209 { 0x0021, 0x0F }, /* Select XTAL as input */
210 { 0x0022, 0x00 }, /* Not in datasheet */
211 { 0x002B, 0x02 }, /* SPI config */
212 { 0x002C, 0x20 }, /* LOS enable for XTAL */
213 { 0x002D, 0x00 }, /* LOS timing */
214 { 0x002E, 0x00 },
215 { 0x002F, 0x00 },
216 { 0x0030, 0x00 },
217 { 0x0031, 0x00 },
218 { 0x0032, 0x00 },
219 { 0x0033, 0x00 },
220 { 0x0034, 0x00 },
221 { 0x0035, 0x00 },
222 { 0x0036, 0x00 },
223 { 0x0037, 0x00 },
224 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
225 { 0x0039, 0x00 },
226 { 0x003A, 0x00 },
227 { 0x003B, 0x00 },
228 { 0x003C, 0x00 },
229 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
230 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
231 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
232 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
233 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
234 { 0x009E, 0x00 }, /* Not in datasheet */
235 { 0x0102, 0x01 }, /* Enable outputs */
236 { 0x013F, 0x00 }, /* Not in datasheet */
237 { 0x0140, 0x00 }, /* Not in datasheet */
238 { 0x0141, 0x40 }, /* OUT LOS */
239 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
240 { 0x0203, 0x00 },
241 { 0x0204, 0x00 },
242 { 0x0205, 0x00 },
243 { 0x0206, 0x00 }, /* PXAXB (2^x) */
244 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
245 { 0x0209, 0x00 },
246 { 0x020A, 0x00 },
247 { 0x020B, 0x00 },
248 { 0x020C, 0x00 },
249 { 0x020D, 0x00 },
250 { 0x020E, 0x00 },
251 { 0x020F, 0x00 },
252 { 0x0210, 0x00 },
253 { 0x0211, 0x00 },
254 { 0x0212, 0x00 },
255 { 0x0213, 0x00 },
256 { 0x0214, 0x00 },
257 { 0x0215, 0x00 },
258 { 0x0216, 0x00 },
259 { 0x0217, 0x00 },
260 { 0x0218, 0x00 },
261 { 0x0219, 0x00 },
262 { 0x021A, 0x00 },
263 { 0x021B, 0x00 },
264 { 0x021C, 0x00 },
265 { 0x021D, 0x00 },
266 { 0x021E, 0x00 },
267 { 0x021F, 0x00 },
268 { 0x0220, 0x00 },
269 { 0x0221, 0x00 },
270 { 0x0222, 0x00 },
271 { 0x0223, 0x00 },
272 { 0x0224, 0x00 },
273 { 0x0225, 0x00 },
274 { 0x0226, 0x00 },
275 { 0x0227, 0x00 },
276 { 0x0228, 0x00 },
277 { 0x0229, 0x00 },
278 { 0x022A, 0x00 },
279 { 0x022B, 0x00 },
280 { 0x022C, 0x00 },
281 { 0x022D, 0x00 },
282 { 0x022E, 0x00 },
283 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
284 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
285 { 0x026C, 0x00 },
286 { 0x026D, 0x00 },
287 { 0x026E, 0x00 },
288 { 0x026F, 0x00 },
289 { 0x0270, 0x00 },
290 { 0x0271, 0x00 },
291 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
292 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
293 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
294 { 0x033C, 0x00 },
295 { 0x033D, 0x00 },
296 { 0x033E, 0x00 },
297 { 0x033F, 0x00 },
298 { 0x0340, 0x00 },
299 { 0x0341, 0x00 },
300 { 0x0342, 0x00 },
301 { 0x0343, 0x00 },
302 { 0x0344, 0x00 },
303 { 0x0345, 0x00 },
304 { 0x0346, 0x00 },
305 { 0x0347, 0x00 },
306 { 0x0348, 0x00 },
307 { 0x0349, 0x00 },
308 { 0x034A, 0x00 },
309 { 0x034B, 0x00 },
310 { 0x034C, 0x00 },
311 { 0x034D, 0x00 },
312 { 0x034E, 0x00 },
313 { 0x034F, 0x00 },
314 { 0x0350, 0x00 },
315 { 0x0351, 0x00 },
316 { 0x0352, 0x00 },
317 { 0x0353, 0x00 },
318 { 0x0354, 0x00 },
319 { 0x0355, 0x00 },
320 { 0x0356, 0x00 },
321 { 0x0357, 0x00 },
322 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
323 { 0x0359, 0x00 }, /* Nx_DELAY */
324 { 0x035A, 0x00 },
325 { 0x035B, 0x00 },
326 { 0x035C, 0x00 },
327 { 0x035D, 0x00 },
328 { 0x035E, 0x00 },
329 { 0x035F, 0x00 },
330 { 0x0360, 0x00 },
331 { 0x0361, 0x00 },
332 { 0x0362, 0x00 }, /* Nx_DELAY end */
333 { 0x0802, 0x00 }, /* Not in datasheet */
334 { 0x0803, 0x00 }, /* Not in datasheet */
335 { 0x0804, 0x00 }, /* Not in datasheet */
336 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
337 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
338 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
339 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
340 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
341 { 0x0A02, 0x00 }, /* Not in datasheet */
342 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
343};
344
345/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
346static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
347 u64 *val1, u32 *val2)
348{
349 int err;
350 u8 r[10];
351
352 err = regmap_bulk_read(regmap, reg, r, 10);
353 if (err < 0)
354 return err;
355
356 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
357 (get_unaligned_le32(r));
358 *val2 = get_unaligned_le32(&r[6]);
359
360 return 0;
361}
362
363static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
364 u64 n_num, u32 n_den)
365{
366 u8 r[10];
367
368 /* Shift left as far as possible without overflowing */
369 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
370 n_num <<= 1;
371 n_den <<= 1;
372 }
373
374 /* 44 bits (6 bytes) numerator */
375 put_unaligned_le32(n_num, r);
376 r[4] = (n_num >> 32) & 0xff;
377 r[5] = (n_num >> 40) & 0x0f;
378 /* 32 bits denominator */
379 put_unaligned_le32(n_den, &r[6]);
380
381 /* Program the fraction */
382 return regmap_bulk_write(regmap, reg, r, sizeof(r));
383}
384
385/* VCO, we assume it runs at a constant frequency */
386static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
387 unsigned long parent_rate)
388{
389 struct clk_si5341 *data = to_clk_si5341(hw);
390 int err;
391 u64 res;
392 u64 m_num;
393 u32 m_den;
394 unsigned int shift;
395
396 /* Assume that PDIV is not being used, just read the PLL setting */
397 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
398 &m_num, &m_den);
399 if (err < 0)
400 return 0;
401
402 if (!m_num || !m_den)
403 return 0;
404
405 /*
406 * Though m_num is 64-bit, only the upper bits are actually used. While
407 * calculating m_num and m_den, they are shifted as far as possible to
408 * the left. To avoid 96-bit division here, we just shift them back so
409 * we can do with just 64 bits.
410 */
411 shift = 0;
412 res = m_num;
413 while (res & 0xffff00000000ULL) {
414 ++shift;
415 res >>= 1;
416 }
417 res *= parent_rate;
418 do_div(res, (m_den >> shift));
419
420 /* We cannot return the actual frequency in 32 bit, store it locally */
421 data->freq_vco = res;
422
423 /* Report kHz since the value is out of range */
424 do_div(res, 1000);
425
426 return (unsigned long)res;
427}
428
69275187
ML		 429static int si5341_clk_get_selected_input(struct clk_si5341 *data)
430{
431 int err;
432 u32 val;
433
434 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
435 if (err < 0)
436 return err;
437
438 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
439}
440
441static u8 si5341_clk_get_parent(struct clk_hw *hw)
442{
443 struct clk_si5341 *data = to_clk_si5341(hw);
444 int res = si5341_clk_get_selected_input(data);
445
446 if (res < 0)
447 return 0; /* Apparently we cannot report errors */
448
449 return res;
450}
451
452static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
453{
454 int err;
455 u8 val;
456
457 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
458 /* Enable register-based input selection */
459 val |= SI5341_IN_SEL_REGCTRL;
460
461 err = regmap_update_bits(data->regmap,
462 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
463 if (err < 0)
464 return err;
465
466 if (index < 3) {
467 /* Enable input buffer for selected input */
468 err = regmap_update_bits(data->regmap,
469 SI5341_IN_EN, 0x07, BIT(index));
470 if (err < 0)
471 return err;
472
473 /* Enables the input to phase detector */
474 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
475 0x7 << SI5341_INX_TO_PFD_SHIFT,
476 BIT(index + SI5341_INX_TO_PFD_SHIFT));
477 if (err < 0)
478 return err;
479
480 /* Power down XTAL oscillator and buffer */
481 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
482 SI5341_XAXB_CFG_PDNB, 0);
483 if (err < 0)
484 return err;
485
486 /*
487 * Set the P divider to "1". There's no explanation in the
488 * datasheet of these registers, but the clockbuilder software
489 * programs a "1" when the input is being used.
490 */
491 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
492 if (err < 0)
493 return err;
494
495 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
496 if (err < 0)
497 return err;
498
499 /* Set update PDIV bit */
500 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
501 if (err < 0)
502 return err;
503 } else {
504 /* Disable all input buffers */
505 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
506 if (err < 0)
507 return err;
508
509 /* Disable input to phase detector */
510 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
511 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
512 if (err < 0)
513 return err;
514
515 /* Power up XTAL oscillator and buffer */
516 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
517 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
518 if (err < 0)
519 return err;
520 }
521
522 return 0;
523}
524
525static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
526{
527 struct clk_si5341 *data = to_clk_si5341(hw);
528
529 return si5341_clk_reparent(data, index);
530}
531
3044a860 532static const struct clk_ops si5341_clk_ops = {
69275187
ML		 533 .set_parent = si5341_clk_set_parent,
534 .get_parent = si5341_clk_get_parent,
3044a860
ML		 535 .recalc_rate = si5341_clk_recalc_rate,
536};
537
538/* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
539
540/* The synthesizer is on if all power and enable bits are set */
541static int si5341_synth_clk_is_on(struct clk_hw *hw)
542{
543 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
544 int err;
545 u32 val;
546 u8 index = synth->index;
547
548 err = regmap_read(synth->data->regmap,
549 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
550 if (err < 0)
551 return 0;
552
553 if (!(val & BIT(index)))
554 return 0;
555
556 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
557 if (err < 0)
558 return 0;
559
560 if (!(val & BIT(index)))
561 return 0;
562
563 /* This bit must be 0 for the synthesizer to receive clock input */
564 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
565 if (err < 0)
566 return 0;
567
568 return !(val & BIT(index));
569}
570
571static void si5341_synth_clk_unprepare(struct clk_hw *hw)
572{
573 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
574 u8 index = synth->index; /* In range 0..5 */
575 u8 mask = BIT(index);
576
577 /* Disable output */
578 regmap_update_bits(synth->data->regmap,
579 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
580 /* Power down */
581 regmap_update_bits(synth->data->regmap,
582 SI5341_SYNTH_N_PDNB, mask, 0);
583 /* Disable clock input to synth (set to 1 to disable) */
584 regmap_update_bits(synth->data->regmap,
585 SI5341_SYNTH_N_CLK_DIS, mask, mask);
586}
587
588static int si5341_synth_clk_prepare(struct clk_hw *hw)
589{
590 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
591 int err;
592 u8 index = synth->index;
593 u8 mask = BIT(index);
594
595 /* Power up */
596 err = regmap_update_bits(synth->data->regmap,
597 SI5341_SYNTH_N_PDNB, mask, mask);
598 if (err < 0)
599 return err;
600
601 /* Enable clock input to synth (set bit to 0 to enable) */
602 err = regmap_update_bits(synth->data->regmap,
603 SI5341_SYNTH_N_CLK_DIS, mask, 0);
604 if (err < 0)
605 return err;
606
607 /* Enable output */
608 return regmap_update_bits(synth->data->regmap,
609 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
610}
611
612/* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
613static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
614 unsigned long parent_rate)
615{
616 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
617 u64 f;
618 u64 n_num;
619 u32 n_den;
620 int err;
621
622 err = si5341_decode_44_32(synth->data->regmap,
623 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
624 if (err < 0)
625 return err;
626
627 /*
628 * n_num and n_den are shifted left as much as possible, so to prevent
629 * overflow in 64-bit math, we shift n_den 4 bits to the right
630 */
631 f = synth->data->freq_vco;
632 f *= n_den >> 4;
633
634 /* Now we need to to 64-bit division: f/n_num */
635 /* And compensate for the 4 bits we dropped */
636 f = div64_u64(f, (n_num >> 4));
637
638 return f;
639}
640
641static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
642 unsigned long *parent_rate)
643{
644 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
645 u64 f;
646
647 /* The synthesizer accuracy is such that anything in range will work */
648 f = synth->data->freq_vco;
649 do_div(f, SI5341_SYNTH_N_MAX);
650 if (rate < f)
651 return f;
652
653 f = synth->data->freq_vco;
654 do_div(f, SI5341_SYNTH_N_MIN);
655 if (rate > f)
656 return f;
657
658 return rate;
659}
660
661static int si5341_synth_program(struct clk_si5341_synth *synth,
662 u64 n_num, u32 n_den, bool is_integer)
663{
664 int err;
665 u8 index = synth->index;
666
667 err = si5341_encode_44_32(synth->data->regmap,
668 SI5341_SYNTH_N_NUM(index), n_num, n_den);
669
670 err = regmap_update_bits(synth->data->regmap,
671 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
672 if (err < 0)
673 return err;
674
675 return regmap_write(synth->data->regmap,
676 SI5341_SYNTH_N_UPD(index), 0x01);
677}
678
679
680static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
681 unsigned long parent_rate)
682{
683 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
684 u64 n_num;
685 u32 n_den;
686 u32 r;
687 u32 g;
688 bool is_integer;
689
690 n_num = synth->data->freq_vco;
3044a860
ML		 691
692 /* see if there's an integer solution */
693 r = do_div(n_num, rate);
694 is_integer = (r == 0);
695 if (is_integer) {
696 /* Integer divider equal to n_num */
697 n_den = 1;
698 } else {
699 /* Calculate a fractional solution */
700 g = gcd(r, rate);
701 n_den = rate / g;
702 n_num *= n_den;
703 n_num += r / g;
704 }
705
706 dev_dbg(&synth->data->i2c_client->dev,
707 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
708 synth->index, n_num, n_den,
709 is_integer ? "int" : "frac");
710
711 return si5341_synth_program(synth, n_num, n_den, is_integer);
712}
713
714static const struct clk_ops si5341_synth_clk_ops = {
715 .is_prepared = si5341_synth_clk_is_on,
716 .prepare = si5341_synth_clk_prepare,
717 .unprepare = si5341_synth_clk_unprepare,
718 .recalc_rate = si5341_synth_clk_recalc_rate,
719 .round_rate = si5341_synth_clk_round_rate,
720 .set_rate = si5341_synth_clk_set_rate,
721};
722
723static int si5341_output_clk_is_on(struct clk_hw *hw)
724{
725 struct clk_si5341_output *output = to_clk_si5341_output(hw);
726 int err;
727 u32 val;
728
729 err = regmap_read(output->data->regmap,
730 SI5341_OUT_CONFIG(output), &val);
731 if (err < 0)
732 return err;
733
734 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
735 return (val & 0x03) == SI5341_OUT_CFG_OE;
736}
737
738/* Disables and then powers down the output */
739static void si5341_output_clk_unprepare(struct clk_hw *hw)
740{
741 struct clk_si5341_output *output = to_clk_si5341_output(hw);
742
743 regmap_update_bits(output->data->regmap,
744 SI5341_OUT_CONFIG(output),
745 SI5341_OUT_CFG_OE, 0);
746 regmap_update_bits(output->data->regmap,
747 SI5341_OUT_CONFIG(output),
748 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
749}
750
751/* Powers up and then enables the output */
752static int si5341_output_clk_prepare(struct clk_hw *hw)
753{
754 struct clk_si5341_output *output = to_clk_si5341_output(hw);
755 int err;
756
757 err = regmap_update_bits(output->data->regmap,
758 SI5341_OUT_CONFIG(output),
759 SI5341_OUT_CFG_PDN, 0);
760 if (err < 0)
761 return err;
762
763 return regmap_update_bits(output->data->regmap,
764 SI5341_OUT_CONFIG(output),
765 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
766}
767
768static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
769 unsigned long parent_rate)
770{
771 struct clk_si5341_output *output = to_clk_si5341_output(hw);
772 int err;
773 u32 val;
774 u32 r_divider;
775 u8 r[3];
776
777 err = regmap_bulk_read(output->data->regmap,
778 SI5341_OUT_R_REG(output), r, 3);
779 if (err < 0)
780 return err;
781
782 /* Calculate value as 24-bit integer*/
783 r_divider = r[2] << 16 | r[1] << 8 | r[0];
784
785 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
786 if (!r_divider)
787 return 0;
788
789 /* Divider is 2*(Rx_REG+1) */
790 r_divider += 1;
791 r_divider <<= 1;
792
793 err = regmap_read(output->data->regmap,
794 SI5341_OUT_CONFIG(output), &val);
795 if (err < 0)
796 return err;
797
798 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
799 r_divider = 2;
800
801 return parent_rate / r_divider;
802}
803
804static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
805 unsigned long *parent_rate)
806{
807 unsigned long r;
808
809 r = *parent_rate >> 1;
810
811 /* If rate is an even divisor, no changes to parent required */
812 if (r && !(r % rate))
813 return (long)rate;
814
815 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
816 if (rate > 200000000) {
817 /* minimum r-divider is 2 */
818 r = 2;
819 } else {
820 /* Take a parent frequency near 400 MHz */
821 r = (400000000u / rate) & ~1;
822 }
823 *parent_rate = r * rate;
824 } else {
825 /* We cannot change our parent's rate, report what we can do */
826 r /= rate;
827 rate = *parent_rate / (r << 1);
828 }
829
830 return rate;
831}
832
833static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
834 unsigned long parent_rate)
835{
836 struct clk_si5341_output *output = to_clk_si5341_output(hw);
837 /* Frequency divider is (r_div + 1) * 2 */
838 u32 r_div = (parent_rate / rate) >> 1;
839 int err;
840 u8 r[3];
841
842 if (r_div <= 1)
843 r_div = 0;
844 else if (r_div >= BIT(24))
845 r_div = BIT(24) - 1;
846 else
847 --r_div;
848
849 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
850 err = regmap_update_bits(output->data->regmap,
851 SI5341_OUT_CONFIG(output),
852 SI5341_OUT_CFG_RDIV_FORCE2,
853 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
854 if (err < 0)
855 return err;
856
857 /* Always write Rx_REG, because a zero value disables the divider */
858 r[0] = r_div ? (r_div & 0xff) : 1;
859 r[1] = (r_div >> 8) & 0xff;
860 r[2] = (r_div >> 16) & 0xff;
861 err = regmap_bulk_write(output->data->regmap,
862 SI5341_OUT_R_REG(output), r, 3);
863
864 return 0;
865}
866
867static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
868{
869 return regmap_update_bits(output->data->regmap,
870 SI5341_OUT_MUX_SEL(output), 0x07, index);
871}
872
873static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
874{
875 struct clk_si5341_output *output = to_clk_si5341_output(hw);
876
877 if (index >= output->data->num_synth)
878 return -EINVAL;
879
880 return si5341_output_reparent(output, index);
881}
882
883static u8 si5341_output_get_parent(struct clk_hw *hw)
884{
885 struct clk_si5341_output *output = to_clk_si5341_output(hw);
3044a860
ML		 886 u32 val;
887
84afc9ec 888 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
3044a860
ML		 889
890 return val & 0x7;
891}
892
893static const struct clk_ops si5341_output_clk_ops = {
894 .is_prepared = si5341_output_clk_is_on,
895 .prepare = si5341_output_clk_prepare,
896 .unprepare = si5341_output_clk_unprepare,
897 .recalc_rate = si5341_output_clk_recalc_rate,
898 .round_rate = si5341_output_clk_round_rate,
899 .set_rate = si5341_output_clk_set_rate,
900 .set_parent = si5341_output_set_parent,
901 .get_parent = si5341_output_get_parent,
902};
903
904/*
905 * The chip can be bought in a pre-programmed version, or one can program the
906 * NVM in the chip to boot up in a preset mode. This routine tries to determine
907 * if that's the case, or if we need to reset and program everything from
908 * scratch. Returns negative error, or true/false.
909 */
910static int si5341_is_programmed_already(struct clk_si5341 *data)
911{
912 int err;
913 u8 r[4];
914
915 /* Read the PLL divider value, it must have a non-zero value */
916 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
917 r, ARRAY_SIZE(r));
918 if (err < 0)
919 return err;
920
921 return !!get_unaligned_le32(r);
922}
923
924static struct clk_hw *
925of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
926{
927 struct clk_si5341 *data = _data;
928 unsigned int idx = clkspec->args[1];
929 unsigned int group = clkspec->args[0];
930
931 switch (group) {
932 case 0:
933 if (idx >= data->num_outputs) {
934 dev_err(&data->i2c_client->dev,
935 "invalid output index %u\n", idx);
936 return ERR_PTR(-EINVAL);
937 }
938 return &data->clk[idx].hw;
939 case 1:
940 if (idx >= data->num_synth) {
941 dev_err(&data->i2c_client->dev,
942 "invalid synthesizer index %u\n", idx);
943 return ERR_PTR(-EINVAL);
944 }
945 return &data->synth[idx].hw;
946 case 2:
947 if (idx > 0) {
948 dev_err(&data->i2c_client->dev,
949 "invalid PLL index %u\n", idx);
950 return ERR_PTR(-EINVAL);
951 }
952 return &data->hw;
953 default:
954 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
955 return ERR_PTR(-EINVAL);
956 }
957}
958
959static int si5341_probe_chip_id(struct clk_si5341 *data)
960{
961 int err;
962 u8 reg[4];
963 u16 model;
964
965 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
966 ARRAY_SIZE(reg));
967 if (err < 0) {
968 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
969 return err;
970 }
971
972 model = get_unaligned_le16(reg);
973
974 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
975 model, reg[2], reg[3]);
976
977 switch (model) {
978 case 0x5340:
979 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
980 data->num_synth = SI5340_NUM_SYNTH;
981 data->reg_output_offset = si5340_reg_output_offset;
982 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
983 break;
984 case 0x5341:
985 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
986 data->num_synth = SI5341_NUM_SYNTH;
987 data->reg_output_offset = si5341_reg_output_offset;
988 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
989 break;
f9eec2ea
ML		 990 case 0x5342:
991 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
992 data->num_synth = SI5342_NUM_SYNTH;
993 data->reg_output_offset = si5340_reg_output_offset;
994 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
995 break;
996 case 0x5344:
997 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
998 data->num_synth = SI5344_NUM_SYNTH;
999 data->reg_output_offset = si5340_reg_output_offset;
1000 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1001 break;
1002 case 0x5345:
1003 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1004 data->num_synth = SI5345_NUM_SYNTH;
1005 data->reg_output_offset = si5341_reg_output_offset;
1006 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1007 break;
3044a860
ML		 1008 default:
1009 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1010 model);
1011 return -EINVAL;
1012 }
1013
f9eec2ea
ML		 1014 data->chip_id = model;
1015
3044a860
ML		 1016 return 0;
1017}
1018
1019/* Read active settings into the regmap cache for later reference */
1020static int si5341_read_settings(struct clk_si5341 *data)
1021{
1022 int err;
1023 u8 i;
1024 u8 r[10];
1025
1026 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1027 if (err < 0)
1028 return err;
1029
1030 err = regmap_bulk_read(data->regmap,
1031 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1032 if (err < 0)
1033 return err;
1034
1035 err = regmap_bulk_read(data->regmap,
1036 SI5341_SYNTH_N_CLK_DIS, r, 1);
1037 if (err < 0)
1038 return err;
1039
1040 for (i = 0; i < data->num_synth; ++i) {
1041 err = regmap_bulk_read(data->regmap,
1042 SI5341_SYNTH_N_NUM(i), r, 10);
1043 if (err < 0)
1044 return err;
1045 }
1046
1047 for (i = 0; i < data->num_outputs; ++i) {
1048 err = regmap_bulk_read(data->regmap,
1049 data->reg_output_offset[i], r, 4);
1050 if (err < 0)
1051 return err;
1052
1053 err = regmap_bulk_read(data->regmap,
1054 data->reg_rdiv_offset[i], r, 3);
1055 if (err < 0)
1056 return err;
1057 }
1058
1059 return 0;
1060}
1061
1062static int si5341_write_multiple(struct clk_si5341 *data,
1063 const struct si5341_reg_default *values, unsigned int num_values)
1064{
1065 unsigned int i;
1066 int res;
1067
1068 for (i = 0; i < num_values; ++i) {
1069 res = regmap_write(data->regmap,
1070 values[i].address, values[i].value);
1071 if (res < 0) {
1072 dev_err(&data->i2c_client->dev,
1073 "Failed to write %#x:%#x\n",
1074 values[i].address, values[i].value);
1075 return res;
1076 }
1077 }
1078
1079 return 0;
1080}
1081
1082static const struct si5341_reg_default si5341_preamble[] = {
1083 { 0x0B25, 0x00 },
1084 { 0x0502, 0x01 },
1085 { 0x0505, 0x03 },
1086 { 0x0957, 0x1F },
1087 { 0x0B4E, 0x1A },
1088};
1089
f9eec2ea
ML		 1090static const struct si5341_reg_default si5345_preamble[] = {
1091 { 0x0B25, 0x00 },
1092 { 0x0540, 0x01 },
1093};
1094
3044a860
ML		 1095static int si5341_send_preamble(struct clk_si5341 *data)
1096{
1097 int res;
1098 u32 revision;
1099
1100 /* For revision 2 and up, the values are slightly different */
1101 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1102 if (res < 0)
1103 return res;
1104
1105 /* Write "preamble" as specified by datasheet */
1106 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1107 if (res < 0)
1108 return res;
f9eec2ea
ML		 1109
1110 /* The si5342..si5345 require a different preamble */
1111 if (data->chip_id > 0x5341)
1112 res = si5341_write_multiple(data,
1113 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1114 else
1115 res = si5341_write_multiple(data,
1116 si5341_preamble, ARRAY_SIZE(si5341_preamble));
3044a860
ML		 1117 if (res < 0)
1118 return res;
1119
1120 /* Datasheet specifies a 300ms wait after sending the preamble */
1121 msleep(300);
1122
1123 return 0;
1124}
1125
1126/* Perform a soft reset and write post-amble */
1127static int si5341_finalize_defaults(struct clk_si5341 *data)
1128{
1129 int res;
1130 u32 revision;
1131
1132 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1133 if (res < 0)
1134 return res;
1135
1136 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1137
1138 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1139 if (res < 0)
1140 return res;
1141
f9eec2ea
ML		 1142 /* The si5342..si5345 have an additional post-amble */
1143 if (data->chip_id > 0x5341) {
1144 res = regmap_write(data->regmap, 0x540, 0x0);
1145 if (res < 0)
1146 return res;
1147 }
1148
3044a860
ML		 1149 /* Datasheet does not explain these nameless registers */
1150 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1151 if (res < 0)
1152 return res;
1153 res = regmap_write(data->regmap, 0x0B25, 0x02);
1154 if (res < 0)
1155 return res;
1156
1157 return 0;
1158}
1159
1160
1161static const struct regmap_range si5341_regmap_volatile_range[] = {
1162 regmap_reg_range(0x000C, 0x0012), /* Status */
1163 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1164 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
69275187
ML		 1165 /* Update bits for P divider and synth config */
1166 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
3044a860
ML		 1167 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1168 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1169 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1170 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1171 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1172};
1173
1174static const struct regmap_access_table si5341_regmap_volatile = {
1175 .yes_ranges = si5341_regmap_volatile_range,
1176 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1177};
1178
1179/* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1180static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1181 {
1182 .range_min = 0,
1183 .range_max = SI5341_REGISTER_MAX,
1184 .selector_reg = SI5341_PAGE,
1185 .selector_mask = 0xff,
1186 .selector_shift = 0,
1187 .window_start = 0,
1188 .window_len = 256,
1189 },
1190};
1191
1192static const struct regmap_config si5341_regmap_config = {
1193 .reg_bits = 8,
1194 .val_bits = 8,
1195 .cache_type = REGCACHE_RBTREE,
1196 .ranges = si5341_regmap_ranges,
1197 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1198 .max_register = SI5341_REGISTER_MAX,
1199 .volatile_table = &si5341_regmap_volatile,
1200};
1201
1202static int si5341_dt_parse_dt(struct i2c_client *client,
1203 struct clk_si5341_output_config *config)
1204{
1205 struct device_node *child;
1206 struct device_node *np = client->dev.of_node;
1207 u32 num;
1208 u32 val;
1209
1210 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1211 SI5341_MAX_NUM_OUTPUTS);
1212
1213 for_each_child_of_node(np, child) {
1214 if (of_property_read_u32(child, "reg", &num)) {
1215 dev_err(&client->dev, "missing reg property of %s\n",
1216 child->name);
1217 goto put_child;
1218 }
1219
1220 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1221 dev_err(&client->dev, "invalid clkout %d\n", num);
1222 goto put_child;
1223 }
1224
1225 if (!of_property_read_u32(child, "silabs,format", &val)) {
1226 /* Set cm and ampl conservatively to 3v3 settings */
1227 switch (val) {
1228 case 1: /* normal differential */
1229 config[num].out_cm_ampl_bits = 0x33;
1230 break;
1231 case 2: /* low-power differential */
1232 config[num].out_cm_ampl_bits = 0x13;
1233 break;
1234 case 4: /* LVCMOS */
1235 config[num].out_cm_ampl_bits = 0x33;
1236 /* Set SI recommended impedance for LVCMOS */
1237 config[num].out_format_drv_bits |= 0xc0;
1238 break;
1239 default:
1240 dev_err(&client->dev,
1241 "invalid silabs,format %u for %u\n",
1242 val, num);
1243 goto put_child;
1244 }
1245 config[num].out_format_drv_bits &= ~0x07;
1246 config[num].out_format_drv_bits |= val & 0x07;
1247 /* Always enable the SYNC feature */
1248 config[num].out_format_drv_bits |= 0x08;
1249 }
1250
1251 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1252 if (val > 0xf) {
1253 dev_err(&client->dev,
1254 "invalid silabs,common-mode %u\n",
1255 val);
1256 goto put_child;
1257 }
1258 config[num].out_cm_ampl_bits &= 0xf0;
1259 config[num].out_cm_ampl_bits |= val & 0x0f;
1260 }
1261
1262 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1263 if (val > 0xf) {
1264 dev_err(&client->dev,
1265 "invalid silabs,amplitude %u\n",
1266 val);
1267 goto put_child;
1268 }
1269 config[num].out_cm_ampl_bits &= 0x0f;
1270 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1271 }
1272
1273 if (of_property_read_bool(child, "silabs,disable-high"))
1274 config[num].out_format_drv_bits |= 0x10;
1275
1276 config[num].synth_master =
1277 of_property_read_bool(child, "silabs,synth-master");
1278
1279 config[num].always_on =
1280 of_property_read_bool(child, "always-on");
1281 }
1282
1283 return 0;
1284
1285put_child:
1286 of_node_put(child);
1287 return -EINVAL;
1288}
1289
1290/*
1291 * If not pre-configured, calculate and set the PLL configuration manually.
1292 * For low-jitter performance, the PLL should be set such that the synthesizers
1293 * only need integer division.
1294 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1295 * the chip to generate any frequency on its outputs, but jitter performance
1296 * may be sub-optimal.
1297 */
1298static int si5341_initialize_pll(struct clk_si5341 *data)
1299{
1300 struct device_node *np = data->i2c_client->dev.of_node;
1301 u32 m_num = 0;
1302 u32 m_den = 0;
69275187 1303 int sel;
3044a860
ML		 1304
1305 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1306 dev_err(&data->i2c_client->dev,
1307 "PLL configuration requires silabs,pll-m-num\n");
1308 }
1309 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1310 dev_err(&data->i2c_client->dev,
1311 "PLL configuration requires silabs,pll-m-den\n");
1312 }
1313
1314 if (!m_num || !m_den) {
1315 dev_err(&data->i2c_client->dev,
1316 "PLL configuration invalid, assume 14GHz\n");
69275187
ML		 1317 sel = si5341_clk_get_selected_input(data);
1318 if (sel < 0)
1319 return sel;
1320
1321 m_den = clk_get_rate(data->input_clk[sel]) / 10;
3044a860
ML		 1322 m_num = 1400000000;
1323 }
1324
1325 return si5341_encode_44_32(data->regmap,
1326 SI5341_PLL_M_NUM, m_num, m_den);
1327}
1328
69275187
ML		 1329static int si5341_clk_select_active_input(struct clk_si5341 *data)
1330{
1331 int res;
1332 int err;
1333 int i;
1334
1335 res = si5341_clk_get_selected_input(data);
1336 if (res < 0)
1337 return res;
1338
1339 /* If the current register setting is invalid, pick the first input */
1340 if (!data->input_clk[res]) {
1341 dev_dbg(&data->i2c_client->dev,
1342 "Input %d not connected, rerouting\n", res);
1343 res = -ENODEV;
1344 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1345 if (data->input_clk[i]) {
1346 res = i;
1347 break;
1348 }
1349 }
1350 if (res < 0) {
1351 dev_err(&data->i2c_client->dev,
1352 "No clock input available\n");
1353 return res;
1354 }
1355 }
1356
1357 /* Make sure the selected clock is also enabled and routed */
1358 err = si5341_clk_reparent(data, res);
1359 if (err < 0)
1360 return err;
1361
1362 err = clk_prepare_enable(data->input_clk[res]);
1363 if (err < 0)
1364 return err;
1365
1366 return res;
1367}
1368
3044a860
ML		 1369static int si5341_probe(struct i2c_client *client,
1370 const struct i2c_device_id *id)
1371{
1372 struct clk_si5341 *data;
1373 struct clk_init_data init;
69275187 1374 struct clk *input;
3044a860
ML		 1375 const char *root_clock_name;
1376 const char *synth_clock_names[SI5341_NUM_SYNTH];
1377 int err;
1378 unsigned int i;
1379 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1380 bool initialization_required;
1381
1382 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1383 if (!data)
1384 return -ENOMEM;
1385
1386 data->i2c_client = client;
1387
69275187
ML		 1388 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1389 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1390 if (IS_ERR(input)) {
1391 if (PTR_ERR(input) == -EPROBE_DEFER)
1392 return -EPROBE_DEFER;
1393 data->input_clk_name[i] = si5341_input_clock_names[i];
1394 } else {
1395 data->input_clk[i] = input;
1396 data->input_clk_name[i] = __clk_get_name(input);
1397 }
3044a860
ML		 1398 }
1399
1400 err = si5341_dt_parse_dt(client, config);
1401 if (err)
1402 return err;
1403
1404 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1405 &init.name))
1406 init.name = client->dev.of_node->name;
1407 root_clock_name = init.name;
1408
1409 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1410 if (IS_ERR(data->regmap))
1411 return PTR_ERR(data->regmap);
1412
1413 i2c_set_clientdata(client, data);
1414
1415 err = si5341_probe_chip_id(data);
1416 if (err < 0)
1417 return err;
1418
3044a860
ML		 1419 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1420 initialization_required = true;
1421 } else {
1422 err = si5341_is_programmed_already(data);
1423 if (err < 0)
1424 return err;
1425
1426 initialization_required = !err;
1427 }
1428
1429 if (initialization_required) {
1430 /* Populate the regmap cache in preparation for "cache only" */
1431 err = si5341_read_settings(data);
1432 if (err < 0)
1433 return err;
1434
1435 err = si5341_send_preamble(data);
1436 if (err < 0)
1437 return err;
1438
1439 /*
1440 * We intend to send all 'final' register values in a single
1441 * transaction. So cache all register writes until we're done
1442 * configuring.
1443 */
1444 regcache_cache_only(data->regmap, true);
1445
1446 /* Write the configuration pairs from the firmware blob */
1447 err = si5341_write_multiple(data, si5341_reg_defaults,
1448 ARRAY_SIZE(si5341_reg_defaults));
1449 if (err < 0)
1450 return err;
69275187
ML		 1451 }
1452
1453 /* Input must be up and running at this point */
1454 err = si5341_clk_select_active_input(data);
1455 if (err < 0)
1456 return err;
3044a860 1457
69275187 1458 if (initialization_required) {
3044a860
ML		 1459 /* PLL configuration is required */
1460 err = si5341_initialize_pll(data);
1461 if (err < 0)
1462 return err;
1463 }
1464
1465 /* Register the PLL */
69275187
ML		 1466 init.parent_names = data->input_clk_name;
1467 init.num_parents = SI5341_NUM_INPUTS;
3044a860
ML		 1468 init.ops = &si5341_clk_ops;
1469 init.flags = 0;
1470 data->hw.init = &init;
1471
1472 err = devm_clk_hw_register(&client->dev, &data->hw);
1473 if (err) {
1474 dev_err(&client->dev, "clock registration failed\n");
1475 return err;
1476 }
1477
1478 init.num_parents = 1;
1479 init.parent_names = &root_clock_name;
1480 init.ops = &si5341_synth_clk_ops;
1481 for (i = 0; i < data->num_synth; ++i) {
1482 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1483 "%s.N%u", client->dev.of_node->name, i);
1484 init.name = synth_clock_names[i];
1485 data->synth[i].index = i;
1486 data->synth[i].data = data;
1487 data->synth[i].hw.init = &init;
1488 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1489 if (err) {
1490 dev_err(&client->dev,
1491 "synth N%u registration failed\n", i);
1492 }
1493 }
1494
1495 init.num_parents = data->num_synth;
1496 init.parent_names = synth_clock_names;
1497 init.ops = &si5341_output_clk_ops;
1498 for (i = 0; i < data->num_outputs; ++i) {
1499 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1500 client->dev.of_node->name, i);
1501 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1502 data->clk[i].index = i;
1503 data->clk[i].data = data;
1504 data->clk[i].hw.init = &init;
1505 if (config[i].out_format_drv_bits & 0x07) {
1506 regmap_write(data->regmap,
1507 SI5341_OUT_FORMAT(&data->clk[i]),
1508 config[i].out_format_drv_bits);
1509 regmap_write(data->regmap,
1510 SI5341_OUT_CM(&data->clk[i]),
1511 config[i].out_cm_ampl_bits);
1512 }
1513 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1514 kfree(init.name); /* clock framework made a copy of the name */
1515 if (err) {
1516 dev_err(&client->dev,
1517 "output %u registration failed\n", i);
1518 return err;
1519 }
1520 if (config[i].always_on)
1521 clk_prepare(data->clk[i].hw.clk);
1522 }
1523
1524 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1525 data);
1526 if (err) {
1527 dev_err(&client->dev, "unable to add clk provider\n");
1528 return err;
1529 }
1530
1531 if (initialization_required) {
1532 /* Synchronize */
1533 regcache_cache_only(data->regmap, false);
1534 err = regcache_sync(data->regmap);
1535 if (err < 0)
1536 return err;
1537
1538 err = si5341_finalize_defaults(data);
1539 if (err < 0)
1540 return err;
1541 }
1542
1543 /* Free the names, clk framework makes copies */
1544 for (i = 0; i < data->num_synth; ++i)
1545 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1546
1547 return 0;
1548}
1549
1550static const struct i2c_device_id si5341_id[] = {
1551 { "si5340", 0 },
1552 { "si5341", 1 },
f9eec2ea
ML		 1553 { "si5342", 2 },
1554 { "si5344", 4 },
1555 { "si5345", 5 },
3044a860
ML		 1556 { }
1557};
1558MODULE_DEVICE_TABLE(i2c, si5341_id);
1559
1560static const struct of_device_id clk_si5341_of_match[] = {
1561 { .compatible = "silabs,si5340" },
1562 { .compatible = "silabs,si5341" },
f9eec2ea
ML		 1563 { .compatible = "silabs,si5342" },
1564 { .compatible = "silabs,si5344" },
1565 { .compatible = "silabs,si5345" },
3044a860
ML		 1566 { }
1567};
1568MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1569
1570static struct i2c_driver si5341_driver = {
1571 .driver = {
1572 .name = "si5341",
1573 .of_match_table = clk_si5341_of_match,
1574 },
1575 .probe = si5341_probe,
1576 .id_table = si5341_id,
1577};
1578module_i2c_driver(si5341_driver);
1579
1580MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1581MODULE_DESCRIPTION("Si5341 driver");
1582MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)