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3044a860 ML |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
f9eec2ea | 3 | * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345 |
3044a860 ML |
4 | * Copyright (C) 2019 Topic Embedded Products |
5 | * Author: Mike Looijmans <mike.looijmans@topic.nl> | |
f9eec2ea ML |
6 | * |
7 | * The Si5341 has 10 outputs and 5 synthesizers. | |
8 | * The Si5340 is a smaller version of the Si5341 with only 4 outputs. | |
9 | * The Si5345 is similar to the Si5341, with the addition of fractional input | |
10 | * dividers and automatic input selection. | |
11 | * The Si5342 and Si5344 are smaller versions of the Si5345. | |
3044a860 ML |
12 | */ |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/gcd.h> | |
18 | #include <linux/math64.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/regmap.h> | |
b7bbf6ec | 22 | #include <linux/regulator/consumer.h> |
3044a860 ML |
23 | #include <linux/slab.h> |
24 | #include <asm/unaligned.h> | |
25 | ||
69275187 ML |
26 | #define SI5341_NUM_INPUTS 4 |
27 | ||
3044a860 | 28 | #define SI5340_MAX_NUM_OUTPUTS 4 |
f9eec2ea ML |
29 | #define SI5341_MAX_NUM_OUTPUTS 10 |
30 | #define SI5342_MAX_NUM_OUTPUTS 2 | |
31 | #define SI5344_MAX_NUM_OUTPUTS 4 | |
32 | #define SI5345_MAX_NUM_OUTPUTS 10 | |
3044a860 | 33 | |
3044a860 | 34 | #define SI5340_NUM_SYNTH 4 |
f9eec2ea ML |
35 | #define SI5341_NUM_SYNTH 5 |
36 | #define SI5342_NUM_SYNTH 2 | |
37 | #define SI5344_NUM_SYNTH 4 | |
38 | #define SI5345_NUM_SYNTH 5 | |
3044a860 ML |
39 | |
40 | /* Range of the synthesizer fractional divider */ | |
41 | #define SI5341_SYNTH_N_MIN 10 | |
42 | #define SI5341_SYNTH_N_MAX 4095 | |
43 | ||
44 | /* The chip can get its input clock from 3 input pins or an XTAL */ | |
45 | ||
46 | /* There is one PLL running at 13500–14256 MHz */ | |
47 | #define SI5341_PLL_VCO_MIN 13500000000ull | |
48 | #define SI5341_PLL_VCO_MAX 14256000000ull | |
49 | ||
50 | /* The 5 frequency synthesizers obtain their input from the PLL */ | |
51 | struct clk_si5341_synth { | |
52 | struct clk_hw hw; | |
53 | struct clk_si5341 *data; | |
54 | u8 index; | |
55 | }; | |
56 | #define to_clk_si5341_synth(_hw) \ | |
57 | container_of(_hw, struct clk_si5341_synth, hw) | |
58 | ||
59 | /* The output stages can be connected to any synth (full mux) */ | |
60 | struct clk_si5341_output { | |
61 | struct clk_hw hw; | |
62 | struct clk_si5341 *data; | |
b7bbf6ec | 63 | struct regulator *vddo_reg; |
3044a860 ML |
64 | u8 index; |
65 | }; | |
66 | #define to_clk_si5341_output(_hw) \ | |
67 | container_of(_hw, struct clk_si5341_output, hw) | |
68 | ||
69 | struct clk_si5341 { | |
70 | struct clk_hw hw; | |
71 | struct regmap *regmap; | |
72 | struct i2c_client *i2c_client; | |
73 | struct clk_si5341_synth synth[SI5341_NUM_SYNTH]; | |
74 | struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; | |
69275187 ML |
75 | struct clk *input_clk[SI5341_NUM_INPUTS]; |
76 | const char *input_clk_name[SI5341_NUM_INPUTS]; | |
3044a860 ML |
77 | const u16 *reg_output_offset; |
78 | const u16 *reg_rdiv_offset; | |
79 | u64 freq_vco; /* 13500–14256 MHz */ | |
80 | u8 num_outputs; | |
81 | u8 num_synth; | |
f9eec2ea | 82 | u16 chip_id; |
ab89a343 | 83 | bool xaxb_ext_clk; |
2f02c5e4 | 84 | bool iovdd_33; |
3044a860 ML |
85 | }; |
86 | #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) | |
87 | ||
88 | struct clk_si5341_output_config { | |
89 | u8 out_format_drv_bits; | |
90 | u8 out_cm_ampl_bits; | |
b7bbf6ec | 91 | u8 vdd_sel_bits; |
3044a860 ML |
92 | bool synth_master; |
93 | bool always_on; | |
94 | }; | |
95 | ||
96 | #define SI5341_PAGE 0x0001 | |
97 | #define SI5341_PN_BASE 0x0002 | |
98 | #define SI5341_DEVICE_REV 0x0005 | |
99 | #define SI5341_STATUS 0x000C | |
71dcc4d1 RH |
100 | #define SI5341_LOS 0x000D |
101 | #define SI5341_STATUS_STICKY 0x0011 | |
102 | #define SI5341_LOS_STICKY 0x0012 | |
3044a860 | 103 | #define SI5341_SOFT_RST 0x001C |
69275187 | 104 | #define SI5341_IN_SEL 0x0021 |
6e7d2de1 | 105 | #define SI5341_DEVICE_READY 0x00FE |
69275187 | 106 | #define SI5341_XAXB_CFG 0x090E |
2f02c5e4 | 107 | #define SI5341_IO_VDD_SEL 0x0943 |
69275187 ML |
108 | #define SI5341_IN_EN 0x0949 |
109 | #define SI5341_INX_TO_PFD_EN 0x094A | |
110 | ||
71dcc4d1 RH |
111 | /* Status bits */ |
112 | #define SI5341_STATUS_SYSINCAL BIT(0) | |
113 | #define SI5341_STATUS_LOSXAXB BIT(1) | |
114 | #define SI5341_STATUS_LOSREF BIT(2) | |
115 | #define SI5341_STATUS_LOL BIT(3) | |
116 | ||
69275187 ML |
117 | /* Input selection */ |
118 | #define SI5341_IN_SEL_MASK 0x06 | |
119 | #define SI5341_IN_SEL_SHIFT 1 | |
120 | #define SI5341_IN_SEL_REGCTRL 0x01 | |
121 | #define SI5341_INX_TO_PFD_SHIFT 4 | |
122 | ||
123 | /* XTAL config bits */ | |
124 | #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0) | |
125 | #define SI5341_XAXB_CFG_PDNB BIT(1) | |
3044a860 ML |
126 | |
127 | /* Input dividers (48-bit) */ | |
128 | #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10)) | |
129 | #define SI5341_IN_PSET(x) (0x020E + ((x) * 10)) | |
69275187 | 130 | #define SI5341_PX_UPD 0x0230 |
3044a860 ML |
131 | |
132 | /* PLL configuration */ | |
133 | #define SI5341_PLL_M_NUM 0x0235 | |
134 | #define SI5341_PLL_M_DEN 0x023B | |
135 | ||
136 | /* Output configuration */ | |
137 | #define SI5341_OUT_CONFIG(output) \ | |
138 | ((output)->data->reg_output_offset[(output)->index]) | |
139 | #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) | |
140 | #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) | |
141 | #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) | |
142 | #define SI5341_OUT_R_REG(output) \ | |
143 | ((output)->data->reg_rdiv_offset[(output)->index]) | |
144 | ||
b7bbf6ec RH |
145 | #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38 |
146 | ||
3044a860 ML |
147 | /* Synthesize N divider */ |
148 | #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) | |
149 | #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) | |
150 | #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11)) | |
151 | ||
152 | /* Synthesizer output enable, phase bypass, power mode */ | |
153 | #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03 | |
154 | #define SI5341_SYNTH_N_PIBYP 0x0A04 | |
155 | #define SI5341_SYNTH_N_PDNB 0x0A05 | |
156 | #define SI5341_SYNTH_N_CLK_DIS 0x0B4A | |
157 | ||
158 | #define SI5341_REGISTER_MAX 0xBFF | |
159 | ||
160 | /* SI5341_OUT_CONFIG bits */ | |
161 | #define SI5341_OUT_CFG_PDN BIT(0) | |
162 | #define SI5341_OUT_CFG_OE BIT(1) | |
163 | #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) | |
164 | ||
165 | /* Static configuration (to be moved to firmware) */ | |
166 | struct si5341_reg_default { | |
167 | u16 address; | |
168 | u8 value; | |
169 | }; | |
170 | ||
69275187 ML |
171 | static const char * const si5341_input_clock_names[] = { |
172 | "in0", "in1", "in2", "xtal" | |
173 | }; | |
174 | ||
3044a860 | 175 | /* Output configuration registers 0..9 are not quite logically organized */ |
f9eec2ea | 176 | /* Also for si5345 */ |
3044a860 ML |
177 | static const u16 si5341_reg_output_offset[] = { |
178 | 0x0108, | |
179 | 0x010D, | |
180 | 0x0112, | |
181 | 0x0117, | |
182 | 0x011C, | |
183 | 0x0121, | |
184 | 0x0126, | |
185 | 0x012B, | |
186 | 0x0130, | |
187 | 0x013A, | |
188 | }; | |
189 | ||
f9eec2ea | 190 | /* for si5340, si5342 and si5344 */ |
3044a860 ML |
191 | static const u16 si5340_reg_output_offset[] = { |
192 | 0x0112, | |
193 | 0x0117, | |
194 | 0x0126, | |
195 | 0x012B, | |
196 | }; | |
197 | ||
198 | /* The location of the R divider registers */ | |
199 | static const u16 si5341_reg_rdiv_offset[] = { | |
200 | 0x024A, | |
201 | 0x024D, | |
202 | 0x0250, | |
203 | 0x0253, | |
204 | 0x0256, | |
205 | 0x0259, | |
206 | 0x025C, | |
207 | 0x025F, | |
208 | 0x0262, | |
209 | 0x0268, | |
210 | }; | |
211 | static const u16 si5340_reg_rdiv_offset[] = { | |
212 | 0x0250, | |
213 | 0x0253, | |
214 | 0x025C, | |
215 | 0x025F, | |
216 | }; | |
217 | ||
218 | /* | |
219 | * Programming sequence from ClockBuilder, settings to initialize the system | |
220 | * using only the XTAL input, without pre-divider. | |
221 | * This also contains settings that aren't mentioned anywhere in the datasheet. | |
222 | * The "known" settings like synth and output configuration are done later. | |
223 | */ | |
224 | static const struct si5341_reg_default si5341_reg_defaults[] = { | |
225 | { 0x0017, 0x3A }, /* INT mask (disable interrupts) */ | |
226 | { 0x0018, 0xFF }, /* INT mask */ | |
227 | { 0x0021, 0x0F }, /* Select XTAL as input */ | |
228 | { 0x0022, 0x00 }, /* Not in datasheet */ | |
229 | { 0x002B, 0x02 }, /* SPI config */ | |
230 | { 0x002C, 0x20 }, /* LOS enable for XTAL */ | |
231 | { 0x002D, 0x00 }, /* LOS timing */ | |
232 | { 0x002E, 0x00 }, | |
233 | { 0x002F, 0x00 }, | |
234 | { 0x0030, 0x00 }, | |
235 | { 0x0031, 0x00 }, | |
236 | { 0x0032, 0x00 }, | |
237 | { 0x0033, 0x00 }, | |
238 | { 0x0034, 0x00 }, | |
239 | { 0x0035, 0x00 }, | |
240 | { 0x0036, 0x00 }, | |
241 | { 0x0037, 0x00 }, | |
242 | { 0x0038, 0x00 }, /* LOS setting (thresholds) */ | |
243 | { 0x0039, 0x00 }, | |
244 | { 0x003A, 0x00 }, | |
245 | { 0x003B, 0x00 }, | |
246 | { 0x003C, 0x00 }, | |
247 | { 0x003D, 0x00 }, /* LOS setting (thresholds) end */ | |
248 | { 0x0041, 0x00 }, /* LOS0_DIV_SEL */ | |
249 | { 0x0042, 0x00 }, /* LOS1_DIV_SEL */ | |
250 | { 0x0043, 0x00 }, /* LOS2_DIV_SEL */ | |
251 | { 0x0044, 0x00 }, /* LOS3_DIV_SEL */ | |
252 | { 0x009E, 0x00 }, /* Not in datasheet */ | |
253 | { 0x0102, 0x01 }, /* Enable outputs */ | |
254 | { 0x013F, 0x00 }, /* Not in datasheet */ | |
255 | { 0x0140, 0x00 }, /* Not in datasheet */ | |
256 | { 0x0141, 0x40 }, /* OUT LOS */ | |
257 | { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/ | |
258 | { 0x0203, 0x00 }, | |
259 | { 0x0204, 0x00 }, | |
260 | { 0x0205, 0x00 }, | |
261 | { 0x0206, 0x00 }, /* PXAXB (2^x) */ | |
262 | { 0x0208, 0x00 }, /* Px divider setting (usually 0) */ | |
263 | { 0x0209, 0x00 }, | |
264 | { 0x020A, 0x00 }, | |
265 | { 0x020B, 0x00 }, | |
266 | { 0x020C, 0x00 }, | |
267 | { 0x020D, 0x00 }, | |
268 | { 0x020E, 0x00 }, | |
269 | { 0x020F, 0x00 }, | |
270 | { 0x0210, 0x00 }, | |
271 | { 0x0211, 0x00 }, | |
272 | { 0x0212, 0x00 }, | |
273 | { 0x0213, 0x00 }, | |
274 | { 0x0214, 0x00 }, | |
275 | { 0x0215, 0x00 }, | |
276 | { 0x0216, 0x00 }, | |
277 | { 0x0217, 0x00 }, | |
278 | { 0x0218, 0x00 }, | |
279 | { 0x0219, 0x00 }, | |
280 | { 0x021A, 0x00 }, | |
281 | { 0x021B, 0x00 }, | |
282 | { 0x021C, 0x00 }, | |
283 | { 0x021D, 0x00 }, | |
284 | { 0x021E, 0x00 }, | |
285 | { 0x021F, 0x00 }, | |
286 | { 0x0220, 0x00 }, | |
287 | { 0x0221, 0x00 }, | |
288 | { 0x0222, 0x00 }, | |
289 | { 0x0223, 0x00 }, | |
290 | { 0x0224, 0x00 }, | |
291 | { 0x0225, 0x00 }, | |
292 | { 0x0226, 0x00 }, | |
293 | { 0x0227, 0x00 }, | |
294 | { 0x0228, 0x00 }, | |
295 | { 0x0229, 0x00 }, | |
296 | { 0x022A, 0x00 }, | |
297 | { 0x022B, 0x00 }, | |
298 | { 0x022C, 0x00 }, | |
299 | { 0x022D, 0x00 }, | |
300 | { 0x022E, 0x00 }, | |
301 | { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */ | |
302 | { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */ | |
303 | { 0x026C, 0x00 }, | |
304 | { 0x026D, 0x00 }, | |
305 | { 0x026E, 0x00 }, | |
306 | { 0x026F, 0x00 }, | |
307 | { 0x0270, 0x00 }, | |
308 | { 0x0271, 0x00 }, | |
309 | { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */ | |
310 | { 0x0339, 0x1F }, /* N_FSTEP_MSK */ | |
311 | { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */ | |
312 | { 0x033C, 0x00 }, | |
313 | { 0x033D, 0x00 }, | |
314 | { 0x033E, 0x00 }, | |
315 | { 0x033F, 0x00 }, | |
316 | { 0x0340, 0x00 }, | |
317 | { 0x0341, 0x00 }, | |
318 | { 0x0342, 0x00 }, | |
319 | { 0x0343, 0x00 }, | |
320 | { 0x0344, 0x00 }, | |
321 | { 0x0345, 0x00 }, | |
322 | { 0x0346, 0x00 }, | |
323 | { 0x0347, 0x00 }, | |
324 | { 0x0348, 0x00 }, | |
325 | { 0x0349, 0x00 }, | |
326 | { 0x034A, 0x00 }, | |
327 | { 0x034B, 0x00 }, | |
328 | { 0x034C, 0x00 }, | |
329 | { 0x034D, 0x00 }, | |
330 | { 0x034E, 0x00 }, | |
331 | { 0x034F, 0x00 }, | |
332 | { 0x0350, 0x00 }, | |
333 | { 0x0351, 0x00 }, | |
334 | { 0x0352, 0x00 }, | |
335 | { 0x0353, 0x00 }, | |
336 | { 0x0354, 0x00 }, | |
337 | { 0x0355, 0x00 }, | |
338 | { 0x0356, 0x00 }, | |
339 | { 0x0357, 0x00 }, | |
340 | { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */ | |
341 | { 0x0359, 0x00 }, /* Nx_DELAY */ | |
342 | { 0x035A, 0x00 }, | |
343 | { 0x035B, 0x00 }, | |
344 | { 0x035C, 0x00 }, | |
345 | { 0x035D, 0x00 }, | |
346 | { 0x035E, 0x00 }, | |
347 | { 0x035F, 0x00 }, | |
348 | { 0x0360, 0x00 }, | |
349 | { 0x0361, 0x00 }, | |
350 | { 0x0362, 0x00 }, /* Nx_DELAY end */ | |
351 | { 0x0802, 0x00 }, /* Not in datasheet */ | |
352 | { 0x0803, 0x00 }, /* Not in datasheet */ | |
353 | { 0x0804, 0x00 }, /* Not in datasheet */ | |
354 | { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ | |
355 | { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ | |
3044a860 ML |
356 | { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ |
357 | { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ | |
358 | { 0x0A02, 0x00 }, /* Not in datasheet */ | |
359 | { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ | |
3c9b49b0 RH |
360 | { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */ |
361 | { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */ | |
3044a860 ML |
362 | }; |
363 | ||
364 | /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ | |
365 | static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, | |
366 | u64 *val1, u32 *val2) | |
367 | { | |
368 | int err; | |
369 | u8 r[10]; | |
370 | ||
371 | err = regmap_bulk_read(regmap, reg, r, 10); | |
372 | if (err < 0) | |
373 | return err; | |
374 | ||
375 | *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) | | |
376 | (get_unaligned_le32(r)); | |
377 | *val2 = get_unaligned_le32(&r[6]); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, | |
383 | u64 n_num, u32 n_den) | |
384 | { | |
385 | u8 r[10]; | |
386 | ||
387 | /* Shift left as far as possible without overflowing */ | |
388 | while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { | |
389 | n_num <<= 1; | |
390 | n_den <<= 1; | |
391 | } | |
392 | ||
393 | /* 44 bits (6 bytes) numerator */ | |
394 | put_unaligned_le32(n_num, r); | |
395 | r[4] = (n_num >> 32) & 0xff; | |
396 | r[5] = (n_num >> 40) & 0x0f; | |
397 | /* 32 bits denominator */ | |
398 | put_unaligned_le32(n_den, &r[6]); | |
399 | ||
400 | /* Program the fraction */ | |
401 | return regmap_bulk_write(regmap, reg, r, sizeof(r)); | |
402 | } | |
403 | ||
404 | /* VCO, we assume it runs at a constant frequency */ | |
405 | static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw, | |
406 | unsigned long parent_rate) | |
407 | { | |
408 | struct clk_si5341 *data = to_clk_si5341(hw); | |
409 | int err; | |
410 | u64 res; | |
411 | u64 m_num; | |
412 | u32 m_den; | |
413 | unsigned int shift; | |
414 | ||
415 | /* Assume that PDIV is not being used, just read the PLL setting */ | |
416 | err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, | |
417 | &m_num, &m_den); | |
418 | if (err < 0) | |
419 | return 0; | |
420 | ||
421 | if (!m_num || !m_den) | |
422 | return 0; | |
423 | ||
424 | /* | |
425 | * Though m_num is 64-bit, only the upper bits are actually used. While | |
426 | * calculating m_num and m_den, they are shifted as far as possible to | |
427 | * the left. To avoid 96-bit division here, we just shift them back so | |
428 | * we can do with just 64 bits. | |
429 | */ | |
430 | shift = 0; | |
431 | res = m_num; | |
432 | while (res & 0xffff00000000ULL) { | |
433 | ++shift; | |
434 | res >>= 1; | |
435 | } | |
436 | res *= parent_rate; | |
437 | do_div(res, (m_den >> shift)); | |
438 | ||
439 | /* We cannot return the actual frequency in 32 bit, store it locally */ | |
440 | data->freq_vco = res; | |
441 | ||
442 | /* Report kHz since the value is out of range */ | |
443 | do_div(res, 1000); | |
444 | ||
445 | return (unsigned long)res; | |
446 | } | |
447 | ||
69275187 ML |
448 | static int si5341_clk_get_selected_input(struct clk_si5341 *data) |
449 | { | |
450 | int err; | |
451 | u32 val; | |
452 | ||
453 | err = regmap_read(data->regmap, SI5341_IN_SEL, &val); | |
454 | if (err < 0) | |
455 | return err; | |
456 | ||
457 | return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT; | |
458 | } | |
459 | ||
460 | static u8 si5341_clk_get_parent(struct clk_hw *hw) | |
461 | { | |
462 | struct clk_si5341 *data = to_clk_si5341(hw); | |
463 | int res = si5341_clk_get_selected_input(data); | |
464 | ||
465 | if (res < 0) | |
466 | return 0; /* Apparently we cannot report errors */ | |
467 | ||
468 | return res; | |
469 | } | |
470 | ||
471 | static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) | |
472 | { | |
473 | int err; | |
474 | u8 val; | |
475 | ||
476 | val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK; | |
477 | /* Enable register-based input selection */ | |
478 | val |= SI5341_IN_SEL_REGCTRL; | |
479 | ||
480 | err = regmap_update_bits(data->regmap, | |
481 | SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val); | |
482 | if (err < 0) | |
483 | return err; | |
484 | ||
485 | if (index < 3) { | |
486 | /* Enable input buffer for selected input */ | |
487 | err = regmap_update_bits(data->regmap, | |
488 | SI5341_IN_EN, 0x07, BIT(index)); | |
489 | if (err < 0) | |
490 | return err; | |
491 | ||
492 | /* Enables the input to phase detector */ | |
493 | err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, | |
494 | 0x7 << SI5341_INX_TO_PFD_SHIFT, | |
495 | BIT(index + SI5341_INX_TO_PFD_SHIFT)); | |
496 | if (err < 0) | |
497 | return err; | |
498 | ||
499 | /* Power down XTAL oscillator and buffer */ | |
500 | err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, | |
501 | SI5341_XAXB_CFG_PDNB, 0); | |
502 | if (err < 0) | |
503 | return err; | |
504 | ||
505 | /* | |
506 | * Set the P divider to "1". There's no explanation in the | |
507 | * datasheet of these registers, but the clockbuilder software | |
508 | * programs a "1" when the input is being used. | |
509 | */ | |
510 | err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); | |
511 | if (err < 0) | |
512 | return err; | |
513 | ||
514 | err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); | |
515 | if (err < 0) | |
516 | return err; | |
517 | ||
518 | /* Set update PDIV bit */ | |
519 | err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); | |
520 | if (err < 0) | |
521 | return err; | |
522 | } else { | |
523 | /* Disable all input buffers */ | |
524 | err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); | |
525 | if (err < 0) | |
526 | return err; | |
527 | ||
528 | /* Disable input to phase detector */ | |
529 | err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, | |
530 | 0x7 << SI5341_INX_TO_PFD_SHIFT, 0); | |
531 | if (err < 0) | |
532 | return err; | |
533 | ||
ab89a343 | 534 | /* Power up XTAL oscillator and buffer, select clock mode */ |
69275187 | 535 | err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, |
ab89a343 RH |
536 | SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN, |
537 | SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ? | |
538 | SI5341_XAXB_CFG_EXTCLK_EN : 0)); | |
69275187 ML |
539 | if (err < 0) |
540 | return err; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int si5341_clk_set_parent(struct clk_hw *hw, u8 index) | |
547 | { | |
548 | struct clk_si5341 *data = to_clk_si5341(hw); | |
549 | ||
550 | return si5341_clk_reparent(data, index); | |
551 | } | |
552 | ||
3044a860 | 553 | static const struct clk_ops si5341_clk_ops = { |
69275187 ML |
554 | .set_parent = si5341_clk_set_parent, |
555 | .get_parent = si5341_clk_get_parent, | |
3044a860 ML |
556 | .recalc_rate = si5341_clk_recalc_rate, |
557 | }; | |
558 | ||
559 | /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ | |
560 | ||
561 | /* The synthesizer is on if all power and enable bits are set */ | |
562 | static int si5341_synth_clk_is_on(struct clk_hw *hw) | |
563 | { | |
564 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
565 | int err; | |
566 | u32 val; | |
567 | u8 index = synth->index; | |
568 | ||
569 | err = regmap_read(synth->data->regmap, | |
570 | SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); | |
571 | if (err < 0) | |
572 | return 0; | |
573 | ||
574 | if (!(val & BIT(index))) | |
575 | return 0; | |
576 | ||
577 | err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); | |
578 | if (err < 0) | |
579 | return 0; | |
580 | ||
581 | if (!(val & BIT(index))) | |
582 | return 0; | |
583 | ||
584 | /* This bit must be 0 for the synthesizer to receive clock input */ | |
585 | err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); | |
586 | if (err < 0) | |
587 | return 0; | |
588 | ||
589 | return !(val & BIT(index)); | |
590 | } | |
591 | ||
592 | static void si5341_synth_clk_unprepare(struct clk_hw *hw) | |
593 | { | |
594 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
595 | u8 index = synth->index; /* In range 0..5 */ | |
596 | u8 mask = BIT(index); | |
597 | ||
598 | /* Disable output */ | |
599 | regmap_update_bits(synth->data->regmap, | |
600 | SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); | |
601 | /* Power down */ | |
602 | regmap_update_bits(synth->data->regmap, | |
603 | SI5341_SYNTH_N_PDNB, mask, 0); | |
604 | /* Disable clock input to synth (set to 1 to disable) */ | |
605 | regmap_update_bits(synth->data->regmap, | |
606 | SI5341_SYNTH_N_CLK_DIS, mask, mask); | |
607 | } | |
608 | ||
609 | static int si5341_synth_clk_prepare(struct clk_hw *hw) | |
610 | { | |
611 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
612 | int err; | |
613 | u8 index = synth->index; | |
614 | u8 mask = BIT(index); | |
615 | ||
616 | /* Power up */ | |
617 | err = regmap_update_bits(synth->data->regmap, | |
618 | SI5341_SYNTH_N_PDNB, mask, mask); | |
619 | if (err < 0) | |
620 | return err; | |
621 | ||
622 | /* Enable clock input to synth (set bit to 0 to enable) */ | |
623 | err = regmap_update_bits(synth->data->regmap, | |
624 | SI5341_SYNTH_N_CLK_DIS, mask, 0); | |
625 | if (err < 0) | |
626 | return err; | |
627 | ||
628 | /* Enable output */ | |
629 | return regmap_update_bits(synth->data->regmap, | |
630 | SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); | |
631 | } | |
632 | ||
633 | /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ | |
634 | static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, | |
635 | unsigned long parent_rate) | |
636 | { | |
637 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
638 | u64 f; | |
639 | u64 n_num; | |
640 | u32 n_den; | |
641 | int err; | |
642 | ||
643 | err = si5341_decode_44_32(synth->data->regmap, | |
644 | SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); | |
645 | if (err < 0) | |
646 | return err; | |
78f6f406 RH |
647 | /* Check for bogus/uninitialized settings */ |
648 | if (!n_num || !n_den) | |
649 | return 0; | |
3044a860 ML |
650 | |
651 | /* | |
652 | * n_num and n_den are shifted left as much as possible, so to prevent | |
653 | * overflow in 64-bit math, we shift n_den 4 bits to the right | |
654 | */ | |
655 | f = synth->data->freq_vco; | |
656 | f *= n_den >> 4; | |
657 | ||
7c55e8ef | 658 | /* Now we need to do 64-bit division: f/n_num */ |
3044a860 ML |
659 | /* And compensate for the 4 bits we dropped */ |
660 | f = div64_u64(f, (n_num >> 4)); | |
661 | ||
662 | return f; | |
663 | } | |
664 | ||
665 | static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
666 | unsigned long *parent_rate) | |
667 | { | |
668 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
669 | u64 f; | |
670 | ||
671 | /* The synthesizer accuracy is such that anything in range will work */ | |
672 | f = synth->data->freq_vco; | |
673 | do_div(f, SI5341_SYNTH_N_MAX); | |
674 | if (rate < f) | |
675 | return f; | |
676 | ||
677 | f = synth->data->freq_vco; | |
678 | do_div(f, SI5341_SYNTH_N_MIN); | |
679 | if (rate > f) | |
680 | return f; | |
681 | ||
682 | return rate; | |
683 | } | |
684 | ||
685 | static int si5341_synth_program(struct clk_si5341_synth *synth, | |
686 | u64 n_num, u32 n_den, bool is_integer) | |
687 | { | |
688 | int err; | |
689 | u8 index = synth->index; | |
690 | ||
691 | err = si5341_encode_44_32(synth->data->regmap, | |
692 | SI5341_SYNTH_N_NUM(index), n_num, n_den); | |
693 | ||
694 | err = regmap_update_bits(synth->data->regmap, | |
695 | SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); | |
696 | if (err < 0) | |
697 | return err; | |
698 | ||
699 | return regmap_write(synth->data->regmap, | |
700 | SI5341_SYNTH_N_UPD(index), 0x01); | |
701 | } | |
702 | ||
703 | ||
704 | static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
705 | unsigned long parent_rate) | |
706 | { | |
707 | struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); | |
708 | u64 n_num; | |
709 | u32 n_den; | |
710 | u32 r; | |
711 | u32 g; | |
712 | bool is_integer; | |
713 | ||
714 | n_num = synth->data->freq_vco; | |
3044a860 ML |
715 | |
716 | /* see if there's an integer solution */ | |
717 | r = do_div(n_num, rate); | |
718 | is_integer = (r == 0); | |
719 | if (is_integer) { | |
720 | /* Integer divider equal to n_num */ | |
721 | n_den = 1; | |
722 | } else { | |
723 | /* Calculate a fractional solution */ | |
724 | g = gcd(r, rate); | |
725 | n_den = rate / g; | |
726 | n_num *= n_den; | |
727 | n_num += r / g; | |
728 | } | |
729 | ||
730 | dev_dbg(&synth->data->i2c_client->dev, | |
731 | "%s(%u): n=0x%llx d=0x%x %s\n", __func__, | |
732 | synth->index, n_num, n_den, | |
733 | is_integer ? "int" : "frac"); | |
734 | ||
735 | return si5341_synth_program(synth, n_num, n_den, is_integer); | |
736 | } | |
737 | ||
738 | static const struct clk_ops si5341_synth_clk_ops = { | |
739 | .is_prepared = si5341_synth_clk_is_on, | |
740 | .prepare = si5341_synth_clk_prepare, | |
741 | .unprepare = si5341_synth_clk_unprepare, | |
742 | .recalc_rate = si5341_synth_clk_recalc_rate, | |
743 | .round_rate = si5341_synth_clk_round_rate, | |
744 | .set_rate = si5341_synth_clk_set_rate, | |
745 | }; | |
746 | ||
747 | static int si5341_output_clk_is_on(struct clk_hw *hw) | |
748 | { | |
749 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
750 | int err; | |
751 | u32 val; | |
752 | ||
753 | err = regmap_read(output->data->regmap, | |
754 | SI5341_OUT_CONFIG(output), &val); | |
755 | if (err < 0) | |
756 | return err; | |
757 | ||
758 | /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ | |
759 | return (val & 0x03) == SI5341_OUT_CFG_OE; | |
760 | } | |
761 | ||
762 | /* Disables and then powers down the output */ | |
763 | static void si5341_output_clk_unprepare(struct clk_hw *hw) | |
764 | { | |
765 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
766 | ||
767 | regmap_update_bits(output->data->regmap, | |
768 | SI5341_OUT_CONFIG(output), | |
769 | SI5341_OUT_CFG_OE, 0); | |
770 | regmap_update_bits(output->data->regmap, | |
771 | SI5341_OUT_CONFIG(output), | |
772 | SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN); | |
773 | } | |
774 | ||
775 | /* Powers up and then enables the output */ | |
776 | static int si5341_output_clk_prepare(struct clk_hw *hw) | |
777 | { | |
778 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
779 | int err; | |
780 | ||
781 | err = regmap_update_bits(output->data->regmap, | |
782 | SI5341_OUT_CONFIG(output), | |
783 | SI5341_OUT_CFG_PDN, 0); | |
784 | if (err < 0) | |
785 | return err; | |
786 | ||
787 | return regmap_update_bits(output->data->regmap, | |
788 | SI5341_OUT_CONFIG(output), | |
789 | SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE); | |
790 | } | |
791 | ||
792 | static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, | |
793 | unsigned long parent_rate) | |
794 | { | |
795 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
796 | int err; | |
797 | u32 val; | |
798 | u32 r_divider; | |
799 | u8 r[3]; | |
800 | ||
2a8b5394 AW |
801 | err = regmap_read(output->data->regmap, |
802 | SI5341_OUT_CONFIG(output), &val); | |
803 | if (err < 0) | |
804 | return err; | |
805 | ||
806 | /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */ | |
807 | if (val & SI5341_OUT_CFG_RDIV_FORCE2) | |
808 | return parent_rate / 2; | |
809 | ||
3044a860 ML |
810 | err = regmap_bulk_read(output->data->regmap, |
811 | SI5341_OUT_R_REG(output), r, 3); | |
812 | if (err < 0) | |
813 | return err; | |
814 | ||
815 | /* Calculate value as 24-bit integer*/ | |
816 | r_divider = r[2] << 16 | r[1] << 8 | r[0]; | |
817 | ||
818 | /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ | |
819 | if (!r_divider) | |
820 | return 0; | |
821 | ||
822 | /* Divider is 2*(Rx_REG+1) */ | |
823 | r_divider += 1; | |
824 | r_divider <<= 1; | |
825 | ||
3044a860 ML |
826 | |
827 | return parent_rate / r_divider; | |
828 | } | |
829 | ||
830 | static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
831 | unsigned long *parent_rate) | |
832 | { | |
833 | unsigned long r; | |
834 | ||
78f6f406 RH |
835 | if (!rate) |
836 | return 0; | |
837 | ||
3044a860 ML |
838 | r = *parent_rate >> 1; |
839 | ||
840 | /* If rate is an even divisor, no changes to parent required */ | |
841 | if (r && !(r % rate)) | |
842 | return (long)rate; | |
843 | ||
844 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { | |
845 | if (rate > 200000000) { | |
846 | /* minimum r-divider is 2 */ | |
847 | r = 2; | |
848 | } else { | |
849 | /* Take a parent frequency near 400 MHz */ | |
850 | r = (400000000u / rate) & ~1; | |
851 | } | |
852 | *parent_rate = r * rate; | |
853 | } else { | |
854 | /* We cannot change our parent's rate, report what we can do */ | |
855 | r /= rate; | |
856 | rate = *parent_rate / (r << 1); | |
857 | } | |
858 | ||
859 | return rate; | |
860 | } | |
861 | ||
862 | static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
863 | unsigned long parent_rate) | |
864 | { | |
865 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
78f6f406 | 866 | u32 r_div; |
3044a860 ML |
867 | int err; |
868 | u8 r[3]; | |
869 | ||
78f6f406 RH |
870 | if (!rate) |
871 | return -EINVAL; | |
872 | ||
873 | /* Frequency divider is (r_div + 1) * 2 */ | |
874 | r_div = (parent_rate / rate) >> 1; | |
875 | ||
3044a860 ML |
876 | if (r_div <= 1) |
877 | r_div = 0; | |
878 | else if (r_div >= BIT(24)) | |
879 | r_div = BIT(24) - 1; | |
880 | else | |
881 | --r_div; | |
882 | ||
883 | /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ | |
884 | err = regmap_update_bits(output->data->regmap, | |
885 | SI5341_OUT_CONFIG(output), | |
886 | SI5341_OUT_CFG_RDIV_FORCE2, | |
887 | (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0); | |
888 | if (err < 0) | |
889 | return err; | |
890 | ||
891 | /* Always write Rx_REG, because a zero value disables the divider */ | |
892 | r[0] = r_div ? (r_div & 0xff) : 1; | |
893 | r[1] = (r_div >> 8) & 0xff; | |
894 | r[2] = (r_div >> 16) & 0xff; | |
895 | err = regmap_bulk_write(output->data->regmap, | |
896 | SI5341_OUT_R_REG(output), r, 3); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) | |
902 | { | |
903 | return regmap_update_bits(output->data->regmap, | |
904 | SI5341_OUT_MUX_SEL(output), 0x07, index); | |
905 | } | |
906 | ||
907 | static int si5341_output_set_parent(struct clk_hw *hw, u8 index) | |
908 | { | |
909 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
910 | ||
911 | if (index >= output->data->num_synth) | |
912 | return -EINVAL; | |
913 | ||
914 | return si5341_output_reparent(output, index); | |
915 | } | |
916 | ||
917 | static u8 si5341_output_get_parent(struct clk_hw *hw) | |
918 | { | |
919 | struct clk_si5341_output *output = to_clk_si5341_output(hw); | |
3044a860 ML |
920 | u32 val; |
921 | ||
84afc9ec | 922 | regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val); |
3044a860 ML |
923 | |
924 | return val & 0x7; | |
925 | } | |
926 | ||
927 | static const struct clk_ops si5341_output_clk_ops = { | |
928 | .is_prepared = si5341_output_clk_is_on, | |
929 | .prepare = si5341_output_clk_prepare, | |
930 | .unprepare = si5341_output_clk_unprepare, | |
931 | .recalc_rate = si5341_output_clk_recalc_rate, | |
932 | .round_rate = si5341_output_clk_round_rate, | |
933 | .set_rate = si5341_output_clk_set_rate, | |
934 | .set_parent = si5341_output_set_parent, | |
935 | .get_parent = si5341_output_get_parent, | |
936 | }; | |
937 | ||
938 | /* | |
939 | * The chip can be bought in a pre-programmed version, or one can program the | |
940 | * NVM in the chip to boot up in a preset mode. This routine tries to determine | |
941 | * if that's the case, or if we need to reset and program everything from | |
942 | * scratch. Returns negative error, or true/false. | |
943 | */ | |
944 | static int si5341_is_programmed_already(struct clk_si5341 *data) | |
945 | { | |
946 | int err; | |
947 | u8 r[4]; | |
948 | ||
949 | /* Read the PLL divider value, it must have a non-zero value */ | |
950 | err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, | |
951 | r, ARRAY_SIZE(r)); | |
952 | if (err < 0) | |
953 | return err; | |
954 | ||
955 | return !!get_unaligned_le32(r); | |
956 | } | |
957 | ||
958 | static struct clk_hw * | |
959 | of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data) | |
960 | { | |
961 | struct clk_si5341 *data = _data; | |
962 | unsigned int idx = clkspec->args[1]; | |
963 | unsigned int group = clkspec->args[0]; | |
964 | ||
965 | switch (group) { | |
966 | case 0: | |
967 | if (idx >= data->num_outputs) { | |
968 | dev_err(&data->i2c_client->dev, | |
969 | "invalid output index %u\n", idx); | |
970 | return ERR_PTR(-EINVAL); | |
971 | } | |
972 | return &data->clk[idx].hw; | |
973 | case 1: | |
974 | if (idx >= data->num_synth) { | |
975 | dev_err(&data->i2c_client->dev, | |
976 | "invalid synthesizer index %u\n", idx); | |
977 | return ERR_PTR(-EINVAL); | |
978 | } | |
979 | return &data->synth[idx].hw; | |
980 | case 2: | |
981 | if (idx > 0) { | |
982 | dev_err(&data->i2c_client->dev, | |
983 | "invalid PLL index %u\n", idx); | |
984 | return ERR_PTR(-EINVAL); | |
985 | } | |
986 | return &data->hw; | |
987 | default: | |
988 | dev_err(&data->i2c_client->dev, "invalid group %u\n", group); | |
989 | return ERR_PTR(-EINVAL); | |
990 | } | |
991 | } | |
992 | ||
993 | static int si5341_probe_chip_id(struct clk_si5341 *data) | |
994 | { | |
995 | int err; | |
996 | u8 reg[4]; | |
997 | u16 model; | |
998 | ||
999 | err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, | |
1000 | ARRAY_SIZE(reg)); | |
1001 | if (err < 0) { | |
1002 | dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); | |
1003 | return err; | |
1004 | } | |
1005 | ||
1006 | model = get_unaligned_le16(reg); | |
1007 | ||
1008 | dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", | |
1009 | model, reg[2], reg[3]); | |
1010 | ||
1011 | switch (model) { | |
1012 | case 0x5340: | |
1013 | data->num_outputs = SI5340_MAX_NUM_OUTPUTS; | |
1014 | data->num_synth = SI5340_NUM_SYNTH; | |
1015 | data->reg_output_offset = si5340_reg_output_offset; | |
1016 | data->reg_rdiv_offset = si5340_reg_rdiv_offset; | |
1017 | break; | |
1018 | case 0x5341: | |
1019 | data->num_outputs = SI5341_MAX_NUM_OUTPUTS; | |
1020 | data->num_synth = SI5341_NUM_SYNTH; | |
1021 | data->reg_output_offset = si5341_reg_output_offset; | |
1022 | data->reg_rdiv_offset = si5341_reg_rdiv_offset; | |
1023 | break; | |
f9eec2ea ML |
1024 | case 0x5342: |
1025 | data->num_outputs = SI5342_MAX_NUM_OUTPUTS; | |
1026 | data->num_synth = SI5342_NUM_SYNTH; | |
1027 | data->reg_output_offset = si5340_reg_output_offset; | |
1028 | data->reg_rdiv_offset = si5340_reg_rdiv_offset; | |
1029 | break; | |
1030 | case 0x5344: | |
1031 | data->num_outputs = SI5344_MAX_NUM_OUTPUTS; | |
1032 | data->num_synth = SI5344_NUM_SYNTH; | |
1033 | data->reg_output_offset = si5340_reg_output_offset; | |
1034 | data->reg_rdiv_offset = si5340_reg_rdiv_offset; | |
1035 | break; | |
1036 | case 0x5345: | |
1037 | data->num_outputs = SI5345_MAX_NUM_OUTPUTS; | |
1038 | data->num_synth = SI5345_NUM_SYNTH; | |
1039 | data->reg_output_offset = si5341_reg_output_offset; | |
1040 | data->reg_rdiv_offset = si5341_reg_rdiv_offset; | |
1041 | break; | |
3044a860 ML |
1042 | default: |
1043 | dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", | |
1044 | model); | |
1045 | return -EINVAL; | |
1046 | } | |
1047 | ||
f9eec2ea ML |
1048 | data->chip_id = model; |
1049 | ||
3044a860 ML |
1050 | return 0; |
1051 | } | |
1052 | ||
1053 | /* Read active settings into the regmap cache for later reference */ | |
1054 | static int si5341_read_settings(struct clk_si5341 *data) | |
1055 | { | |
1056 | int err; | |
1057 | u8 i; | |
1058 | u8 r[10]; | |
1059 | ||
1060 | err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); | |
1061 | if (err < 0) | |
1062 | return err; | |
1063 | ||
1064 | err = regmap_bulk_read(data->regmap, | |
1065 | SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3); | |
1066 | if (err < 0) | |
1067 | return err; | |
1068 | ||
1069 | err = regmap_bulk_read(data->regmap, | |
1070 | SI5341_SYNTH_N_CLK_DIS, r, 1); | |
1071 | if (err < 0) | |
1072 | return err; | |
1073 | ||
1074 | for (i = 0; i < data->num_synth; ++i) { | |
1075 | err = regmap_bulk_read(data->regmap, | |
1076 | SI5341_SYNTH_N_NUM(i), r, 10); | |
1077 | if (err < 0) | |
1078 | return err; | |
1079 | } | |
1080 | ||
1081 | for (i = 0; i < data->num_outputs; ++i) { | |
1082 | err = regmap_bulk_read(data->regmap, | |
1083 | data->reg_output_offset[i], r, 4); | |
1084 | if (err < 0) | |
1085 | return err; | |
1086 | ||
1087 | err = regmap_bulk_read(data->regmap, | |
1088 | data->reg_rdiv_offset[i], r, 3); | |
1089 | if (err < 0) | |
1090 | return err; | |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int si5341_write_multiple(struct clk_si5341 *data, | |
1097 | const struct si5341_reg_default *values, unsigned int num_values) | |
1098 | { | |
1099 | unsigned int i; | |
1100 | int res; | |
1101 | ||
1102 | for (i = 0; i < num_values; ++i) { | |
1103 | res = regmap_write(data->regmap, | |
1104 | values[i].address, values[i].value); | |
1105 | if (res < 0) { | |
1106 | dev_err(&data->i2c_client->dev, | |
1107 | "Failed to write %#x:%#x\n", | |
1108 | values[i].address, values[i].value); | |
1109 | return res; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static const struct si5341_reg_default si5341_preamble[] = { | |
1117 | { 0x0B25, 0x00 }, | |
1118 | { 0x0502, 0x01 }, | |
1119 | { 0x0505, 0x03 }, | |
3c9b49b0 | 1120 | { 0x0957, 0x17 }, |
3044a860 ML |
1121 | { 0x0B4E, 0x1A }, |
1122 | }; | |
1123 | ||
f9eec2ea ML |
1124 | static const struct si5341_reg_default si5345_preamble[] = { |
1125 | { 0x0B25, 0x00 }, | |
1126 | { 0x0540, 0x01 }, | |
1127 | }; | |
1128 | ||
3044a860 ML |
1129 | static int si5341_send_preamble(struct clk_si5341 *data) |
1130 | { | |
1131 | int res; | |
1132 | u32 revision; | |
1133 | ||
1134 | /* For revision 2 and up, the values are slightly different */ | |
1135 | res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); | |
1136 | if (res < 0) | |
1137 | return res; | |
1138 | ||
1139 | /* Write "preamble" as specified by datasheet */ | |
1140 | res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); | |
1141 | if (res < 0) | |
1142 | return res; | |
f9eec2ea ML |
1143 | |
1144 | /* The si5342..si5345 require a different preamble */ | |
1145 | if (data->chip_id > 0x5341) | |
1146 | res = si5341_write_multiple(data, | |
1147 | si5345_preamble, ARRAY_SIZE(si5345_preamble)); | |
1148 | else | |
1149 | res = si5341_write_multiple(data, | |
1150 | si5341_preamble, ARRAY_SIZE(si5341_preamble)); | |
3044a860 ML |
1151 | if (res < 0) |
1152 | return res; | |
1153 | ||
1154 | /* Datasheet specifies a 300ms wait after sending the preamble */ | |
1155 | msleep(300); | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | /* Perform a soft reset and write post-amble */ | |
1161 | static int si5341_finalize_defaults(struct clk_si5341 *data) | |
1162 | { | |
1163 | int res; | |
1164 | u32 revision; | |
1165 | ||
2f02c5e4 RH |
1166 | res = regmap_write(data->regmap, SI5341_IO_VDD_SEL, |
1167 | data->iovdd_33 ? 1 : 0); | |
1168 | if (res < 0) | |
1169 | return res; | |
1170 | ||
3044a860 ML |
1171 | res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); |
1172 | if (res < 0) | |
1173 | return res; | |
1174 | ||
1175 | dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); | |
1176 | ||
1177 | res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); | |
1178 | if (res < 0) | |
1179 | return res; | |
1180 | ||
f9eec2ea ML |
1181 | /* The si5342..si5345 have an additional post-amble */ |
1182 | if (data->chip_id > 0x5341) { | |
1183 | res = regmap_write(data->regmap, 0x540, 0x0); | |
1184 | if (res < 0) | |
1185 | return res; | |
1186 | } | |
1187 | ||
3044a860 ML |
1188 | /* Datasheet does not explain these nameless registers */ |
1189 | res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); | |
1190 | if (res < 0) | |
1191 | return res; | |
1192 | res = regmap_write(data->regmap, 0x0B25, 0x02); | |
1193 | if (res < 0) | |
1194 | return res; | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | ||
1200 | static const struct regmap_range si5341_regmap_volatile_range[] = { | |
1201 | regmap_reg_range(0x000C, 0x0012), /* Status */ | |
1202 | regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */ | |
1203 | regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */ | |
69275187 ML |
1204 | /* Update bits for P divider and synth config */ |
1205 | regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD), | |
3044a860 ML |
1206 | regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)), |
1207 | regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)), | |
1208 | regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)), | |
1209 | regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)), | |
1210 | regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)), | |
1211 | }; | |
1212 | ||
1213 | static const struct regmap_access_table si5341_regmap_volatile = { | |
1214 | .yes_ranges = si5341_regmap_volatile_range, | |
1215 | .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range), | |
1216 | }; | |
1217 | ||
1218 | /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ | |
1219 | static const struct regmap_range_cfg si5341_regmap_ranges[] = { | |
1220 | { | |
1221 | .range_min = 0, | |
1222 | .range_max = SI5341_REGISTER_MAX, | |
1223 | .selector_reg = SI5341_PAGE, | |
1224 | .selector_mask = 0xff, | |
1225 | .selector_shift = 0, | |
1226 | .window_start = 0, | |
1227 | .window_len = 256, | |
1228 | }, | |
1229 | }; | |
1230 | ||
6e7d2de1 RH |
1231 | static int si5341_wait_device_ready(struct i2c_client *client) |
1232 | { | |
1233 | int count; | |
1234 | ||
1235 | /* Datasheet warns: Any attempt to read or write any register other | |
1236 | * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the | |
1237 | * NVM programming and may corrupt the register contents, as they are | |
1238 | * read from NVM. Note that this includes accesses to the PAGE register. | |
1239 | * Also: DEVICE_READY is available on every register page, so no page | |
1240 | * change is needed to read it. | |
1241 | * Do this outside regmap to avoid automatic PAGE register access. | |
1242 | * May take up to 300ms to complete. | |
1243 | */ | |
1244 | for (count = 0; count < 15; ++count) { | |
1245 | s32 result = i2c_smbus_read_byte_data(client, | |
1246 | SI5341_DEVICE_READY); | |
1247 | if (result < 0) | |
1248 | return result; | |
1249 | if (result == 0x0F) | |
1250 | return 0; | |
1251 | msleep(20); | |
1252 | } | |
1253 | dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); | |
1254 | return -EIO; | |
1255 | } | |
1256 | ||
3044a860 ML |
1257 | static const struct regmap_config si5341_regmap_config = { |
1258 | .reg_bits = 8, | |
1259 | .val_bits = 8, | |
1260 | .cache_type = REGCACHE_RBTREE, | |
1261 | .ranges = si5341_regmap_ranges, | |
1262 | .num_ranges = ARRAY_SIZE(si5341_regmap_ranges), | |
1263 | .max_register = SI5341_REGISTER_MAX, | |
1264 | .volatile_table = &si5341_regmap_volatile, | |
1265 | }; | |
1266 | ||
b7bbf6ec RH |
1267 | static int si5341_dt_parse_dt(struct clk_si5341 *data, |
1268 | struct clk_si5341_output_config *config) | |
3044a860 ML |
1269 | { |
1270 | struct device_node *child; | |
b7bbf6ec | 1271 | struct device_node *np = data->i2c_client->dev.of_node; |
3044a860 ML |
1272 | u32 num; |
1273 | u32 val; | |
1274 | ||
1275 | memset(config, 0, sizeof(struct clk_si5341_output_config) * | |
1276 | SI5341_MAX_NUM_OUTPUTS); | |
1277 | ||
1278 | for_each_child_of_node(np, child) { | |
1279 | if (of_property_read_u32(child, "reg", &num)) { | |
b7bbf6ec | 1280 | dev_err(&data->i2c_client->dev, "missing reg property of %s\n", |
3044a860 ML |
1281 | child->name); |
1282 | goto put_child; | |
1283 | } | |
1284 | ||
1285 | if (num >= SI5341_MAX_NUM_OUTPUTS) { | |
b7bbf6ec | 1286 | dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num); |
3044a860 ML |
1287 | goto put_child; |
1288 | } | |
1289 | ||
1290 | if (!of_property_read_u32(child, "silabs,format", &val)) { | |
1291 | /* Set cm and ampl conservatively to 3v3 settings */ | |
1292 | switch (val) { | |
1293 | case 1: /* normal differential */ | |
1294 | config[num].out_cm_ampl_bits = 0x33; | |
1295 | break; | |
1296 | case 2: /* low-power differential */ | |
1297 | config[num].out_cm_ampl_bits = 0x13; | |
1298 | break; | |
1299 | case 4: /* LVCMOS */ | |
1300 | config[num].out_cm_ampl_bits = 0x33; | |
1301 | /* Set SI recommended impedance for LVCMOS */ | |
1302 | config[num].out_format_drv_bits |= 0xc0; | |
1303 | break; | |
1304 | default: | |
b7bbf6ec | 1305 | dev_err(&data->i2c_client->dev, |
3044a860 ML |
1306 | "invalid silabs,format %u for %u\n", |
1307 | val, num); | |
1308 | goto put_child; | |
1309 | } | |
1310 | config[num].out_format_drv_bits &= ~0x07; | |
1311 | config[num].out_format_drv_bits |= val & 0x07; | |
1312 | /* Always enable the SYNC feature */ | |
1313 | config[num].out_format_drv_bits |= 0x08; | |
1314 | } | |
1315 | ||
1316 | if (!of_property_read_u32(child, "silabs,common-mode", &val)) { | |
1317 | if (val > 0xf) { | |
b7bbf6ec | 1318 | dev_err(&data->i2c_client->dev, |
3044a860 ML |
1319 | "invalid silabs,common-mode %u\n", |
1320 | val); | |
1321 | goto put_child; | |
1322 | } | |
1323 | config[num].out_cm_ampl_bits &= 0xf0; | |
1324 | config[num].out_cm_ampl_bits |= val & 0x0f; | |
1325 | } | |
1326 | ||
1327 | if (!of_property_read_u32(child, "silabs,amplitude", &val)) { | |
1328 | if (val > 0xf) { | |
b7bbf6ec | 1329 | dev_err(&data->i2c_client->dev, |
3044a860 ML |
1330 | "invalid silabs,amplitude %u\n", |
1331 | val); | |
1332 | goto put_child; | |
1333 | } | |
1334 | config[num].out_cm_ampl_bits &= 0x0f; | |
1335 | config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; | |
1336 | } | |
1337 | ||
1338 | if (of_property_read_bool(child, "silabs,disable-high")) | |
1339 | config[num].out_format_drv_bits |= 0x10; | |
1340 | ||
1341 | config[num].synth_master = | |
1342 | of_property_read_bool(child, "silabs,synth-master"); | |
1343 | ||
1344 | config[num].always_on = | |
1345 | of_property_read_bool(child, "always-on"); | |
b7bbf6ec RH |
1346 | |
1347 | config[num].vdd_sel_bits = 0x08; | |
1348 | if (data->clk[num].vddo_reg) { | |
1349 | int vdd = regulator_get_voltage(data->clk[num].vddo_reg); | |
1350 | ||
1351 | switch (vdd) { | |
1352 | case 3300000: | |
1353 | config[num].vdd_sel_bits |= 0 << 4; | |
1354 | break; | |
1355 | case 1800000: | |
1356 | config[num].vdd_sel_bits |= 1 << 4; | |
1357 | break; | |
1358 | case 2500000: | |
1359 | config[num].vdd_sel_bits |= 2 << 4; | |
1360 | break; | |
1361 | default: | |
1362 | dev_err(&data->i2c_client->dev, | |
1363 | "unsupported vddo voltage %d for %s\n", | |
1364 | vdd, child->name); | |
1365 | goto put_child; | |
1366 | } | |
1367 | } else { | |
1368 | /* chip seems to default to 2.5V when not set */ | |
1369 | dev_warn(&data->i2c_client->dev, | |
1370 | "no regulator set, defaulting vdd_sel to 2.5V for %s\n", | |
1371 | child->name); | |
1372 | config[num].vdd_sel_bits |= 2 << 4; | |
1373 | } | |
3044a860 ML |
1374 | } |
1375 | ||
1376 | return 0; | |
1377 | ||
1378 | put_child: | |
1379 | of_node_put(child); | |
1380 | return -EINVAL; | |
1381 | } | |
1382 | ||
1383 | /* | |
1384 | * If not pre-configured, calculate and set the PLL configuration manually. | |
1385 | * For low-jitter performance, the PLL should be set such that the synthesizers | |
1386 | * only need integer division. | |
1387 | * Without any user guidance, we'll set the PLL to 14GHz, which still allows | |
1388 | * the chip to generate any frequency on its outputs, but jitter performance | |
1389 | * may be sub-optimal. | |
1390 | */ | |
1391 | static int si5341_initialize_pll(struct clk_si5341 *data) | |
1392 | { | |
1393 | struct device_node *np = data->i2c_client->dev.of_node; | |
1394 | u32 m_num = 0; | |
1395 | u32 m_den = 0; | |
69275187 | 1396 | int sel; |
3044a860 ML |
1397 | |
1398 | if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { | |
1399 | dev_err(&data->i2c_client->dev, | |
1400 | "PLL configuration requires silabs,pll-m-num\n"); | |
1401 | } | |
1402 | if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { | |
1403 | dev_err(&data->i2c_client->dev, | |
1404 | "PLL configuration requires silabs,pll-m-den\n"); | |
1405 | } | |
1406 | ||
1407 | if (!m_num || !m_den) { | |
1408 | dev_err(&data->i2c_client->dev, | |
1409 | "PLL configuration invalid, assume 14GHz\n"); | |
69275187 ML |
1410 | sel = si5341_clk_get_selected_input(data); |
1411 | if (sel < 0) | |
1412 | return sel; | |
1413 | ||
1414 | m_den = clk_get_rate(data->input_clk[sel]) / 10; | |
3044a860 ML |
1415 | m_num = 1400000000; |
1416 | } | |
1417 | ||
1418 | return si5341_encode_44_32(data->regmap, | |
1419 | SI5341_PLL_M_NUM, m_num, m_den); | |
1420 | } | |
1421 | ||
69275187 ML |
1422 | static int si5341_clk_select_active_input(struct clk_si5341 *data) |
1423 | { | |
1424 | int res; | |
1425 | int err; | |
1426 | int i; | |
1427 | ||
1428 | res = si5341_clk_get_selected_input(data); | |
1429 | if (res < 0) | |
1430 | return res; | |
1431 | ||
1432 | /* If the current register setting is invalid, pick the first input */ | |
1433 | if (!data->input_clk[res]) { | |
1434 | dev_dbg(&data->i2c_client->dev, | |
1435 | "Input %d not connected, rerouting\n", res); | |
1436 | res = -ENODEV; | |
1437 | for (i = 0; i < SI5341_NUM_INPUTS; ++i) { | |
1438 | if (data->input_clk[i]) { | |
1439 | res = i; | |
1440 | break; | |
1441 | } | |
1442 | } | |
1443 | if (res < 0) { | |
1444 | dev_err(&data->i2c_client->dev, | |
1445 | "No clock input available\n"); | |
1446 | return res; | |
1447 | } | |
1448 | } | |
1449 | ||
1450 | /* Make sure the selected clock is also enabled and routed */ | |
1451 | err = si5341_clk_reparent(data, res); | |
1452 | if (err < 0) | |
1453 | return err; | |
1454 | ||
1455 | err = clk_prepare_enable(data->input_clk[res]); | |
1456 | if (err < 0) | |
1457 | return err; | |
1458 | ||
1459 | return res; | |
1460 | } | |
1461 | ||
9b13ff43 RH |
1462 | static ssize_t input_present_show(struct device *dev, |
1463 | struct device_attribute *attr, | |
1464 | char *buf) | |
1465 | { | |
1466 | struct clk_si5341 *data = dev_get_drvdata(dev); | |
1467 | u32 status; | |
1468 | int res = regmap_read(data->regmap, SI5341_STATUS, &status); | |
1469 | ||
1470 | if (res < 0) | |
1471 | return res; | |
1472 | res = !(status & SI5341_STATUS_LOSREF); | |
982c5953 | 1473 | return sysfs_emit(buf, "%d\n", res); |
9b13ff43 RH |
1474 | } |
1475 | static DEVICE_ATTR_RO(input_present); | |
1476 | ||
1477 | static ssize_t input_present_sticky_show(struct device *dev, | |
1478 | struct device_attribute *attr, | |
1479 | char *buf) | |
1480 | { | |
1481 | struct clk_si5341 *data = dev_get_drvdata(dev); | |
1482 | u32 status; | |
1483 | int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); | |
1484 | ||
1485 | if (res < 0) | |
1486 | return res; | |
1487 | res = !(status & SI5341_STATUS_LOSREF); | |
982c5953 | 1488 | return sysfs_emit(buf, "%d\n", res); |
9b13ff43 RH |
1489 | } |
1490 | static DEVICE_ATTR_RO(input_present_sticky); | |
1491 | ||
1492 | static ssize_t pll_locked_show(struct device *dev, | |
1493 | struct device_attribute *attr, | |
1494 | char *buf) | |
1495 | { | |
1496 | struct clk_si5341 *data = dev_get_drvdata(dev); | |
1497 | u32 status; | |
1498 | int res = regmap_read(data->regmap, SI5341_STATUS, &status); | |
1499 | ||
1500 | if (res < 0) | |
1501 | return res; | |
1502 | res = !(status & SI5341_STATUS_LOL); | |
982c5953 | 1503 | return sysfs_emit(buf, "%d\n", res); |
9b13ff43 RH |
1504 | } |
1505 | static DEVICE_ATTR_RO(pll_locked); | |
1506 | ||
1507 | static ssize_t pll_locked_sticky_show(struct device *dev, | |
1508 | struct device_attribute *attr, | |
1509 | char *buf) | |
1510 | { | |
1511 | struct clk_si5341 *data = dev_get_drvdata(dev); | |
1512 | u32 status; | |
1513 | int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); | |
1514 | ||
1515 | if (res < 0) | |
1516 | return res; | |
1517 | res = !(status & SI5341_STATUS_LOL); | |
982c5953 | 1518 | return sysfs_emit(buf, "%d\n", res); |
9b13ff43 RH |
1519 | } |
1520 | static DEVICE_ATTR_RO(pll_locked_sticky); | |
1521 | ||
1522 | static ssize_t clear_sticky_store(struct device *dev, | |
1523 | struct device_attribute *attr, | |
1524 | const char *buf, size_t count) | |
1525 | { | |
1526 | struct clk_si5341 *data = dev_get_drvdata(dev); | |
1527 | long val; | |
1528 | ||
1529 | if (kstrtol(buf, 10, &val)) | |
1530 | return -EINVAL; | |
1531 | if (val) { | |
1532 | int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); | |
1533 | ||
1534 | if (res < 0) | |
1535 | return res; | |
1536 | } | |
1537 | return count; | |
1538 | } | |
1539 | static DEVICE_ATTR_WO(clear_sticky); | |
1540 | ||
1541 | static const struct attribute *si5341_attributes[] = { | |
1542 | &dev_attr_input_present.attr, | |
1543 | &dev_attr_input_present_sticky.attr, | |
1544 | &dev_attr_pll_locked.attr, | |
1545 | &dev_attr_pll_locked_sticky.attr, | |
1546 | &dev_attr_clear_sticky.attr, | |
1547 | NULL | |
1548 | }; | |
1549 | ||
adc00f60 | 1550 | static int si5341_probe(struct i2c_client *client) |
3044a860 ML |
1551 | { |
1552 | struct clk_si5341 *data; | |
1553 | struct clk_init_data init; | |
69275187 | 1554 | struct clk *input; |
3044a860 ML |
1555 | const char *root_clock_name; |
1556 | const char *synth_clock_names[SI5341_NUM_SYNTH]; | |
1557 | int err; | |
1558 | unsigned int i; | |
1559 | struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; | |
1560 | bool initialization_required; | |
71dcc4d1 | 1561 | u32 status; |
3044a860 ML |
1562 | |
1563 | data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); | |
1564 | if (!data) | |
1565 | return -ENOMEM; | |
1566 | ||
1567 | data->i2c_client = client; | |
1568 | ||
6e7d2de1 RH |
1569 | /* Must be done before otherwise touching hardware */ |
1570 | err = si5341_wait_device_ready(client); | |
1571 | if (err) | |
1572 | return err; | |
1573 | ||
69275187 ML |
1574 | for (i = 0; i < SI5341_NUM_INPUTS; ++i) { |
1575 | input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); | |
1576 | if (IS_ERR(input)) { | |
1577 | if (PTR_ERR(input) == -EPROBE_DEFER) | |
1578 | return -EPROBE_DEFER; | |
1579 | data->input_clk_name[i] = si5341_input_clock_names[i]; | |
1580 | } else { | |
1581 | data->input_clk[i] = input; | |
1582 | data->input_clk_name[i] = __clk_get_name(input); | |
1583 | } | |
3044a860 ML |
1584 | } |
1585 | ||
b7bbf6ec RH |
1586 | for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { |
1587 | char reg_name[10]; | |
1588 | ||
1589 | snprintf(reg_name, sizeof(reg_name), "vddo%d", i); | |
1590 | data->clk[i].vddo_reg = devm_regulator_get_optional( | |
1591 | &client->dev, reg_name); | |
1592 | if (IS_ERR(data->clk[i].vddo_reg)) { | |
1593 | err = PTR_ERR(data->clk[i].vddo_reg); | |
1594 | data->clk[i].vddo_reg = NULL; | |
1595 | if (err == -ENODEV) | |
1596 | continue; | |
1597 | goto cleanup; | |
1598 | } else { | |
1599 | err = regulator_enable(data->clk[i].vddo_reg); | |
1600 | if (err) { | |
1601 | dev_err(&client->dev, | |
1602 | "failed to enable %s regulator: %d\n", | |
1603 | reg_name, err); | |
1604 | data->clk[i].vddo_reg = NULL; | |
1605 | goto cleanup; | |
1606 | } | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | err = si5341_dt_parse_dt(data, config); | |
3044a860 | 1611 | if (err) |
b7bbf6ec | 1612 | goto cleanup; |
3044a860 ML |
1613 | |
1614 | if (of_property_read_string(client->dev.of_node, "clock-output-names", | |
1615 | &init.name)) | |
1616 | init.name = client->dev.of_node->name; | |
1617 | root_clock_name = init.name; | |
1618 | ||
1619 | data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); | |
b7bbf6ec RH |
1620 | if (IS_ERR(data->regmap)) { |
1621 | err = PTR_ERR(data->regmap); | |
1622 | goto cleanup; | |
1623 | } | |
3044a860 ML |
1624 | |
1625 | i2c_set_clientdata(client, data); | |
1626 | ||
1627 | err = si5341_probe_chip_id(data); | |
1628 | if (err < 0) | |
b7bbf6ec | 1629 | goto cleanup; |
3044a860 | 1630 | |
3044a860 ML |
1631 | if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { |
1632 | initialization_required = true; | |
1633 | } else { | |
1634 | err = si5341_is_programmed_already(data); | |
1635 | if (err < 0) | |
b7bbf6ec | 1636 | goto cleanup; |
3044a860 ML |
1637 | |
1638 | initialization_required = !err; | |
1639 | } | |
ab89a343 RH |
1640 | data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node, |
1641 | "silabs,xaxb-ext-clk"); | |
2f02c5e4 RH |
1642 | data->iovdd_33 = of_property_read_bool(client->dev.of_node, |
1643 | "silabs,iovdd-33"); | |
3044a860 ML |
1644 | |
1645 | if (initialization_required) { | |
1646 | /* Populate the regmap cache in preparation for "cache only" */ | |
1647 | err = si5341_read_settings(data); | |
1648 | if (err < 0) | |
b7bbf6ec | 1649 | goto cleanup; |
3044a860 ML |
1650 | |
1651 | err = si5341_send_preamble(data); | |
1652 | if (err < 0) | |
b7bbf6ec | 1653 | goto cleanup; |
3044a860 ML |
1654 | |
1655 | /* | |
1656 | * We intend to send all 'final' register values in a single | |
1657 | * transaction. So cache all register writes until we're done | |
1658 | * configuring. | |
1659 | */ | |
1660 | regcache_cache_only(data->regmap, true); | |
1661 | ||
1662 | /* Write the configuration pairs from the firmware blob */ | |
1663 | err = si5341_write_multiple(data, si5341_reg_defaults, | |
1664 | ARRAY_SIZE(si5341_reg_defaults)); | |
1665 | if (err < 0) | |
b7bbf6ec | 1666 | goto cleanup; |
69275187 ML |
1667 | } |
1668 | ||
1669 | /* Input must be up and running at this point */ | |
1670 | err = si5341_clk_select_active_input(data); | |
1671 | if (err < 0) | |
b7bbf6ec | 1672 | goto cleanup; |
3044a860 | 1673 | |
69275187 | 1674 | if (initialization_required) { |
3044a860 ML |
1675 | /* PLL configuration is required */ |
1676 | err = si5341_initialize_pll(data); | |
1677 | if (err < 0) | |
b7bbf6ec | 1678 | goto cleanup; |
3044a860 ML |
1679 | } |
1680 | ||
1681 | /* Register the PLL */ | |
69275187 ML |
1682 | init.parent_names = data->input_clk_name; |
1683 | init.num_parents = SI5341_NUM_INPUTS; | |
3044a860 ML |
1684 | init.ops = &si5341_clk_ops; |
1685 | init.flags = 0; | |
1686 | data->hw.init = &init; | |
1687 | ||
1688 | err = devm_clk_hw_register(&client->dev, &data->hw); | |
1689 | if (err) { | |
1690 | dev_err(&client->dev, "clock registration failed\n"); | |
b7bbf6ec | 1691 | goto cleanup; |
3044a860 ML |
1692 | } |
1693 | ||
1694 | init.num_parents = 1; | |
1695 | init.parent_names = &root_clock_name; | |
1696 | init.ops = &si5341_synth_clk_ops; | |
1697 | for (i = 0; i < data->num_synth; ++i) { | |
1698 | synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, | |
1699 | "%s.N%u", client->dev.of_node->name, i); | |
1700 | init.name = synth_clock_names[i]; | |
1701 | data->synth[i].index = i; | |
1702 | data->synth[i].data = data; | |
1703 | data->synth[i].hw.init = &init; | |
1704 | err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); | |
1705 | if (err) { | |
1706 | dev_err(&client->dev, | |
1707 | "synth N%u registration failed\n", i); | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | init.num_parents = data->num_synth; | |
1712 | init.parent_names = synth_clock_names; | |
1713 | init.ops = &si5341_output_clk_ops; | |
1714 | for (i = 0; i < data->num_outputs; ++i) { | |
1715 | init.name = kasprintf(GFP_KERNEL, "%s.%d", | |
1716 | client->dev.of_node->name, i); | |
1717 | init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0; | |
1718 | data->clk[i].index = i; | |
1719 | data->clk[i].data = data; | |
1720 | data->clk[i].hw.init = &init; | |
1721 | if (config[i].out_format_drv_bits & 0x07) { | |
1722 | regmap_write(data->regmap, | |
1723 | SI5341_OUT_FORMAT(&data->clk[i]), | |
1724 | config[i].out_format_drv_bits); | |
1725 | regmap_write(data->regmap, | |
1726 | SI5341_OUT_CM(&data->clk[i]), | |
1727 | config[i].out_cm_ampl_bits); | |
b7bbf6ec RH |
1728 | regmap_update_bits(data->regmap, |
1729 | SI5341_OUT_MUX_SEL(&data->clk[i]), | |
1730 | SI5341_OUT_MUX_VDD_SEL_MASK, | |
1731 | config[i].vdd_sel_bits); | |
3044a860 ML |
1732 | } |
1733 | err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); | |
1734 | kfree(init.name); /* clock framework made a copy of the name */ | |
1735 | if (err) { | |
1736 | dev_err(&client->dev, | |
1737 | "output %u registration failed\n", i); | |
b7bbf6ec | 1738 | goto cleanup; |
3044a860 ML |
1739 | } |
1740 | if (config[i].always_on) | |
1741 | clk_prepare(data->clk[i].hw.clk); | |
1742 | } | |
1743 | ||
49a8f2bc | 1744 | err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get, |
3044a860 ML |
1745 | data); |
1746 | if (err) { | |
1747 | dev_err(&client->dev, "unable to add clk provider\n"); | |
b7bbf6ec | 1748 | goto cleanup; |
3044a860 ML |
1749 | } |
1750 | ||
1751 | if (initialization_required) { | |
1752 | /* Synchronize */ | |
1753 | regcache_cache_only(data->regmap, false); | |
1754 | err = regcache_sync(data->regmap); | |
1755 | if (err < 0) | |
b7bbf6ec | 1756 | goto cleanup; |
3044a860 ML |
1757 | |
1758 | err = si5341_finalize_defaults(data); | |
1759 | if (err < 0) | |
b7bbf6ec | 1760 | goto cleanup; |
3044a860 ML |
1761 | } |
1762 | ||
71dcc4d1 RH |
1763 | /* wait for device to report input clock present and PLL lock */ |
1764 | err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status, | |
1765 | !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)), | |
1766 | 10000, 250000); | |
1767 | if (err) { | |
1768 | dev_err(&client->dev, "Error waiting for input clock or PLL lock\n"); | |
b7bbf6ec | 1769 | goto cleanup; |
71dcc4d1 RH |
1770 | } |
1771 | ||
1772 | /* clear sticky alarm bits from initialization */ | |
1773 | err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); | |
1774 | if (err) { | |
1775 | dev_err(&client->dev, "unable to clear sticky status\n"); | |
b7bbf6ec | 1776 | goto cleanup; |
71dcc4d1 RH |
1777 | } |
1778 | ||
9b13ff43 RH |
1779 | err = sysfs_create_files(&client->dev.kobj, si5341_attributes); |
1780 | if (err) { | |
1781 | dev_err(&client->dev, "unable to create sysfs files\n"); | |
1782 | goto cleanup; | |
1783 | } | |
1784 | ||
3044a860 ML |
1785 | /* Free the names, clk framework makes copies */ |
1786 | for (i = 0; i < data->num_synth; ++i) | |
1787 | devm_kfree(&client->dev, (void *)synth_clock_names[i]); | |
1788 | ||
1789 | return 0; | |
b7bbf6ec RH |
1790 | |
1791 | cleanup: | |
1792 | for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { | |
1793 | if (data->clk[i].vddo_reg) | |
1794 | regulator_disable(data->clk[i].vddo_reg); | |
1795 | } | |
1796 | return err; | |
1797 | } | |
1798 | ||
1799 | static int si5341_remove(struct i2c_client *client) | |
1800 | { | |
1801 | struct clk_si5341 *data = i2c_get_clientdata(client); | |
1802 | int i; | |
1803 | ||
9b13ff43 RH |
1804 | sysfs_remove_files(&client->dev.kobj, si5341_attributes); |
1805 | ||
b7bbf6ec RH |
1806 | for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { |
1807 | if (data->clk[i].vddo_reg) | |
1808 | regulator_disable(data->clk[i].vddo_reg); | |
1809 | } | |
1810 | ||
1811 | return 0; | |
3044a860 ML |
1812 | } |
1813 | ||
1814 | static const struct i2c_device_id si5341_id[] = { | |
1815 | { "si5340", 0 }, | |
1816 | { "si5341", 1 }, | |
f9eec2ea ML |
1817 | { "si5342", 2 }, |
1818 | { "si5344", 4 }, | |
1819 | { "si5345", 5 }, | |
3044a860 ML |
1820 | { } |
1821 | }; | |
1822 | MODULE_DEVICE_TABLE(i2c, si5341_id); | |
1823 | ||
1824 | static const struct of_device_id clk_si5341_of_match[] = { | |
1825 | { .compatible = "silabs,si5340" }, | |
1826 | { .compatible = "silabs,si5341" }, | |
f9eec2ea ML |
1827 | { .compatible = "silabs,si5342" }, |
1828 | { .compatible = "silabs,si5344" }, | |
1829 | { .compatible = "silabs,si5345" }, | |
3044a860 ML |
1830 | { } |
1831 | }; | |
1832 | MODULE_DEVICE_TABLE(of, clk_si5341_of_match); | |
1833 | ||
1834 | static struct i2c_driver si5341_driver = { | |
1835 | .driver = { | |
1836 | .name = "si5341", | |
1837 | .of_match_table = clk_si5341_of_match, | |
1838 | }, | |
adc00f60 | 1839 | .probe_new = si5341_probe, |
b7bbf6ec | 1840 | .remove = si5341_remove, |
3044a860 ML |
1841 | .id_table = si5341_id, |
1842 | }; | |
1843 | module_i2c_driver(si5341_driver); | |
1844 | ||
1845 | MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); | |
1846 | MODULE_DESCRIPTION("Si5341 driver"); | |
1847 | MODULE_LICENSE("GPL"); |