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6d6a1d82 SH |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * System Control and Power Interface (SCMI) Protocol based clock driver | |
4 | * | |
38a0e5b7 | 5 | * Copyright (C) 2018-2022 ARM Ltd. |
6d6a1d82 SH |
6 | */ |
7 | ||
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/scmi_protocol.h> | |
14 | #include <asm/div64.h> | |
15 | ||
03a95cf2 CM |
16 | #define NOT_ATOMIC false |
17 | #define ATOMIC true | |
18 | ||
beb076bb CM |
19 | static const struct scmi_clk_proto_ops *scmi_proto_clk_ops; |
20 | ||
6d6a1d82 SH |
21 | struct scmi_clk { |
22 | u32 id; | |
1b39ff51 | 23 | struct device *dev; |
6d6a1d82 SH |
24 | struct clk_hw hw; |
25 | const struct scmi_clock_info *info; | |
beb076bb | 26 | const struct scmi_protocol_handle *ph; |
6d6a1d82 SH |
27 | }; |
28 | ||
29 | #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw) | |
30 | ||
31 | static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw, | |
32 | unsigned long parent_rate) | |
33 | { | |
34 | int ret; | |
35 | u64 rate; | |
36 | struct scmi_clk *clk = to_scmi_clk(hw); | |
37 | ||
beb076bb | 38 | ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate); |
6d6a1d82 SH |
39 | if (ret) |
40 | return 0; | |
41 | return rate; | |
42 | } | |
43 | ||
44 | static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
45 | unsigned long *parent_rate) | |
46 | { | |
6d6a1d82 SH |
47 | u64 fmin, fmax, ftmp; |
48 | struct scmi_clk *clk = to_scmi_clk(hw); | |
49 | ||
50 | /* | |
51 | * We can't figure out what rate it will be, so just return the | |
52 | * rate back to the caller. scmi_clk_recalc_rate() will be called | |
53 | * after the rate is set and we'll know what rate the clock is | |
54 | * running at then. | |
55 | */ | |
56 | if (clk->info->rate_discrete) | |
57 | return rate; | |
58 | ||
59 | fmin = clk->info->range.min_rate; | |
60 | fmax = clk->info->range.max_rate; | |
61 | if (rate <= fmin) | |
62 | return fmin; | |
63 | else if (rate >= fmax) | |
64 | return fmax; | |
65 | ||
66 | ftmp = rate - fmin; | |
67 | ftmp += clk->info->range.step_size - 1; /* to round up */ | |
7a8655e1 | 68 | do_div(ftmp, clk->info->range.step_size); |
6d6a1d82 | 69 | |
7a8655e1 | 70 | return ftmp * clk->info->range.step_size + fmin; |
6d6a1d82 SH |
71 | } |
72 | ||
73 | static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
74 | unsigned long parent_rate) | |
75 | { | |
76 | struct scmi_clk *clk = to_scmi_clk(hw); | |
77 | ||
beb076bb | 78 | return scmi_proto_clk_ops->rate_set(clk->ph, clk->id, rate); |
6d6a1d82 SH |
79 | } |
80 | ||
81 | static int scmi_clk_enable(struct clk_hw *hw) | |
82 | { | |
83 | struct scmi_clk *clk = to_scmi_clk(hw); | |
84 | ||
03a95cf2 | 85 | return scmi_proto_clk_ops->enable(clk->ph, clk->id, NOT_ATOMIC); |
6d6a1d82 SH |
86 | } |
87 | ||
88 | static void scmi_clk_disable(struct clk_hw *hw) | |
89 | { | |
90 | struct scmi_clk *clk = to_scmi_clk(hw); | |
91 | ||
03a95cf2 | 92 | scmi_proto_clk_ops->disable(clk->ph, clk->id, NOT_ATOMIC); |
6d6a1d82 SH |
93 | } |
94 | ||
38a0e5b7 CM |
95 | static int scmi_clk_atomic_enable(struct clk_hw *hw) |
96 | { | |
97 | struct scmi_clk *clk = to_scmi_clk(hw); | |
98 | ||
03a95cf2 | 99 | return scmi_proto_clk_ops->enable(clk->ph, clk->id, ATOMIC); |
38a0e5b7 CM |
100 | } |
101 | ||
102 | static void scmi_clk_atomic_disable(struct clk_hw *hw) | |
103 | { | |
104 | struct scmi_clk *clk = to_scmi_clk(hw); | |
105 | ||
03a95cf2 | 106 | scmi_proto_clk_ops->disable(clk->ph, clk->id, ATOMIC); |
38a0e5b7 CM |
107 | } |
108 | ||
1b39ff51 CM |
109 | static int scmi_clk_atomic_is_enabled(struct clk_hw *hw) |
110 | { | |
111 | int ret; | |
112 | bool enabled = false; | |
113 | struct scmi_clk *clk = to_scmi_clk(hw); | |
114 | ||
115 | ret = scmi_proto_clk_ops->state_get(clk->ph, clk->id, &enabled, ATOMIC); | |
116 | if (ret) | |
117 | dev_warn(clk->dev, | |
118 | "Failed to get state for clock ID %d\n", clk->id); | |
119 | ||
120 | return !!enabled; | |
121 | } | |
122 | ||
38a0e5b7 | 123 | /* |
1b39ff51 CM |
124 | * We can provide enable/disable/is_enabled atomic callbacks only if the |
125 | * underlying SCMI transport for an SCMI instance is configured to handle | |
126 | * SCMI commands in an atomic manner. | |
38a0e5b7 CM |
127 | * |
128 | * When no SCMI atomic transport support is available we instead provide only | |
129 | * the prepare/unprepare API, as allowed by the clock framework when atomic | |
130 | * calls are not available. | |
131 | * | |
132 | * Two distinct sets of clk_ops are provided since we could have multiple SCMI | |
133 | * instances with different underlying transport quality, so they cannot be | |
134 | * shared. | |
135 | */ | |
6d6a1d82 SH |
136 | static const struct clk_ops scmi_clk_ops = { |
137 | .recalc_rate = scmi_clk_recalc_rate, | |
138 | .round_rate = scmi_clk_round_rate, | |
139 | .set_rate = scmi_clk_set_rate, | |
6d6a1d82 SH |
140 | .prepare = scmi_clk_enable, |
141 | .unprepare = scmi_clk_disable, | |
142 | }; | |
143 | ||
38a0e5b7 CM |
144 | static const struct clk_ops scmi_atomic_clk_ops = { |
145 | .recalc_rate = scmi_clk_recalc_rate, | |
146 | .round_rate = scmi_clk_round_rate, | |
147 | .set_rate = scmi_clk_set_rate, | |
148 | .enable = scmi_clk_atomic_enable, | |
149 | .disable = scmi_clk_atomic_disable, | |
1b39ff51 | 150 | .is_enabled = scmi_clk_atomic_is_enabled, |
38a0e5b7 CM |
151 | }; |
152 | ||
153 | static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, | |
154 | const struct clk_ops *scmi_ops) | |
6d6a1d82 SH |
155 | { |
156 | int ret; | |
fcd2e0de SH |
157 | unsigned long min_rate, max_rate; |
158 | ||
6d6a1d82 SH |
159 | struct clk_init_data init = { |
160 | .flags = CLK_GET_RATE_NOCACHE, | |
161 | .num_parents = 0, | |
38a0e5b7 | 162 | .ops = scmi_ops, |
6d6a1d82 SH |
163 | .name = sclk->info->name, |
164 | }; | |
165 | ||
166 | sclk->hw.init = &init; | |
167 | ret = devm_clk_hw_register(dev, &sclk->hw); | |
fcd2e0de SH |
168 | if (ret) |
169 | return ret; | |
170 | ||
171 | if (sclk->info->rate_discrete) { | |
172 | int num_rates = sclk->info->list.num_rates; | |
173 | ||
174 | if (num_rates <= 0) | |
175 | return -EINVAL; | |
176 | ||
177 | min_rate = sclk->info->list.rates[0]; | |
178 | max_rate = sclk->info->list.rates[num_rates - 1]; | |
179 | } else { | |
180 | min_rate = sclk->info->range.min_rate; | |
181 | max_rate = sclk->info->range.max_rate; | |
182 | } | |
183 | ||
184 | clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate); | |
6d6a1d82 SH |
185 | return ret; |
186 | } | |
187 | ||
188 | static int scmi_clocks_probe(struct scmi_device *sdev) | |
189 | { | |
190 | int idx, count, err; | |
38a0e5b7 CM |
191 | unsigned int atomic_threshold; |
192 | bool is_atomic; | |
6d6a1d82 SH |
193 | struct clk_hw **hws; |
194 | struct clk_hw_onecell_data *clk_data; | |
195 | struct device *dev = &sdev->dev; | |
196 | struct device_node *np = dev->of_node; | |
197 | const struct scmi_handle *handle = sdev->handle; | |
beb076bb | 198 | struct scmi_protocol_handle *ph; |
6d6a1d82 | 199 | |
beb076bb | 200 | if (!handle) |
6d6a1d82 SH |
201 | return -ENODEV; |
202 | ||
beb076bb CM |
203 | scmi_proto_clk_ops = |
204 | handle->devm_protocol_get(sdev, SCMI_PROTOCOL_CLOCK, &ph); | |
205 | if (IS_ERR(scmi_proto_clk_ops)) | |
206 | return PTR_ERR(scmi_proto_clk_ops); | |
207 | ||
208 | count = scmi_proto_clk_ops->count_get(ph); | |
6d6a1d82 | 209 | if (count < 0) { |
e665f029 | 210 | dev_err(dev, "%pOFn: invalid clock output count\n", np); |
6d6a1d82 SH |
211 | return -EINVAL; |
212 | } | |
213 | ||
0ed2dd03 KC |
214 | clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), |
215 | GFP_KERNEL); | |
6d6a1d82 SH |
216 | if (!clk_data) |
217 | return -ENOMEM; | |
218 | ||
219 | clk_data->num = count; | |
220 | hws = clk_data->hws; | |
221 | ||
38a0e5b7 CM |
222 | is_atomic = handle->is_transport_atomic(handle, &atomic_threshold); |
223 | ||
6d6a1d82 SH |
224 | for (idx = 0; idx < count; idx++) { |
225 | struct scmi_clk *sclk; | |
38a0e5b7 | 226 | const struct clk_ops *scmi_ops; |
6d6a1d82 SH |
227 | |
228 | sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); | |
229 | if (!sclk) | |
230 | return -ENOMEM; | |
231 | ||
beb076bb | 232 | sclk->info = scmi_proto_clk_ops->info_get(ph, idx); |
6d6a1d82 SH |
233 | if (!sclk->info) { |
234 | dev_dbg(dev, "invalid clock info for idx %d\n", idx); | |
3537a75e | 235 | devm_kfree(dev, sclk); |
6d6a1d82 SH |
236 | continue; |
237 | } | |
238 | ||
239 | sclk->id = idx; | |
beb076bb | 240 | sclk->ph = ph; |
1b39ff51 | 241 | sclk->dev = dev; |
6d6a1d82 | 242 | |
38a0e5b7 CM |
243 | /* |
244 | * Note that when transport is atomic but SCMI protocol did not | |
245 | * specify (or support) an enable_latency associated with a | |
246 | * clock, we default to use atomic operations mode. | |
247 | */ | |
248 | if (is_atomic && | |
249 | sclk->info->enable_latency <= atomic_threshold) | |
250 | scmi_ops = &scmi_atomic_clk_ops; | |
251 | else | |
252 | scmi_ops = &scmi_clk_ops; | |
253 | ||
254 | err = scmi_clk_ops_init(dev, sclk, scmi_ops); | |
6d6a1d82 SH |
255 | if (err) { |
256 | dev_err(dev, "failed to register clock %d\n", idx); | |
257 | devm_kfree(dev, sclk); | |
258 | hws[idx] = NULL; | |
259 | } else { | |
38a0e5b7 CM |
260 | dev_dbg(dev, "Registered clock:%s%s\n", |
261 | sclk->info->name, | |
262 | scmi_ops == &scmi_atomic_clk_ops ? | |
263 | " (atomic ops)" : ""); | |
6d6a1d82 SH |
264 | hws[idx] = &sclk->hw; |
265 | } | |
266 | } | |
267 | ||
7f9badfc SH |
268 | return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, |
269 | clk_data); | |
6d6a1d82 SH |
270 | } |
271 | ||
272 | static const struct scmi_device_id scmi_id_table[] = { | |
43998dfe | 273 | { SCMI_PROTOCOL_CLOCK, "clocks" }, |
6d6a1d82 SH |
274 | { }, |
275 | }; | |
276 | MODULE_DEVICE_TABLE(scmi, scmi_id_table); | |
277 | ||
278 | static struct scmi_driver scmi_clocks_driver = { | |
279 | .name = "scmi-clocks", | |
280 | .probe = scmi_clocks_probe, | |
6d6a1d82 SH |
281 | .id_table = scmi_id_table, |
282 | }; | |
283 | module_scmi_driver(scmi_clocks_driver); | |
284 | ||
285 | MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>"); | |
286 | MODULE_DESCRIPTION("ARM SCMI clock driver"); | |
287 | MODULE_LICENSE("GPL v2"); |