[linux-2.6-block.git] / drivers / clk / clk-mux.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)

static u8 clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_mux *mux = to_clk_mux(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	/*
	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	 * to 0x7 (index starts at one)
	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	 * val = 0x4 really means "bit 2, index starts at bit 0"
	 */
	val = clk_readl(mux->reg) >> mux->shift;
	val &= mux->mask;

	if (mux->table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (mux->table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val;
	unsigned long flags = 0;

	if (mux->table) {
		index = mux->table[index];
	} else {
		if (mux->flags & CLK_MUX_INDEX_BIT)
			index = 1 << index;

		if (mux->flags & CLK_MUX_INDEX_ONE)
			index++;
	}

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);
	else
		__acquire(mux->lock);

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		val = mux->mask << (mux->shift + 16);
	} else {
		val = clk_readl(mux->reg);
		val &= ~(mux->mask << mux->shift);
	}
	val |= index << mux->shift;
	clk_writel(val, mux->reg);

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);
	else
		__release(mux->lock);

	return 0;
}

const struct clk_ops clk_mux_ops = {
	.get_parent = clk_mux_get_parent,
	.set_parent = clk_mux_set_parent,
	.determine_rate = __clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_mux_ops);

const struct clk_ops clk_mux_ro_ops = {
	.get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_mux *mux;
	struct clk *clk;
	struct clk_init_data init;
	u8 width = 0;

	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the mux */
	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
	if (!mux) {
		pr_err("%s: could not allocate mux clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_ops;
	else
		init.ops = &clk_mux_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux assignments */
	mux->reg = reg;
	mux->shift = shift;
	mux->mask = mask;
	mux->flags = clk_mux_flags;
	mux->lock = lock;
	mux->table = table;
	mux->hw.init = &init;

	clk = clk_register(dev, &mux->hw);

	if (IS_ERR(clk))
		kfree(mux);

	return clk;
}
EXPORT_SYMBOL_GPL(clk_register_mux_table);

struct clk *clk_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);

void clk_unregister_mux(struct clk *clk)
{
	struct clk_mux *mux;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	mux = to_clk_mux(hw);

	clk_unregister(clk);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_unregister_mux);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Simple multiplexer clock implementation
	11	*/
	12
9d9f78ed MT	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18
	19	/*
	20	* DOC: basic adjustable multiplexer clock that cannot gate
	21	*
	22	* Traits of this clock:
	23	* prepare - clk_prepare only ensures that parents are prepared
	24	* enable - clk_enable only ensures that parents are enabled
	25	* rate - rate is only affected by parent switching. No clk_set_rate support
	26	* parent - parent is adjustable through clk_set_parent
	27	*/
	28
	29	#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
	30
	31	static u8 clk_mux_get_parent(struct clk_hw *hw)
	32	{
	33	struct clk_mux *mux = to_clk_mux(hw);
497295af	34	int num_parents = clk_hw_get_num_parents(hw);
9d9f78ed MT	35	u32 val;
	36
	37	/*
	38	* FIXME need a mux-specific flag to determine if val is bitwise or numeric
	39	* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	40	* to 0x7 (index starts at one)
	41	* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	42	* val = 0x4 really means "bit 2, index starts at bit 0"
	43	*/
aa514ce3	44	val = clk_readl(mux->reg) >> mux->shift;
ce4f3313 PDS	45	val &= mux->mask;
	46
	47	if (mux->table) {
	48	int i;
	49
	50	for (i = 0; i < num_parents; i++)
	51	if (mux->table[i] == val)
	52	return i;
	53	return -EINVAL;
	54	}
9d9f78ed MT	55
	56	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
	57	val = ffs(val) - 1;
	58
	59	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
	60	val--;
	61
ce4f3313	62	if (val >= num_parents)
9d9f78ed MT	63	return -EINVAL;
	64
	65	return val;
	66	}
9d9f78ed MT	67
	68	static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
	69	{
	70	struct clk_mux *mux = to_clk_mux(hw);
	71	u32 val;
	72	unsigned long flags = 0;
	73
3837bd27	74	if (mux->table) {
ce4f3313	75	index = mux->table[index];
3837bd27	76	} else {
ce4f3313	77	if (mux->flags & CLK_MUX_INDEX_BIT)
6793b3cd	78	index = 1 << index;
ce4f3313 PDS	79
	80	if (mux->flags & CLK_MUX_INDEX_ONE)
	81	index++;
	82	}
9d9f78ed MT	83
	84	if (mux->lock)
	85	spin_lock_irqsave(mux->lock, flags);
661e2180 SB	86	else
661e2180 SB	87	__acquire(mux->lock);
9d9f78ed	88
ba492e90 HZ	89	if (mux->flags & CLK_MUX_HIWORD_MASK) {
	90	val = mux->mask << (mux->shift + 16);
	91	} else {
aa514ce3	92	val = clk_readl(mux->reg);
ba492e90 HZ	93	val &= ~(mux->mask << mux->shift);
ba492e90 HZ	94	}
9d9f78ed	95	val \|= index << mux->shift;
aa514ce3	96	clk_writel(val, mux->reg);
9d9f78ed MT	97
	98	if (mux->lock)
	99	spin_unlock_irqrestore(mux->lock, flags);
661e2180 SB	100	else
661e2180 SB	101	__release(mux->lock);
9d9f78ed MT	102
	103	return 0;
	104	}
9d9f78ed	105
822c250e	106	const struct clk_ops clk_mux_ops = {
9d9f78ed MT	107	.get_parent = clk_mux_get_parent,
9d9f78ed MT	108	.set_parent = clk_mux_set_parent,
e366fdd7	109	.determine_rate = __clk_mux_determine_rate,
9d9f78ed MT	110	};
	111	EXPORT_SYMBOL_GPL(clk_mux_ops);
	112
c57acd14 TF	113	const struct clk_ops clk_mux_ro_ops = {
	114	.get_parent = clk_mux_get_parent,
	115	};
	116	EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
	117
ce4f3313	118	struct clk clk_register_mux_table(struct device dev, const char *name,
2893c379 SH	119	const char * const *parent_names, u8 num_parents,
2893c379 SH	120	unsigned long flags,
ce4f3313 PDS	121	void __iomem *reg, u8 shift, u32 mask,
ce4f3313 PDS	122	u8 clk_mux_flags, u32 table, spinlock_t lock)
9d9f78ed MT	123	{
9d9f78ed MT	124	struct clk_mux *mux;
27d54591	125	struct clk *clk;
0197b3ea	126	struct clk_init_data init;
ba492e90 HZ	127	u8 width = 0;
	128
	129	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
	130	width = fls(mask) - ffs(mask) + 1;
	131	if (width + shift > 16) {
	132	pr_err("mux value exceeds LOWORD field\n");
	133	return ERR_PTR(-EINVAL);
	134	}
	135	}
9d9f78ed	136
27d54591	137	/* allocate the mux */
10363b58	138	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
9d9f78ed MT	139	if (!mux) {
	140	pr_err("%s: could not allocate mux clk\n", __func__);
	141	return ERR_PTR(-ENOMEM);
	142	}
	143
0197b3ea	144	init.name = name;
c57acd14 TF	145	if (clk_mux_flags & CLK_MUX_READ_ONLY)
	146	init.ops = &clk_mux_ro_ops;
	147	else
	148	init.ops = &clk_mux_ops;
f7d8caad	149	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	150	init.parent_names = parent_names;
	151	init.num_parents = num_parents;
	152
9d9f78ed MT	153	/* struct clk_mux assignments */
	154	mux->reg = reg;
	155	mux->shift = shift;
ce4f3313	156	mux->mask = mask;
9d9f78ed MT	157	mux->flags = clk_mux_flags;
9d9f78ed MT	158	mux->lock = lock;
ce4f3313	159	mux->table = table;
31df9db9	160	mux->hw.init = &init;
9d9f78ed	161
0197b3ea	162	clk = clk_register(dev, &mux->hw);
27d54591 MT	163
	164	if (IS_ERR(clk))
	165	kfree(mux);
	166
	167	return clk;
9d9f78ed	168	}
5cfe10bb	169	EXPORT_SYMBOL_GPL(clk_register_mux_table);
ce4f3313 PDS	170
ce4f3313 PDS	171	struct clk clk_register_mux(struct device dev, const char *name,
2893c379 SH	172	const char * const *parent_names, u8 num_parents,
2893c379 SH	173	unsigned long flags,
ce4f3313 PDS	174	void __iomem *reg, u8 shift, u8 width,
	175	u8 clk_mux_flags, spinlock_t *lock)
	176	{
	177	u32 mask = BIT(width) - 1;
	178
	179	return clk_register_mux_table(dev, name, parent_names, num_parents,
	180	flags, reg, shift, mask, clk_mux_flags,
	181	NULL, lock);
	182	}
5cfe10bb	183	EXPORT_SYMBOL_GPL(clk_register_mux);
4e3c021f KK	184
	185	void clk_unregister_mux(struct clk *clk)
	186	{
	187	struct clk_mux *mux;
	188	struct clk_hw *hw;
	189
	190	hw = __clk_get_hw(clk);
	191	if (!hw)
	192	return;
	193
	194	mux = to_clk_mux(hw);
	195
	196	clk_unregister(clk);
	197	kfree(mux);
	198	}
	199	EXPORT_SYMBOL_GPL(clk_unregister_mux);